Digital Integrated Circuits

(83-313)

Lecture 11:
Other Memories
Prof. Adam Teman
27 May 2022

Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed,
please feel free to email adam.teman@biu.ac.il and I will address this as soon as possible.
 Lecture Content

2
© Adam May 27, 2022
Teman,
 1 2 3 4 5
Hierarchy ROM DRAM NVM Emerging NVM

The Memory Hierarchy

 Semiconductor Memory Classification
Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory

(CAM)

Read/Write Memory Read Only Memory

Shift Registers Queues
(RAM) (ROM)
(Volatile) (Nonvolatile)

Serial In Parallel In First In Last In

Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out
(SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO)

Mask ROM Programmable Erasable Electrically Flash ROM

ROM Programmable Erasable
(PROM) ROM Programmable
(EPROM) ROM From Weste, Harris 2011
4 (EEPROM) © Adam May 27, 2022
Teman,
 Memory Hierarchy of a Personal Computer

Source: Teman, et al., Wiley 2022

5 © Adam May 27, 2022
Teman,
Another View

© Adam May 27, 2022

Teman,
 1 2 3 4 5
Hierarchy ROM DRAM NVM Emerging NVM

READ Only Memory (ROM)

7
SRAM Drawbacks BL BLB

• The 6T SRAM is by far the dominant WL

M3 M6
WL

on-chip (embedded) memory solution M2 M5

• Static operation Q QB
• High noise margins M1 M4
• Differential (→Fast) readout
• Symmetric structure → dense layout
• But six transistors is still a lot…
• On-chip SRAM is (usually) limited to a <30 MB
• Smallest Linux distro requires >64 MB to run
• Windows 10 requires >2 GB to run

• Can we achieve higher density?

© Adam May 27, 2022
Teman,
Do all memories need R/W access? Memory Arrays

• We needed a lot of design to enable Random Access Memory Serial Access Memory Content Addressable Memory
(CAM)

both read and write Read/Write Memory

(RAM)
Read Only Memory
(ROM)
Shift Registers Queues
(Volatile) (Nonvolatile)

• But some memories are Read Only Serial In Parallel In First In Last In
Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out
(SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO)

• Can we manufacture a memory with Mask ROM Programmable

ROM
(PROM)
Erasable
Programmable
ROM
Electrically
Erasable
Programmable
Flash ROM

predefined content that can only be read? (EPROM) ROM

(EEPROM)

• One option is to define it in the RTL…

• But what if we want it to be nicely structured and
easily modified for bug fixes and future versions of our product?

• The solution: Mask ROM

© Adam May 27, 2022
Teman,
Reminder: NOR vs. NAND Pull-Down Networks
• In a NOR gate, we only need one • In a NAND gate, we need all paths to
conducting path to pull down the output be conducting to pull down the output

Vcc

NMOS
NOR gate
Source: Wikipedia © Adam May 27, 2022
Teman,
Read-Only Memory Cells

© Adam May 27, 2022

Teman, 11
NOR ROM
• 4-word x 6-bit NOR-ROM
• Selected word-line high

• Represented with dot diagram

From Weste, Harris 2011

© Adam May 27, 2022

Teman, 12
NOR ROM Layout Cell (11l x 7l)

• Programming using the Contact Layer Only

VDD
Pull-up
devices

WL[0]
GND
WL[1] Polysilicon

WL[2]
Metal1
GND Diffusion
WL[3]
Metal1 on
Diffusion
BL[0] BL[1] BL[2] BL[3]

© Adam May 27, 2022

Teman, 13
 NAND ROM
• 4-word 4-bit NAND ROM
• All word-lines high by default
with exception of selected row

14 © Adam May 27, 2022

Teman,
NAND ROM Layout
Polysilicon
• Programming using Implants Only
Threshold-altering
• No contact to VDD or GND necessary implant

→ Drastically reduced cell size Cell (5l x 6l) Metal1 on Diffusion

• Loss in performance
compared to
NOR ROM

© Adam May 27, 2022

Teman, 15
One-Time-Programmable Memory (OTP)
• Mask ROM is set during fabrication
• An actual lithography mask encodes the ROM content.
• A re-spin of the chip is needed in order to change the ROM.
• Programmable Read-Only Memories (PROM) are an alternative
• Content of the PROM can be programmed (blown) after manufacturing
• Generally, One-Time-Programmable (OTP) devices used today.
• Often used to store boot code, encryption keys and configuration parameters.
• Achieved by integrating an “antifuse”
within the CMOS process
• Apply a high-voltage pulse (~6V) across the gate
→ oxide breakdown.

Source: Chung, 2020 © Adam May 27, 2022

Teman,
 1 2 3 4 5
Hierarchy ROM DRAM NVM Emerging NVM

Dynamic RAM (DRAM)

17
ROMs are very limited in usage
• ROMs can be only used for data that is:
• Written during manufacturing
• Can only be read.
• OTPs:
• Can be configured after manufacturing
• But still, only once.

• How can we make a high-density (→ high-capacity) memory

that can be used for both reading and writing?

© Adam May 27, 2022

Teman,
Let’s go dynamic
• The Intel 1103 used a 3T DRAM cell
• Store data on capacitor (Cs)
• Write through M1
• Read through M2 and M3
• Advantages:
• No constraints on device ratios.
• Reads are non-destructive.
• Disadvantages
• Data leaks away over time
• “Weak 1” stored on node X.
• Single-ended read operation

© Adam May 27, 2022

Teman, 19
3T DRAM Layout
• Route word-lines (WWL, RWL) in Poly
• Route bit-lines (BL1, BL2) and GND in M2
• Disadvantage:
• Contact-dominated layout

© Adam May 27, 2022

Teman, 20
Can we go even smaller?
• Dennard (IBM, 1967) patented a 1T cell
• Data is dynamically stored on Cs.
• Write and read through M1
• Read achieved through charge sharing
between Cs and CBL:
CS
V = VBL − Vpre = VBIT − Vpre
CS + CBL
• Drawbacks:
• Weak ‘1’ stored on Cs
• Charge sharing is slow, small delta
• Read is destructive. Write back is necessary

© Adam May 27, 2022

Teman, 21
 1-Transistor 1-Capacitor (1T-1C) DRAM Cell
• Standard process:
• Use polysilicon diffusion capacitance
• Expensive in area (50 fF = 50 X Abitcell)
• Popular in 70s and 80s

• Stacked Capacitor
• Make a “radiator” on top of the cell

• Trenched Capacitor
• Dig a ditch under the cell
• Fill it with conductor, insulator, conductor

22 © Adam May 27, 2022

Teman,
 Latch-Based Sense Amplifier (DRAM)
EQ
• Initialized in its meta-stable point with EQ BL BL

• Once adequate voltage gap created, V DD

sense amp enabled with SE

SE
• Positive feedback quickly forces output
to a stable operating point.

SE

23 © Adam May 27, 2022

Teman,
DRAM Architecture
• To get a 16GB DRAM DIMM (Dual-Inline Memory Module)
• DIMM has two ranks
• Each rank (64-bit I/O) has 8 chips (1 GB/chip)
• Each chip (8-bit I/O) has 8 banks (128 MB/bank)
• Each bank (1-bit I/O) is divided into 8 arrays (16 MB/array)
• Each array is divided into ~128 1024x1024 bit MATs (sub-arrays)
• So, to access DRAM:
• First provide Row Access Strobe (RAS) – 10 bits to MAT
• Readout latches rows (~128 x 1024 bits) in Sense Amps
• ~7 bits of RAS select 1024 bits into bank Row Buffer
• Then Column Access Strobe (CAS)
• Select 1-bit from Row Buffer to bank output.
Rixner,Memory Access
Scheduling. ISCA 2000 © Adam May 27, 2022
Teman,
Embedded DRAM
• DRAM requires a special (dedicated) process (Fab)
• Manufactured by only a handful of providers
(predominantly Micron, Samsung and SK Hynix)
• Is supplied on an external standalone chip.
• However, it is possible to make an on-chip “embedded” version
J.Barth, IBM
• Known as “eDRAM” SRDC 2009
• Requires special process cost-adders to fabricate
trench capacitors (IBM) or stacked MIM (Intel)
• Recent chips with L4 eDRAM
• Intel Broadwell – 128 MB
• IBM z15 SC – 960 MB

Source: Wikichip Source: AnandTech © Adam May 27, 2022

Teman,
Gain-Cell Embedded DRAM
• eDRAM is not “Logic Compatible”
• Process adders are expensive
• Not available for many processes
• Yet to be demonstrated under 14nm
• Why not go back to the old Intel DRAM?
• Use parasitic capacitance for storage node
• Manipulate current gain of read transistor
• Known as “Gain-Cell embedded DRAM”
• 2T, 3T, 4T, and others demonstrated DynOR

• Most-scaled demonstrated GC-eDRAM

• “DynOR” – 28nm FD-SOI (Giterman, TCAS-I 2017)
• “DAFNA” – 28nm (Giterman, JSSC 2018)
• “Negev” – 16nm (Giterman, SSC-L 2020) Negev DAFNA
© Adam May 27, 2022
Teman,
 1 2 3 4 5
Hierarchy ROM DRAM NVM Emerging NVM

Non-Volatile Memory (NVM)

27
Memory Volatility
• SRAM and DRAM are examples of Volatile memories
• They only store their data as long as a power source is connected
• Mask ROM and OTP are non-Volatile
• Their content is saved regardless of the state of the battery

• What about non-Volatile Read/Write Memories?

© Adam May 27, 2022

Teman,
The Floating-gate transistor (EPROM)

“as important in the development of the microcomputer

industry as the microprocessor itself.”
Gordon Moore on Dov Frohman’s EPROM
29
© Adam May 27, 2022
Teman,
Floating-Gate Transistor Programming

© Adam May 27, 2022

Teman, 30
A “Programmable-Threshold” Transistor

© Adam May 27, 2022

Teman, 31
FLOTOX EEPROM

© Adam May 27, 2022

Teman, 32
 EEPROM Cell
• Absolute threshold control is hard
• Unprogrammed transistor might be depletion

• Therefore, use a 2 transistor cell:

• Program it such that VT>VDD
• Erase it, such that VT is really low (even VT<0)

33 © Adam May 27, 2022

Teman,
Flash EEPROM

Many other options …

© Adam May 27, 2022

Teman,
Cross-sections of NVM cells

Flash EPROM
Courtesy Intel
© Adam May 27, 2022
Teman,
Two major architectures: NOR and NAND
Source: Micron

• NOR Flash • NAND Flash

• BL contact in each cell • Single BL contact
• Fast read • Slow (serial) read
• Cell size: 10F2 • Cell size: 4F2

Layout

Layout

Cross Section
Cross Section © Adam May 27, 2022
Teman,
NOR Flash Operation
• Program
• Run current through and apply vertical field
• Takes a long time (µsecs)
• Readout and see if programming successful.
• Erase
• First program all cells in block
• Then Erase entire block and verify
• Read
• Apply median voltage on the gate (e.g., 5V)
• ‘0’ State – BL will discharge
• ‘1’ State – BL will stay charged

© Adam May 27, 2022

Teman,
NAND Flash Operation
Gate

• Erase: ONO

• Source Line = 20V Word line(poly)

Gate FG
• BL=20V WL=0 Oxide
• All devices normally on
• Program (Write ‘1’): Source: Toshiba
Unit Cell
• Source Line disconnected
• BL=0V
• WLselected=20V WLunselected=5V
• Read:
• Source Line connected
• BL connected
• WLselected=0V WLunselected=5V Source line
(Diff. Layer) © Adam May 27, 2022
Teman, 38
 NAND vs. NOR
• NOR architectures are large, but fast.
• Actually, NOR is fast for READs, but slow for WRITEs and ERASEs, as they
need precise control over threshold voltages.
• NORs are used for applications such as program code storage that are read a
lot and at high speeds.
• NAND architectures are slow, but small.
• Actually, just READs are slow. Programming and Erasure are relatively fast.
• Used for video and audio file storage, where we need high density,
as well as fast write/erase times.
• NAND is about 40% smaller than NOR and generally uses Fowler Nordheim
tunneling for program and erase.

39 © Adam May 27, 2022

Teman,
Increasing Flash Density
Planar NAND Architecture

• Add levels to every bit

• MLC = Multi-level Cell
• Or perhaps go in the third dimension…

Source: Western Digital

Source: Kingston © Adam May 27, 2022
Teman,
 1 2 3 4 5
Hierarchy ROM DRAM NVM Emerging NVM

Emerging Memories
 bitcell
F2 (F-squared)
The “Universal Memory” Minimum bitcell size measured

2F
as F2, where F is the minimum 4F2

• A single memory technology with the feature size.

The smallest possible structure
2F

advantages of all existing technologies is 4F2 achieved through a crossbar

and without their limitations.
• The requirements of a Universal Memory are:
• High Density → Flash
• Scalability → SRAM
• Unlimited Retention → Flash/HDD
• High Performance → SRAM
• Unlimited endurance → SRAM/DRAM
• Process Integration → SRAM/eDRAM
• Low Power → NVM + Low Voltage

© Adam May 27, 2022

Teman,
Fundamental Circuit Elements
R v C
Four basic circuit variables:
• Voltage v(t )

• Current i (t )
i ∫ q
 i ( ) d
t
• Charge q(t )
−

 ( )
t
• Flux  (t ) v  d
−
L φ M
• The “memristor” – the missing fourth element?
L.O. Chua, “Memristor – The Missing Circuit Element,” IEEE Trans., 1971 © Adam May 27, 2022
Teman,
 The Missing Memristor Found!
• HP Labs, 2008

D.B. Strukov et al, “The missing memristor found,” Nature, 2008 © Adam May 27, 2022
Teman,
Charge vs. Resistive memories
• Charge Memory
(e.g., DRAM)
• Write data by capturing charge Q
• Read data by detecting voltage V

• Resistive Memory
(e.g., PCM, STT-MRAM, memristors)
• Write data by pulsing current dQ/dt
• Read data by detecting resistance R
• Often constructed as a resistive crossbar.

Source: Teman, et al., Wiley 2022 © Adam May 27, 2022

Teman,
Resistive Memory Array Architectures

Source: Teman, et al., Wiley 2022

> 8F2 4F2
© Adam May 27, 2022
Teman,
 Emerging Nonvolatile Memory Technologies
• PCM
• Inject current to change material phase
• Resistance determined by phase
• STT-MRAM
• Inject current to change magnet polarity
• Resistance determined by polarity
• Memristors/RRAM/ReRAM
• Inject current to change atomic structure
• Resistance determined by atom distance
• FeRAM
• Utilize the ferroelectric effect
• Resistance determined by dipole
D. Ielmini and G. Pedretti, Adv. Intell. Syst. 2000040 (2020) © Adam May 27, 2022
Teman,
Phase Change Memory (PCM)
• Chalcogenide glass (e.g., CD-ROM) exists in two states:
• Amorphous: High Resistance
• Crystalline: Low Resistance
• Advantages
• Scalable (sub 10nm)
• Dense (4F2, MLC, 3D Stacking)
• Non-Volatile
• Read/Write Performance
(between DRAM and Flash)
• Current availability:
• Intel Optane (3D Xpoint)
• STMicro, Samsung
Source: Teman, et al., Wiley 2022
© Adam May 27, 2022
Teman,
Magnetoresistance RAM (STT MRAM)
• Resistance controlled by spin across Magnetic Tunnel Junction (MTJ)
• Parallel spin state: Low Resistance
• Anti-parallel spin state: High Resistance
• Advantages
• Scalable (sub 10nm)
• Non-Volatile
• Read/Write Performance
(comparable to DRAM)
• Endurance/Retention
• Current availability:
• Everspin (1Gb, 28nm, standalone)
• eMRAM: TSMC, GF, Samsung, Intel, UMC
• Avalanche, Renesas, IBM © Adam May 27, 2022
Teman,
Spin-Transfer Orbit MRAM (SOT-MRAM)
• Decouple read and write operations of MRAM
• Higher write speeds
• Higher endurance
• SRAM Competitor
(Last-layer cache
replacement)

Source: Teman, et al., Wiley 2022 © Adam May 27, 2022

Teman,
Resistive RAM (ReRAM/RRAM)
• Change resistance by creating a conductive filament:
• Conductive Bridge (CBRAM)
• Oxygen Vacancy (OxRAM)
• Advantages
• Scalable (sub 10nm)
• Dense (4F2, MLC, 3D Stacking)
• Non-Volatile
• Read/Write Performance (between DRAM and Flash)
• Current availability:
• Adesto (now Dialog) CBRAM licensed to GF
• Cerfe Labs (ARM) CeRAM licensed from Symetrix
• eReRAM offered by TSMC, GlobalFoundries
• Mitsubishi, Fujitsu, Panasonic Winbond
• WeeBit-Nano – promising Israeli start-up
Source: Teman, et al., Wiley 2022
© Adam May 27, 2022
Teman,
Carbon-Nanotube RAM (CNT-RAM/NRAM)
• Create conductive bridge by connecting
or disconnecting stochastic arrays of
carbon nanotubes (CNTs)
• Held together by strong Van der Waals
binding forces.
• 5nm bitcell expected to have approximately
1000 switchable CNT junctions
• Also demonstrated 3D Stacking
• Commercialized by Nantero

Source: Wikichip, Nantero © Adam May 27, 2022

Teman,
 Ferroelectric Memory (FeRAM, FeFET)
• Ferroelectricity:
• A material with an electric polarization that can be
reversed by application of an external electric field.
• FRAM:
• A very old technology (invented 1952)
• Classic bitcell: PZT-based 1T-1C (130nm)
• FeFET:
• Based on ferroelectric HfO2 (discovered in 2007)
• Add HfO2 layer → 1T bitcell
• Being developed by FMC

Source: FMC © Adam May 27, 2022

Teman,
Comparison between technologies

Source: Teman, et al., Wiley 2022

© Adam May 27, 2022
Teman,
RRAM demos

© Adam May 27, 2022

Teman,
Summary

© Adam May 27, 2022

Teman,
 Further Reading
• Rabaey, et al. “Digital Integrated Circuits” (2nd Edition)
• Elad Alon, Berkeley ee141 (online)
• Weste, Harris, “CMOS VLSI Design (4th Edition)” S. Kvatinsky “Memristors: Not
Just Memory”, ChipEx 2013
• S. Kvatinsky “Emerging Non-volatile Memories: Opportunities and Challenges”,
DevelopEx 2015
• Samira Khan, U. Virginia CS6354
• Daniele Ielmini “Resistive switching memory for in-memory computing
applications”, ESSCIRC Tutorial 2020

57
© Adam May 27, 2022
Teman,