CXA2069Q

S2-Compatible 7-Input 3-Output Audio/Video Switch

Description
The CXA2069Q is a 7-input, 3-output audio/video 64 pin QFP (Plastic)
switch featuring I2C bus compatibility for TVs. This
IC has input pins that are compatible with S2
protocol.

Features
• 4 inputs that are compatible with S2 protocol
• Serial control with I2C bus
• 7 inputs, 3 outputs
Absolute Maximum Ratings (Ta=25 °C)
• The desired inputs can be selected independently
• Supply voltage VCC 12 V
for each of the 3 outputs
• Operating temperature
• Wide band video amplifier (20 MHz, –3 dB)
Topr –20 to +75 °C
• Y/C MIX circuit
• Storage temperature
• Slave address can be changed (90H/92H)
Tstg –65 to +150 °C
• Audio muting from external pin
• Allowable power dissipation
• High impedance maintained by I2C bus lines (SDA,
PD 1300 mW
SCL) even when power is OFF
• Wide audio dynamic range (3 Vrms typ.)
Operating Conditions
Supply voltage 9±0.5 V
Applications
Audio/video switch featuring I2C bus compatibility
for TVs

Structure
Bipolar silicon monolithic IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

—1—
E96Y05B81
 CXA2069Q

Block Diagram
TV 63

V1 1
53 VOUT1
V2 8 6dB
V3 15 49 YIN1
V4 22 56 YOUT1
V5 30
6dB 55 TRAP1
V6 60

58 COUT1
6dB
51 CIN1

Y1 3
10 6dB
Y2
44 V/YOUT2
Y3 17

Y4 24
6dB 46 TRAP2

47 COUT2

6dB

5 41 VOUT3
C1
12 6dB
C2

C3 19

C4 26 39 YOUT3

6dB

37 COUT3

6dB 57 VGND

BIAS 50 BIAS

42 VCC
LTV 62 6dB
35 AGND
LV1 2 52 LOUT1
LV2 9 54 ROUT1
LV3 16 0dB
6dB 43 LOUT2
LV4 23
45 ROUT2
LV5 29
38 LOUT3
LV6 59
0dB 40 ROUT3
RTV 64
RV1 4
36 DC OUT
RV2 11
33 SCL
RV3 18 6dB
34 SDA
RV4 25
32 ADR
RV5 31
RV6 7 S-1
61 6dB
14 S-2

Logic 21 S-3

28 S-4
6dB
6 S2-1

13 S2-2
Audio system is attenuated by 6dB at input,
and a total gain is 0dB (LOUT1 and ROUT1 20 S2-3
can be changed to –6dB). 6dB 27 S2-4

48 MUTE

—2—
 Pin Configuration

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

VCC
SCL

SDA

YIN1

CIN1
BIAS
52 32

MUTE
AGND

LOUT2

TRAP2
LOUT3

ROUT2
COUT3

VOUT3
ROUT3
YOUT3

COUT2
LOUT1 ADR

DC OUT

V/YOUT2
53 VOUT1 RV5 31

54 ROUT1 V5 30

55 TRAP1 LV5 29

56 YOUT1 S-4 28

57 VGND S2-4 27

—3—
58 COUT1 CXA2069Q C4 26

59 LV6 RV4 25

60 V6 Y4 24

61 RV6 LV4 23

62 LTV V4 22

63 TV S-3 21
RTV S2-3
64 20

S-1
RV3

RV1
V3

V1
C2

LV2

S2-1
Y3

Y1
S-2

RV2

V2
C3

C1
LV3

LV1
S2-2

Y2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CXA2069Q
 CXA2069Q

Pin Description
Pin Pin
Symbol Equivalent circuit Description
No. voltage
VCC
63 TV
1 V1 63
22
8 V2 1 150
30 Video signal inputs.
15 V3 4.0 V
8 Input composite video signals.
60
22 V4
15
30 V5 3µA
60 V6

VCC
3
3 Y1 Y/C separation signal inputs.
10
10 Y2 150 Input luminance signals.
17
17 Y3 4.0 V The YIN1 pin inputs the signal
24
24 Y4 obtained by Y/C separating the
49 YIN1 49 VOUT1 pin output.
3µA

VCC
5
5 C1 20k Y/C separation signal inputs.
12
12 C2 Input chrominance signals.
19
19 C3 4.5 V 150 The CIN1 pin inputs the signal
26
26 C4 obtained by Y/C separating the
27k
51 CIN1 51 VOUT1 pin output.

62 64
62, 2 LTV, LV1 VCC
2 4
9, 16 LV2, LV3
9 11 33k
23, 29 LV4, LV5
16 18
59, 64 LV6, RTV 4.5 V Audio signal inputs.
27k
4, 11 RV1, RV2 23 25
15k
18, 25 RV3, RV4 29 31

31, 61 RV5, RV6 59 61

VCC

250
VCC

53 VOUT1 Video signal outputs.

3.9 V 30k
41 VOUT3 53
Output composite video signals.
27k
41 23.5k

—4—
 CXA2069Q

Pin Pin
Symbol Equivalent circuit Description
No. voltage

VCC VCC VCC

VCC

Video signal output.

Either composite video signal output
44 V/YOUT2 3.8 V 44
or luminance signal output can be
selected by I2C bus control.

VCC VCC VCC

VCC
56 YOUT1 3.3 V

Video signal outputs.

56
Output luminance signals.
39
39 YOUT3 3.8 V

VCC VCC VCC

VCC

58 COUT1 58
Video signal outputs.
47 COUT2 4.5 V 47
Output chrominance signals.
37 COUT3 37

VCC VCC

52 LOUT1
54 52
43 LOUT2 56
38 LOUT3 45 43 Audio signal outputs.
4.5V 20k
54 ROUT1 40 38 Zo=50 Ω (within DC ±2 mA)
45 ROUT2
20k
40 ROUT3

Detects the S2-compatible DC

superimposed onto the C signal.
VCC VCC
VCC 4 : 3 video signal at 1.3 V or less
6
6 S2-1 4 : 3 letter-box signal at 1.3 V or more
13
13 S2-2 147 to 2.5 V or less
— 20
20 S2-3 16 : 9 picture squeezed signal at 2.5 V
27 S2-4 27 or more
100k
This pin is pulled down to GND by a
100 kΩ resistor, so the 4 : 3 video
signal is selected when open.
—5—
 CXA2069Q

Pin Pin
Symbol Equivalent circuit Description
No. voltage
Composite video/S selector.
5V VCC VCC The detection results are written
VCC
7 50k to the status register.
7 S-1
S signal at 3.5 V or less
14 S-2 14
— 100k 50k Composite video signal at 3.5 V
21 S-3 21
or more
28 S-4 28
This pin is pulled up to 5 V by a 100 kΩ
100k
resistor, so the composite video signal
is selected when open.

VCC
Selects the slave address
for the I2C bus.
147 72k
32 ADR — 32 90H at 1.5 V or less
92H at 2.5 V or more
28k
90H when open.

VCC

I2C bus signal input

4k
33 SCL — 33 VILmax=1.5 V
VIHmin=3.0 V
10.5k

VCC

I2C bus signal input

4k VILmax=1.5 V
34 SDA — 34
VIHmin=3.0 V
VOLmax=0.4 V

—6—
 CXA2069Q

Pin Pin
Symbol Equivalent circuit Description
No. voltage
Outputs the S2-compatible DC
superimposed onto the COUT3 output.
The DC is superimposed by connecting
this pin to the COUT3 output via a
capacitor.
VCC
Control is performed by the I2C bus.
When 0 V is output, Q1 is ON and the
4k 1k impedance is 5 kΩ.
36 DC_OUT — 36 Q1
S2 protocol output impedance of
28k 10 ±3 kΩ is realized by attaching
external resistance of 4.7 kΩ.
DC_OUT (bus) Output DC
0 4.5 V
1 0V
2 1.9 V
3 4.5 V

VCC

55 TRAP1 100
3.8 V 55 Connects trap circuit for subcarrier.
46 TRAP2
46
1k

VCC

Audio signal output mute.

147 72k Mute OFF at 1.5 V or less
48 MUTE — 48
Mute ON at 2.5 V or more
28k Mute OFF when open.

VCC
VCC VCC

20k
147 Internal reference bias (VCC/2).
50 BIAS 4.5 V 50
Connect to GND via a capacitor.
20k

—7—
 CXA2069Q

Electrical Characteristics (Ta=25 °C VCC=9 V)

Item Symbol Conditions Min. Typ. Max. Unit

Current consumption ICC No signal, no load 40 55 72 mA

Video system (Measurement circuit ; Fig. 1)

Gain GVv f=100 kHz, 0.3 Vp-p input 5.9 6.4 6.9 dB

Frequency response
FBWv1 f=100 kHz, input frequency where output 15 20 MHz
characteristics
amplitude is –3 dB with 0.3 Vp-p output
Frequency response
FBWv2 serving as 0 dB 10 15 — MHz
characteristics (Y/C mix)
f=100 kHz, maximum with
Input dynamic range Ddv 1.4 — — Vp-p
distortion < 1.0 %

Cross talk Vctv f=4.43 MHz, 1 Vp-p input — — –50 dB

Audio system (Measurement circuits ; Fig. 2 to Fig. 5)

f=1 kHz, 1 Vp-p input, 5.7 kΩ
Gain GVA –1 0 1 dB
resistor inserted to input
f=1 kHz, input frequency where output
Frequency response
FBWA amplitude is –3 dB with 1 Vp-p output 50 — — kHz
characteristics
serving as 0 dB
Total harmonic f=1 kHz, 2.2 Vp-p input, where 400 Hz
THD — 0.03 0.05 %
distortion HPF+80 kHz LPF are inserted

Input dynamic range DdA f=1 kHz, maximum with distortion < 0.3 % 2.8 3.0 — Vrms

Cross talk VctA f=1 kHz, 1 Vp-p input — –90 –80 dB

Ripple rejection ratio VctA f=100 Hz, 0.3 Vp-p applied to VCC — –55 –40 dB

Output DC offset Voff Offset voltage between input and output –30 — 30 mV

When 400 Hz HPF+30 kHz LPF

Residual noise VNA 0 20 30 µVrms
are inserted
f=1 kHz, 1 Vrms input
S/N ratio S/N –100 –90 dB
fCL=400 Hz, fCH=30kHz

—8—
 CXA2069Q

Logic system

Item Symbol Conditions Min. Typ. Max. Unit

High level
VIH 3.0 — 5.0 V
input voltage
Low level
VIL 0 — 1.5 V
input voltage
Low level
VOL With SDA 3 mA current supplied 0 — 0.4 V
output voltage
High level
IIH VIH=4.5V 0 — 10 µA
input current
Low level
IIL VIL=0.4V 0 — 10 µA
input current
Maximum clock
fSCL 0 — 100 kHz
frequency
Minimum waiting time
tBUF 4.7 — — µs
for data change
Minimum waiting time
tHD;STA 4.0 — — µs
for data transfer start
Low level clock
tLOW 4.7 — — µs
pulse width
High level clock
tHIGH 4.0 — — µs
pulse width
Minimum waiting time
tSU;STA 4.7 — — µs
for start preparation
Minimum data
tHD;DAT 300 — — ns
hold time
Minimum data
tSU;DAT 250 — — ns
preparation time

Rise time tR — — 1 µs

Fall time tF — — 300 ns

Minimum waiting time

tSU;STO 4.7 — — µs
for stop preparation

—9—
 CXA2069Q

Measurement point

V
22µ

10k
10k
10k

10k
10k

10k
10k

10k
10k
10µ

75
75
µcon

1k
0.47µ
0.1µ

10µ
10µ
10µ

10µ
10µ

10µ
10µ

10µ
10µ
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

ROUT2

SDA
MUTE

COUT3
CIN1

ROUT3
LOUT2
TRAP2

AGND
YIN1

LOUT3
VOUT3
V/YOUT2

SCL
COUT2

DC OUT
BIAS

YOUT3
VCC
10k 10µ
52 32
LOUT1 ADR
10k 10µ 1µ 600
53 VOUT1 RV5 31
10k 10µ 0.47µ 75
54 ROUT1 V5 30
1µ 600
55 TRAP1 LV5 29
10k 10µ
56 YOUT1 S-4 28

57 VGND S2-4 27
10k 10µ 0.1µ 75
58 COUT1 CXA2069Q C4 26
600 1µ 1µ 600
59 LV6 RV4 25
75 0.47µ 0.47µ 75
60 V6 Y4 24
600 1µ 1µ 600
61 RV6 LV4 23
600 1µ 0.47µ 75
62 LTV V4 22
75 0.47µ
63 TV S-3 21
600 1µ RTV S2-3
64 20
S2-1

S2-2

RV3
RV1

RV2
LV2

LV3
LV1

S-1

S-2
C2

V3
V1

C3
C1

Y3
Y1

V2

Y2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0.47µ

0.47µ

0.47µ
0.47µ

0.47µ

0.47µ
0.1µ

0.1µ
0.1µ

1µ

1µ
1µ

1µ

1µ
1µ

600

600

600
600

600

600
75

75
75

75

75
75

75

75
75

Input signal
Signal is input from one of the following pins: 1, 3, 5, 8, 10, 12, 15, 17, 19, 22, 24, 26, 30, 60 and 63.
Output signal is measured from one of the following pins: 37, 39, 41, 44, 47, 53, 56 and 58.

Fig. 1 Video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit

Measurement point

V
22µ
10k
10k
10k
10k

10k
10k
10k

10k
10k

10µ
75
75

µcon
1k
0.47µ
0.1µ

10µ
10µ
10µ
10µ

10µ
10µ
10µ

10µ
10µ

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
ROUT2

SDA
MUTE

COUT3
CIN1

ROUT3
LOUT2
TRAP2

AGND
YIN1

LOUT3
VOUT3
V/YOUT2

SCL
COUT2

DC OUT
BIAS

YOUT3
VCC

10k 10µ
52 32
LOUT1 ADR
10k 10µ 5.7k 1µ 600
53 VOUT1 RV5 31
10k 10µ 0.47µ 75
54 ROUT1 V5 30
5.7k 1µ 600
55 TRAP1 LV5 29
10k 10µ
56 YOUT1 S-4 28

57 VGND S2-4 27
10k 10µ 0.1µ 75
58 COUT1 CXA2069Q C4 26
600 1µ 5.7k 5.7k 1µ 600
59 LV6 RV4 25
75 0.47µ 0.47µ 75
60 V6 Y4 24
600 1µ 5.7k 5.7k 1µ 600
61 RV6 LV4 23
600 1µ 5.7k 0.47µ 75
62 LTV V4 22
75 0.47µ 63
TV S-3 21
600 1µ 5.7k RTV S2-3
64 20
S2-1

S2-2

RV3
RV1

RV2
LV2

LV3
LV1

S-1

S-2
C2

V3
V1

C3
C1

Y3
Y1

V2

Y2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
1µ 5.7k

1µ 5.7k

1µ 5.7k
0.47µ

0.47µ
1µ 5.7k

1µ 5.7k

0.47µ
1µ 5.7k
0.47µ

0.47µ

0.47µ
0.1µ

0.1µ
0.1µ

75

75
75

75

75
75

75

75
75

600

600

600
600

600

600

Input signal
Signal is input from one of the following pins: 2, 4, 9, 11, 16, 18, 23, 25, 29, 31, 59, 61, 62 and 64.
Output signal is measured from one of the following pins: 38, 40, 43, 45, 52 and 54.

Fig. 2 Audio system (gain, frequency response characteristics,

total harmonic distortion, input dynamic range, cross talk) measurement circuit

—10—
 CXA2069Q

Measurement point

100Hz, 0.3Vp-p

10k
10k
10k

10k
10k

10k
10k

10k
10k
10µ

75
75
µcon

1k
0.47µ
0.1µ

10µ
10µ
10µ

10µ
10µ

10µ
10µ

10µ
10µ
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

ROUT2

SDA
MUTE

COUT3
CIN1

ROUT3
LOUT2
TRAP2

AGND
YIN1

LOUT3
VOUT3
V/YOUT2

SCL
COUT2

DC OUT
BIAS

YOUT3
VCC
10k 10µ
52 32
LOUT1 ADR
10k 10µ 1µ 600
53 VOUT1 RV5 31
10k 10µ 0.47µ 75
54 ROUT1 V5 30
1µ 600
55 TRAP1 LV5 29
10k 10µ
56 YOUT1 S-4 28

57 VGND S2-4 27
10k 10µ 0.1µ 75
58 COUT1 CXA2069Q C4 26
600 1µ 1µ 600
59 LV6 RV4 25
75 0.47µ 0.47µ 75
60 V6 Y4 24
600 1µ 1µ 600
61 RV6 LV4 23
600 1µ 0.47µ 75
62 LTV V4 22
75 0.47µ
63 TV S-3 21
600 1µ RTV S2-3
64 20
S2-1

S2-2

RV3
RV1

RV2
LV2

LV3
LV1

S-1

S-2
C2

V3
V1

C3
C1

Y3
Y1

V2

Y2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0.47µ

0.47µ

0.47µ
0.47µ

0.47µ

0.47µ
0.1µ

0.1µ
0.1µ

1µ

1µ
1µ

1µ

1µ
1µ

600

600

600
600

600

600
75

75
75

75

75
75

75

75
75

A f=100Hz, 0.3Vp-p signal is applied to Vcc and the output signals from Pins 38, 40, 43, 45, 52 and 54 are measured.

Fig. 3 Audio system (ripple rejection ratio) measurement circuit

Measurement point

V
22µ
10k
10k
10k
10k

10k
10k
10k

10k
10k

10µ
75
75

µcon
1k
0.47µ
0.1µ

10µ
10µ
10µ
10µ

10µ
10µ
10µ

10µ
10µ

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
ROUT2

SDA
MUTE

COUT3
CIN1

ROUT3
LOUT2
TRAP2

AGND
YIN1

LOUT3
VOUT3
V/YOUT2

SCL
COUT2

DC OUT
BIAS

YOUT3
VCC

10k 10µ
52 32
LOUT1 ADR
10k 10µ 5.7k 1µ 600
53 VOUT1 RV5 31
10k 10µ 0.47µ 75
54 ROUT1 V5 30
5.7k 1µ 600
55 TRAP1 LV5 29
10k 10µ
56 YOUT1 S-4 28

57 VGND S2-4 27
10k 10µ 0.1µ 75
58 COUT1 CXA2069Q C4 26
600 1µ 5.7k 5.7k 1µ 600
59 LV6 RV4 25
75 0.47µ 0.47µ 75
60 V6 Y4 24
600 1µ 5.7k 5.7k 1µ 600
61 RV6 LV4 23
600 1µ 5.7k 0.47µ 75
62 LTV V4 22
75 0.47µ 63
TV S-3 21
600 1µ 5.7k RTV S2-3
64 20
S2-1

S2-2

RV3
RV1

RV2
LV2

LV3
LV1

S-1

S-2
C2

V3
V1

C3
C1

Y3
Y1

V2

Y2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
1µ 5.7k

1µ 5.7k

1µ 5.7k
0.47µ

0.47µ
1µ 5.7k

0.47µ
1µ 5.7k

1µ 5.7k
0.47µ

0.47µ

0.47µ
0.1µ

0.1µ
0.1µ

75

75
75

75

75
75

75

75
75

600

600

600
600

600

600

V
Measurement point

Fig. 4 Audio system (output DC offset voltage) measurement circuit

—11—
 CXA2069Q

40dB
Measurement point

V
10µ 4.5V 22µ

10k
10k
10k
10k

10k
10k
10k

10k
10k
75
75
µcon

1k
0.47µ
0.1µ

10µ
10µ
10µ
10µ

10µ
10µ
10µ

10µ
10µ
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

ROUT2

SDA
MUTE

COUT3
CIN1

ROUT3
LOUT2
TRAP2

AGND
YIN1

LOUT3
VOUT3
V/YOUT2

SCL
COUT2

DC OUT
BIAS

YOUT3
VCC
10k 10µ
52 32
LOUT1 ADR
10k 10µ 1µ 600
53 VOUT1 RV5 31
10k 10µ 0.47µ 75
54 ROUT1 V5 30
1µ 600
55 TRAP1 LV5 29
10k 10µ
56 YOUT1 S-4 28

57 VGND S2-4 27
10k 10µ 0.1µ 75
58 COUT1 CXA2069Q C4 26
600 1µ 1µ 600
59 LV6 RV4 25
75 0.47µ 0.47µ 75
60 V6 Y4 24
600 1µ 1µ 600
61 RV6 LV4 23
600 1µ 0.47µ 75
62 LTV V4 22
75 0.47µ
63 TV S-3 21
600 1µ RTV S2-3
64 20
S2-1

S2-2

RV3
RV1

RV2
LV2

LV3
LV1

S-1

S-2
C2

V3
V1

C3
C1

Y3
Y1

V2

Y2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0.47µ

0.47µ

0.47µ
0.47µ

0.47µ

0.47µ
0.1µ

0.1µ
0.1µ

1µ

1µ
1µ

1µ

1µ
1µ

600

600

600
600

600

600
75

75
75

75

75
75

75

75
75

Fig. 5 Audio system (residual noise) measurement circuit

—12—
 Application Circuit

• Depending on the output bias of the comb filters, pay attention to

µcon the polarities of the capacitors since the bias at Pins 49 and 51 is
VIDEO 2 output VIDEO 3 output approximately 3.1V and 4.5V, respectively.
• Connect Pin 32 to VCC when setting the slave address of the IC
to 92H.
• The audio output can be muted by setting Pin 48 to 3.5V or more.
• The TRAPs (Pins 46 and 55) are of 3.58MHz subcarrier.
COMB • The output impedance of the audio signal source must be 4.7kΩ.
22µ
FILTER 10µ • Pay attention to the polarities of the capacitors since each output
of video system and audio system has optional bias, respectively.

220

220
1k 0.1µ
0.1µ 0.47µ

620 180µ 10p

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Drive this input with low impedance

VCC
SCL

SDA

YIN1

CIN1
BIAS
52 32 to prevent cross talk for this pin.

MUTE
AGND

LOUT2

TRAP2
LOUT3

ROUT2
COUT3

VOUT3
ROUT3
YOUT3

COUT2
LOUT1 ADR 1µ

DC OUT

V/YOUT2
53 VOUT1 RV5 31
0.47µ
54 ROUT1 V5 30
10p 180µ 620 1µ
55 TRAP1 LV5 29

VIDEO 1 output
VIDEO 5 input

56 YOUT1 S-4 28
1µ
57 VGND S2-4 27
0.1µ 75
58 COUT1 CXA2069Q C4 26
1µ 1µ
59 LV6 RV4 25

—13—
0.47µ 0.47µ
60 V6 Y4 24
1µ 1µ

VIDEO 6 input
61 RV6 LV4 23
VIDEO 4 input

1µ 0.47µ
62 LTV V4 22
0.47µ
63 TV S-3 21
1µ

TV input
RTV S2-3
64 20

S-1
RV3

RV1
V3

V1
C2

LV2

S2-1
Y3

Y1
S-2

RV2

V2
C3

C1
LV3

LV1
S2-2

Y2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

1µ
1µ

1µ
1µ
1µ

1µ
0.1µ
0.1µ

0.47µ
0.47µ
0.47µ

0.47µ
0.47µ
0.47µ

0.1µ
75 75 75

75
75
75

75
75
75

470k
470k
470k

470k
470k
470k

1µ
1µ

1µ

VIDEO 1 input VIDEO 2 input VIDEO 3 input

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXA2069Q
 CXA2069Q

I2C BUS Control Signal

34 SDA
tBUF

33 SCL

tR tF
tHD;STA tLOW tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO

P S S P

Fig. 6 I2C BUS Control Signal Timing Chart

Description of Operation
The CXA2069Q is a TV I2C bus-compatible AV switch IC. The video system and the stereo audio system
both have 7 inputs and 3 outputs each. 4 of the 7 video system inputs support S2 and S protocols.
The desired inputs can be independently assigned to each output (in the audio system, the left and right
channels are processed as one unit) by I2C bus control. However, the same input is assigned to both the
video and audio system output 3.

I2C BUS Registers

1) I2C BUS
The I2C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA–serial data,
SCL–serial clock) provide control over start, stop, data transfer, synchronization, and collision
avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR
format.

SDA A A

MSB LSB MSB LSB

SCL
S P
1 2 3 4 5 6 7 8 9 1 2 9

S : Start condition ; SDA is set “Low” when SCL is “High”

P : Stop condition ; SDA is set “High” when SCL is “High”
A : Acknowledge ; signal sent from the slave

Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which
indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave∗1 IC
receives data at the rising edge of SCL and the master∗2 IC changes data at the falling edge of SCL.

∗1 Slave : An IC that is placed under the control of the master.

In a normal system, all devices excluding the central microcomputer are slaves.
∗2 Master : A central microcomputer or other controlling IC.
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 CXA2069Q

2) Control Registers
The CXA2069Q control is exercised by writing 3-byte data into the three 8-bit control registers which
control the output selector circuits for the 3 outputs.
S Slave address A DATA1 A DATA2 A DATA3 A P
S ; Start condition
A ; Acknowledge
P ; Stop condition

O Control register structure (DATA1 to DATA3)

• All registers are set to “0” during IC power on.
• “∗” indicates undefined.
b7 b6 b5 b4 b3 b2 b1 b0
Slave add. 1 0 0 1 0 0 ADR R/W
DATA1 A-GAIN S/COMP1 V-IN1 A-IN1
DATA2 V/YOUT S/COMP2 V-IN2 A-IN2
DATA3 ∗ S/COMP3 AV-IN3 DC OUT ∗

R/W (1) : Read/write mode

0 : Control data write
1 : Status register read

ADR (1) : This bit sets the slave address set by the address pin.
0 : 90H
1 : 92H

A-GAIN (1) : LOUT1/ROUT1 output gain selector

0 : 0 dB output
1 : –6 dB output

S/COMP1 to S/COMP3 (1 each) : S terminal input/composite signal input selectors

By setting S/COMP1 to “0”, when composite signal input is selected, YOUT1/COUT1 output the
inputs from YIN1/CIN1 during video 1 output.
0 : Composite signal inputs (TV, V1 to V6 inputs)
1 : S terminal inputs (Y1/C1 to Y4/C4 inputs)

V/YOUT (1) : This bit selects the output to Pin 44 (V/YOUT2).

0 : VOUT (composite signal) output
1 : YOUT (luminance signal) output

V-IN1 to V-IN2 (3 each) : These bits select the input signals output to each video output.
V-IN1 corresponds to the VOUT1 and YOUT1/COUT1 outputs, and V-IN2 to the VOUT2 and
YOUT2/COUT2 outputs.
0 : Mute 4 : Selects the V3 and Y3/C3 inputs
1 : Selects the TV input 5 : Selects the V4 and Y4/C4 inputs
2 : Selects the V1 and Y1/C1 inputs 6 : Selects the V5 input
3 : Selects the V2 and Y2/C2 inputs 7 : Selects the V6 input

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 CXA2069Q

A-IN1 to A-IN2 (3 each) : These bits select the input signals output to each audio output.
A-IN1 corresponds to the LOUT1/ROUT1 outputs, and A-IN2 to the LOUT2/ROUT2 outputs.
0 : Mute 4 : Selects the LV3/RV3 inputs
1 : Selects the LTV/RTV inputs 5 : Selects the LV4/RV4 inputs
2 : Selects the LV1/RV1 inputs 6 : Selects the LV5/RV5 inputs
3 : Selects the LV2/RV2 inputs 7 : Selects the LV6/RV6 inputs

AV-IN3 (3) : This bit selects the input signals output to output 3.
Both the video output and the audio output are selected at the same time only for AV-IN3.
0 : Mute 4 : Selects the V3, Y3/C3 and LV3/RV3 inputs
1 : Selects the TV and LTV/RTV inputs 5 : Selects the V4, Y4/C4 and LV4/RV4 inputs
2 : Selects the V1, Y1/C1 and LV1/RV1 inputs 6 : Selects the V5 and LV5/RV5 inputs
3 : Selects the V2, Y2/C2 and LV2/RV2 inputs 7 : Selects the V6 and LV6/RV6 inputs

DC OUT (2) : These bits set the DC voltage output from Pin 35 (DC OUT).
0 : 4.5 V
1:0V
2 : 1.9 V
3 : 4.5 V

3) Status Registers
• When reading two bytes
S Slave address A DATA1 A DATA2 NA P
• When reading one byte
S Slave address A DATA1 NA P
S; Start condition
A; Acknowledge
NA ; No acknowledge
P; Stop condition

When communication is to be terminated in the status register reading mode, the “no-acknowledge”
signal is needed to assure that the master does not issue the acknowledge signal to the slave.
It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after
DATA1.

O Status register structure (DATA1 to DATA2)

b7 b6 b5 b4 b3 b2 b1 b0
Slave add. 1 0 0 1 0 0 ADR 1
DATA1 S1SEL S2SEL S3SEL S4SEL S-C1 S-C2
DATA2 S1SEL S2SEL S3SEL S4SEL S-C3 S-C4

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 CXA2069Q

S1SEL to S4SEL (1 each) : S-1 to S-4 pin status S-1 to S-4 pin DC voltage S1SEL to S4SEL
0 ; S-1 to S-4 pins are not grounded. 3.5 V or more 0
1 ; S-1 to S-4 pins are grounded. 3.5 V or less 1
S1SEL to S4SEL are actually determined by
comparing the S-1 to S-4 pin DC voltages with
3.5 V.

S-C1, S-C2, S-C3, S-C4 (2 each) : S2-1, S2-2, S2-3 and S2-4 pin status
0 ; 4 : 3 video signal S2-1 to S2-4 pin DC voltage S-C1 to S-C4
1 ; 4 : 3 letter-box signal 1.3 V or less 0
2 ; 16 : 9 video squeezed signal 1.3 V or more to 2.5 V or less 1
3 ; No signal 2.5 V or more 2
S-C1 to S-C4 are actually determined by S-1 to S-4 OPEN 3
comparing the S2-1 to S2-4 pin DC voltages
with two threshold. However, when the S-1 to
S-4 pins are open, the outputs are fixed to “3”.

4) Power-on Reset
The CXA2069Q has an internal power-on reset function that sets each control register to “0” during IC
power ON.
The power-on reset VTH has hysteresis.

Power-on reset
released

Power-on reset

VCC
4.5V 5.6V

—17—
 CXA2069Q

Video system frequency response characteristics

8
TV, V1 to V6 → VOUT1 to VOUT3
Video system input/output gain [dB]

Y1 to Y4 → YOUT1 to YOUT3
C1 to C4 → COUT1 to COUT3
6

4 Y1/C1 to Y4/C4
→ VOUT1 to VOUT3

–2
100k 1M 10M 100M
Frequency [Hz]

Audio system frequency response characteristics

2
L/RTV, L/R1 to L/R6 → LOUT1 (0dB)
Audio system input/output gain [dB]

L/RTV, L/R1 to L/R6 → LOUT2 to LOUT3

0

–2

–4
L/RTV, L/R1 to L/R6 → LOUT1 (–6dB)
–6

–8
1k 10k 100k 1M
Frequency [Hz]

Audio system distortion vs. Input amplitude

10

f=1kHz
400Hz HPF, 80kHz LPF
1
Total harmonic distortion [%]

0.1
LOUT1 output (0dB gain)

LOUT2 and
0.01 LOUT 3 outputs

0.002
0 1 2 3 4
Input amplitude [Vrms]
—18—
 CXA2069Q

Package Outline Unit : mm

64PIN QFP(PLASTIC)

23.9 ± 0.4
+ 0.4 + 0.1
20.0 – 0.1 0.15 – 0.05

51 33 0.15

52 32

17.9 ± 0.4
14.0 – 0.1
+ 0.4

16.3
64 20
+ 0.2
0.1 – 0.05

1
19

0.8 ± 0.2
1.0 + 0.15 + 0.35
0.4 – 0.1 2.75 – 0.15
0° to10°
0.2 M

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM

PLATING
EIAJ CODE QFP064-P-1420 LEAD MATERIAL 42/COPPER ALLOY

JEDEC CODE PACKAGE MASS 1.5g

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