DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

VLSI DESIGN (3151105)

Name : Milan Gauswami

Enrollment No.: 210280111113

Semester: 5th

Division: B

Batch : B1
 L.D. College of Engineering, Ahmedabad

CERTIFICATE

This is to certify that Mr/Ms _________________________

Enrollment No. ______________ of B.E. (E.C.) SEM-V of
this institute (GTU Code: 028) has satisfactorily completed
the practical work of the subject VLSI (3151105) prescribed
by Gujarat Technological University during the academic
term July-2023 to December-2023. Date of Submission:
Place: L.D. College of Engineering, Ahmedabad.

Date of Submission:
Place: L.D. College of Engineering, Ahmedabad.

Internal faculty External faculty Head of department

 INDEX
Sr. Page
List of Experiment Date Signature
No No.

10

11

12

13

14

15

16

17
 Experiment: 1

Aim: Introduction to programmable devices (FPGA, CPLD), Hardware

Description Language (VHDL), and the use programming tool.

1. PLD Devices
1.1 ROM :
ROM (Read-Only Memory) is a type of computer memory that stores data that cannot be easily
modified or overwritten by normal computer operations. It is a non-volatile memory, meaning its
contents are retained even when the computer is powered off. ROM is used to store essential system
firmware, software programs, and data that should remain unchanged over time.

There are different types of ROM, such as:

1. Mask ROM (MROM): Programmed during manufacturing and cannot be changed
afterward.
2. PROM (Programmable ROM): Can be programmed by the user after purchase.
3. EPROM (Erasable Programmable ROM): Can be erased and reprogrammed using
ultraviolet light.
4. EEPROM (Electrically Erasable Programmable ROM): Can be erased and reprogrammed
electronically, often used for BIOS updates.

1.2 PLA :
A PLA, or Programmable Logic Array, is a digital electronic device used in digital circuit design. It
is a type of programmable logic device that allows you to create custom digital logic circuits by
programming the connections between its inputs and outputs.
A PLA consists of an array of programmable AND gates followed by programmable OR gates. The
AND gates take input signals and determine whether they are active or not, and the OR gates
combine these signals to generate the final output.

Here’s how it works:

1. Inputs: The input signals are fed into the programmable AND gates. These gates allow
you to specify which combinations of inputs should produce an active output.
2. Programmable Connections: You program the connections between the inputs and the
AND gates, specifying which inputs should be considered for each AND gate.
 3. Intermediate Outputs: The outputs of the AND gates are then connected to the
programmable OR gates. Again, you program the connections between the AND gates
and the OR gates to determine how the intermediate outputs are combined.
4. Final Outputs: The outputs of the OR gates represent the final outputs of the PLA. You
can program these connections to create the desired logic functions.

PLAs are versatile devices that can be configured to implement a wide range of logic functions and
combinational logic circuits. They are commonly used in digital circuit design, prototyping, and
small-scale custom logic implementations. However, with the advancement of technology, more
complex and flexible programmable logic devices like FPGAs (Field-Programmable Gate Arrays)
have largely superseded PLAs in many applications.

1.3 PAL :
Programmable Array Logic (PAL) is a type of digital logic device used in electronics and computer
hardware design. It falls under the category of programmable logic devices (PLDs). PAL devices
are designed to implement specific logic functions by allowing users to program the device to
perform desired operations.

PAL devices consist of an array of programmable AND gates followed by OR gates. Here’s how
they work:

1. AND Array : The AND array is composed of multiple input lines and programmable AND
gates. Each AND gate can have multiple inputs, which are connected to various
combinations of input signals. These input signals could come from switches, other logic
gates, or external devices.
2. OR Array : The outputs of the programmable AND gates are fed into the OR array. The OR
array combines the outputs of the AND gates using programmable connections to generate
the final output signals.

The programming of a PAL device involves setting the connections within the AND and OR arrays
to create the desired logic function. This is typically done using a hardware description language
(HDL) or a schematic entry tool provided by the manufacturer. By configuring the connections and
inputs, you can create custom logic functions that suit your specific design requirements.

1.4 CPLD :
Complex Programmable Logic Device (CPLD) is a type of programmable logic device used in
digital circuit design. It provides a higher level of complexity and flexibility compared to simpler
devices like PALs (Programmable Array Logic).
CPLDs consist of multiple blocks of programmable logic, often referred to as "microcells" or "logic
blocks." Each block contains a combination of programmable AND & OR gates, as well as flip-
flops. These blocks can be interconnected and programmed to implement complex digital logic
functions.

Here are key points about CPLDs:

1. Logic Blocks : CPLDs have multiple logic blocks, each capable of performing
combinational logic and sequential logic operations.
2. Interconnect Matrix : The logic blocks are connected through an interconnect matrix,
allowing signals to flow between different blocks and facilitating the implementation of
complex logic functions.
3. Programmability : Users program CPLDs using a hardware description language (HDL) or
design tools provided by the manufacturer. The programming configures the logic functions
and interconnections within the device.
4. Applications : CPLDs are used in various applications, including digital signal processing,
control systems, communication devices, and more. They are particularly suited for designs
that require moderate to high logic complexity.
5. Flexibility : CPLDs offer greater flexibility and capacity compared to PALs, making them
suitable for designs that require more intricate logic operations.
6. Re-configurability : CPLDs can be reprogrammed to adapt to changing design requirements,
allowing for iterative design and testing.
7. Performance : While CPLDs offer higher complexity than PALs, they are generally not as
powerful or complex as Field-Programmable Gate Arrays (FPGAs).

1.5 FPGA :
A Field-Programmable Gate Array (FPGA) is a highly configurable and programmable integrated
circuit used in digital circuit design and electronic systems. Unlike fixed-function integrated
circuits, FPGAs allow users to define their own digital logic circuits and even create custom digital
hardware.

Here are key points about FPGAs :

1. Logic Blocks : FPGAs consist of an array of programmable logic blocks, each containing
look-up tables (LUTs), flip-flops, and other elements. These logic blocks can be
interconnected and configured to perform complex digital operations.
2. Interconnect Network : The logic blocks are connected through a highly flexible
interconnect network. This network enables users to establish connections between logic
blocks to implement specific logic functions.
3. Programmability : Users program FPGAs using hardware description languages (HDLs) or
design tools provided by the FPGA manufacturer. The programming configures the logic
functions, interconnections, and behavior of the device.
4. Parallel Processing : FPGAs excel at parallel processing tasks, making them suitable for
applications that require high-speed data processing, signal processing, and real-time
operations.
5. Re-configurability : FPGAs can be reprogrammed multiple times, allowing for iterative
design and testing. This makes them valuable for prototyping and rapid development.
6. High Complexity : FPGAs offer a high level of logic complexity, making them capable of
implementing complex and intricate digital systems.
7. Custom Hardware : FPGAs enable the creation of custom digital hardware, making them
well-suited for applications where specialized processing or unique functionality is required.
 8. Application Areas : FPGAs are used in a wide range of fields, including
telecommunications, aerospace, industrial automation, image and video processing,
cryptography, and more.
9. Performance and Power Consumption : FPGAs can achieve high performance, but their
power consumption can vary based on the design and utilization of resources.

1.6 Difference between ROM, PAL, PLA, CPLD, FPGA :

Points ROM PAL PLA CPLD FPGA
ROM is a PLA is a CPLD is a FPGA is a highly
PAL is type of
nonvolatile programmable programmable configurable,
programmable
memory that logic device logic device programmable
logic device
stores data used for more used for integrated circuit
used to
Function permanently complex implementing for custom digital
implement
and can only combinational moderate to hardware design.
simple
be read. logic functions. complex
combinational
digital logic
logic functions.
functions.
ROM stores Comprises Contains both Comprises Contains an array
fixed data or programmable programmable multiple of programmable
software AND gates AND and OR blocks of logic blocks,
instructions, followed by arrays, allowing programmable interconnected
Architecture
typically fixed OR gates. more flexibility. logic, often through a
used for including flip- configurable
booting up a flops. interconnect
device. network.
ROM is not Users program Users program Users program Users program the
programmab the connections both the AND & the logic logic blocks and
le after within the AND OR arrays to blocks and interconnects to
Programm-
making ; its array to create define the logic interconnects implement custom
ability content is desired logic function. to create digital circuits.
fixed during functions. desired logic
production. functions.
Cannot be Suitable for Offers higher Offers greater Offers highest level
modified or relatively simple complexity than flexibility and of logic complexity
Modification/ reprogramm logic functions; PAL, making it capacity than and customization
Complexity ed after lacks internal suitable for PAL or PLA among the
production. registers. more intricate devices. mentioned devices.
designs.
Used for Commonly used Used for more Suitable for Widely used for a
storing for small-scale complex logic custom digital range of
firmware, logic simplification circuit design, applications,
Usage BIOS, other simplification, and custom control system including DSP,
critical data replacement of digital circuit ,moderate communication,
in electronic discrete design. complexity and complex digital
devices. components. applications. system design.

2. Introduction to HDL :
Hardware Description Language (HDL) is a specialized programming language used for designing
and describing digital logic circuits and systems. HDLs are essential tools for designing hardware at
various levels of abstraction, from simple digital gates to complex integrated circuits. They enable
engineers and designers to describe the behavior and structure of digital circuits in a human-
readable and machine-proccesable format.

Here's an introduction to HDLs:

1. Digital Logic Description : HDLs provide a way to specify the behavior and structure of
digital logic circuits. You can use HDL to describe how logic elements (gates, flip-flops,
etc.) interact and create the desired functionality.
2. Abstraction Levels : HDLs allow designers to work at different levels of abstraction, from
high-level system description down to gate-level implementation. This flexibility makes
HDLs suitable for both system architects and digital circuit designers.
3. Simulation and Verification : One of the significant advantages of HDLs is their ability to
simulate and verify designs before actual hardware implementation. Designers can simulate
their logic circuits to ensure correctness and test different scenarios.
4. Synthesis : HDL code can be synthesized into actual hardware components. Synthesis tools
analyze the HDL description and generate a netlist of gates, flip-flops, and other components
that implement the desired logic.
5. Types of HDLs : There are two main types of HDLs: VHDL (VHSIC Hardware Description
Language) and Verilog. VHDL was developed by the U.S. Department of Defense and is
known for its strict syntax and strong typing. Verilog, originally developed by Gateway
Design Automation (acquired by Cadence Design Systems), is more widely used in industry
and is known for its concise and C-like syntax.
6. Design Hierarchy : HDLs support design hierarchy, allowing designers to create modular
and reusable components. Designs can be divided into smaller blocks, making them easier to
manage and maintain.
7. Test benches : HDL designs are often accompanied by test benches, which are HDL
programs used to simulate and test the functionality of the main design. Test benches help
verify that the design behaves as intended.
8. Applications : HDLs are used in a variety of applications, including digital circuit design,
FPGA and ASIC development, system-on-chip (SoC) design, digital signal processing, and
more.

3. Difference between High level language & HDL :

Points High Level Language HDL
HLLs are designed primarily for HDLs are designed specifically for
software development, focusing on describing and modeling digital
Purpose
creating applications, algorithms, and hardware circuits and systems.
software programs.
HLLs offer a high level of abstraction, HDLs operate at a lower level of
allowing programmers to focus on the abstraction, allowing designers to
Abstraction
logic and functionality of the software specify the behavior and structure of
level
without worrying about hardware hardware components, such as gates,
details. flip-flops, and interconnections.
HLLs target the execution on general- HDLs target the design and
purpose processors, such as CPUs, to implementation of digital circuits,
Target
run applications on computers and including FPGAs, ASICs, and other
devices. digital hardware components.
Syntax HLLs have a syntax that is closer to HDLs have a syntax tailored to
human language and are easier to describing hardware components,
read and write. Examples include C, such as logic gates and sequential
C++, Java, Python, and Ruby. elements. Examples include VHDL and
 Verilog.
HLLs are used for developing a wide HDLs are used in digital design for
range of software applications, creating custom digital circuits,
Usage including desktop applications, mobile systems-on-chip (SoCs), digital signal
apps, web applications, and more. processing, and other hardware-
centric applications.
While HLLs are not inherently HDLs are specifically designed for
designed for hardware simulation, simulation and verification of
software simulators and emulators hardware designs. They allow
Simulation
are used to test and debug software designers to simulate and test the
programs. behavior of digital circuits before
actual implementation.

4. Types of HDL language:

4.1 VHDL (VHSIC Hardware Description Language) :
Origin and Purpose :
 VHDL was developed in the 1980s as part of the U.S. Department of Defense’s Very High-
Speed Integrated Circuit (VHSIC) program.
 It was designed to standardize the process of describing digital systems for both simulation
and synthesis.

Syntax and Characteristics :

 VHDL has a verbose and explicit syntax, emphasizing clarity and precision in design
descriptions.
 It uses a strong typing system, ensuring strict data type checking
 VHDL supports both structural and behavioral modeling, allowing designers to describe
how a circuit behaves as well as its physical structure.

Applications :
 Due to its rigor and thoroughness, VHDL is commonly used in safety-critical and mission-
critical applications, such as aerospace and defense.
 It is favored for projects where simulation and verification are crucial, as its explicit syntax
aids in catching potential errors.

Design Paradigm :
 VHDL encourages a structured design approach, promoting the creation of reusable and
hierarchical modules.
 Designers define entities (similar to modules) with input and output ports, and then describe
their behavior using processes, functions, and procedures.

4.2 Verilog :
Origin and Purpose :
 Verilog was developed by Gateway Design Automation (acquired by Cadence Design
Systems) in the mid-1980s.
 It aimed to simplify the process of designing and simulating digital circuits.

Syntax and Characteristics :

 Verilog has a more concise and C-like syntax compared to VHDL.
  It is known for its procedural programming capabilities, making it easier to model complex
behaviors and sequential operations.
 Verilog is often described as more intuitive for behavioral modeling due to its similarity to
programming languages like C.

Applications :
 Verilog is widely used in industry for a broad range of digital design projects, from small
circuits to complex systems-on-chip (SoCs).
 It is popular in projects where ease of use, quick development, and flexibility are important.

Design Paradigm :
 Verilog allows a mix of structural and behavioral modeling approaches. Designers can create
modules and describe behavior using procedural blocks.
 Procedural blocks in Verilog, like “always” blocks, are used to describe how signals change
over time and model sequential logic.

4.3 Comparison :
 VHDL emphasizes explicitness and precision, making it well-suited for safety-critical
applications and projects where verification is paramount.
 Verilog offers a more flexible and intuitive approach to behavioral modeling, making it
popular for a wide range of design projects.

5. Vendors and types of FPGA :

FPGAs (Field-Programmable Gate Arrays) are widely used in various industries for custom digital
hardware design, offering flexibility, re-configurability, and high-performance processing. There are
several FPGA vendors that provide a range of FPGA families and types to cater to different design
requirements.

1. Xilinx :
 FPGA Families : Xilinx offers several FPGA families, including Virtex, Kintex, Artix, and
Spartan. These families vary in terms of performance, logic capacity, and features.
 Use Cases : Xilinx FPGAs are used in a wide range of applications, including data centers,
automotive, aerospace, telecommunications, and more.
 Notable FPGA : Xilinx’s Versal ACAP (Adaptive Compute Acceleration Platform)
combines FPGA fabric with adaptable hardware engines and AI capabilities.

2. Intel (formerly Altera) :

 FPGA Families : Intel provides FPGA families like Stratix, Arria, and Cyclone. These
families cater to different performance levels and applications.
 Use Cases : Intel FPGAs find applications in networking, cloud computing, industrial
automation, and military systems.
 Notable FPGA : Intel’s Agilex FPGA family emphasizes versatility and agility for a wide
range of workloads.

3. Lattice Semiconductor :
 FPGA Families : Lattice offers FPGA families like ECP, MachXO, and iCE. These are
known for low-power consumption and are suitable for edge devices and small-scale
applications.
  Use Cases : Lattice FPGAs are used in mobile devices, consumer electronics, IoT, and
industrial control systems.
 Notable FPGA : Lattice’s CrossLink-NX FPGA family focuses on bridging and connectivity
solutions.

4. Microchip Technology (formerly Microsemi) :

 FPGA Families : Microchip provides FPGA families like SmartFusion, IGLOO, and
PolarFire. These are often used in aerospace, defense, and communication applications.
 Use Cases : Microchip FPGAs are employed in safety-critical systems, radiation-hardened
designs, and high-reliability applications.
 Notable FPGA :Microchip’s PolarFire FPGA family emphasizes low power consumption
and security features.

5. Achronix Semiconductor :
 FPGA Families : Achronix offers FPGA families like Speedster and Speedcore. Speedster
FPGAs are known for high-performance processing, while Speedcore focuses on embedding
FPGA fabric into ASICs.
 Use Cases : Achronix FPGAs are used in data centers, networking, machine learning, and
high-frequency trading.
 Notable FPGA : Achronix’s Speedster7t FPGA family is designed for high-performance
compute and AI applications.

Types of FPGA:
1. High-Performance FPGAs :
 Designed for applications that require extensive processing power, such as data centers,
scientific computing, and high-performance computing.
 Feature large logic capacity, high-speed I/O interfaces, and specialized hardware for
accelerating complex computations.

2. Low-Power FPGAs :
 Optimized for applications where power efficiency is crucial, such as portable devices, IoT
devices, and battery-powered systems.
 Focus on reducing power consumption while maintaining reasonable performance and
functionality.

3. High-Capacity FPGAs :
 Equipped with a significant number of logic cells, memory blocks, and I/O interfaces.
  Ideal for applications demanding a large amount of logic and memory resources, such as
video processing, networking, and data storage.

4. Small-Form-Factor FPGAs :
 Compact FPGAs suitable for space-constrained applications, including embedded systems,
sensor nodes, and edge devices.
 Offer a balance between resource availability and physical size.

5. Mixed-Signal FPGAs :
 Combine digital programmable logic with analog components, enabling integration of
digital and analog functionality on a single chip.
 Used in applications like sensor interfaces, data conversion, and analog signal processing.

6. DSP FPGAs :
 Optimized for digital signal processing tasks, including filtering, modulation, demodulation,
and audio processing.
 Feature specialized DSP blocks and math functions for efficient signal processing.

7. Configuration Flash FPGAs :

 Utilize non-volatile configuration memory to store FPGA configurations, allowing for
instant-on operation and secure configuration storage.
 Suitable for applications requiring quick startup and reliable configuration.

8. Reconfigurable FPGAs :
 Enable partial reconfiguration of specific portions of the FPGA while the rest of the design
remains operational.
 Useful for systems that need to adapt to changing requirements or tasks.
9. SoC FPGAs :
 Integrate FPGA fabric with embedded processors (such as ARM cores) and other system
components on a single chip.
 Enable seamless integration of custom hardware acceleration with general-purpose
processing.

10. High-Speed Connectivity FPGAs :

 Feature high-speed transceivers for implementing high-bandwidth communication interfaces
like PCIe, Ethernet, USB, and more.
 Used in applications requiring fast data transfer and communication.
 Experiment-2

Aim: Implementation of basic logic gates and its testing.

Introduction of gates:
1. AND gate:
Boolean Equation : Y = A ∙ B

Input A Input B Output Y

0 0 0
0 1 0
1 0 0
1 1 1

Verilog Code:

1. Data Flow: 2. Structural: 3. Behavioral:

module and_gate ( module and_gate ( module and_gate (
input wire in0,in1, input wire in0,in1, input wire in0,in1,
output wire out); output wire out); output reg [0:0]out);

assign out = in0 & in1; and (out,in0,in1); always @(in0,in1)

begin
endmodule endmodule if((in0 & in1) ===
1)
out <= 1;
else
out <= 0;
end

endmodule

Output Waveform:
2. OR gate:

Boolean Equation: Y = A + B

Input A Input B Output Y

0 0 0
0 1 1
1 0 1
1 1 1

Verilog Code:

1. Data Flow: 2. Structural: 3. Behavioral:

module or_gate ( module or_gate ( module or_gate (
input wire in0,in1, input wire in0,in1, input wire in0,in1,
output wire out); output wire out); output reg [0:0]out);

assign out = in0 | in1; or (out,in0,in1); always @(in0,in1)

begin
endmodule endmodule if((in0 | in1) === 0)
out <= 0;
else
out <= 1;
end

endmodule
Output Waveform:

3. NOT gate:
Boolean Equation: Y = A
he output mayalculated using the Boolean equation Y=A’.
Input A Output Y
0 1
1 0
Verilog Code:

1. Data Flow: 2. Structural: 3. Behavioral:

module not_gate (in,out); module not_gate (in,out); module not_gate (
input wire in; input wire in; input wire in,
output wire out; output wire out; output reg [0:0]out);

assign out = ~in; not (out,in); always @(in)

out <= ~in;
endmodule endmodule
endmodule

Output Waveform:

4. NOR gate:
Boolean Equation: Y = A+ B

Input A Input B Output Y

0 0 1
0 1 0
1 0 0
1 1 0

Verilog Code:

1. Data Flow: 2. Structural: 3. Behavioral:

module nor_gate ( module nor_gate ( module nor_gate (
input wire in0,in1, input wire in0,in1, input wire in0,in1,
output wire out); output wire out); output reg [0:0]out);

assign out = ~(in0 | in1); nor (out,in0,in1); always @(in0,in1)

begin
endmodule endmodule if((in0 | in1) ===
0)
out <= 1;
else
out <= 0;
end

endmodule
Output Waveform:

5. NAND gate:
Boolean Equation: Y = A ∙ B

Input A Input B Output Y

0 0 1
0 1 1
1 0 1
1 1 0

Verilog Code:

1. Data Flow: 2. Structural: 3. Behavioral:

module nand_gate ( module nand_gate ( module nand_gate (
input wire in0,in1, input wire in0,in1, input wire in0,in1,
output wire out); output wire out); output reg [0:0]out);

assign out = ~(in0 & nand (out,in0,in1); always @(in0,in1)

in1); begin
endmodule if((in0 & in1) ===
endmodule 1)
out <=0;
else
out <= 1;
end

endmodule

Output Waveform:
6. XOR gate:
Boolean Equation: Y = A Ꚛ B

Input A Input B Output Y

0 0 0
0 1 1
1 0 1
1 1 0

Verilog Code:
1. Data Flow: 2. Structural 3. Behavioral
module xor_gate ( module xor_gate ( module xor_gate (
input wire in0,in1, input wire in0,in1, input wire in0,in1,
output wire out); output wire out); output reg [0:0]out);

assign out = (in0 ^ in1); xor (out,in0,in1); always @(in0,in1)

begin
endmodule endmodule if(in0 === in1)
out <=0;
else
out <= 1;
end

endmodule

Output Waveform:

7. XNOR gate:
Boolean Equation: Y = A Ꙩ B

Input A Input B Output Y

0 0 1
0 1 0
1 0 0
1 1 1
Verilog Code:

1. Data Flow: 2. Structural 3. Behavioral

module xnor_gate ( module xnor_gate ( module xnor_gate (
input wire in0,in1, input wire in0,in1, input wire in0,in1,
output wire out); output wire out); output reg [0:0]out);

assign out = ~(in0 ^ in1); xnor (out,in0,in1); always @(in0,in1)

begin
endmodule endmodule if(in0 === in1)
out
<=1;
Output Waveform: else
out <=
0;
end
 Experiment-3
Aim: Implementation of adder and subtractors circuit & subtractor and its testing.

1. Half Adder:
Boolean Equation: S = A Ꚛ B
C=A∙B

Input A Input B Sum Carry

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Verilog Code:

Data Flow: Structural: Behavioral:

module half_adder ( module half_adder ( module half_adder (
input a,b, input a,b, input wire [0:1]in,
output s,c); output s,c); output reg [0:0] s,c);

assign s=a^b; xor(s,a,b); always @(in)

assign c=a&b; and(c,a,b); begin
case(in)
endmodule endmodule 2'b11:
begin
s<=0;
c<=1;
end
2'b10:
begin
s<=1;
c<=0;
end
2'b01:
begin
s<=1;
c<=0;
end
default:
begin
s<=0;
c<=0;
end
endcase
end
endmodule
Output Waveform:

2. full Adder :
. Boolean Equation: S = A Ꚛ B Ꚛ Cin
Cout = (A ∙ B) + Cin ∙ (A Ꚛ B)

Input A Input B Input C Sum Carry

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Verilog Code:

Data Flow: Structural:

module full_adder ( module full_adder (
input a,b,c_in, input a,b,c_in,
output s,c_out); output s,c_out,
output wire [0:2]tm);
assign s=a^(b^c_in);
assign c_out=(a&b) | xor (s,a,b,c_in);
(b&c_in) | (c_in&a); and(tm[0],a,b);
and(tm[1],c_in,b);
endmodule and(tm[2],a,c_in);
or(c_out,tm[0],tm[1],tm[2]);

endmodule
 Behavioral:
module full_adder (
input wire [0:2]in,
output reg [0:0]s,
output reg [0:0]c_out);

always @ (in)
begin
if((in===3'b001) | (in===3'b001) | (in===3'b100))
begin
s<= 1;
c_out <=0;
end
else if((in===3'b011) | (in===3'b110) | (in===3'b101))
begin
s<= 0;
c_out <=1;
end
else
begin
s<= 1;
c_out <=1;
end
end
endmodule

Output Waveform:

3. Half Subtractor:

Boolean Equation: S = A Ꚛ B
C= A∙B

Input A Input B Difference Borrow

0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Verilog Code:

Data Flow: Structural: Behavioral:

module half_sub( module half_sub( module half_sub (
input a,b, input a,b, input wire [0:2]in,
output sub,brw); output wire tm, output reg [0:0]s,
output sub,brw); output reg [0:0]b);
assign sub = a^b;
assign brw = (~a)&b; xor(sub,a,b); always @ (in)
not(tm,a); begin
endmodule and(brw,a,b); if(in[0]===in[1])
begin
endmodule s<=0;
b<=0;
end
else if(in===2'b01)
begin
s<= 1;
b<=1;
end
else
begin
s<= 1;
b<=0;
end
end
endmodule

Output Waveform:
4. Full Subtractor :
Boolean Equation: S = A Ꚛ B Ꚛ Cin , Bout = (B ∙ Bin) + (A Ꙩ B)

Input A Input B Input C Sum Carry

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Verilog code:

Data Flow: Behavioral:

module full_sub( module full_sub(
input a,b,brw_in, input wire [0:2]in,
output sub,brw_out); output reg [0:0]s,
output reg [0:0]b);
assign sub = (a^b)^brw_in; always @ (in)
assign brw_out = brw_in&(~(a^b)) | begin
(~a)&b; if ((in === 3'b001)|(in === 3'b101)|(in ===
endmodule 3'b100))
begin
s<=1;
b<=0;
end
Structural: else if (in === 3'b111) begin
module full_sub( s<=1;
input a,b,b_in, b<=1;
output wire s,b_out,tm1,tm2); end
xor(s,a,b,b_in); else begin
xor(tm1,a,b); s<=0;
and(tm2,b,b_in); b<=1;
or (b_out,tm1,tm2); end
end
endmodule endmodule

Output Waveform:
 Experiment-4
Aim: Implementation of Multiplexer & Demultiplexer and its testing.

1. MUX 4x1:
Boolean Equation: = s1’s0’D + s1’s0D +
s1s0’D + s1s0D

S0 S1 Output
0 0 Ch0
0 1 Ch1
1 0 Ch2
1 1 Ch3

Verilog Code:

Data Flow: Behavioral:

module mux_4x1( module mux_4x1(
input [1:0]sw, input wire [1:0]sw,
input [3:0]ch, input wire [3:0]ch,
output d); output reg [0:0]d);

assign d=((~sw[1]) & (~sw[0]) & always @(sw,ch)

ch[0] ) | ((~sw[1]) & sw[0] & ch[1] ) | begin
((~sw[0]) & sw[1] & ch[2] ) | (sw[1] case(sw)
& sw[0] & ch[3]); 2'b11: d<=ch[3];
2'b10: d<=ch[2];
endmodule 2'b01: d<=ch[1];
default: d<=ch[0];
endcase
end
endmodule
Structural:
module mux_4x1(
input [1:0]sw, input [3:0]ch,
output wire [1:0]sw_not,
output wire [3:0]tm,
output wire d);

not (sw_not[0],sw[0]);
not (sw_not[1],sw[1]); S0 S1 S2 Output
and(tm[0],sw_not[0],sw_not[1],ch[0]); 0 0 0 I0
and(tm[1],sw[0],sw_not[1],ch[1]); 0 0 1 I1
and(tm[2],sw_not[0],sw[1],ch[2]); 0 1 0 I2
and(tm[3],sw[0],sw[1],ch[3]);
0 1 1 I3
or(d,tm[0],tm[1],tm[2],tm[3]);
1 0 0 I4
endmodule 1 0 1 I5
1 1 0 I6
1 1 1 I7
Data Flow:
module mux_8x1(
input wire [0:7]I,
input wire [0:2]S,
Output Waveform:
output Y);

assign Y = ((~S[0]) & (~S[1]) & (~S[2]) & (I[0])) | ((~S[0]) & (~S[1]) & (S[2]) &
(I[1])) | ((~S[0]) & (S[1]) & (~S[2]) & (I[2])) | ((~S[0]) & (S[1]) & (S[2]) & (I[3])) |
((S[0]) & (~S[1]) & (~S[2]) & (I[4])) | ((S[0]) & (~S[1]) & (S[2]) & (I[5])) | ((S[0]) &
(S[1]) & (~S[2]) & (I[6])) | ((S[0]) & (S[1]) & (S[2]) & (I[7]));

endmodule

2. MUX 8x1:
Boolean Equation: Y =S1’S1’S2’I0 + S1’S1’S2’I0 +
S1’S1’S2’I0 + S1’S1’S2’I0 + S1’S1’S2’I0 +
S1’S1’S2’I0 + S1’S1’S2’I0 + S1’S1’S2’I0

S0 S1 S2 Output
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

Verilog Code:
Structural: Behavioral:
module mux_8x1( module mux_8x1(
input wire [0:7]I, input wire [2:0]sw,
input wire [0:2]S, input wire [7:0]ch,
output wire [0:7]tm, output reg [0:0]d);
output wire [0:2]S_not, always @(sw)
output Y); begin
case(sw)
not(S_not[0],S[0]); 3'b000: d=ch[0];
not(S_not[1],S[1]); 3'b001: d=ch[1];
not(S_not[2],S[2]); 3'b010: d=ch[2];
3'b011: d=ch[3];
and(tm[0],S_not[0],S_not[1],S_not[2],I[0]); 3'b100: d=ch[4];
and(tm[1],S_not[0],S_not[1],S[2],I[1]); 3'b101: d=ch[5];
and(tm[2],S_not[0],S[1],S_not[2],I[2]); 3'b110: d=ch[6];
and(tm[3],S_not[0],S_not[1],S[2],I[3]); default :
and(tm[4],S[0],S_not[1],S_not[2],I[4]); d=ch[7];
and(tm[5],S[0],S_not[1],S[2],I[5]); endcase
and(tm[6],S[0],S[1],S_not[2],I[6]); end
and(tm[7],S[0],S[1],S[2],I[7]); endmodule

or(Y,tm[0],tm[1],tm[2],tm[3],tm[4],tm[5],tm[6],tm[7]);

endmodule

Output Waveform:
4. DEMUX 1x4:
Boolean Equation: Y0=S0’S1’D, Y0=S0S1’D, Y0=S0’S1D, Y0=S0S1D

Verilog Code:

Behavioral: Data Flow:

module demux_1x4 ( module demux_1x4 (
input wire d, input d,
input wire [1:0]sw, input [1:0]sw,
output reg [3:0]out); output [3:0]out);
always @(sw,d) assign out[3] = sw[1] & sw[0] & d;
begin assign out[2] = sw[1] & (~sw[0]) & d;
case(sw) assign out[1] = (~sw[1]) & sw[0] & d;
2'b11:out[3]<=d; assign out[0] = (~sw[1]) & (~sw[0]) &
2'b10:out[2]<=d; d;
2'b01:out[1]<=d; endmodule
2'b00:out[0]<=d;
endcase
end Structural:
endmodule module demux_1x4 (
input wire d,
input wire[1:0]sw,
output wire[1:0]sw_not,
output wire [3:0]out);

not(sw_not[0],sw[0]);
not(sw_not[1],sw[1]);

and(out[0],sw_not[0],sw_not[1],d);
and(out[1],sw_not[0],sw[1],d);
and(out[2],sw[0],sw_not[1],d);
and(out[3],sw[0],sw[1],d);

endmodule
Output Waveform:
 Experiment-5
Aim: Implementation of 3 to 8 Decoder & 8 to 3 encoder and its testing.

3 to 8 Decoder:
Boolean Equation: Y0=A0’A1’A2’, Y1=A0’A1’A2, Y2=A0’A1A2’, Y3=A0’A1A2,
Y4=A0A1’A2’, Y5=A0A1’A2, Y6=A0A1A2’, Y7=A0A1A2

A A A Y Y Y Y Y Y Y Y
0 1 2 0 1 2 3 4 5 6 7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Verilog Code:

Structural: Behavioral:
module decode_3x8 ( module decode_3x8(
output wire [0:7]out, input wire [2:0]in,
input wire [0:2]in, output reg [7:0]out);
output wire [0:2]in_not);
always @(in)
not(in_not[0],in[0]); begin
not(in_not[1],in[1]); case(in)
not(in_not[2],in[2]); 3'b000: out=8'b00000001;
3'b001: out=8'b00000010;
and(out[0],in_not[0],in_not[1],in_not[2]); 3'b010: out=8'b00000100;
and(out[1],in_not[0],in_not[1],in[2]); 3'b011: out=8'b00001000;
and(out[2],in_not[0],in[1],in_not[2]); 3'b100: out=8'b00010000;
and(out[3],in_not[0],in[1],in[2]); 3'b101: out=8'b00100000;
and(out[4],in[0],in_not[1],in_not[2]); 3'b110: out=8'b01000000;
and(out[5],in[0],in_not[1],in[2]); default : out=8'b10000000;
and(out[6],in[0],in[1],in_not[2]); endcase
and(out[7],in[0],in[1],in[2]); end
endmodule
endmodule
 Data Flow:
module decode_3x8 (
output wire [0:7]out,
input wire [0:2]in);

assign out[0] = (~in[0]) & (~in[1]) &

(~in[2]);
assign out[1] = (~in[0]) & (~in[1]) &
(in[2]);
assign out[2] = (~in[0]) & (in[1]) &
(~in[2]);
assign out[3] = (~in[0]) & (in[1]) & (in[2]);
assign out[4] = (in[0]) & (~in[1]) &
(~in[2]);
assign out[5] = (in[0]) & (~in[1]) & (in[2]);
assign out[6] = (in[0]) & (in[1]) & (~in[2]);
assign out[7] = (in[0]) & (in[1]) & (in[2]);

Output Waveform:
8 to 3 Encoder:
Boolean Equation: A0 = Y0 + Y1 + Y3 + Y5 + Y, A1 = Y2 + Y3 + Y6 + Y7 , A2 = Y4 + Y5 +
Y6 + Y
Y Y1 Y2 Y Y4 Y5 Y6 Y A0 A A2
0 3 7 1
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Verilog Code:

Data Flow:
Behavioral:
module encode_8x3(
module encode_8x3(
input wire [0:7]in,
input wire [7:0]in,
output wire [0:2]out);
output reg [2:0]out);
assign out[0] = in[4] | in[5] | in[6] | in[7];
always @(in)
assign out[1] = in[2] | in[3] | in[6] | in[7];
begin
assign out[2] = in[1] | in[3] | in[5] | in[7];
case(in)
endmodule
8'b00000010: out=3'b001;
8'b00000100: out=3'b010;
8'b00001000: out=3'b011;
Structural:
8'b00010000: out=3'b100;
module encode_8x3(
8'b00100000: out=3'b101;
input wire [0:7]in,
8'b01000000: out=3'b110;
output wire [0:2]out);
8'b10000000: out=3'b111;
or(out[0],in[4],in[5],in[6],in[7]);
default : out=3'b000;
or(out[1],in[2],in[3],in[6],in[7]);
endcase
or(out[2],in[1],in[3],in[5],in[7]);
end
endmodule
endmodule

Output Waveform:
 Experiment-6

Aim: Implementation of J-K and D Flip Flops and its testing.

JK Flip-Flop :
Boolean Equation: Q = J Q' + K' QQ' = J' Q + KQ'

CLK J K Q Q’
ʃ 0 0 Q Q’
ʃ 0 1 0 0
ʃ 1 0 0 1
ʃ 1 1 T T

Verilog Code:

module jk_ff(
input j,k,rst,pst,clk,
output reg q,q_bar);
always @ (posedge clk) begin
if(rst)
q<=0;
else if (pst)
q<=1;
else begin
if(!j &&!k)
q<=q;
else if (j && !k)
q<=1;
else if (!j && k)
q<=0;
else
q<=~q;
end
q_bar <=~q;
end
endmodule
Output Waveform:

D Flip-Flop :
Boolean Equation: Q = D , Q' = D'

CL
D Q Q’
K
ʃ 0 0 1
ʃ 1 1 0

Verilog Code:
module d_ff(
input d,rst,pst,clk,
output reg q,q_bar);

always @ (posedge clk) begin

if(rst)
q<=0;
else if (pst)
q<=1;
else begin
if(d)
q<=1;
else
q<=0;
end
q_bar <= ~q;
end
endmodule

Output Waveform:
T Flip-Flop :
Boolean Equation: Q = (T Q'(t)) + (T'Q(t))

CL
T Q Q’
K
ʃ 0 0 0
ʃ 1 1 1

Verilog Code:

module t_ff(
input t,rst,pst,clk,
output reg q,q_bar);

always @ (posedge clk) begin

if(rst)begin
q<=0;
q_bar <=1;
end
else if (pst)begin
q<=1;
q_bar <=0;
end
else begin
if(t)begin
q<=q_bar;
q_bar <=~q;
end
else begin
q<=q;
q_bar <=q_bar;
end
end
end
endmodule

Output Waveform:
 Experiment-7
Aim: Implementation of sequential adder and its testing

4 Bit Adder:
Binary adders are implemented to add two binary numbers. So in order to
add two 4 bit binary numbers, we will need to use 4 full-adders. The
connection of full-adders to create binary adder circuit is discussed
in block diagram below.

In this implementation, carry of each full-adder is connected to previous

carry.
Sum_out = [(in_x) XOR (in_y)] XOR [(carry_in)]
Carry_out = [(in_x) AND (in_y)] OR [ (in_x XOR in_y) AND carry_in ]

module four_bit_adder (A,B,Sum,CarryOut);

input [3:0] A;
input [3:0] B;
output [3:0] Sum;
output CarryOut;

assign Sum = A + B;
assign CarryOut = (A[3] & B[3]) | (A[2] & B[2]) | (A[1] & B[1]) | (A[0]
& B[0]);

endmodule

Out
 Experiment-8
Aim: Implementation of BCD Counter and its testing.

BCD Counter:

Verilog Code:
CL
module bcd_counter ( Reset Count
input wire clk,rst, K
output reg [0:3]count); ʃ 0 0 0 0 0
ʃ 0 0 0 0 1
always @(posedge clk) begin ʃ 0 0 0 1 0
if (rst ===1) begin
count<=0; ʃ 0 0 0 1 1
end
ʃ 0 0 1 0 0
else begin ʃ 0 0 1 0 1
if (count ===4'b1001) begin
count <= 0; ʃ 0 0 1 1 0
end
ʃ 0 0 1 1 1
else begin
count <= count + 1'b1; ʃ 0 1 0 0 0
end
end ʃ 0 1 0 0 1
end ʃ 0 0 0 0 0
endmodule

RTL Viewer:
Output Waveform:
 Experiment-9
Aim: Implementation of two 8-bit multiplier and its testing.

8-Bit Multiplier:
Verilog Code:
module multiplier_8bit(
input wire [0:7]a,
input wire [0:7]b,
output wire [0:15]result);

assign result = a*b;

endmodule

RTL Viewer:

Output Waveform:
 Experiment-10

Aim: Simulation and verification of two input CMOS NOR gate using
SPICE.
PROGRAM:
CMOS nor
vpower vdd 0 1.8v
vgnd vss 0 0

* element description
M1 Vout Vin1 vss 0 CMOSN w=5u l=.18u
M2 3 Vin2 vdd vdd CMOSP w=2.5u l=.18u
M3 Vout Vin2 vss 0 CMOSN w=5u l=.18u
M4 Vout Vin1 3 vdd CMOSP w=2.5u l=.18u
CL Vout vss 0.1p

*voltage supply

*VDD 3 0 2v
Vpul1 Vin1 0 pulse(0 1.8 10n 1n 1n 20n 60n)
Vpul2 Vin2 0 pulse(0 1.8 0n 1n 1n 15n 60n)

*model files
.include modelcard.pmos
.include modelcard.nmos

*analysis type

.tran 0 40n 1n

*output performance

.control
run
set color0= white
set xbrushwidth = 2
plot Vout Vin1 Vin2

.endc
 Experiment-11

Aim: Simulation of CMOS Inverter using SPICE for transfer

characteristic.

PROGRAMl:

*CMOS inverter
* element description
M1 2 1 0 0 CMOSN w=5u l=.18u
M2 2 1 3 3 CMOSP w=2.5u l=.18u
CL 2 0 0.1p

*voltage supply
VDD 3 0 2v
Vpul 1 0 pulse(0 2 0n 1n 1n 10n 20n)

*model files
.include modelcard.pmos
.include modelcard.nmos

*analysis type
.dc vpul 0 2 .1
.tran 1 40n 1n

* output performance
.control run
plot v(2) v(1)
.endc

SPICE WINDOW OUTPUT:

 Experiment-12
Aim: To generate layout of for CMOS Inverter circuit and simulate it for verification.

CMOS Inverter Layout:

CMOS Inverter Waveform:

 Experiment-13
Aim: To generate layout of for CMOS NAND circuit and simulate it for verification.

CMOS NAND Layout:

CMOS NAND Waveform:
 Experiment-14
Aim: To generate layout of for CMOS NOR circuit and simulate it for verification.

CMOS NOR Layout:

CMOS NOR Waveform:

 Experiment-15
Aim: To generate layout of for CMOS Comparator circuit and simulate it for
verification.

CMOS Comparator Layout:

CMOS Comparator Waveform:

 Experiment-16

Aim: Layout Design of Boolean Function.