‘Scanned with CamScannerDebugging Means to look for any errors in a program or on circuit board Static Debugging: Similar to visual inspection of a circuit board; it is the paper- and-pencil check of a flowchart and machine code. Dynamic Debugging: Involves observing the output, or register contents, following the execution of each instruction (the single-step technique) or of a group of instructions (the breakpoint technique). Dynamic Debugging Techniques: + Single Step + Register Examine + Breakpoint ‘Sanned wih CamScannerThe single step key on a keyboard allows you to execute one instruction at a time, and to observe the results following each instruction. As you push the single step key, you will be able to observe addresses and codes as they are executed. With the single step technique you will be able to spot Incorrect Addresses, Incorrect jump locations for loops, Incorrect data or missing codes. ‘Scanned wih CamScanner‘Scanned with CamScannerBreakpoint: It is generally a software routine that allows you to execute a program in sections. The breakpoint can be set up in your program by using RST instructions. When you push the Execute Key ‘your program will be executed until the breakpoint, where the monitor takes over again. The registers can be examined for expected results. If the segment of the program is found satisfactory, a second breakpoint can be set up at a subsequent memory address to debug the next segment of the program. With the breakpoint facility you can isolate the segment of the program with errors. Then that segment of the program can be debugged with the single step facility. ‘Scanned wih CamScanner| Stops to design a software Counter: +A counter is designed simply by loading an appropriate number into one of the registers and using the INR (Inerement by one) or the DCR (Decrement by One) instructions A loop |9 established to update the count, and each count |S. checked to determine whether it has reached the final number; If not, the loop Is repeated. ‘Scanned wih Canc‘Scanned with CamScannerSystem Clock period T= : Where fis the system clock frequency and is equal to 3 MHz With 3 MHz system clock frequency the clock period T is calculated as: Te Foe = 0.33 ns Thus time delay in a loop is calculated as TiX(Tx Loop Tstates x N\o) = (0.83 x 10°F x 15.*255) Maximum delay using single register is 1282 jes oF 12 msec = 1262.25 ps = L2ms ‘Scanned wih CansScanner‘Scanned with CamScanner‘Scanned with CamScanner‘Scanned with CamScannerCounters and Time Delays “Counters are used primarily to keep track of events, while time delays are important in setting up accurate timing between two events of designing counters and time delays {ruction is far more flexible and less an the design process using Scanned wih CanScannerPeripheral or Direct /0 #1f peripheral /O MPU Uses 06 address lines to send the addresses of an /O device, These 08 address lines are dapable of identifying 266 Input devices and 266 ouput devices, Thus, in this teathod, /O addresses fange is from 00h to PPh, These addresses are knew as alther VO device addresses or 1/0 port numbers ui and oulpul deviegs are differentiated by the control signals wie Instructions (IN and OUT) are Used for data Scanned wih CanScanner‘Seanned with CanSeannerMemory-Mapped /0 uu 16 addres ‘Scanned with GamScenner‘Scanned with CamScannerInput/Output (V0) 1. Peripheral (or Direct) /O 2, Memory-Mapped /0 methods differ from each c 4, Number of address lines used in identifying an /0 device 2. Type of control signal used to enable the device ns used for data transfer ‘Scanned wih CamScanner‘Scanned with GamScanner‘Scanned with CamScanner‘Scanned with CamScanner‘Scanned with CamScannerScanned wih CanScanner‘Scanned with GamScannerScanned wih CanScannerMultiplexing + In the previous example, one output port and seven data lines was — required to display one hex digit. ! | *To display several digits with this technique, additional hardware is required in proportion to the number of digits to be displayed - which can be costly. * The number of hardware chips needed for multiple-digit display can be minimized by using the technique called multiplexing whereby the data lines and output po ‘ y various seven segment LEDs. The basic circuit for multiplexed display is shown below: ‘Seanned with CanSeannerThe code of the first digit to be displayed at LED1 is sent on the data lines by outputting to port The corresponding seven segment LED is turned on by sending a bit to the cathode through port B. Next LED 2 is turned on and LED 1 is turned off. Each seven segment LED is tumed on and sequentially. The cycle is repeated fast enough that the display appears stable. =e — Scqmen Daves Daw Da —\Y Outpat Bas Pot ‘Seanned wih CanSeanner| Program: Seven Segment Display with Multiplexing | START: MVIB, 01H MVIC, 04H LXIH, CODES NEXT: MOV A, M OUT F6H MOVA,B OUT F5H INXH RLC MOV B,A DCR C JNZ NEXT JMP START ‘Scanned with GamScanner‘Scanned with CamScanner‘Scanned with CamScannerThe code of the first digit to be displayed at LED1 is sent on the data lines by outputting to port The corresponding seven segment LED is turned on by sending a bit to the cathode through port B. Next LED 2 is turned on and LED 1 is turned off. Each seven segment LED is tumed on and sequentially. The cycle is repeated fast enough that the display appears stable. =e — Scqmen Daves Daw Da —\Y Outpat Bas Pot ‘Seanned wih CanSeanner| Program: Seven Segment Display with Multiplexing | START: MVIB, 01H MVIC, 04H LXIH, CODES NEXT: MOV A, M OUT F6H MOVA,B OUT F5H INXH RLC MOV B,A DCR C JNZ NEXT JMP START ‘Scanned with GamScanner‘Scanned with CamScanner‘Scanned with CamScanner‘Scanned with CamScannerProgram: KEYBOARD SUBROUTINE PUSH H INFTH RAR PUSH B ANI OFH JNC XRAA CPI OFH sig . perc MOV LA JZ JNZ OUT FSH CALL DBONCE MOVAH IN F7H MVIA,7FH DCRB ANIOFH MVIB, O4H JNZ CPI OFH RLC JM x MOV AL INZ MOVH,A rs CALL DBONCE OUT FSH OPH INFTH RET ‘Scanned wih CansScannerSi 3 is it tep 2: When the microprocessor is executing a program, it checks the INTR during the execution of each instruction. If the line INTR is high and the interrupt is enabled, the microprocessor completes the n, disable the interrupt enable flip-flop and sends @ signal called INTA Interrupt request until the interrupt flip- Step 3 current instructior ‘Acknowledge (active low). The processor cannot accept any interrupt flop is enabled again. in instruction, preferably, @ restart (RST) instruction, a t-byte call instruction that transfers the e OOH and restarts the execution at that signal INTA is used to insert a nal hardware. The RST instru ion on pag Step 4: The through additior program control memory location after executing Step 5. es the memory addi Step 5 If the microprocessor receil “ location. instruction on the stack. The progral iction is to a specific memory locatic ress of the next ‘Seannad with Can'Seanner‘Scanned with CamScannerPROBLEM STATEMENT MAIN PROGRAM: e Service Routine FLASH OUTPORT! 2000h LXI SP, XX99H El 2070 PUSH B MVC, 01H PUSH PSW 7 MVIA, OOH MVIB, OAH CALL DELAY OUT PORT! MVIA, OOH MVIC, 01H ’ ee CALL DELAY ae INRA INZ FLAS JMP NXTON PoP PSW PoP B amp . RET ‘Seanned with CanSeanner‘Scanned wth CamScannerDISCRIPTION OF THE INTERRUPT PROCESS it it it. The ram will * in conic} fom Ort PH wits dey ane second belweon eae oo 2. To interrupt the processor, push the switch. The INT line goes high. 3. Assuming the switch is pushed when the Processor is executing the instruction OUT at memory location XXO6H, the following ‘sequence of events occurs. a. The microprocessor completes the execution of the instruction OUT, . It'senses that the line INT is high, and that the interrupt is enabled. ¢. The microprocessor disables the interrupt, stops execution, and sends out a control signal INTA (Interrupt Acknowledge). 4. The INTA (active low) enables the tri-state buffer, and the instruction EFH is placed on the data bus. ‘Or saves the addres i at locations 98H a ee ra } instruction (MVI C, 01H) on the stack nd 97H, and t n locations 0028-29-2AH sh hee rated fansterred to memory location 0028H. The \othe ae re ould have the following jum instruction to transfer the Program JMP- XX70! Scanned wih CanScanner4. The program jump to the service routine at XX70H. 5. The service routine saves the registers which are being used in the and loads the count ten in register B to output five flashes and also five 6. The service routine enable the interrupt before returning to the main 7. When the service routine executes the RET instruction, the retrieves the memory address XXO8H from the top of the stack and binary continuing. TESTING INTERRUPT ON A SINGLE-BOARD COMPUTER SYSTEM Step 3e in the above description assumes that you are ling the system have access to location EPROM or ROM on 00H. In /, you have no | access to restarts locations if the system has already been designed. Then how _ you transfer the program control from a restart location to the service routine? In single-board microcomputer are usually reserved users, and the system design at a restarts location jump somewhere in R/W memory. ‘Scanned wih CanScannerFor examples, in Intel's SDK-85 system, R/W memory begins at page 20H, and you find the following instruction in the monitor program at memory location 0028H: 0028 JMP 20C2H If instruction RST 5 is inserted, it transfer the program to location 0028H, and the monitor transfer the program from 002BH to location 20C2H To implement the interrupt shown in figure 20C2 C3 JMP SERV 20C3 70 204 20 This instruction will be transfer the program to the service routine located at 2070H. THE 8085 INTERRUPTS The 8085 has five interrupt inputs. One is called INTR, which is identical with the INT input in the 8080A. The other four are automatically vectored (transferred) to specific location on memory page 00H without any external “> ‘Scanned wih CansScanner4, TRAP O024H 2 RSTTS 003CH 3, ROTOS 0034H 4, RST 8S 002CH TRAP * \\\s a non-maskable interrupt known as NMI a8 the highest priority; i\ need not be enabled: and it cannot be disabled, * Ne \evel and edge sensitive, mearing that the input Should go high and stay high to be acknowledge oa again until it makes a * a transition from high to low to high Nol be acknowled RST 15,68, and 55 Theve are the maskable interrupts and these ar EL (Enable | N) Tuph Mask) bled under program control with two instructions: ‘Seanned with CanSeannerinstructon SIM Set interrupt Mask: This is a 1-byte instruction. J This instructon reads the contents of the accumulator and enable or disables the interrupts ‘according to the contents of the accumulator. (2 Bits D- and D, of the accumulator are used for serial VO and do not effect the interrupt D, = 1 enables the senal VO. Bit D, is a control bit and should = 1, in order for bits D,..D, and D, to be effective Logic 0) and D, wil enable the corresponding interrupts. and logic | will disable the: 1 Bits 0, is additional control for the RST 7.5 .IfD, = 1, the RST 7.5 fip-op is reset. This is overnde RST 7 5 without senncing it ‘Scanned wih CanScannerInstruction SIM: Set Interrupt Mask: This is a 1-byte instruction. Q This instruction reads the contents of the accumulator and enable or disables the interrupts according to the contents of the accumulator. Q Bits D, and D, of the accumulator are used for serial |/O and do not effect the interrupt D, = 1 enables the serial 1/0. Q Bit D; is a control bit and should = 1, in order for bits D),D, and D, to be effective Logic 0 in Dy and D, will enable the corresponding interrupts, and logic 1 will disable the interrupts. Q Bits D, is additional control for the RST 7.5 . If D, = 1, the RST 7.5 flip-flop is reset. This is override RST 7.5 without servicing it o% RST7.S MASK IE RST6.5 MASK © = available RSTS.5 MASK SV masked 1f 0, bits 0-2 ignorgy “enn Te Mop 1s reset OFF Ignored If 1, bit 7 is output to Serial Output Data Latch ‘Scanned wih CamScanner‘Scanned with CamScannerINSTRUCTION RIM: Read Interrupt Mask: This is a 1-byte instruction. OThis instruction load the accumulator with eight bits indicating the current status of the interrupt mask, the interrupt enable, pending interrupts, and serial input data. The RIM instruction loads the accumulator with the following information: Ciets] Ts [:[ Je] Tao fms [es ss] [wr] wos] Mss CA 1 L | el Interrupt Enable Flag 1 = enabled - Pending Interrupts: | pending - io ‘Scanned wih CanScanner‘Scanned with CamScannerIAA] ure paw] ppqrunueutorg pvisonys = ~ ~ — viva Scanned with CamScanner‘Scanned with CamScannerDATA OU PTT ae PANDSTARE ‘Scanned wih CanScannerDATA OUTPUT WITH HANDSHAKE Si The MPU writes a byte into the output port of the programmable device by sending control signal WR. St The device informs the peripheral, by sending handshake signal OBF (Output Buffer Full), that a byte is on the way. The peripheral acknowledges the byte by sending back the ACK (Acknowledge) signal to the device. The device interrupts the MPU to ask for the next byte, or the MPU finds out that the byte has been acknowledge through the status check. ‘Scanned wih CanScannerEE > The 8255 has 24 VO pins that can be grouped primarily in two 8-bits parallel ports + Port A and Port B, with the remaining eight bits as Port C + The eight bits of port C can be used as individual bits or grouped in two 4-bits ports: Copper and Crowen > The functions of these ports are defined by writing a control word in the control register. ‘Seanned with CanSeannerDATA OU PTT ae PANDSTARE ‘Scanned wih CanScannerDATA OUTPUT WITH HANDSHAKE Si The MPU writes a byte into the output port of the programmable device by sending control signal WR. St The device informs the peripheral, by sending handshake signal OBF (Output Buffer Full), that a byte is on the way. The peripheral acknowledges the byte by sending back the ACK (Acknowledge) signal to the device. The device interrupts the MPU to ask for the next byte, or the MPU finds out that the byte has been acknowledge through the status check. ‘Scanned wih CanScannerEE > The 8255 has 24 VO pins that can be grouped primarily in two 8-bits parallel ports + Port A and Port B, with the remaining eight bits as Port C + The eight bits of port C can be used as individual bits or grouped in two 4-bits ports: Copper and Crowen > The functions of these ports are defined by writing a control word in the control register. ‘Seanned with CanSeanner‘Scanned with CamScanner‘Scanned wih CamScanneri || A ma arCONTROL REGISTER® >The contents of the control register called a control word, specify an VO function for each port. This register is not accessible for READ operation. »Bit D, of the control register specifies either the /O function or the bit set/reset function, If bit D,=1, D,- Dp determine /O functions in various modes as in figure, If bit D,=0, Port C operates in the BSR mode. The BSR mode control does not affect the func SIAN REARDS ‘Scanned wih CanScanner‘Seanned wih CanSeannerMode 0: Simple input or output ‘Scanned with CamScanner‘Scanned with CamScanner‘Scanned wih CanScannerEs Write 8085 ALP for interfacing between 8085 and 8255 in mode 0. Here P, and P, are holding two 8-bit values, take the nos. from P, and P, , add them and send the result to Po MVIA, 92H OUT 83H IN 80H MOV B,A IN 81H ADD B OUT 82H ‘Seanned wih CanSeanner‘Scanned with CamScannerThe BSR mode is concerned only with the eight bits of ports C, which can be set or reset by writing an appropriate control word in the control register. A control word with bit D-=0 is recognized as a BSR control word, and it does not alter any previously transmitted control word with | bit D-=1 ; thus the VO operations of ports A and B are not affected bya | BSR control word, individual bits of port C can be used for applications uch as an on/off switch. ‘Scanned wih CansScanner oThis control word, when written in the control register, sets or reset one bit at a time, as specified in figure. Generally Set = 0 TH = Bu7 ‘Seanned with CanSeannerWrite a BSR control word subroutine to set bits PC7 and PC3 and reset them after 10ms. MVIA, OFH OUT 83H MVIA, 07H OUT 83H CALL DELAY MVIA, 06H OUT 83H MVIA, OEH OUT 83H RET ‘Seanned with CanSeannerIn mode 1, handshake signals are exchanged between the MPU and peripherals prior to data transfer. The features of this mode include the following : 1. Two ports (A and B) function as 8-bit I/O ports. They can be configured either as input or output ports, 2. Each port uses three line from port C as handshake signals. The remaining two lines of port C can be used for simple I/O functions. 3. Input and output data are latched. 4. Interrupt logic is supported ‘Seanned wih CanSeanner‘Scanned wih CanScannereee The functions of input contro! signals are follows: Qs i This signal (active low) is generated by a peripheral device to indicate thal ft has transmitted a byte of data. The 8255A, in response to STR, generates IBF and INTR Oipr ull) This signal is an acknowledgement by the 8255A to indicate that the: has received the data byte. This is reset when the MPU reads the data. QINTR(! 1) This Is an output signal that may be used to interrupt the MPU. \s generated it ST, IBF, and INTE (Internal flip-top) are all at logic 1. This is reset by the falling | of the RD signals, QIN E ) This is an internal fip-fop used to enable of disable the generation of the INTR signal The two flipflops INTE, and INT are sevreset Using the BSR mode, The INTE, 1s enabled and disabled through PC,, and INTE, is enabled or disabled through PC, ‘Scanned wih CanScanner‘Scanned wih CanScanner‘Scanned with CamScanner| ooo alo i the ineracing uti ————— Shown below is the interfacing using 8255 in mode 1, Port A is designed as the input port for a keyboard with interrupt /O, and port B is designedas the output port for a printer with status check /O. a) Find port addresses by analysing the decode logic. (b) Determine the control word (c) Determine the BSR to enable INTE, (4) Determine the masking byte to verity the OBFs line in the status check VO (e) intialization instructions, interrupt service subroutine and printer subroutine to output the characters that are in memory. ‘Scanned wih CanScanner‘Scanned with CanSeannerMode 2 and Made 0 (lmputi ‘Mode 2 and Mode | (Output) [EXE ‘Scanned wih CanScanner‘Scanned with CamScanner| ooo alo i the ineracing uti ————— Shown below is the interfacing using 8255 in mode 1, Port A is designed as the input port for a keyboard with interrupt /O, and port B is designedas the output port for a printer with status check /O. a) Find port addresses by analysing the decode logic. (b) Determine the control word (c) Determine the BSR to enable INTE, (4) Determine the masking byte to verity the OBFs line in the status check VO (e) intialization instructions, interrupt service subroutine and printer subroutine to output the characters that are in memory. ‘Scanned wih CanScanner‘Scanned with CanSeannerMode 2 and Made 0 (lmputi ‘Mode 2 and Mode | (Output) [EXE ‘Scanned wih CanScanner‘Scanned wih CanScanner'8253/8254 is functionally similarto the software designed counters and timers. It generates accurate time delays land can be used for applications such as real-time clock, an event counter, a digital one shot, a square wave |generator, a complex waveform generator. + The 8253/8254 includes 03 identical 16-bit counters that can operate independently in any one of six modes and each counter is capable of handling clock inputs up to 0-10 MHz (8254)/0-2.6 MHz (8253). r itis a 24-pin IC and requires +5 V power supply. To operate a counter, a 16-bit count is loaded in its register and on command it begins to decrement the count until it reaches 0. At the end of the count, it generates a pulse that can be used to interrupt the MPU. The counter can count either in binary or BCD. In addition, a count can be read by the MPU while the counter is decrementing. 8254 has a powerful command called RE ws the user to check the count value, the programmed mode, the current mode, inter. 8253 has no such command. ‘Seanned with CanSeanner