Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-1

LECTURE 350 – LOW VOLTAGE OP AMPS

(READING: AH – 415-432)
Objective
The objective of this presentation is:
1.) How to design standard circuit blocks with reduced power supply voltage
2.) Introduce new methods of designing low voltage circuits
Outline
• Low voltage input stages
• Low voltage bias circuits
• Low voltage op amps
• Examples
• Summary

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-2

Introduction
While low voltage op amps can be easily designed in weak inversion, strong
inversion leads to higher performance and is the focus of this section.
Semiconductor Industry Associates Roadmap for Power Supplies:
Feature Size
0.35µm 0.25µm 0.18µm 0.13µm 0.10µm 0.07µm

3.0V
Power Supply Voltage

2.5V

2.0V
Desktop Systems
1.5V

Single
1.0V
Cell
Portable Systems Voltage
1995 1998 2001 2004 2007 2010
Year Fig. 7.6-2

Threshold voltages will remain about 0.5 to 0.7V in order to allow the MOSFET to be
turned off.
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-3

Implications of Low-Voltage, Strong-Inversion Operation

• Reduced power supply means decreased dynamic range
• Nonlinearity will increase because the transistor is working close to VDS(sat)
• Large values of λ because the transistor is working close to VDS(sat)
• Increased drain-bulk and source-bulk capacitances because they are less reverse biased.
• Large values of currents and W/L ratios to get high transconductance
• Small values of currents and large values of W/L will give smallVDS(sat)
• Severely reduced input common mode range
• Switches will require charge pumps

Approach
• Low voltage input stages with reasonable ICMR
• Low voltage bias and load circuits
• Low voltage op amps

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-4

Differential Amplifier with Current Source Loads

VDD
+
Minimum power supply (ICMR = 0): VBias
VDD(min) = VSD3(sat)-VT1+VGS1+VDS5(sat) VSD3(sat) -
= VSD3(sat)+VDS1(sat)+VDS5(sat) M3 M4

-VT1
Input common-mode range: vicm M1 M2
Vicm(upper) = VDD - VSD3(sat) + VT1 VGS1

Vicm(lower) = VDS5(sat) + VGS1

VDS5(sat) +
VBias M5
-
Fig. 7.6-3
Example:
If the threshold magnitudes are 0.7V, VDD = 1.5V and the saturation voltages are
0.3V, then
Vicm(upper) = 1.5 - 0.3 + 0.7 = 1.9V and Vicm(lower) = 0.3 + 1.0 = 1.3V
giving an ICMR of 0.6V.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-5

VDD
Increasing ICMR using Parallel Input Stages
Turn-on voltage for the n-channel input: M6 MN3 MP5
MN4

Vonn = VDSN5(sat) + VGSN1

Vicm Vicm
Turn-on voltage for the p-channel input: IBias MP1 MP2
MN1 MN2
Vonp = VDD - VSDP5(sat) - VSGP1
The sum of Vonn and Vonp equals the minimum
M7 MP4
power supply. MP3 MN5
Fig. 7.6-4
Regions of operation:
VDD > Vicm > Vonp: (n-channel on and p-channel off) gm(eq) = gmN
Vonp ≥ Vicm ≥ Vonn: (n-channel on and p-channel on) gm(eq) = gmN + gmP
Vonn > Vicm > 0 : (n-channel off and p-channel on) gm(eq) = gmP
where gm(eq) is the equivalent input transconductance of the above input stage, gmN is
the input transconductance for the n-channel input and gmP is the input transconduct-
ance for the p-channel gm(eff)
input. gmN+gmP

gmP gmN
n-channel off Vonn n-channel on Vonp n-channel on
p-channel on p-channel on p-channel off
Vicm
0 VSDP5(sat)+VGSN1 VDD-VSDP5(sat)+VGSN1 VDD Fig. 7.6-5

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-6

Removing the Nonlinearity in Transconductances as a Function of ICMR

Increase the bias current in the different- VDD
3:1
ial amplifier that is on when the other Ib
differential amplifier is off.
Inn Ip
Three regions of operation depending on VB2 Vicm MP1 MP2 Vicm VB1
the value of Vicm: MB2 MB1
MN1 MN2
1.) Vicm < Vonn: n-channel diff. amp.
off and p-channel on with Ip = 4Ib: Ipp
In
K P ’W P
gm(eff) = LP 2 Ib Ib
1:3
2.) Vonn < Vicm < Vonp: both on with Fig. 7.6-6

In = Ip = Ib :
K N ’W N K P ’W P
gm(eff) = LN Ib + LP Ib
3.) Vicm > Vonp: p-channel diff. amp. off and n-channel on with In = 4Ib:
K N ’W N
gm(eff) = LN 2 Ib

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-7

How Does the Current Compensation Work?

Set VB1 = Vonn and VB2 = Vonp.
VDD
If vicm <Vonp then Ip = Ib and Inn=0
Ib
vicm vicm If vicm >Vonp then Ip = 0 and Inn=Ib
MB1
Inn Ip
MN1 MN2
Vonn
In Ipp vicm MP1 MP2 v
icm
MB2
If vicm >Vonn then In = Ib and Ipp=0
Ib Vonp
If vicm <Vonn then In = 0 and Ipp=Ib
Fig. 7.6-6A
Result:
gm(eff)

gmN=gmP

0 Vicm
0 Vonn Vonp VDD Fig. 7.6-7
The above techniques and many similar ones are good for power supply values down to
about 1.5V. Below than, different techniques must be used or the technology must be
modified (natural devices).
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-8

;;
Bulk-Driven MOSFET
A depletion device would permit large ICMR even with very small power supply voltages
because VGS is zero or negative.
When a MOSFET is driven from the bulk with the gate held constant, it acts like a

;;
depletion transistor.
Cross-section of an n-channel vBS VDD

;;
;;;;;
;; ;; ;;
VDS VGS
bulk-driven MOSFET:

;;;;;;
Bulk Drain Gate Source Substrate

;;
;;;;;
;;
Channel
p+ n+ n+ n+
QP
Depletion p-well
Region QV

n substrate
Large signal equation: Fig. 7.6-8

K N’W
iD = 2L VGS - VT0 - γ 2|φF| - vBS + γ 2|φF|2
Small-signal transconductance:
γ (2KN’W/L)ID
gmbs = 2 2|φ | - V
F BS
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-9

Bulk-Driven MOSFET - Continued

Transconductance characteristics: 2000
Bulk-source driven

Drain Current (µA)

1500

Saturation: VDS > VBS – VP gives, 1000

VBS = VP + VON
500


VBS2 IDSS
Gate-source
iD = IDSS 1 - VP  driven
 
Comments: 0
-3 -2 -1 0 1 2 3
• gm (bulk) > gm(gate) if VBS > 0 Gate-Source or Bulk-Source Voltage (Volts) Fig. 7.6-9

(forward biased )
• Noise of both configurations are the same (any differences comes from the gate versus
bulk noise)
• Bulk-driven MOSFET tends to be more linear at lower currents than the gate-driven
MOSFET
• Very useful for generation of IDSS floating current sources.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-10

Bulk-Driven, n-channel Differential Amplifier

What is the ICMR?
Vicm(min) = VSS + VDS5(sat) + VBS1 = VSS + VDS5(sat) - |VP1| + VDS1(sat)
Note that Vicm can be less than VSS if |VP1| > VDS5(sat) + VDS1(sat)
Vicm(max) = ?
As Vicm increases, the current through VDD
M1 and M2 is constant so the source M3 M4
increases. However, the gate voltage stays M7
constant so that VGS1 decreases. Since
the current must remain constant through
M1 and M2 because of M5, the bulk- vi1 vi2
IBias
source voltage becomes less negative + + +
causing VTN1 to decrease and maintain VBS1 M1VGS- M2VBS2
- -
the currents through M1 and M2 constant.
If Vicm is increased sufficiently, the bulk- M5
M6
source voltage will become positive.
However, current does not start to flow
until VBS is greater than 0.3 volts so the VSS Fig. 7.6-10
effective Vicm(max) is
Vicm(max) ≈ VDD - VSD3(sat) - VDS1(sat) + VBS1.
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-11

Illustration of the ICMR of the Bulk-Driven, Differential Amplifier

250nA

200nA

Bulk-Source Current
150nA

100nA

50nA

-50nA
-0.50V -0.25V 0.00V 0.25V 0.50V
Input Common-Mode Voltage Fig. 7.6-10A
Comments:
• Effective ICMR is from VSS to VDD -0.3V
• The transconductance of the input stage can vary as much as 100% over the ICMR
which makes it very difficult to compensate
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-12

Low-Voltage Current Mirrors using the Bulk-Driven MOSFET

The biggest problem with current mirrors is the large minimum input voltage required for
previously examined current mirrors.
If the bulk-driven MOSFET is biased with a current that exceeds IDSS then it is
enhancement and can be used as a current mirror.
Cascode Current Mirror
VDD VDD All W/L's = 200µm/4µm
-5
6 10
2µm CMOS
iin iin iout 5 10-5 Iin=50µA

M3 M4 4 10-5 Iin=40µA
iout
Iout (A)

+ + + 3 10-5 Iin=30µA
VGS3 VBS3 VGS4
- -M2
M1 M2 - M1 2 10-5 Iin=20µA

+ + + + + + Iin=10µA
VGS VBS - VGS VGS1 VBS1
- VGS2 1 10-5
- - - -
0
Simple bulk-driven Cascodebulk-driven 0 0.2 0.4 0.6 0.8 1
current mirror current mirror. Fig.7.6-11 Vout (V) Fig. 7.6-12

The cascode current mirror gives a minimum input voltage of less than 0.5V for currents
less than 100µA

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-13

Simple Current Mirror with Level Shifting

Since the drain can be VT less than the gate, the drain could be biased to reduce the
minimum input voltage as illustrated.
VDD

iin IBias

VEB + iout
- Q3

M1 M2

Fig. 7.6-13

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-14

A Low-Voltage Current Mirror with Wide Input and Output Swings

The current mirror below requires a power supply of VT+3VON and has a Vin(min) =
VON and a Vout(min) = 2VON (less for the regulated cascode output mirror).
VDD VDD

I1-IB IB IB I2 I1 IB1 IB2 IB1 I2

iin iout iin iout

M7
M3 M4 M7 M3 M4
or
M6 M6 M5

M1 M2 M1
M5 IB2 M2

Fig. 7.6-13A

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-15

Bandgap Topologies Compatible with Low Voltage Power Supply

VDD VDD VDD VDD
VDD VDD VDD
IPTAT IVBE
IVBE INL IPTAT
VRef VRef
VRef R2
VPTAT IPTAT
INL R3
VBE

R1

Voltage-mode bandgap topology. Current-mode bandgap topology. Voltage-current mode bandgap topology.
Fig. 7.6-14

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-16

Method of Generating Currents with VBE and PTAT Temperature Coefficients

VDD
IVBE
Buss
M9
M7 M8 IPTAT
Buss IVBE
IVBE M5
M3 M4 +
M6
IPTAT IPTAT
Q1 Q2 R4 Vout2
+
+ +
VBE
R3 R1 VPTAT R2 Vout1
- - - -
Figure 7.6-15A

 V PTAT R2
Vout1 = IPTATR2 =  R1 R2 = VPTAT R1
 

 V BE R4
Vout2 = IVBER4 =  R R4 = VBE R
 3  3

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-17

Technique for Canceling the Bandgap Curvature

VDD
1:K2 1:K3
M2 active M2 sat.
M1 M2 M3 M4 M3 off M3 on

Current
K2IVBE K1IPTAT
I2 INL K3INL

INL
IVBE K1IPTAT
Temperature
Circuit to generate nonlinear correction term, INL. Illustration of the various currents.
Fig. 7.6-16
 0, K2IVBE > K1IPTAT
INL =  K I
1 PTAT - K2IVBE, K2IVBE < K1IPTAT

The combination of the above concept with the previous slide yielded a curvature-
corrected bandgap reference of 0.596V with a TC of 20ppm/C° from -15C° to 90C° using
a 1.1V power supply.† In addition, the line regulation was 408 ppm/V for 1.2≤VDD≤10V
and 2000 ppm/V for 1.1≤VDD≤10V. The quiescent current was 14µA.

†
G.A. Rincon-Mora and P.E. Allen, “A 1.1-V Current-Mode and Piecewise-Linear Curvature-Corrected Bandgap Reference,” J. of Solid-State
Circuits, vol. 33, no. 10, October 1998, pp. 1551-1554.
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-18

Low-Voltage Op Amp using Classical Techniques (VDD ≥2VT)

VDD
M3 M4 + + +
VT+VON
M15 VON VT+2VON -
- M12 M13
+ -
VT+VON M7 M11
+
M6 - R1 VON
IBias M1 M2 vout
- Cc
vin -
+ CL
M5 M8 M9 M14
M16 M10

Fig. 7.6-17
Clever use of classical techniques.
Balanced inputs.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-19

Example 7.6-1 - Design of a Low-Voltage Op Amp using the Previous Topology

Use the parameters of Table 3.1-2 to design the op amp above to meet the
specifications given below.
VDD = 2V Vicm(max) = 2.5V Vicm(min) = 1V
Vout(max) = 1.75V Vout(min) = 0.5V GB = 10MHz
Slew rate = ±10V/µs Phase margin = 60° for CL = 10pF
Solution
Assuming the conditions for a two-stage op amp necessary to achieve 60° phase
margin and that the RHP zero is at least 10GB gives
Cc = 0.2CL = 2pF
The slew rate is directly related to the current in M5 and gives
I5 = Cc·SR = 2x10-12·107 = 20µA
We also know the input transconductances from GB and Cc. They are given as
gm1 = gm2 = GB·Cc = 20πx106·2x10-12 = 125.67µS
Knowing the current flow in M1 and M2 gives the W/L ratios as
W 1 W2 gm12 (125.67x10-6)2
L1 = L2 = 2KN’(I1/2) = 2·110x10-6·10x10-6 = 7.18

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-20

Example 7.6-1 - Continued

Next, we find the W/L of M5 that will satisfy Vicm(min) specification.
Vicm(min) = VDS5(sat) + VGS1(10µA) = 1V
This gives
2·10
VDS5(sat) = 1 - 110·7.18 - 0.75 = 1-0.159-0.75 = 0.0909V
2·I5 W5 2·20
∴ VDS5(sat) = 0.0909 = KN’(W 5/L5) → L5 = 110·(0.0909)2 = 44
The design of M3 and M4 is accomplished from the upper input common mode voltage:
Vicm(max) = VDD-VSD3(sat)+VTN = 2-VSD3(sat)+0.75 = 2.5V
Solving for VSD3(sat) gives 0.25V. Assume that the currents in M6 and M7 are 20µA.
This gives a current of 30µA in M3 and M4. Knowing the current in M3 (M4) gives
2·30 W 3 W4 2·30
VSD3(sat) ≤ 50·(W3/L3) → L3 = L4 ≥ (0.25)2·50 = 19.2
Next, using the VSD(sat) = V ON of M3 and M4, design M10 through M12. Let us
assume that I10 = I5 = 20µA which gives W10/L10 = 44. R1 is designed as R1 =
0.25V/20µA = 12.5kΩ. The W/L ratios of M11 and M12 can be expressed as
W 11 W 12 2·I11 2·20
L11 L12 KP’·VSD11(sat)2 50·(0.25)2 = 12.8
= = =

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-21

Example 7.6-1 - Continued

Since the source-gate voltages and currents of M6 and M7 are the same as M11 and M12
then the W/L values are equal. Thus
W6/L6 = W7/L7 = 12.8
M8 and M9 should be as small as possible to reduce the parasitic (mirror) pole.
However, the voltage drop across M4, M6 and M8 must be less than the power supply.
Using this to design the gate-source voltage of M8 gives
VGS8 = VDD - 2VON = 2V - 2·0.25 = 1.5V
Thus,
W 8 W9 2·I8 2·30
L8 L9 KN’·VDS8(sat)2 = 110·(0.75)2 = 0.97 ≈ 1
= =
Because M8 and M9 are small, the mirror pole will be insignificant. The next poles of
interest would be those at the sources of M6 and M7. Assuming the channel length is
1µm, these poles are given as
gm6 2KP'·(W6/L6)·I6 2·50·12.8·20 x10-6
p6 ≈ CGS6 = (2/3)·W6·L6·Cox = (2/3)·12.8·1·2.47x10-15 = 7.59x109 rads/sec
which is about 100 times greater than GB.
Finally, the W/L ratios of the second stage must be designed. We can either use the
relationship for 60° phase margin of gm14 = 10gm1 = 1256.7µS or consider proper
mirroring between M9 and M14.
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-22

Example 7.6-1 - Continued

Substituting 1256.7µS for gm14 and 0.5V for VDS14 in W/L = gm/(KN' VDS(sat)) gives
W14/L14 = 22.85 which gives I14 = 314µA. The W/L of M13 is designed by the
necessary current ratio desired between the two transistors and is
W 13 I13 314
L13 I12 12 20 ·12.8 = 201
= I =
Now, check to make sure that the Vout(max) is satisfied. The saturation voltage of M13 is
2·I13 2·314
VSD13(sat) = KP' (W13/L13) = 50·201 = 0.25V
which exactly meets the specification. For proper mirroring, the W/L ratio of M14 is,
W 9 I9 W 14
L9 = I14 L14 = 1.46
Since W9/L9 was selected as 1, this is close enough.
The parameters are gds7 = 1µS, gds8 = 0.8µS, gds13 = 15.7µS and gds14 = 12.56µS.
Therefore small signal voltage gain is (RI ≈ rds9 because M7 is part of a cascode conf.)
vout  gm1   gm14  125.6 1256.7
vin ≈gds9 gds13+gds14 =  1.8   28.26  = 69.78·44.47 = 3,103V/V
The power dissipation, including Ibias of 20µA, is 708µW.
The minimum power supply voltage is VT + 3∆V ≈ 1.5V if VT = 0.7V and ∆V ≈ 0.25V.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-23

A 1-Volt, Two-Stage Op Amp

Uses a bulk-driven differential input amplifier.

VDD=1V
6000/6 6000/6 3000/6 6000/6
M12
M8 M9 M10 M11
vin- 2000/2 vin+
Cc=30pF vout
IBias M1 M2
Rz=1kΩ
Q5 Q6 CL
M3 M4
M7
400/2 400/2 400/2

Fig. 7.6-18

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-24

Performance of the 1-Volt, Two-Stage Op Amp

Specification (VDD=0.5V, VSS=-0.5V) Measured Performance (CL = 22pF)
DC open-loop gain 49dB (Vicm mid range)
Power supply current 300µA
Unity-gainbandwidth (GB) 1.3MHz (Vicm mid range)
Phase margin 57° (Vicm mid range)
Input offset voltage ±3mV
Input common mode voltage range -0.475V to 0.450V
Output swing -0.475V to 0.491V
Positive slew rate +0.7V/µsec
Negative slew rate -1.6V/µsec
THD, closed loop gain of -1V/V -60dB (0.75Vp-p, 1kHz sinewave)
-59dB (0.75Vp-p, 10kHz sinewave)
THD, closed loop gain of +1V/V -59dB (0.75Vp-p, 1kHz sinewave)
-57dB (0.75Vp-p, 10kHz sinewave)
Spectral noise voltage density 367nV/ Hz @ 1kHz
181nV/ Hz @ 10kHz,
81nV/ Hz @ 100kHz
444nV/ Hz @ 1MHz
Positive Power Supply Rejection 61dB at 10kHz, 55dB at 100kHz, 22dB at 1MHz
Negative Power Supply Rejection 45dB at 10kHz, 27dB at 100kHz, 5dB at 1MHz
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-25

Further Considerations of the using the Bulk - Current Driven Bulk†

The bulk can be used to reduce the threshold sufficiently to permit low voltage
applications. The key is to keep the substrate current confined.
One possible technique is:

;;
S S Gate
IE p+ p+
B

;;
G B G
n+
D ICD ICS
D Source Drain
IBB IBB
n-well
p- substrate
Reduced Threshold MOSFET Parasitic BJT Layout Fig. 7.6-19

Problem:
Want to limit the BJT current to some value called, Imax.
Therefore,
Imax
IBB = βCS + βCD + 1

†
T. Lehmann and M. Cassia, “1V Power Supply CMOS Cascode Amplifier,” IEEE J. of Solid-State Circuits, Vol. 36, No. 7, 2001
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-26

Current-Driven Bulk Technique - Continued VDD

Bias circuit for keeping the Imax defined
independent of BJT betas. VBias1
M7
M3
IS,E
M6
Note: R
ID,C = IDC + ID ID,C IBB M1 M2
IS,E = ID + IE + IR
M5 M4
M8 +

VBias
VBias2 IR
-
The circuit feedback causes a bulk bias current VSS Fig. 7.6-20
IBB and hence a bias voltage VBIAS such that
IS,E = ID + IBB(1+βCS + βCD) + IR regardless of the actual values of the β’s.
Use VBias1 and VBias2 to set ID,C ≈ 1.1ID , IS,E ≈ 1.3ID and IR ≈ 0.1ID which sets Imax
at 0.1ID.
For the circuit to work,
VBE < VTN + IRR and |VTP| + VDS(sat) < VTN + IRR
If |VTP| > VTN, then the level shifter IRR can be eliminated.
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-27

A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique

VDD
VBiasP M11 M12

M6 M13
Cx M9 M10
M17
+
vin M1 M2 vout
-
CL
M7 M8

VBiasN M3 M5 M4 M14
M15
M16

VSS Fig. 7.6-21

Transistors with forward-biased bulks are in a shaded box.
For large common mode input changes, Cx, is necessary to avoid slewing in the input
stage.
To get more voltage headroom at the output, the transistors of the cascode mirror have
their bulks current driven.
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-28

A 1-Volt, Folded-Cascode OTA using the Current-Driven Bulk Technique -

Continued
Experimental results:
0.5µm CMOS, 40µA total bias current (Cx = 10pF)
Supply Voltage 1.0V 0.8V 0.7V
Common-mode 0.0V-0.65V 0.0V-0.4V 0.0V-0.3V
input range
High gain output 0.35V- 0.25V-0.5V 0.2V-0.4V
range 0.75V
Output saturation 0.1V-0.9V 0.15V- 0.1V-0.6V
limits 0.65V
DC gain 62dB-69dB 46dB-53dB 33dB-36dB
Gain-Bandwidth 2.0MHz 0.8MHz 1.3MHz
Slew-Rate 0.5V/µs 0.4V/µs 0.1V/µs
(CL=20pF)
Phase margin 57° 54° 48°
(CL=20pF)
The nominal value of bulk current is 10nA gives a 10% increase in differential pair
quiescent current assuming a BJT β of 100.
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Lecture 350 – Low Voltage Op Amps (3/26/02) Page 350-29

SUMMARY
• Integrated circuit power supplies are rapidly decreasing (today 2-3Volts)
• Classical analog circuit design techniques begin to deteriorate at 1.5-2 Volts
• Approaches for lower voltage circuits:
- Use natural NMOS transistors (VT ≈ 0.1V)
- Drive the bulk terminal
- Forward bias the bulk
- Use depeletion devices
• The dynamic range will be compressed if the noise is not also reduced
• Fortunately, the threshold reduction continues to allow the techniques of this section to
be used in today’s technology

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002