You

Define the terms dependability, availability, reliability,

safety, and criticality with reference to embedded
system characteristics.
< 1/2 >

ChatGPT
Dependability: The measure of a system's overall
reliability, availability, maintainability, and safety. It
reflects the system's ability to deliver services that
can be trusted.

Availability: The proportion oftime a system is

operational and can perform its intended functions. It
is usually expressed as a percentage of uptime over
a given period.
Reliability: The probability that a system will perform
its intended functions without failure over a specified
time under defined conditions. It is a key aspect of a
system's dependability.
"Safety: The degree to which a system minimizes
risksof harm to users, operators, and the
environment. In embedded systems, safety
measures are crucial, especially in critical
applications like automotive or medical devices.
Criticality: Refers to the importance of a system's
functions, where failure could lead to severe
consequences. Critical embedded systems often
require higher levels of reliability and safety
measures due to the potential impact of failure.
<2/2 >
 The following are the important features exhibited by embedded systems.

perform a single job repetitively.

Most embedded systemscontroller that can take
1. Single functioned system:machine user inputs
has an embedded
rOr example, a washing
perform A cell-phone can receive
the job of washing.pcople.
n terms of knob settings and two A general purpose
transmit signals to enable communication betweendoing a lot many operations. An
And other hand is capable of
System (like a desktop) on thesingle fnction efficientlyas compared to a gerneral purpose
embedded system will do the all embedded systems
system. However, it should be kept in mind thatfeatures, may be able to
computational as other
For example, the cell-phone,
are notsingle functioned. photograph camera, tune to a radio station, play
SMSs, take with add-on utilized to perform complex
send/receive be
and so on. But it cannot
music, connect to the Internet a desktop, it cannot be programmed for this purpose.
scientific computationunlike interact with the
physical environment:Most embedded systems
2. Interction with the environmnt using sen
environment Around them. Data are collected from the the environment. A
physical control some of the parameters of
sors while actuators are used to system may have number of
temperature sensors fitted at
room temperature monitoring readings, it can actuate
Depending upon the temperature
various locations in the room.
instruments distributed in the room.
a number heating/cooling mouse, screen, etc. in
common user interfaces like keyboard,
3. User interface: Unlike the embedded systems often contain dedicated user interfaces
general computing systems, Diodes (LEDs), steering wheels, etc. This
consisting of push buttons, Light Emitting computers and thus, information processing
to the
gives an impression of the absence of
general users.
4. Dependable system: Embedded systems are often used in safety-critical applications,
instrumentation, etC. This demands a high degree
like nuclear power plants, medical
of dependability on such systems. It is more so, because(embedded systems often work
with the environment and impacting upon it directly.
in autonomous mode, interacting dependable system must ensure easy maintainability,
Apart from system reliability, a and security of information it
good availability, high degree of safety to the environment card information to
processes. For example, asmart card reader should not release the
any undesired agency.
from several
5. Tightly constrained system: Embedded system design is often constrained so that the overall
angles. For example, it should be a low-cost solution
L system to the problem
is cheap. Size of the embedded system, its perfoYmance and power budget also put
severe constraint on thechoice of the target implernentation. For the battery to last long
and reduced battery-pack size, the system must be a low-power one. These constraints,
though present inother computing systems, may not be that stringent there.
6. Real-time system: Most embedded systems are real-time in nature.(They must respond
to a request from the environment within ainite and fixed amount of time) Failure,
to do so mayleadto a catastrophic situation. For example, failure to acivate ire
extinguishers imnediately after getting a fire alarm through sensors, may estroy the
entire plant. Such systems are called hard real-tine systems. On the other hand, if the
effect is not that serious, the system is asoft real-time system. For example, failure to

1.2 Design Metrics 3

processthe image frame just arrived may create some noise in the display of the image
for some time.
7. Hybrid systems: Many of the real-time systems are hybrid in nature, as they include
both analog and digital components.
8. Reactie systems Reactive systems have continual interaction with the environment.
The behaviour of the system is very much dependent on the events occurring in the
environment. This type of systems normally have a set of states. Depending upon the
Occurrence ofevents, state transitions in the system take place. On the other hand, a
proactive system may not be interactive in nature. Once initiated/a proactive systen
may work on its own to produce output.
 1.2 Design Metrics
The design metrics are the optimization goals that an embedded system designer wants to
achieve. The commonly used metrics are the following:
1 Sustem cost: It consists of two types of costs, namely the non-recurring engineering
NRE) Cost and the recurring cost. The NRE cost is one timethe expenditure incurred
inthe design stage of the system. Qnce the system has been designed, extra units 'can
he Droduced at a much lesser cost. This type of situation occurs commonly in designing
VLSIchips. The NRE cost is very high as it includes the process of generating masks.
However, once the mask preparation has been done, it can be replicated over a large
silicon die to produces targe number of similar chips, reducing the per unit cost.
2. Size: Size of the system is very importnt. (The size may be measured in silicon area
for hardware, whereas it refers to the code size for the software portion of the embedded
system. )The code size'affects_the memory space requirement, increasing the overall
chip/boárd size.
3. Performance: It refers to the speed of the designed system. Normally, the specification
of the system will have some performance requirements to be met by the design. This is
one of the vital factors infuencing the decision regarding the final implementation. For
example, the same functionality implemented in software will have lesser speed than a
hardware realization. In the hardware realization also, an application specific integrated
circut (ASIC) will have better performance as compared to Field Programmable Gate
Arrays (FPGAs) or other general purpose processors.
Pouer requiremnt: This is the other most important design metric, particularly because
the embedded systems are expected to have light weight, long battery life. This neces
Sitates plastic packaging, absence of cooling fans, etc./Thus, power requirement and the
associated heat dissipatión of the system should be very low.)
Sktte
fte
esgn fleribility:(It refers to the effort needed to modify &system if the specifcation
thanges to some extent later. While a software implementation is most fexible, ASIC is
mes
Hexible one, withFPGAs lying at an intermediary stage. The main problem in
he design change is the repetition'of the NRE cost which is the minimum for software.
6
NRE
Design humaround time:(This is the time, needed to complete the design starting from
specification upto taking it to the obsolesence of
market. Due to the very high rate of

Introduction
electronic goods, it is imperative that this time be small. The requirement often forces
the designers to use off-the-shelf components, rather than doing a costIy redesign of
system components. Design reuse is the key term here.
I. System maintainability: This refers to the ease of maintaining and monitoring the health
of the system after it has been put into the Held.A gOod design is well docunented such
the
that even designers excepting those who designed the system originally, can modify
system, if necessary.
the ability to check the systen
O esting and verification of functionality: It refers to operation
functionality and get confidence regarding the correct of it. It may be noted
that in the system life-cycle, verifcation is generally carried outall after the design has
system features
been completed/ The goal of design verifcation is to see whether the
have been designed properly or not) There is no physical system available at this point
of time. On the other hand, testing is needed to check for correct functioning of each
unit produced. Thus, verification comes as an NRE cost while testing comes as a part
of unit cost.
BASIC STRUCTURE OF AN EMBEDDED SYSTEM:
A-D Processor & D-A
Sensor Actuator
Converter ASIC Converter

Memory

1. SENSOR - IT MEASURES THE PHYSICAL QUANTITY AND CONVERTS IT TO AN ELECTRICAL SIGNAL WHICH CAN BE
READ BY AN OBSERVER OR BY ANY ELECTRONIC INSTRUMENT LIKE AN A2D CONVERTER. A SENSOR STORES THE
MEASURED QUANTITY IN THE MEMORY.
2. A-D CONVERTER - AN ANALOG-TO-DIGITAL CONVERTER CONVERTS THE ANALOG SIGNAL SENT BY THE SENSOR INTO
A DIGITAL SIGNAL.

3. PROCESSOR & ASICS - PROCESSORS PROCESS THE DATA TO MEASURE THE OUTPUT AND STORE IT IN THE MEMORY.

4. D-A CONVERTER- ADIGITAL-TO-ANALOG CONVERTER CONVERTS THE DIGITAL DATA FED BY THE PROCESSOR TO
ANALOG DATA

5. ACTUATOR - AN ACTUATOR COMPARES THE OUTPUT GIVEN BY THE D-A CONVERTER TO THE ACTUAL (EXPECTED)
OUTPUT STORED IN IT AND STORES THE APPROVED OUTPUT.
) You
What is the function of the following ARM instruction:

(1) LDR R1, [-R2]

(ii) MUL R2, RO, R1

(ii) SWP RO, R1, [R2]

(iv) SWI #11

(v) BMIaddr
< 2/2 >

ChatGPT

"LDR R1, [-R2]: Load Register. It loads the word at the

memory address specified by the value in register R2
into register R1. The square brackets and the minus
sign indicate post-indexing addressing mode,
meaning the address is updated after the load.
" MUL R2, RO, R1: Multiply. It multiplies the values in
registers RO and R1and stores the result in register
R2.

" SWP R0, R1, [R2]: Swap. It atomically swaps the

contents of the memory location addressed by R2
with the value in R1. The original content of the
memory location is loaded into RO.
"sWI #11: Software Interrupt. It triggersa software
interrupt with a specific interrupt number. In this
case, #11 indicatesa particular software service or
function.
BMI addr: Branch on Minus. It performs a branch to
the address specified if the sign flag (N) is set,
indicating a negative result from a previous
operation.
B You
Which instruction is used to enter the THUMB
instruction set? Mention two similarities and two
differences between ARM and THUMB Instruction sets

ChatGPT
The instruction to switch to the THUMB instruction set

in ARM architecture is the 'BX (Branch and Exchange)

instruction. Specifically,the BX instruction with the
T bit set in the destination address is used to switch
to the THUMB state.

Similarities between ARM and THUMB:

1. Registers: ARM and THUMBshare the same general

purpose registers. For example, RO in ARM
corresponds to RO in THUMB.
2. Memory Access: Both instruction sets support similar
memory access instructions, allowing for versatile data
manipulation.

Differences between ARM and THUMB:

1. Instruction Size: The most significant difference is the

size of instructions. ARM instructions are 32 bits, while
THUMB instructions are 16 bits, allowing for more
compact code in THUMB mode.
2. Instruction Set Complexity: ARM instructions tend to
be more powerfuland versatile due to their larger size,
gcomplex operations. In contrast, THUMB
instructions are simpler and more streamlined,
sacrificing some complexity for reduced code size.
 Key Features
1. SPlis a communication protocol used for data transfer between a master device and multiple
peripheral slave devices.
2. It operates synchronously, and all transmissions are controlled by the master through a
Common clock.
3. Both the master and slave devices contain serial shift registers, facilitating efficient data
exchange.
4. Master initiates data transfer by writing a byte to its SPl shift register and sending it to slave
via MOSI signal line.
5.Simultaneously, the slave transfers its shift register's content back to the master via the
MISO(Master In Slave Out) signal line, enabling bidirectional communication.
6. SPlsupports a wide input supply range of 1.65 Vto 3.7 V, making it suitable for low-power
applications.
7. It allows for multibyte transmission, commonly using 8-bit words, and other word sizes
can be employed based on application requirements.
8. Multiple peripheral slave devices can be connected to a single master through chip
select signals, enabling efficient communication with specific slaves.
9. The master can customize the clock signal's polarity (CPOL) and phase (CPHA) to
control the data capture and transmission timing.
10. SPl is commonly used in various applications, including touch-screen controllers, audio
codecs, real-time clocks, EEPROM storage, and ADCs.
11. While SPI lacks a built-in addressing mechanism for multiple slaves, its simplicity and
versatility make it a powerful choice for embedded systems.
1) You
What are the various features of the USB
communication protocol? What are the types of data
transfer associated with USB? How are USB devices
powered?
< 2/3 >

ChatGPT
Features of USB Communication Protocol:

1. Plug and Play: USB supports hot-swapping, allowing

devices to be connected or disconnected without

restarting the computer.

2. Speeds: USB offers different data transfer rates,
including USB 2.0 (up to 480 Mbps) and USB
3.0/3.1/3.2 (up to 5 Gbps, 10 Gbps, or 20 Gbps).
3. Power Supply: USB provides power to connected
devices, simplifying device power requirements.
4. Universal Connectivity: USB is widely used across
various devices, including computers, printers,
cameras, and more.
5. Host-Device Architecture: USB operates in a host
device architecture where a host (usually a computer)
controls communication with connected devices.

Types of Data Transfer Associated with USB:

1. Control Transfer: Used for configuration and control of

devices.
2. Bulk Transfer: Efficient for large data blocks with error
checking.
3. Interrupt Transfer: Supports small, periodic data
transfers with guaranteed timing.
4. Isochronous Transfer: ldeal for time-sensitive
applications like streaming audio or video.

USB Device Powering:

1. Bus-Powered: Devices draw power from the USB bus,

suitable for low-power devices like keyboards or mice.
2. Self-Powered: Devices have their power source and
use USB for data transfer only.
3. Battery Charging: USB can provide power for charging
devices like smartphones, cameras, etc., through
dedicated charging ports or standard data ports.
4. Power Delivery (PD): USB Power Delivery protocol
allows devices to negotiate for higher power levels,
supporting faster charging for compatible devices.
< 2/2 > 9
USB supports four different types of data transfers:

1. Control Transfer: This transfer type is used to configure the bus and exchange
status information with the device. It is typically used for device configuration and
control operations.

2. Bulk Transfer: Bulk transfer is an asynchronous bidirectional transfer used to

move large amounts of data. It is commonly used for tasks like file transfers.

3. Isochronous Transfer: lsochronous transfer is used for time-critical data

transfer to an output device. It is unidirectional and does not include error
checking. This transfer type is suitable for real-time audio and video streaming.

4. Interrupt Transfer: Interrupt transfer allows the device to receive or transmit

data at regular intervals, ranging from 1to 25 milliseconds. It is used for devices
that require low-latency communication, such as USB keyboards and mice.
B You
What are the uses of timers in-embedded systems?
Differentiate between timers and counters

ChatGPT
Uses of Timers in Embedded Systems:

1. Task Scheduling: Timers are used to schedule specific

tasks or events at predetermined intervals.
2. Pulse Width Modulation (PWM): Timers generate
PWM signals, which are crucial for controlling the
speed of motors, brightness of LEDs, and other analog
like functions.

3. Real-Time Clocks (RTCs): Timers can function as real

time clocks, keeping track of time and date in
embedded systems.
4. Delay Generation: Timers provide precise delays,
ensuring accurate timing in various operations.
5. Frequency Generation: Timers can generate specific
frequencies required for communication protocols or
other timing-sensitive applications.
6. Capture and Compare Operations: Timers capture
external signals or compare internalcounter values
with predefined values, facilitating tasks like
measuring external event durations.

Difference between Timers and Counters:

1. Function:

" Timer: Measures time intervals and generates

events at specified intervals.
" Counter: Counts external events, like pulses or
transitions,and keeps track of the count.
2. Initialization:

" Timer: Typically initialized to a specific value,

counting down to zero or counting up from zero.
Counter: Initialized based on external events,
counting the occurrences of those events.
3. Use Cases:

" Timer: Used for generating time delays, PWM

signals,or scheduling events.
" Counter: Used for counting external events, such as
the number of pulses from asensor.
4. Direction:

" Timer: Can be configured to count up or down.

" Counter: Typically counts in one direction,often up.

In summary, while timers focus on measuring time and

generating timed events, counters are more geared
towards counting external events. In practice, many
microcontrollers integrate both timers and counters in a
single module for flexibility and versatility,.
(3) You
What are the constituents of a generic FPGA?
< 2/2 >

G ChatGPT
A
generic Field-Programmable Gate Array (FPGA)
consists of several key components that enable its
programmability and flexibility:

1. Configurable Logic Blocks (CLBS): These are the basic

building blocks of an FPGA, containing a combination
of look-up tables (LUTS), flip-flops, and multiplexers.
CLBs can be configured to implement various digital
functions.
2. Interconnect:

Switch Matrix: Provides the routing resources that

connect various CLBs and other elements within the
FPGA.

Programmable Routing Channels:Facilitate the

connection of signals between different
components on the FPGA.
3. Input/Output Blocks (|0Bs): These blocks interface
the FPGA with external components. They include
input buffers, output buffers, and programmable \/O
standards to adapt to different voltage levels.
4. Clock Management:
PLL (Phase-Locked Loop): Generates stable clock
signals and allows for frequency synthesis.
" DLL (Delay-Locked Loop): Aligns signals in time
domain applications.
5. Memory Blocks:
Block RAM (BRAM): Provides on-chip memory that
can be used for data storage or as FIFO buffers.
Distributed RAM: Smal, fast memory elements
distributed across the FPGA fabric.

6. Digital Signal Processing (DSP) Blocks: Specialized

blocks designed for efficient implementation of
mathematical operations commonly used in signal
processing applications.
7. Configuration Memory: Stores the configuration
bitstream that defines the logic functions and
interconnections within the FPGA. This memory is
typically non-volatile and can be loaded at power-up or
reconfigured on-the-fly.
8. Configuration Interface: Allows external devices to
program the FPGA. It can be a JTAG interface or other
configuration methods.
9. Hard IP Blocks: Some FPGAs include predefined hard
IP blocks,such as processors (e.g., ARM cores), PCle
controllers, or other specialized functions.
10. Analog Blocks (optional): Some FPGAs include analog
components like analog-to-digital converters (ADCs)
or digital-to-analog converters (DACs).

These constituents collectively provide the

reconfigurability and versatility that make FPGAs
suitable for a wide range of applications, from digital
signalprocessing to prototyping and rapid
development of digital systems.
< 3/3 >
 Design Entry Design Verification

Schematic | Behaviour

Behavioural Simulation

Design
Synthesis

Functional Simulation
Design Timing Analysis
Implementation
Back Annotation Timing Simulation

In-circuit Verification
Device Programming9

Fig. 4.9 FPGA design flow

 FPGA Design Flow
Design Entry:
Choose between schematic entry or behavioral description using VHDL/Verlog.
Schematic ent1ry visually represents the design using library modules and interconnections.
Behavioral description involves coding the design's functionality in hardware description
languages.
" Behavioral Simulation:
Test design at schematic/ behavioral levels to ensure correct functionality.
Create simulation models and scenarios to verify the design's behaviour.
" Detect and address discrepancies before proceeding to the next phase.
Design Implementation:
Translate design's netlist into target FPGA format.
" Conduct functional simulation to validate translation accuracy.
 FPGA Design Flow
Perform place and route to position logic elements and establish interconnections.
" Analyse timing to ensure signal propagation meets constraints.
" Device Progranming:
" Generate final configuration program for FPGA.
" Load configuration during power-up for SRAM-based FPGAs.
Program antifuses/EPROM for non-volatile FPGAs.
" In-Circuit Verification:
" Some FPGAs offer in-circuit verification modules.
Verify design's correctness within actual hardware.
Identify and rectify discrepancies introduced during design and programming.
 You

Draw the state chart representation of the following specifications of an

online ordering system with 5 states: unprocessed order, rejected order,
accepted order, pending order, and fulfilled order.

(1) On the event of an order being received, we transit from our initial
state to the Unprocessed order state.
(ü) The unprocessed order is then checked.
(i) If the order is rejected, we transit to the Rejected Order state else
move to the Accepted order state
(iv) If the order is accepted and we have the items available we transit to
the Fulfilled order state.
(v) However, if the items are not available, we transit to the Pending Order
state.
(vi) After the order is fulfilled, we transit to the final state

S ChatGPT
plaintext O Copy code

| Unprocessed Rejected
Order | on reject Order

V V | on accept

Accepted |<-. Pending

Order I on Ieject Order

| on fulfill
V

Fulfilled Final
Order | on Ieject State

This state chart represents the online ordering system with the specified
states (Unprocessed Order, Rejected Order, Accepted Order, Pending
Order, and Fulfilled Order) and transitions based on events (order
received, order checked, order accepted, items available, items not
available, order fulfiled). The arrows indicate the flow of transitions
between states, and conditions for transitions are mentioned on the
arrows.

<2/4 >
R You
Discuss the KL partitioning method used in the embedded system.

ChatGPT

KL Partitioning, also known as Kernighan-Lin Partitioning, is a graph

partitioning algorithm commonly used in embedded systems design,
particularly for hardware-software co-design and partitioning tasks.
Here's an overview of the KL Partitioning method:

1. Graph Representation:
" The embedded system is represented as a weighted bipartite graph,
where nodes represent modules or components, and edges
represent the communication or interaction between them.
" Weights on the edges represent the cost or the amount of
communication between the modules.

2. Objective Function:
" The goal is to partition the graph into two disjoint sets (partitions)
such that the total weight of communication between the two
partitions is minimized.
The objective function is to minimize the cut size, which is the total
weight of edges crossing the partitions.
3. KL Partitioning Algorithm:
" Start with a random or initial partitioning of the graph into two sets.
" Iteratively move nodes between the two sets to reduce the cut size.
At each iteration, selecta node to move from one set to the other,
aiming to minimize the increase in the cut size caused by the move.
Repeat this process until further moves do not significantly decrease
the cut size.

4. Node Movement Strategy:

The algorithm employs a heuristic strategy for selecting nodes to
move between partitions. The Kernighan-Lin algorithm uses a "gain"
metric, calculated for each possible node move. The gain is the
difference in the cut size before and after the move.

" Nodes with the highest positive gain are considered for movement.
5. Refinement Process:
After the initial partitioning, the KL algorithm performs multiple
refinement iterations. In each iteration, it optimizes the partitioning
by moving nodes to reduce the cut size further.
6. Stopping Criteria:
" The algorithm terminates when a specified number of iterations are
reached, or when further moves do not lead to a significant reduction
in the cut size.
7. Application in Embedded Systems:
" KL Partitioning is commonly used in the design of embedded
systems to partition the system into hardware and software
components.

"The partitioning process helps in optimizing the overall system

performance by minimizing communication overhead and meeting
constraints.
8. Advantages:
" KL Partitioning provides a good balance between simplicity and
effectiveness.

" It is suitable for awide range of applications, includingembedded

systems.
9. Limitations:
" KL Partitioning is a heuristic method, and the quality of the solution
depends on the initial partitioning and the termination conditions.
" It may not always find the optimal solution, but it is computationally
efficient.

In summary, the KL Partitioning method is a graph-based heuristic

algorithm that plays a crucial role in optimizing the partitioning of
embedded systems, particularly in hardware-software co-design
Scenarios.
3) You
Discuss Logic and Circuit Level Power Minimization techniques
employed in embedded systems.

ChatGPT
Logic Level Power Minimization Techniques:

1. Gate-Level Power Gating:

" Implementing power gating involves selectively turning off power to
specific blocks or functional units when they are not in use. This
helps reduce static power consumption.
" Power gating is particularly useful in scenarios where certain blocks
of a chip can be powered down during idle states.
2. Clock Gating:

Clock gating involves dynamically disabling the clock signal to

specific registers or functional units when they are not actively
processing data.
" By reducing the clock toggling in idle or low-activity states, clock
gating minimizes dynamic power consumption.
3. Multi-Voltage Design:
Designing different sections of the system with varying voltage levels
allows for lower power consumption in less critical components.
" It is essential to consider voltage scaling carefully to avoid issues like
data corruption due to different voltage levels.
4. Dual Edge Triggering:
Instead of using a single clock edge for triggering, dual-edge
triggering uses both rising and falling edges of the clock signal.
" This can potentially reduce the frequency of clock signals and,
consequently, dynamic power Consumption.

Circuit Level Power Minimization Techniques:

1. Sub-threshold Operation:
"Operating transistors in the sub-threshold region (below the
threshold voltage) can significantly reduce power consumption.
" However, it comes at the cost of slower circuit speed and increased
sensitivity to process variations.
2. Dynamic Voltage and Frequency Scaling (DVFS):
DVFS adjusts the operating voltage and frequency dynamically
based on the workload.

During periods of low activity, voltage and frequency are reduced to

save power.
3. Pipeline Stalling:
" Introducing mechanisms to stall the pipeline during low-activity
periods can reduce the overall power consumption.
This involves detecting idle states and preventing unnecessary
operations.
4. Low Power Flip-Flops:
" Using flip-flops designed specifically for low power consumption can
be effective.

" Techniques include using clock gating within flip-flops, reducing the
number of transitions, and optimizing clock-to-Q delay.
5. MTCMOS (Multi-Threshold CMOS):
"MTCMOS incorporates transistors with different threshold voltages
in the design.
" It allows for selectively turning off power to certain portions of the
circuit during idle times.
6. Leakage Power Reduction Techniques:
" Techniques such as using low-leakage process technologies, reverse
body biasing, and optimizing transistor sizes help minimize leakage
power.

Trade-offs:

" Many power minimization techniques involve trade-offs between power

reduction and performance. For example, lowering the voltage to reduce
power can impact the speed of the circuit.
It's crucial to carefully analyze the requirements of the embedded
system and consider the specific trade-offs that best meet the design
goals.