PUF Based Hardware Security: A Review

Koustav Dey Prof. Malay Kule Prof. Hafizur Rahaman

VLSI Design VLSI Design VLSI Design
IIEST Shibpur IIEST Shibpur IIEST Shibpur
Kolkata, India Kolkata, India Kolkata, India
koustavdey1001@gmail.com malay.kule@gmail.com rahaman_h@yahoo.co.in
2021 International Symposium on Devices, Circuits and Systems (ISDCS) | 978-1-6654-1478-4/20/$31.00 ©2021 IEEE | DOI: 10.1109/ISDCS52006.2021.9397896

Abstract - In modern era, we are harnessing the power of electronic

information so that only the intended person can read and
devices more than ever. It has become a part of our daily lives. process it. Cryptanalysis is the study of
Thus, the protection of the private data and hence the underlying analyzing information in order to study the hidden aspects of
hardware is becoming mandatory. In this survey, we discuss how the systems. Cryptanalysis is used to breach cryptographically
this problem of hardware security is handled through the use of secured systems and read the contents of the
Physically Unclonable Function (PUF) which are circuits used to encrypted messages, even if the cryptographic key is
create unique and reliable signatures of a particular electronic unknown.
circuit. This paper describes in a chronological manner starting
from the times of delay based PUFs to the recent times when we
This paper explores the various methods used for Hardware
have the Machine Learning attack resistant model. It paves the way
for addressing the security concerns of the modern development in Trojan Detection [9] and Prevention through the use of
IOT devices. Physically Unclonable Function (PUF) in a chronological
manner. Various research journals are studied to extract the
Keywords – Hardware Security; Physically Unclonable Function; main developments over its previous version. Their pros and
Machine Learning attack; IOT. cons are noted to connect them in a way to draw a clear
picture of the path of research. This paper, not only helps the
new researcher who wants to explore this field of Hardware
I. INTRODUCTION Security to get a bird’s eye view of the researches going on at
a very short time, but also it helps to derive various insight
In today’s world, it is inevitable to live a day without about different methodologies used.
harnessing the power of technology. With modernisation,
people are becoming more dependent on electronic circuits. The paper is organized in three more sections. Section 2
Thus, the protection of electronic data is of utmost importance. describes some preliminaries; section 3 focuses on main
With the advancement of emerging technologies, newer survey work and section 4 concludes the survey.
threats are also coming out rapidly. So, the researchers have to
know ahead how to detect and prevent these threats [1].
II. PRELIMINARIES
In our modern world, the companies like to outsource A. Basic Concept of PUF
manufacturing tasks in order to minimize cost. Embedded
systems are not always produced by the companies that sell A Physical Unclonable function is a physical object that
them. Also, the country where they will be used might not be provides a "digital fingerprint" output (response) for a given
the same. But outsourced product might not be fully relied input and conditions (challenge). It is used as a unique
upon. Anyone who knows about the manufacturing process identifier for a digital circuit.
could manipulate the final product by introducing minute
changes. For complicated products, minimal changes can be A PUF has the following characteristics.
difficult to detect. Thus, the need for secure hardware system 1) Intra Differences - When same set of stimulus
is obvious since beginning. With modern development of (challenges) is applied to the same device then the outputs
machine learning [4] and AI, the previously made secure (responses) should be close to each other irrespective of
models are broken very easily. The threat looms large as changes in temperature , noise , aging etc . This provides the
because we are heading towards a more connected world with reliability of the PUF.
5G connectivity and Internet of Things (IOT)[11]. Thus, the
recent trend is focusing mainly on these concerns. This paper 2) Intra Differences - When same set of stimulus
explores these highly interesting and relevant fields. (challenges) is applied to different device then the outputs
(responses) should differ largely with each other irrespective
This survey comes under the broad category of of changes in temperature , noise , aging etc . This provides
Cryptology[12] that subsumes both cryptography and the uniqueness of the PUF.
cryptanalysis. Cryptography is the process of protecting

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B. Strong versus Weak PUFs B. Prevention of Hardware Trojan using PE-PUF

There are two types of PUF based on the size of the The shortcomings of only Delay Based PUF get rectified in
Challenge-Response pair (CRP). These are Strong PUF and [2] PE-PUF. A PE-PUF enhances the randomness and
Weak PUF. uniqueness of the signature as it imbibes both process and
environmental variations, such as temperature, power supply
With only a limited CRP space, Weak PUF store less number noise and crosstalk.
of output and in extreme cases may store only a single output.
They are mainly used for seeding a pseudo random number
generator, where the response is used internally as and when Oscillation frequency of a ring oscillator with Ninv inverters,
required. denoted by fos, varies according to the equation

On other hand, Strong PUFs have a large CRP space, where a

large number of unique responses are stored along with
respective unique challenges. This captures the physical
fos= 1 / 2 Ninvtinv
randomness of the circuit more accurately and thus have more
entropy. The Arbiter PUF [1] is one of the most common
Now each inverter delay variations adds up and affects the
Strong PUF.
oscillation frequency.

III. REVIEW ON PUF-BASED HARDWARE SECURITY In their paper, they have used a 7-inverter ring oscillator with
two nearby interconnects as described in Fig 2. They have
used HSPICE and done in 90mm technology.
A. Review on PUF based prevention of Hardware Trojan
Paper [1] describes a simple example of Silicon PUF is Ring –
As the chip size is shrinking day by day, the randomness that
Oscillator PUF where the oscillator contains an odd number of
gets incorporated into the circuit during the manufacturing
gates. Fig:1 . describes a simple ring oscillator where 3 NOT
process are not easily understood. It results in unpredictable
gates are connected in series and a feedback loop is given. The
unit resistance, capacitance and inductance. If we apply the
output will oscillate after we enable the circuit.
same input pattern to different chips then it will show different
effects of temperature, voltage and cross talk.
Here
f = frequency of ring oscillator; This PUF is quite resistant to power side channel attack
n = number of stages; because the three inverters are spread across the whole die.
t = time delay of each stages Fig. 3 shows the power trace of both the PE-PUF, which is
shown by solid line and the only PUF shown by the dashed
Here the frequency is affected by the process variance. line. Comparing, we observe that the oscillation frequency
Delay-based PUF generates unique signatures by imbibing information is not getting exposed through the power trace in
only the process variation but there are some shortcomings case of PE-PUF. Besides in case of PE-PUF the oscillation
due to spatial correlation among the process parameters. So, frequency depends on the input pattern, which is known only
these PUFs are vulnerable as they can be broken by side to designer.
channel attacks and also, they have less uniqueness in their
signatures.

Fig. 1: Simple Ring Oscillator

Fig. 2: Ring Oscillator spread between two nearby

interconnects

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 in [2] and by erasing one of the CRPs by use of Memristors as
in [3].

But recent developments in Machine Learning Attacks are

making them vulnerable to be broken. So researchers are
moving ahead to make it Machine Learning Attack resistant.
The progress made in this topic is discussed.

D. Symmetric function based Memristive PUF

This paper has come up with a new concept of using
memristors as the core element in designing the PUF. It has
Fig 3: Power waveform of traditional PUF vs PE-PUF double layer protection due to the use of symmetric function
to generate the challenges and also due to use of a hardware
security layer.
C. Prevention of Hardware Trojan using Erasable PUF
In their paper [3], Rührmair and van Dijk, showed that many Memristors are like normal resistors but they can change their
advanced PUF based security protocols such as the key resistances depending on the past events. Thus it can be used
agreement, oblivious transfer, and bit commitment can be as a memory because a particular resistance can be related to a
vulnerable if adversaries get access to the PUF and reuse the particular memory. Besides memristors are compatible with
responses used in the protocol after the protocol execution. the nano crossbar technology that is usually implemented in
modern circuits. It can also be used as with analog, logical and
Erasable PUFs are PUFs where the responses of any single neuromorphic circuits.
challenge-response pair (CRP) can be selectively and
dedicatedly erased, without affecting any other responses. Symmetric functions are type of function whose structure is
unaffected by the changes made in the input pattern as long as
There are two types of proposed ERASABLE PUF – same inputs are used. We can use any permutation of inputs
into the symmetric function, the structure will remain same.
Firstly, they proposed a full-fledged logical version of an An n-variable symmetric function can be represented as
erasable PUF, called programmable logically erasable PUF or Sn (a i...a j ...a k).
PLayPUF, where an additional constant-size trusted
computing base keeps track of the usage of every single CRP. As we know that a function, which is monotonic, but not
Knowing the query history of each CRP, a PLayPUF interface strictly monotonic, does not have an inverse. This feature is
can automatically erase an individual CRP, if it has been used further exploited in this paper. If the malicious person gets to
for a certain number of times. This threshold can be know some of the responses also, he cannot make out the
programmed a-priori to limit the usage of a given challenge in corresponding challenge pair because of non- invertibility
the future before erasure. property of the unate symmetric function. In this paper a 5-
variable unate symmetric function is implemented as shown in
Secondly, they introduced two nanotechnological, memristor- figure 4.
based solutions: mrSHICPUFs and erasable mrSPUFs. The
mrSHIC-PUF is a weak PUF in terms of the size of CRP
space, and therefore its readout speed has to be limited
intentionally to prolong the time for exhaustive reading.
However, each individual response can be physically altered
and erased for good. The erasable mrSPUF, as the second
proposed physical erasable PUF, is a strong PUF in terms of
the size of CRP space, such that no limit on readout speed is
needed, but it can only erase/alter CRPs in groups. Both of
these two-physical erasable PUFs improve over the state-of-
the-art erasable SHIC PUF, which does not offer
reconfigurability of erased CRPs making the erasable SHIC
PUF less practical.

Until they were just developing the PUFs to make it more

resistant to Side Channel Attacks (like Power Tracing) and
Fig. 4: A 5-variable unate symmetric function implemented
Logic Testing (Watching the CRPs). They have achieved that
using memristive nanocrossbar arrays
by introducing more Environmental Variations as mentioned

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However, till now, these designs are simulated for ASICs only [6]. Kernels are inner mapping functions on which the
and they are not suitable for FPGAs. Moreover in hardware learning of the support vector machine is dependent.
level the voltage range of the input is fixed so that the
memristor state becomes 1. Any changes made in this value iii) Neural Networks – Our brain contains numerous connected
will be noted and sent to the authenticate side that some neurons that form a network known as neural network. A
unusual is happening. replica of the same network when made using algorithm forms
out Artificial Neural Network or ANN. Each node is
Thus the double security of this design is unique. But like composed of neurons, which help in providing the
other PUF designs it might be tested with various ML computational ability to ANN, and is arranged in the layers
algorithms. [7,8].

The importance of ANN is shown by the Universal

E. Machine Learning attacks on PUF Approximation Theorem, which says that a dual layered ANN
In paper [4] a strong RO – PUF (Ring Oscillator Delay Based comprising some fixed number of hidden neurons can do the
PUF) is considered which is implemented in FPGA. The RO- job of approximating any function with significant efficiency
PUF design shown in their paper is controlled by XOR gates, [7].
which are programmable. Then they are implemented on a
FPGA. Single-Layer Perceptron or SLPs have a single layer of hidden
neurons whereas Multi-Layer Perceptron or MLPs have more.
In the design, 40 CLBs are used and each CLB has 16 Ring Thus, for linear separable problems SLPs are used but for non-
Oscillators. For activation, a signal is used for selecting the linear structured problems MLPs are used. The inputs are then
CLB. The Programmable XOR (PXOR) gates from each CLB tested on biased weight, added and sent to the activation
activate and select the ROs for generating the sample function. The weights and bias of the neurons are changed
frequencies. A total of 640 frequencies are generated. The according to the prediction error dynamically on the known
design is implemented under normal condition on Spartan- dataset known as training dataset.
3E/100k FPGA board. In the FPGA board, six separate
regions are chosen with each containing 40 CLBs. Data is After analyzing the paper [4], the results that come are as
collected from adjacent CLBs in order to prevent ROPUF follows:
response dependency in each region. i) On comparison to Support Vector Machines and Logistic
Regression, Artificial Neural Network works more efficiently
On the other hand, as the attacks are considered we have used in predicting the CRP.
some of the CRPs as the Training Set to the Machine Learning ii) Among the Neural network models, model with Adam
Algorithms. By using three different machine learning models shows prediction rate of 88.6% at maximum when this model
a replica of the PUF is designed. is tested with 85% of data on 15% test data set. It also shows
lower loss compared to Adadelta and Rmsprop.
i) Logistic Regression – It uses sigmoid function at its core .
The output is the f(x) which is dependent on the sigmoid
F. Possibility of a Machine Learning Resistant Strong PUF
function and the weights i.e. w0 which is applied on the input
x. If the value of z is large, then the value of exp(-z) becomes
close to 0 and σ (z) becomes 1. Similarly if value of z is small We know that a Strong PUF contains large number of CRP so
σ (z) becomes 0. they are more resistant. But unfortunately, when an attacker
knows some CRPs, he can use machine learning to create a
The algorithm changes the value of the weight w0 and predicts software to mount a building attack on that PUF. Building a
the output . strong PUF resistant to machine learning attack has been a
topic of research.

However, with innovations in application of machine learning,

almost all Strong PUFs have been broken.

Some of the newer Machine Learning techniques used in this

ii) Support Vector Machines – Support Vector Machines
paper to test our PUF are –
(SVM) is a technique basically used as binary classifiers. The
main aim of this algorithm is to separate out two classes by a
i) Bagging - It is used in ensemble learning where many weak
hyperplane so that there is maximum gap between the classes.
learning models is developed to form a good learning model.
The distance between the input vectors belonging to different
In bagging algorithm, bootstrapping is used to separate
classes should be maximum. The inputs, which are at the
different learning models from the input vector. These
minimum distance from hyperplane, are called support vectors
homogeneous learning models are run in parallel and then
combined in a deterministic method at last. This method

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minimizes the variance and over-fitting thus producing a more XORed with an n-bit challenge and their output is fed as
accurate model. challenge to the Strong PUF.

ii) Boosting - Comparing it with the bagging, it does not have A new PUF ID Generator is proposed in this paper which is
much difference except the fact that here the homogeneous both lightweight and reliable and is named here as Pico-PUF.
weak learning models are run sequentially and not in parallel. This Pico-PUF is utilized to show the feasibility of the MPUF.
During each iteration the data is analyzed, the misclassified 100% reliability is achieved by this design. In general, any
data points are allocated greater weights and correct are given Strong PUF like the Arbiter PUF etc. can be utilized to design
less weight. The new classifier thus formed will learn from the the MPUF.
previously misclassified data. With each iteration, the final
classifier gets stronger gives accurate prediction. Two variants Here we come across a new machine learning technique called
of this method are Adaptive Boosting (AdaBoost) and the CMAES. The reliability based CMAES attack, is the most
Gradient Boosting. effective modeling attack against PUFs. It uses repeated
measurements for the same challenge to analyze the reliability
iii) Stacking – Just as the bagging algorithm it runs the of the response bits and then feeds this observation into a
learning model in parallel but the learning model are not fitness function to find the ‘best-fit’ delay parameters.
homogenous here.

iv) Evolutionary Algorithms (EA) – In this work, the authors IV. C ONCLUSION
have utilized Genetic Algorithm to attack the PUF. There are
also other works, which shows the attack of Evolutionary Throughout the survey we have tried to show the timeline of
Algorithm based model attacks. As a solution an EA gives the research that has happened in the field of Hardware
output as a real number set. Since, Genetic Algorithm (GA) Security using PUF. We have tried to compare the merits and
[13] works well with binary strings and integer data, GA goes demerits of some models. There are also some newly proposed
handy in implementing the CRP data. Just EA concept is PUF models like Symmetric Function Based Memristive
similar to concepts like reproduction, recombination/crossover Polimino PUF [10], which uses a different approach to
and selection. In this work, an open-source toolkit, Pyevolve is enhance the security. With the advent of machine learning
used for experiments. attacks, some of the previously made models were broken. We
came across endeavors that tried to overcome it but as
According to this paper, a Cascaded structure based Strong machine learning algorithms progresses, our PUF needs to be
PUF is immune to known machine learning attacks. This stronger. Finally, we land upon a final model i.e., MPUF that
paper shows the characteristics and functions that the cascaded is resistant to these attacks. It is also observed that Genetic
block must possess in order to be resistant to machine learning Algorithm (GA) based method has better prediction rate in
attacks. It does not go into the implementation detail of the comparison with other reported methods.
circuit design, which is left for the purview of the circuit
designer. It paved the path for systematic design approach. The final design is a MPUF created using a Pico-PUF and an
APUF. To test the resistance of the design against Machine
Learning Attacks, they used two separate attacks. One is the
G. Multi-PUF
CMA-ES attack and the other is the LR attack. When the LR
As research in this field progresses, it is shown that both the attack is done, the MPUF achieves a prediction rate of only
lightweight Arbiter PUF [4] and XOR based PUF[3] have also 50% but it is 100% for the traditional Arbiter PUF. Using
been broken with a considerable number of CRPs . To get rid CMA-ES, the MPUF design shows a prediction rate of around
of this, this paper introduces a new non-linear PUF which is 80% with a sample set of 10,000 CRPs and challenge size of
composed of current mirror and based on Voltage Transfer 32 bits. For traditional PUF, it achieves 100% prediction rate.
Characteristics. However, till now, these designs are simulated For smaller challenge size also, it also shows better results
for ASICs only and they are not suitable for FPGAs. than the traditional Arbiter PUF.

Previously in their work, researchers have tried to combine

both Strong and Weak PUF to create a new PUF with R EFERENCES
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