Design of a new 3-bit Flash Analog to Digital Converter (ADC)

E. O. Ogunti and F. J. Omotayo

Department of Electrical/Electronic Engineering

Federal University of Technology, Akure, Nigeria

Abstract

Resolution and circuit complexity causing high power consumption are the major
problems with Flash ADC, and these have limited its application despite its speed of conversion,
which is the fastest among all types of Analog to Digital Converters. In this paper, a
conventional 3-Bit Flash ADC was designed and compared to a new design method using
voltage division technique in arranging two resistors in series in place of the bit comparator
required by the conventional Flash ADC architecture in order to combat the problem of circuit
complexity and power consumption. Two comparators were successfully used instead of seven
which resulted in 92% reduction in power consumption. The design and analysis reported in this
paper was carried out using National Instruments Multism11.0 and Ultiboard11.0 computer
aided design software for the schematics and Printed Circuit Board (PCB) layout respectively.
Keywords: ADC, new design, power consumption.

analog systems (Gamad et al, 2010) and it is

1.0 INTRODUCTION this superior performance that is behind the

release of most modern electronics in the

Analog to Digital Converters (ADCs)
digital form.
had proved to be inevitable in this world that

transmission, reception and storage of data Generally, an ADC encodes an

have become digital whereas signals around analog signal into a digital word.

us: sound, light, temperature, images, etc are Conventional ADCs work by sampling time

analog in nature. ADCs are currently being varying analog signal at a sampling rate high

adopted in many application fields to enough to fully resolve the highest

improve digital systems, which achieve frequency components. According to the

superior performances when compared to sampling theorem, the minimum sampling

rate is twice the frequency of the highest Flash ADC has proved to be the

frequency contained in the signal source fastest of all the ADCs because it uses

(Stephen et al, 1999). comparators that are connected in parallel

thereby allowing all the magnitude level of

ADC applications can be found in data
the analog signal to be sampled at once. The
acquisition systems, measurement systems
major problems with flash ADCs, however,
and digital communication systems (Gamad
are that of: (1) resolution and (2) circuit
et al, 2010). In view of the wide applications
complexity (Staffin and Lohman, 1953). The
of ADC, it has attracted much design
latter problem has actually reduced the
interest over the years whereby many design
number of bits that can be made, therefore
architectures and techniques have been
limiting the use of flash ADC to designs
developed such as: Successive
where speed and not accuracy is the highest
approximation ADC (Walt, 2003),
design priority and this is the reason why it
Subranging and Pipeline ADC (Staffin and
remains as the only ADC in use in video
Lohman, 1956), Serial Bit-per Stage Binary
signal conversion (Robert et al, 1992). It is
ADC (Smith, 1953), Serial Bit-per Stage
also used in applications that require very
Grey code or Folding ADC (Walt, 2003),
large bandwidth that cannot be addressed in
Counting ADC (Bernard and Claude, 1957);
any other way such as in data acquisition,
Sigma-Delta ADC (Max, 1991) and Flash
satellite communication, radar processing,
ADC (Paul. 1926). Of all the ADCs, the
sampling oscilloscope and high-density disk
Successive approximation type has the
drives (Gamad et al, 2010).
maximum conversion time and is the most

commonly used because of its low cost Considering the usefulness of flash

(Maxim, 2001). ADC in most applications requiring speed,

there is a need to improve on the 2.2 Methodology

disadvantages of the ADC like its resolution, 2.2.1 ADC Designs

circuit complexity and large number of A generic 3-bit Flash ADC using

comparators (2n - 1), where n is the number general Flash ADC architecture Figure 1

of bits, meaning that for 4-bit flash ADC was first designed. This architecture is based

fifteen comparators and sixteen resistors are on 2n-1 numbers of comparators, 2n resistors

needed, and for 8-bit, two hundred and fifty

five comparators and two hundred and fifty

six resistors will be required. This makes it

non practicable for large bit applications

Fig 1: Block diagram for ADC design
(Walt, 2003). The problems addressed in

this study are resolution problem and the use in the voltage divider circuit and resolution

of large number of comparators, causing voltage of Vfull scale/2

n
-1, where n is the

large power consumption in return. number of bit or say resolution of the ADC.

A second design model with the

2. Materials and Method
goals of reducing power consumption while
2.1 Software
improving the resolution of Flash ADC was
The computer aided design tool used
attempted. The strategy was to reduce the
in this work is National Instrument design
number of comparators since the power
suite 11.0 which contains Multisim for
consumed by the ADC is directly related to
schematic capture and Ultiboard for printed
the number of comparators.
circuit board layout.
2.2.2 Low power Flash ADC model design � = resistor on the output loop, and

This model also follows the block �� = resistor on the input loop

diagram in Figure 1. The major R2k = R1k and n = number of bits

improvement is that only two comparators �� = analog signal

were used in the comparator bank (Fig. 2).. Vo = output signal to encoder

The − comparators usually required �

Vo = ⁄� + � * �� Equation 2
�
using the general architecture was reduced
Thus, 2n – 3 resistor ratio with two (2)
to 2 by using a voltage divider circuit. Each
comparators and three (3) resistors are
voltage divider circuit was designed so as to
needed to achieve any n-bit flash ADC.
be able to generate the discrete level of
Where V31 is the voltage that will turn ON
voltages that is required to generate the
the TTL gate at the encoder circuit and V3 is
accuracy of 1V/LSB resolution levels with
the voltage discrete level for 2.5V.
1/2LSB quantization error as in the early
2.2.3 PCB Layout
design. To be able to turn ON the TTL
The design schematics were exported to
gates in the encoding circuit (Fig. 3), a
Ultiboard11.0 for the PCB design. The PCB
minimum voltage of 2.5 V is required, and
settings used for these designs are:
this is the value that each voltage divider
i. Footprint for 14-pin ICs: DIP14A;
circuit need to output. The resistor ratio that
ii. Footprint for 8-pin ICs: DIP8A;
is to be used to replace a comparator is
iii. Footprint for resistors: RES900-
given by equation 1.
300X200;
� .5 ∗ � �
= � �� iv. Trace width: 25mil;
�� ��

Where m = 0.001, 1, 2…2n – 3 v. Board technology: through the hole

K = 1, 2, 3… − (TH);
 vi. Board size: 3inches by 2.7 inches. sinusoidal signal. The equation 3 guides this

behavior.

3. Results and Discussion.

max = � ��
���
3.1 Model Validation
Where Tc is the ADC conversion time and n
DC and sinusoidal signal of different
is the number of bit. �� depends on the
amplitudes ranging from 0.5V to 7V were
propagation delay of the comparators and
used as input signals to check the accuracy
will continue to decrease as technology
of the ADC circuit. BCD and HEX output
continues to scale downwards.
display drivers were used to display the
3.3 Power Consumption
digital word as it will be use in any
The greatest achievement of this
application circuit. The ADC was able to
design is in the reduction of power
correctly convert the analog input signal to
consumption and in the reduction of
digital output. The sinusoidal signal required
complexity of the flash ADC architecture.
DC offset for the correct operation of the
The reduction in the − requirement of
ADC.
the number of comparators has greatly
3.2 Maximum frequency consideration
reduced the complexity of the circuitry of
In order to avoid aperture error, error
the ADC and as a result of the number of
that sets in when analog input voltage
gates and the amount of power dissipation.
changes more than ±1/2LSB, the maximum
The standard ADC dissipates about 261 mW
input frequency of the analog signal is
while the resistor based ADC dissipates
always specified. Thus, for this model, after
about 20 mW per conversion cycle. Other
testing, the maximum analog input
performance metrics of the two designs are
frequency was fixed at 7MHz when using
presented in table 1.
3.4 Printed Circuit Board (PCB) Layout the exposure and etching of the board. The

To implement this design the PCB completed PCB designs for the standard

layout was transformed to physical design ADC and the resistor based ADC without

by first printing the circuit layout onto a the mounted circuit is presented in figures 3

glossy paper using a document laser jet and 4 respectively.

printer. Using PCB cutting machine, photo- The validation test performed using the

resist board was pilled and cut into the board confirms the simulation results

actual design board. Further steps involve

Table 1: Summary of performance metrics of the conventional and the new ADC design.

PARAMETERS MODEL1 MODEL2

Resolution (Bits) 3 3

Minimum required voltage 8V 2.9V

Power Consumption 261.12mW 20.16mW

Number of comparators 7 2

Maximum Input Frequency 7MHz 7MHz

Output Current 10mA 10mA

Output Voltage 5V 5V

Voltage divider circuit resistor ratio in place of comparator nill 2n – 3

Number of resistors needed for Vref voltage divider circuit 2n 3

Conversion time Approx. 8.4ns Approx. 8.4ns

Sampling rate 119MHz 119MHz

 R 23 R 24

4Ω 2.5Ω

R 21 R 22

3Ω 2.5Ω

R8 R 20

2Ω 2.5Ω

R6 R7

1Ω 2.5Ω

R4 R5

0.001Ω 2.5Ω

Vre f
R3 ENC_2
1 8 Co mp 2
5Ω C8
C7 D2 D2
2 C6 D1
C5 D0
7
C4
D1
3 C3
C2
C1 D0
GND
4 5 6 LT 1719CS8 VSS
8-3-line priority encoder
R2
10Ω
1 8 Co mp 1
2
7
3

R1 4 5 6 LT 1719CS8
5Ω
GN D

Vin

VSS

Figure 2: Circuit structure of the proposed new flash ADC architecture

Figure 3: 8- To- 3 Line Priority Encoder Circuit using individual gates
Fig. 4: PCB implementation of conventional flash ADC

Fig. 5: PCB Implementation of flash ADC

4. Conclusion 5. References

This study has been able to Bernard, M.O. and Claude, E.S.

successfully implement the general (1957),"Communication System Employing

architecture of a new 3-bit Flash ADC and Pulse Code Modulation", U.S. Patent

its power consumption has been improved to 2,801,281

the range of approximately 92%. It has been

Gamad, R.S. and Kushwa, C.B. (2010):
shown that the total number of comparators
“New Design Technique of 6-Bit Flash
used for realizing any bit of Flash ADC can
A/D Converter”, International Journal
be put at two and the remaining can be
of Electronic Engineering Research,
replace with voltage divider circuit using
2(1): 9-14
two resistors, with the single disadvantage
Max, W.H. (1991), "Principles of
of inflexible sampling rate. Considering the
Oversampling A/D Conversion", Journal
fact that Flash Analog to Digital Converter
Audio Engineering Society, Vol. 39, No.
is the fastest of all types of Analog to Digital
1/2, pp. 3-26
Converters, this new ADC design can be use

in applications that require speed and low Maxim (2001), “Understanding Flash

power consumption. ADCs”, Application Note 810, Maxim

Integrated Products

Paul, M. R. (1926), "Facsimile Telegraph

System", U.S. Patent 1,608,527.

Robert, F.C. and Fredrick, F.D. (1992), Staffin, R. and Lohman, R. D. (1956),

“Operational Amplifiers and Linear “Signal Amplitude Quantizer”, U.S. Patent

Integrated Circuits”, 4th edition, Prentice- 2,869,079.

Hall of India Private Limited, New Delhi, Stephen, K and Peter, X (1999) “Digital

Pp 401-418 Signal Processing Handbook”, CRC Press,

Smith, B. D. (1953), "Coding by Feedback LLC, London

Methods", Proceedings of the I. R. E., Vol.

Walt, K. (2003), “Mixed signal and DSP
41, pp. 1053-1058
design techniques”, Elsevier Science, USA.