COMPUTER

ORGANIZATION
AND
ARCHITECTURE

Text Book – Carl Hamacher

1
 Unit –I ; Chapter -1

BASIC STRUCTURE OF COMPUTERS

2
COMPUTER TYPES

• Computer is a fast electronic calculating machine that

accepts digitized input information, processes it
according to the list of stored instructions, and
produces the resulting output information.

• Computers are classified based on the parameters

like
• Speed of operation
• Cost
• Computational power
• Type of application
Computer types..
• PERSONAL or DESK TOP COMPUTERS
• Processing & storage units, visual display & audio units, keyboard
• Storage media‐Hard disks, CD‐ROMs
• Eg: Personal computers used in homes and offices
• Advantage: Cost effective, easy to operate, suitable for general purpose
educational or business application
• NOTEBOOK COMPUTERS
• Compact form of personal computer (laptop)
• Advantage is portability
• WORK STATIONS
• More computational power than PC
• Costlier
• Used to solve complex problems which arises in engineering
application (graphics, CAD/CAM etc)
• SERVERS and SUPERCOMPUTERS
• Servers – low end systems Supercomputers –High end Systems
• Servers- have sizeable database storage and capable of handling large no.
of requests to access data.
• Supercomputers –capable of large-scale numerical calculations required in
applications such as weather forecasting, and aircraft design and
simulation.
Functional Units

Input Arithmetic
and logic
Memory

Output Control

I/O Processor
5
Input Unit

• Input Unit reads the data

• The most common Input devices are Keyboard,

joystick, trackballs, microphone and mouse

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Output Unit

• Counterpart of Input unit

• Its function is to send processed results to outside

world

• The familiar example of output device is printer

(various types)

7
Memory Unit
• The function of memory unit is to store programs and data
• There are 2 classes of storage:
• Primary Storage:
• Fast memory that operates at electronic speeds
• The memory contains a large number of semiconductor storage cells,
each capable of storing 1 bit of information
• These cells are processed in groups of fixed size called word
• The number of bits in each word is known as word length
• Range from 16 to 64 bits
• To provide easy access to any word in the memory, a distinct
address is associated with each word location
• Addresses are numbers that identify successive locations

8
Memory Unit

• Memory in which any location can be reached in a short and

fixed amount of time after specifying its address is RAM

• Time required to access one word is called the memory access

time

• Memory of a computer is normally implemented as a memory

hierarchy of 3 or 4 levels of semiconductor RAM units with
different speeds & sizes

• The small, fast, units are called caches

• The largest & slowest unit is referred to as the main memory
• Primary storage is expensive

9
Memory Unit

• Secondary Storage:
• Is used when large amount of data and many programs have to be
stored
• It contains infrequently accessed information
• Additional & cheaper memory
• Ex: Magnetic disks and tapes & optical disks (CD-ROMs)

10
Arithmetic And Logic Unit

• ALU performs all the arithmetic and logic operations

• For ex: addition, multiplication, division, comparison etc

• Any operation is initiated by bringing the required operands

into the processor, where the operation is performed by the
ALU

• When operands are brought into the processor, they are

stored in high- speed storage elements called registers

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Arithmetic and Logic Unit (ALU)

• Each register can store one word of data

• Access time to registers are faster than cache unit

• CU (control unit) & ALU are many times faster than

other devices connected to a computer system
• This enables a single processor to control a number of
external devices such as keyboards, displays, magnetic &
optical disks, sensors & mechanical controllers

12
Control Unit (CU)

• It controls the entire operations of the computer

• The control unit is the nerve centre that sends control signals
to other units and senses their states
• The timing signals that govern the I/O transfers are
generated by control circuits
• Timing signals are signals that determine when a given
action is to take place
• Data transfers b/w processor & memory are also controlled
by CU through timing signals
• A large set of control lines (wires) carries the signals used for
timing & synchronization of events in all units

13
Operation of a Computer - Summarized

• The computer accepts information in the form of pgms &

data through an I/P unit & stores it in the memory

• Information stored in the memory is fetched, under pgm

control, into an ALU, where it is processed

• Processed information leaves the computer through an O/P

unit

• All activities inside the machine are directed by the CU

14
Information Vs Instructions

• Instructions/ Machine instructions :

• Are explicit commands that
• Governs transfer of information within the computer as well as
between computer and its I/O devices
• Specify arithmetic and logic operations to be performed
• Data:
• Numbers and encoded characters that are used as operands by the
instructions
• Any digital information
• Programs can also be considered as data if it is to be processed by
another pgm
• Ex: Compiling a HLL source pgm into machine language pgm, called the
object pgm
(Source pgm is I/P data to compiler & object pgm is O/P data)
• The processed data is called information

15
Information Vs Instructions

• Information must be encoded in a suitable format

• Each number, char, or instruction is encoded as a string of
binary digits called bits, each having either 0 or 1
• Encoding Schemes:
• BCD (Binary - Coded Decimal)
• Each decimal digit is encoded by 4 bits
• ASCII (American standard Code for Information
Interchange)
• Each char is represented as a 7-bit code
• EBCDIC ( Extended Binary- Coded Decimal Interchange
Code)
• 8 bits are used to denote a char

16
 Basic Operational Concepts

• For processing, individual instructions are brought from memory into

the processor, which executes the specified operations
• Data to be used as operands are also stored in memory
• A typical instruction may be:
Add LOC, R0
• Adds the operand at memory location LOC to the operand in register R0 and
store the result in R0 (i.e R0=R0+LOC)
• The original content of LOC is preserved, whereas R0 is overwritten
• In some computers, the above operation requires two instructions
Load LOC, R1
Add R1,R0
• The first instruction transfers the contents of LOC into the processor
register R1
• The second instruction adds the contents of R1 and R0 and places the content
in R0

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Connection between the processor and memory

MAR - Memory Address Register PC - Program Counter

MDR - Memory Data Register IR - Instruction Register
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Different parts of a processor

• CPU = ALU + CU + registers

• Diff: types of registers are:
• IR (instruction register):
• Holds the instruction that is currently being executed
• Its o/p is available to control circuits, which generate the timing signals that
control the various processing elements involved in executing the instruction
• PC (program counter):
• Keeps track of the execution of a pgm
• Contains the memory address of next instruction to be fetched & executed
• During the execution of an instruction, the contents of PC are updated to
correspond to the address of next instruction that is to be fetched from the
memory
• PC points to the next instruction that is to be fetched from memory

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Different parts of a processor

• n general- purpose registers (R0 thru’ Rn-1):

• are used for holding data, intermediate results of operations.
• They are also known as scratch-pad registers.

• MAR (memory address register):

• Facilitates communication with memory
• Holds the address of the location to be accessed
• MDR (memory data register):
• Facilitates communication with memory
• Contains data to be written into or read out of the addressed location

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Execution of an instruction

• Execution of an instruction by CPU during pgm execution

involves the following steps:
• The CU takes the address of the next instruction to be executed from
the PC register & reads instruction from corresponding memory
address into the instruction register of CU
• The CU sends the operation part & address part of instruction to the
decoder & MAR respectively
• The decoder interprets the instruction and accordingly the CU sends
signals to the appropriate unit which needs to be involved in carrying
out the task specified in the instruction
• Ex: if it is arithmetic/logical operation, the signal is sent to ALU
• As each instruction is executed, the address of the next instruction to
be executed will be automatically loaded into the PC register & steps 1
to 4 are repeated

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Steps involving Instruction Fetch & Execution

• Pgms reside in the memory and usually get there

through the i/p unit

INSTRUCTION FETCH :

• Execution of a program starts by setting the PC to

point to the first instruction of the program

• The contents of PC are transferred to the MAR

and a Read control signal is sent to the memory

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Steps involving Instruction Fetch & Execution

• The addressed word (here it is the first instruction of

the program) is read out of memory and loaded into
the MDR

• The contents of MDR are transferred to the

IR
• Now the instruction is ready to be decoded &
executed

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Steps involving Instruction Fetch & Execution

INSTRUCTION EXECUTION :

• The operation field of the instruction in IR is examined to determine the

type of operation to be performed by the ALU

• The specified operation is performed by fetching the operand(s) from

the memory locations or from GP registers in the processor

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Steps involving Instruction Fetch & Execution

• Fetching the operands from the memory requires

sending the memory location address to the MAR and
initiating a Read cycle

• The operand is read from the memory into the MDR

and then from MDR to the ALU

• The ALU performs the desired operation on one or

more operands fetched in this manner and sends the
result either to memory location or to a GP register

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Steps involving Instruction Fetch & Execution

• If the result of this operation is to be stored in the

memory, then the result is sent to MDR

• The address of the location where the result is to be

stored is sent to MAR and a Write cycle is initiated

• Thus, the execute cycle ends for the current instruction

and the PC is incremented to point to the next
instruction for a new fetch cycle.

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Execution of an instruction

• Normal execution of pgms may be preempted if

some device requires urgent servicing
• To deal with the situation immediately, normal
execution of current pgm must be interrupted
• To do this, the device raises an interrupt signal
• Interrupt
• Is a request from an I/O device for service by the
processor
• Processor provides the requested service by
executing an appropriate interrupt-service routine
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Steps to Execute an Instruction-summary
1) The address of first instruction (to be executed) gets loaded into PC.
2) The contents of PC (i.e. address) are transferred to the MAR & control-unit issues Read
signal to memory.
3) After certain amount of elapsed time, the first instruction is read out of memory and placed
into MDR.
4) Next, the contents of MDR are transferred to IR. At this point, the instruction can be
decoded & executed.
5) To fetch an operand, it's address is placed into MAR & control-unit issues Read signal. As a
result, the operand is transferred from memory into MDR, and then it is transferred from
MDR to ALU.
6) Likewise required number of operands is fetched into processor.
7) Finally, ALU performs the desired operation.
8) If the result of this operation is to be stored in the memory, then the result is sent to the
MDR.
9) The address of the location where the result is to be stored is sent to the MAR and a Write
cycle is initiated.
10) At some point during execution, contents of PC are incremented to point to next instruction
in the program.
 Computer Instructions
• Assembly Language • Register Transfer Notation

• MOVE NUM1,R1 • R1  [NUM1]

• MOVE #1,R2 • R2  1

• ADD #1,R1 • R1  1 + [R1]

• ADD R1,R2 • R2  [R1] + [R2]

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The “fetch-execute cycle” – Example Instruction
MOVE NUM1,R1

• Fetch • Execute
• MAR  [PC] • MAR  NUM1
• PC  [PC] + 1 • MDR  [MEM([MAR])]
• MDR  [MEM([MAR])] • R1  [MDR]
• IR  [MDR]

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 Another Example
ADD #1,R1

• Fetch • Execute
• MAR  [PC] • R1  1 + [R1]
• PC  [PC] + 1
• MDR  [MEM([MAR])]
• IR  [MDR]

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Bus Structures

• A group of lines that serves as a connecting path for several devices is

called a bus
• Bus must have lines for
• Data
• Address
• Control

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Single-bus Structure
Input Output Memory Processor

• The simplest way to interconnect functional units is to use a

single bus
• Since the bus can be used for only one transfer at a time,
only two units can actively use the bus at any given time

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Single-bus Structure

34
Simplified Illustration of a Bus

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Single-bus Structure

• It’s basic feature is it’s low cost and flexibility for attaching
peripheral devices

• Systems containing multiple buses increase it’s performance

capability (by concurrency in operations) but at an increased
cost

• Buffer registers within the devices

• Smooths out the differences in speed among processor, memory
and i/o devices
• holds the information during transfers
• Allows processor to switch rapidly from one device to
another
• Ex: use of printer buffer during printing 36
Single-bus Structure

• Transfer of a character from a processor to a

character printer
• Processor sends the character to the printer buffer

• Once buffer is loaded, the printer can start printing without intervention by the
processor

• Prevents high-speed processor from being blocked to a slow i/o device during
a sequence of transfers.

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Two-Bus Structure

I/O bus

Input

Memory

Processor Memory bus

Output

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Two-Bus Structure
• The processor interacts with the memory through a
memory bus and handles input/output functions over
I/O bus.

• I/O and memory access can be performed

simultaneously

• The main advantage of this structure is good

operating speed but on account of more cost.

• The memory bus is also called the front side bus, local bus, system bus,, processor
bus or host bus.
• Connects CPU with memory
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Performance

• The most important measure of the performance in

a computer is how quickly it can execute programs

• The speed of execution depends on the

• design of its hardware
• machine language instructions
• compiler

• For better performance all components should be

designed in a coordinated way
40
Performance

• Performance of computer = program execution

speed
• Elapsed time
• Total time required to execute the pgm
• Measure of computer’s performance
• Depends on speed of processor, disk & I/O
• Processor time
• Period during which the processor is active to execute the
pgm

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The Processor Cache

Main Cache
memory memory Processor

Bus

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The Processor Cache

• At the start of execution, all pgm instructions & the required data
are stored in main memory

• As execution proceeds, instructions are fetched one by one over the

bus into the processor, and a copy is placed in the cache

• When the execution of an instruction calls for data located in the

main memory, the data are fetched & a copy is placed in the cache

• Later, if the same instruction/ data item are needed a second time,
it is read directly from the cache

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The Processor Cache

• A program will be executed faster if the movement of instructions and

data between the processor and main memory is minimized, which is
achieved by using cache

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 Processor Clock

• Processor circuits are controlled by timing signal called a clock

• The regular time intervals are known as clock cycles

• To execute machine instructions the processor divides the action

into a sequence of steps such that each step can be completed in
one clock cycle

• The length T of one clock cycle is an important performance

parameter of processor
• Clock rate or frequency, R=1/T, measured in cycles/sec (Hertz
or Hz)

45
Processor Clock
• Terminology:
• Million - Mega (M) = 106

• Billion - Giga (G) = 109

• f=500 million cycles/sec, T=?

• f= 500 X 106 = 500 MHz
• Clock period T=1/f
=1/ (500 X 106 )= 2 X 10-9 = 2ns

• T= 0.8 ns, f=?

• Clock Rate f=1/T = 1/ (0.8 X 10-9 )= (1.25 X 109 )
= 1.25 GHz =1250 million cycles/sec
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 Basic Performance Equation
• ET=(N × S) / R
• ET is the processor time required to execute a program
• N is the actual number of instructions executed
• S is the average number of basic steps needed to execute one
machine instruction
• R is the clock rate (or frequency f)

• To achieve high performance, reduce the value of ET,

which means reducing N & S and increasing R

47
 Units of Performance Measurement
• MIPS: Million instructions per second

• Megaflops: Million floating point operations per second

• Megahertz: Million clock cycles per second

48
Techniques to improve performance

• Pipelining and Superscalar Operation

➢ Decreases S

• Increasing the clock rate

➢ Increases R

• Choice of Instruction Set : CISC or RISC

➢ Affects N and S

• Use of optimizing compiler

➢ Decreases N

49
Pipelining and Superscalar Operation

• Assumed that instructions are executed one after another

• Improvement in performance can be achieved by

overlapping the successive instructions using a
technique called pipelining

50
Pipelining and Superscalar Operation

• Consider the instruction Add R1,R2,R3

• Which adds the contents of registers R1 & R2 and places the
sum into R3

• Contents of R1 & R2 are first transferred to the inputs of ALU

• After add operation is performed, sum is transferred to R3

• The processor can read the next instruction while the addition
operation is being performed

• Then, if that instruction also uses ALU, it’s operands can be

transferred to the ALU inputs at the same time that the result of
Add instruction is being transferred to R3

51
Pipelining
I1 I2 I3

F1 E1 F2 E2 F3 E3

Sequential Execution

Clock 1 2 3 4

I1 F1 E1
Legends:
I2 F2 E2 I – instruction
F – Fetch
I3 E- Execute
F3 E3

Pipelined Execution 52
Pipelining

• For purpose of computing, effective value of S is 1 (can’t

attain in practice)

• Pipelining increases rate of executing instructions significantly

& causes the value of S to approach 1

• A higher degree of concurrency can be achieved if multiple

instruction pipelines are implemented in the processor
• Means that multiple functional units are used, creating parallel paths
through which different instructions can be executed in parallel
• With this, it becomes possible to start the execution of several
instructions in every clock cycle
• This mode of operation is called Superscalar execution

53
A 2-issue Superscalar execution
• Fetch 2 instructions every clock

1 2 3 4 5
Time [clocks]

I1 F1 E1
I2 F2 E2
I3 F3 E3
I4 F4 E4
I5 F5 E5
I6 F6 E6
Instr.uctions

54
 Clock Rate

• There are 2 possibilities for increasing the clock rate, R

• First, improving the Integrated Circuit (IC) technology makes logic circuits faster,
which reduces the time needed to complete a basic step
• This allows the clock period, P to be reduced and the clock rate, R to be increased
• Second, reducing the amount of processing done in one basic step makes it
possible to reduce clock period, P

55
Instruction Set: CISC & RISC

• Simple instructions require small number of basic steps to execute

(Reduced Instruction Set Computers)

• Complex instructions involve a larger number of basic steps

(Complex Instruction Set Computers)

• For RISC a large number of instruction is needed, lead to large

value for N, and small value for S

• For CISC individual instructions perform more complex operations

with fewer instructions, leading to lower value of N and larger
value of S

• It is not obvious if one choice is better than the other

56
CISC vs RISC

• Complex Instruction Set Computers (CISC)

• Smaller N
• Larger S
• Reduced Instruction Set Computers (RISC)
• Larger N
• Smaller S
• Easier to Pipeline

57
Compiler

• High-level Language → Machine Language

• To reduce N, suitable machine instruction set + compiler that
makes good use of it
• An optimizing compiler must reduce the number of clock cycles
needed to execute a program
• The number of clock cycles is dependent not only on the choice of
instructions but also on the order in which they appear in the
program
• The compiler may rearrange the instructions to achieve better
performance
• Such changes must not affect the result of the computation
• Ultimate objective is to reduce the total no: of clock cycles needed
to perform a required pgmg task

58
 Performance Measurement
• The only parameter that describes the performance of a
computer is the execution time T

• A nonprofit organization called System Performance Evaluation

Corporation (SPEC) provides benchmark programs for different
application domains, together with test results for many
commercially available computers

• Benchmark programs - standardized set of programs used for

measuring performance

59
 Performance Measurement

• A Benchmark Program is compiled and run on computer under test- note

the running time

• The same pgm is compiled and run on a reference computer

• Compute the SPEC ratio as

running time on the refence computer

SPEC Ratio =
running time on the computer under test

SPEC ratio of 50 means comp. under test is 50 times faster than ref. comp.

60
 Performance Measurement

• The above process is repeated for all pgms in the SPEC

suite
• The overall SPEC ratio for the computer
1

 n 
SPEC ratio =   SPECi 
n

 i =1 

Where,
n – number of pgms in the suite
SPECi – ratio for the pgm i in the suite
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 CHAPTER 2

MACHINE INSTRUCTIONS
AND PROGARMS

62
Memory Locations & Addresses
• Word - group of n bits; n is word length
• Word length ranges from 16 to 64 bits

63
64
Encoded information in a 32 bit word

65
Contd..

• If word length = 32 bits, it can store

• One 32 bit 2’s complement no.
• or four ASCII characters
• Address – a number used to access a memory location
• k bit address – 2k addresses
• Used to address 0 to 2k-1 successive locations

66
 Address Space
• Address Space of the computer :- The maximum no. of addressable
locations
• With
• k bit address, Address Space= 2k addresses
• 24 bit, A.S=224=16M
• Note : 210=1K
220=1M
230=1G
240=1T

67
Units of Memory

68
Example 1

69
Example 2

70
Memory Operations
• Two basic operations
• Load ( Read or Fetch )
• copy content of a memory location to processor
• Memory contents remain unchanged
• Store (or Write )
• Transfer an information item from processor to a memory location
• Destroys the former contents of that location
• Processor sends the address of desired mem loc
• Read/write one word/byte at a time
• Processor reg. – capable of holding a word used as
source/ destination of transfer.
• When a Byte is to be transferred
- byte located in lower-order position in the reg. is transferred
71
Instructions & Instruction Sequencing

A computer must have instructions to

perform four types of operations:
➢ Data transfers between the memory and the processor registers
➢ Arithmetic and logic operations on data
➢ Program sequencing and control
➢ I/O transfers

72
• Two types of notations are used to represent the instructions

• Register Transfer Notation (RTN)

• Assembly Language Notation

73
 REGISTER TRANFER NOTATION
• Locations involved in Data transfer are:
Location Symbolic names
Memory LOC, A, NUM
Processor register R0, R5
I/O sub system registers DATAIN, OUTSTATUS

• A name stands for hardware address of a location

• Content of a location – indicated by Square brackets
around the name eg, [LOC] , [R0], [DATAIN]

74
 RTN - Examples
• R1  [LOC]
Means that the contents of location named LOC is transferred into processor
register R1.

• R3  [R1] + [R2]
Add the contents of register R1 and R2, and then place the sum into register
R3

• RHS represents a value, LHS- name of a location where the value is to be

placed (overwritten)

75
ASSEMBLY LANGUAGE NOTATION

• Move LOC,R1
Means that the contents of location LOC is transferred into processor
register R1.

• Add R1,R2,R3
Add the contents of register R1 and R2, and then place the sum into
Register R3.

76
Instruction Execution
& Straight Line Sequencing
Consider a pgm. for C[A]+[B]

Assumptions on m/c features :

- Allows only one memory operand per instruction
- Has a number of registers
- Word length=32 bits
- Memory is byte addressable
- Each Instruction takes 4 bytes

77
Program C[A]+[B] in memory

78
 Straight Line Sequencing

• Place the address of first instruction ( i )

into PC
• Fetch & Execute this instruction
• Increment PC by 4 ( i.e, i+4 ), to point to
the next instruction
• Thus fetch & execute instructions one at a
time in the order of increasing
addresses
79
Executing a given instruction

• 2 phase procedure to execute an instruction

• Phase-1 : Instruction Fetch
• Phase-2 : Instruction Execute

• Instruction Fetch Phase :

• The instruction is fetched from the memory location whose address is in PC
• Place this instruction in the instruction register (IR)

80
 Contd…
• Instruction Execution Phase :
• The operation code of IR is decoded by control unit
• Specified operation is performed using ALU circuits
• Operation may also involve fetching operands from memory or Registers
• Result is stored in destination location
• Increment the contents of PC to point to next instruction

81
A straight-line pgm. to add a list of n numbers

82
Branching
Using a loop to add n numbers.

83
Contd..

• Program Loop : Straight line sequence of instructions executed as

many times as needed

• LOOP – Where the pgm. loop begins

• Branch > 0 – Where the pgm. loop ends

• Register R1 – used as the counter

- determines the number of loop iterations
- decremented by 1 each time through the loop

84
Contd..

• Branch instruction : Loads a new address to PC instead of the next

sequential address
• Branch target : The instruction at the new address
• Conditional Branch : Causes branch only if the specified condition is
satisfied
• Else execute next instruction in sequential order

85
Contd…

• Branch > 0 LOOP : a conditional branch

• Branch to location LOOP if the result of preceding instruction (ie
value in R1) > 0
• Branch doesn’t occur when value in R1=0 (ie at nth pass), and next
instruction ( Move ) is executed

86
Condition Codes
• Condition code flags : Indicate the data condition or
status after an arithmetic/logical operation

• A Flag is a one bit storage unit ( a flip flop )

• Flag is set to 1 or cleared to zero based on the result of

operation

• Condition Code Register / Status Register : is a

processor register which accommodates a group of Flags
87
 Commonly Used Flags of CCR
• N ( negative ) : Set to 1 if the result of
arithmetic/logical operation is negative; otherwise,
cleared to 0

• Z (zero) : Set to 1 if the result of arithmetic or logical

operation is 0; otherwise, cleared to 0

• N & Z flags may also be affected by data transfer

instructions such as Move, Load, or Store

• Enables conditional branching based on the value and

sign of the operand that was moved
88
Contd..
• V (overflow) : Set to 1 if arithmetic overflow occurs, else
cleared to 0

• Programmer can test V flag and branch to appropriate

routine to correct the problem
• Ex: BranchIfOverflow instruction

• C (carry) : Set to 1 if a carry-out results from MSB

position during an arithmetic operation, else cleared to 0

• Branch > 0 - means branch if neither N nor Z flag is

set to 1
89
Conditional Branch Instructions

• Example: A + (-B) A : 1 1 1 1 0 0 0 0 ….-16

• A: 1 1 1 1 0 0 0 0
• B: 0 0 0 1 0 1 0 0 +(−B): 1 1 1 0 1 1 0 0 ….-20
1 11011100 …. -36

C=1 Z=0
S=1
V=0

90
Acknowledgement
Internet

PPT edited by:

Dr. Raju K., Assoc. Prof.
CSE Dept, NMAMIT

91