CY7C67200

EZ-OTG™ Programmable USB

On-The-Go Host/Peripheral Controller
EZ-OTG™ Programmable USB On-The-Go Host/Peripheral Controller

EZ-OTG Features ■ Fast serial port supports from 9600 baud to 2.0M baud
■ SPI supports both master and slave
■ Single-chip programmable USB dual-role (Host/Peripheral)
controller with two configurable Serial Interface Engines (SIEs) ■ Supports 12 MHz external crystal or clock
and two USB ports
■ 2.7 V to 3.6 V power supply voltage
■ Supports USB OTG protocol
■ Package option: 48-pin FBGA
■ On-chip 48-MHz 16-bit processor with dynamically switchable
clock speed Typical Applications
■ Configurable IO block supports a variety of IO options or up to EZ-OTG is a very powerful and flexible dual-role USB controller
25 bits of General Purpose IO (GPIO) that supports a wide variety of applications. It is primarily
■ 4K × 16 internal mask ROM contains built-in BIOS that supports intended to enable USB OTG capability in applications such as:
a communication-ready state with access to I2C™ EEPROM ■ Cellular phones
interface, external ROM, UART, or USB
■ PDAs and pocket PCs
■ 8K x 16 internal RAM for code and data buffering
■ Video and digital still cameras
■ 16-bit parallel host port interface (HPI) with DMA/Mailbox data
path for an external processor to directly access all on-chip ■ MP3 players
memory and control on-chip SIEs
■ Mass storage devices

Logic Block Diagram – CY7C67200

CY7C67200

Timer 0 Timer 1
nRESET Control

Watchdog UART I/F

CY16
16-bit RISC CORE I2C
SHARED INPUT/OUTPUT PINS

Vbus, ID
OTG
EEPROM I/F
D+,D- USB-A

SIE1 HSS I/F

HOST/
Peripheral
USB Ports GPIO [24:0]
SPI I/F

D+,D- USB-A 4Kx16 8Kx16

ROM BIOS RAM
SIE2 HPI I/F

Mobile GPIO
X1
X2 PLL Power
Booster

Errata: For information on silicon errata, see “Errata” on page 84. Details include trigger conditions, devices affected, and proposed workaround.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-08014 Rev. *K Revised November 8, 2016
 CY7C67200

Contents
Introduction ....................................................................... 3 HSS Registers ........................................................... 47
Processor Core Functional Overview ............................. 3 HPI Registers ............................................................ 53
Processor .................................................................... 3 SPI Registers ............................................................ 57
Clocking ....................................................................... 3 UART Registers ........................................................ 65
Memory ....................................................................... 3 Pin Diagram ..................................................................... 67
Interrupts ..................................................................... 3 Pin Descriptions ............................................................. 67
General Timers and Watchdog Timer ......................... 3 Absolute Maximum Ratings .......................................... 69
Power Management .................................................... 3 Operating Conditions ..................................................... 69
Interface Descriptions ...................................................... 3 Crystal Requirements (XTALIN, XTALOUT) ................. 69
USB Interface .............................................................. 4 DC Characteristics ........................................................ 70
OTG Interface .............................................................. 4 USB Transceiver ....................................................... 71
General Purpose IO Interface ..................................... 4 AC Timing Characteristics ............................................. 71
UART Interface ............................................................ 4 Reset Timing ............................................................. 71
I2C EEPROM Interface ............................................... 5 Clock Timing ............................................................. 72
Serial Peripheral Interface ........................................... 5 I2C EEPROM Timing ............................................... 72
High-Speed Serial Interface ........................................ 5 HPI (Host Port Interface) Read Cycle Timing ............ 74
Host Port Interface (HPI) ............................................. 6 HSS BYTE Mode Transmit ........................................ 75
Charge Pump Interface ............................................... 6 HSS Block Mode Transmit ........................................ 75
Booster Interface ......................................................... 7 HSS BYTE and BLOCK Mode Receive .................... 75
Crystal Interface .......................................................... 8 Hardware CTS/RTS Handshake ............................... 76
Boot Configuration Interface ........................................ 8 Register Summary .......................................................... 77
Operational Modes ...................................................... 9 Ordering Information ...................................................... 81
Power Savings and Reset Description ......................... 10 Ordering Code Definitions ......................................... 81
Power Savings Mode Description ............................. 10 Package Diagram ............................................................ 82
Sleep ......................................................................... 10 Acronyms ........................................................................ 83
External (Remote) Wakeup Source ........................... 10 Document Conventions ................................................. 83
Power-On Reset (POR) Description .......................... 10 Units of Measure ....................................................... 83
Reset Pin ................................................................... 10 Errata ............................................................................... 84
USB Reset ................................................................. 10 Part Numbers Affected .............................................. 84
Memory Map .................................................................... 10 CY7C67200 Qualification Status ............................... 84
Mapping ..................................................................... 10 CY7C67200 Errata Summary .................................... 84
Internal Memory ........................................................ 11 Document History Page ................................................. 91
Registers ......................................................................... 11 Sales, Solutions, and Legal Information ...................... 93
Processor Control Registers ..................................... 11 Worldwide Sales and Design Support ....................... 93
Timer Registers ......................................................... 18 Products .................................................................... 93
General USB Registers ............................................. 20 PSoC®Solutions ....................................................... 93
USB Host Only Registers .......................................... 22 Cypress Developer Community ................................. 93
USB Device Only Registers ...................................... 30 Technical Support ..................................................... 93
OTG Control Registers .............................................. 42
GPIO Registers ......................................................... 43

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 CY7C67200

Introduction Memory
EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first USB EZ-OTG has a built-in 4K × 16 masked ROM and an 8K × 16
On-The-Go (OTG) host/peripheral controller. EZ-OTG is internal RAM. The masked ROM contains the EZ-OTG BIOS.
designed to easily interface to most high-performance CPUs to The internal RAM can be used for program code or data.
add USB host functionality. EZ-OTG has its own 16-bit RISC
Interrupts
processor to act as a coprocessor or operate in standalone
mode. EZ-OTG also has a programmable IO interface block EZ-OTG provides 128 interrupt vectors. The first 48 vectors are
allowing a wide range of interface options. hardware interrupts and the following 80 vectors are software
interrupts.
Processor Core Functional Overview
General Timers and Watchdog Timer
An overview of the processor core components are presented in
EZ-OTG has two built-in programmable timers and a watchdog
this section.
timer. All three timers can generate an interrupt to the EZ-OTG.
Processor
Power Management
EZ-OTG has a general purpose 16-bit embedded RISC
EZ-OTG has one main power-saving mode, Sleep. Sleep mode
processor that runs at 48 MHz.
pauses all operations and provides the lowest power state.
Clocking
Interface Descriptions
EZ-OTG requires a 12 MHz source for clocking. Either an
external crystal or TTL-level oscillator may be used. EZ-OTG has EZ-OTG has a variety of interface options for connectivity, with
an internal PLL that produces a 48 MHz internal clock from the several interface options available. See Table 1 to understand
12 MHz source. how the interfaces share pins and can coexist. Below are some
general guidelines:
■ I2C EEPROM and OTG do not conflict with any interfaces
■ HPI is mutually exclusive to HSS, SPI, and UART

Table 1. Interface Options for GPIO Pins

GPIO Pins HPI HSS SPI UART I2C OTG
GPIO31 SCL/SDA
GPIO30 SCL/SDA
GPIO29 OTGID
GPIO24 INT
GPIO23 nRD
GPIO22 nWR
GPIO21 nCS
GPIO20 A1
GPIO19 A0
GPIO15 D15 CTS
GPIO14 D14 RTS
GPIO13 D13 RXD
GPIO12 D12 TXD
GPIO11 D11 MOSI
GPIO10 D10 SCK
GPIO9 D9 nSSI
GPIO8 D8 MISO
GPIO7 D7 TX
GPIO6 D6 RX
GPIO5 D5
GPIO4 D4
GPIO3 D3
GPIO2 D2
GPIO1 D1
GPIO0 D0

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 CY7C67200

USB Interface OTG Interface

EZ-OTG has two built-in Host/Peripheral SIEs that each have a EZ-OTG has one USB port that is compatible with the USB
single USB transceiver, meeting the USB 2.0 specification re- On-The-Go supplement to the USB 2.0 specification. The USB
quirements for full and low speed (high speed is not supported). OTG port has various hardware features to support Session Re-
In Host mode, EZ-OTG supports two downstream ports; each quest Protocol (SRP) and Host Negotiation Protocol (HNP).
supports control, interrupt, bulk, and isochronous transfers. In OTG is only supported on USB PORT 1A.
Peripheral mode, EZ-OTG supports one peripheral port with
eight endpoints for each of the two SIEs. Endpoint 0 is dedicated OTG Features
as the control endpoint and only supports control transfers. End- ■ Internal Charge Pump to supply and control VBUS
points 1 though 7 support Interrupt, bulk (up to 64 bytes per pack-
et), or isochronous transfers (up to 1023 bytes per packet size). ■ VBUS Valid Status (above 4.4 V)
EZ-OTG also supports a combination of Host and Peripheral
ports simultaneously, as shown in Table 2. ■ VBUS Status for 2.4 V < VBUS < 0.8 V

Table 2. USB Port Configuration Options ■ ID Pin Status

Port Configurations Port 1A Port 2A ■ Switchable 2-Kohminternal discharge resistor on VBUS

OTG OTG – ■ Switchable 500-ohm internal pull-up resistor on VBUS
OTG + 1 Host OTG Host ■ Individually switchable internal pull-up and pull-down resistors
OTG + 1 Peripheral OTG Peripheral on the USB data lines
1 Host + 1 Peripheral Host Peripheral
OTG Pins
1 Host + 1 Peripheral Peripheral Host
Table 4. OTG Interface Pins
2 Hosts Host Host
1 Host Host – Pin Name Pin Number
1 Host – Host DM1A F2
2 Peripherals Peripheral Peripheral DP1A E3
1 Peripheral Peripheral – OTGVBUS C1
1 Peripheral – Peripheral OTGID F4
CSwitchA D1
USB Features CSwitchB D2
■ USB 2.0 compatible for full and low speed
General Purpose IO Interface
■ Up to two downstream USB host ports
EZ-OTG has up to 25 GPIO signals available. Several other op-
■ Up to two upstream USB peripheral ports tional interfaces use GPIO pins as well and may reduce the over-
all number of available GPIOs.
■ Configurable endpoint buffers (pointer and length), must reside
in internal RAM GPIO Description
■ Up to eight available peripheral endpoints (1 control endpoint) All Inputs are sampled asynchronously with state changes occur-
ring at a rate of up to two 48 MHz clock cycles. GPIO pins are
■ Supports Control, Interrupt, Bulk, and Isochronous transfers latched directly into registers, a single flip-flop.
■ Internal DMA channels for each endpoint
Unused Pin Descriptions
■ Internal pull up and pull down resistors Unused USB pins must be tri-stated with the D+ line pulled high
■ Internal Series termination resistors on USB data lines through the internal pull-up resistor and the D– line pulled low
through the internal pull-down resistor.
USB Pins Unused GPIO pins must be configured as outputs and driven
Table 3. USB Interface Pins low.
Pin Name Pin Number UART Interface
DM1A F2 EZ-OTG has a built-in UART interface. The UART interface [1]
DP1A E3 supports data rates from 900 to 115.2K baud. It can be used as
DM2A C2 a development port or for other interface requirements. The
UART interface is exposed through GPIO pins.
DP2A D3

Note
1. Errata: The UART is not designed to recognize framing errors. For more information, see the Errata on page 84.

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 CY7C67200

UART Features ■ Slave SPI signaling synchronization and filtering

■ Supports baud rates of 900 to 115.2K ■ Slave SPI clock rates up to 2 MHz
■ 8-N-1 ■ Maskable interrupts for block and byte transfer modes

UART Pins ■ Individual bit transfer for non-byte aligned serial communi-
cation in PIO mode
Table 5. UART Interface Pins
■ Programmable delay timing for the active/inactive master SPI
Pin Name Pin Number clock
TX B5 ■ Auto or manual control for master mode slave select signal
RX B4
■ Complete access to internal memory

I2C EEPROM Interface SPI Pins

EZ-OTG provides a master-only I2C interface for external serial The SPI port has a few different pin location options as shown in
EEPROMs. The serial EEPROM can be used to store Table 7. The pin location is selectable via the GPIO Control reg-
application-specific code and data. This I2C interface [2] is only ister [0xC006].
to be used for loading code out of EEPROM, it is not a general
Table 7. SPI Interface Pins
I2C interface. The I2C EEPROM interface is a BIOS
implementation and is exposed through GPIO pins. Refer to the Pin Name Pin Number
BIOS documentation for additional details on this interface.
nSSI F6 or C6
I2C EEPROM Features SCK D5
■ Supports EEPROMs up to 64 KB (512K bit) MOSI D4
■ Auto-detection of EEPROM size MISO C5

I2C EEPROM Pins High-Speed Serial Interface

Table 6. I2C EEPROM Interface Pins EZ-OTG provides an HSS interface. The HSS interface is a pro-
grammable serial connection with baud rate from 9600 baud to
Pin Name Pin Number
2M baud. The HSS interface supports both byte and block mode
SMALL EEPROM operations as well as hardware and software handshaking. Com-
SCK H3 plete control of EZ-OTG can be accomplished through this inter-
face via an extensible API and communication protocol. The
SDA F3 HSS interface can be exposed through GPIO pins or the External
LARGE EEPROM Memory port.
SCK F3 HSS Features
SDA H3
■ 8-bit, no parity code

Serial Peripheral Interface ■ Programmable baud rate from 9600 baud to 2M baud

EZ-OTG provides an SPI interface for added connectivity. ■ Selectable 1- or 2-stop bit on transmit
EZ-OTG may be configured as either an SPI master or SPI slave. ■ Programmable intercharacter gap timing for Block Transmit
The SPI interface can be exposed through GPIO pins or the Ex-
ternal Memory port. ■ 8-byte receive FIFO
SPI Features ■ Glitch filter on receive

■ Master or slave mode operation ■ Block mode transfer directly to/from EZ-OTG internal memory
(DMA transfer)
■ DMA block transfer and PIO byte transfer modes
■ Selectable CTS/RTS hardware signal handshake protocol
■ Full duplex or half duplex data communication
■ Selectable XON/XOFF software handshake protocol
■ 8-byte receive FIFO and 8-byte transmit FIFO
■ Programmable Receive interrupt, Block Transfer Done inter-
■ Selectable master SPI clock rates from 250 kHz to 12 MHz rupts
■ Selectable master SPI clock phase and polarity ■ Complete access to internal memory

Note
2. Errata: If, while the BIOS is loading fi rmware, the part is reset and at that time the EEPROM is drivi ng the SDA line low, the BIOS will configure the part for co-processor
mode instead of standalone mode. For more information, see the Errata on page 84.

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 CY7C67200

HSS Pins Table 9. HPI Interface Pins [3, 4] (continued)

Table 8. HSS Interface Pins Pin Name Pin Number
Pin Name Pin Number D15 F6
CTS F6 D14 E4
RTS E4 D13 E5
RX E5 D12 E6
TX E6 D11 D4
D10 D5
Host Port Interface (HPI) D9 C6
EZ-OTG has an HPI interface. The HPI interface provides DMA D8 C5
access to the EZ-OTG internal memory by an external host, plus D7 B5
a bidirectional mailbox register for supporting high-level commu-
nication protocols. This port is designed to be the primary D6 B4
high-speed connection to a host processor. Complete control of D5 C4
EZ-OTG can be accomplished through this interface via an D4 B3
extensible API and communication protocol. Other than the
hardware communication protocols, a host processor has D3 A3
identical control over EZ-Host whether connecting to the HPI or D2 C3
HSS port. The HPI interface is exposed through GPIO pins.
D1 A2
Note It should be noted that for up to 3 ms after BIOS starts
D0 B2
executing, GPIO[24:19] and GPIO[15:8] will be driven as outputs
for a test mode. If these pins need to be used as inputs, a series
resistor is required (10 ohm to 48 ohm is recommended). Refer The two HPI address pins are used to address one of four
to BIOS documentation for addition details. See section “Reset possible HPI port registers as shown in Table 10 below.
Pin” on page 10. Table 10. HPI Addressing
HPI Features HPI A[1:0] A1 A0
■ 16-bit data bus interface HPI Data 0 0
■ 16 MB/s throughput HPI Mailbox 0 1

■ Auto-increment of address pointer for fast block mode transfers HPI Address 1 0
HPI Status 1 1
■ Direct memory access (DMA) to internal memory
■ Bidirectional Mailbox register Charge Pump Interface
■ Byte Swapping VBUS for the USB On-The-Go (OTG) port can be produced by
EZ-OTG using its built-in charge pump and some external
■ Complete access to internal memory components. The circuit connections should look similar to
Figure 1 below.
■ Complete control of SIEs through HPI
Figure 1. Charge Pump
■ Dedicated HPI Status register
D2
HPI Pins D1

Table 9. HPI Interface Pins [3, 4] CSWITCHA

CY7C67200
Pin Name Pin Number
CSWITCHB
INT H4 C1
VBUS
nRD G4 OTGVBUS

nWR H5 C2

nCS G5
A1 H6
A0 F5

Notes
3. HPI_INT is for the Outgoing Mailbox Interrupt.
4. HPI strobes are negative logic sampled on rising edge.

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 CY7C67200

Component details: Component details:

■ D1 and D2: Schottky diodes with a current rating greater than ■ L1: Inductor with inductance of 10 µH and a current rating of at
60 mA. least 250 mA
■ C1: Ceramic capacitor with a capacitance of 0.1 µF. ■ D1: Schottky diode with a current rating of at least 250 mA
■ C2: Capacitor value must be no more that 6.5 µF since that is ■ C1: Tantalum or ceramic capacitor with a capacitance of at least
the maximum capacitance allowed by the USB OTG specifi- 2.2 µF
cation for a dual-role device. The minimum value of C2 is 1 µF. Figure 3 shows how to connect the power supply when the
There are no restrictions on the type of capacitor for C2. booster circuit is not being used.
If the VBUS charge pump circuit is not to be used, CSWITCHA, Figure 3. Power Supply Connection Without Booster
CSWITCHB, and OTGVBUS can be left unconnected.

Charge Pump Features BOOSTVcc

3.0V to 3.6V
■ Meets OTG Supplement Requirements, see Table 41, “DC Power Supply
Characteristics: Charge Pump,” on page 70.

Charge Pump Pins

VSWITCH
Table 11. Charge Pump Interface Pins
Pin Name Pin Number
OTGVBUS C1
CSwitchA D1 VCC
AVCC
CSwitchB D2

Booster Interface
EZ-OTG has an on-chip power booster circuit for use with power
supplies that range between 2.7 V and 3.6 V. The booster circuit Booster Pins
boosts the power to 3.3 V nominal to supply power for the entire
chip. The booster circuit requires an external inductor, diode, and Table 12. Charge Pump Interface Pins
capacitor. During power down mode, the circuit is disabled to Pin Name Pin Number
save power. Figure 2 shows how to connect the booster circuit.
BOOSTVcc F1
Figure 2. Power Supply Connection With Booster VSWITCH E2

BOOSTVcc
2.7V to 3.6V
L1 Power Supply

VSWITCH

D1

3.3V

VCC C1
AVCC

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 CY7C67200

Crystal Interface Boot Configuration Interface

The recommended crystal circuit to be used with EZ-OTG is EZ-OTG can boot into any one of four modes. The mode it boots
shown in Figure 4. If an oscillator is used instead of a crystal into is determined by the TTL voltage level of GPIO[31:30] at the
circuit, connect it to XTALIN and leave XTALOUT unconnected. time nRESET is deasserted. Table 14 shows the different boot
For further information on the crystal requirements, see Table 39, pin combinations possible. After a reset pin event occurs, the
“Crystal Requirements,” on page 69. BIOS bootup procedure executes for up to 3 ms. GPIO[31:30]
are sampled by the BIOS during bootup only. After bootup these
Figure 4. Crystal Interface pins are available to the application as GPIOs.
Table 14. Boot Configuration Interface
XTALIN GPIO31 GPIO30 Boot Mode
(Pin 39) (Pin 40)
0 0 Host Port Interface (HPI)

CY7C67200 Y1
0 1 High Speed Serial (HSS)
12MHz
Parallel Resonant 1 0 Serial Peripheral Interface (SPI, slave
Fundamental Mode mode)
500uW
20-33pf ±5% 1 1 I2C EEPROM (Standalone Mode)
XTALOUT
GPIO[31:30] must be pulled high or low, as needed, using
C1 = 22 pF C2 = 22 pF
resistors tied to VCC or GND with resistor values between 5K
ohm and 15K ohm. GPIO[31:30] must not be tied directly to VCC
or GND. Note that in Standalone mode, the pull ups on those two
pins are used for the serial I2C EEPROM (if implemented). The
resistors used for these pull ups must conform to the serial
EEPROM manufacturer's requirements.
Crystal Pins
If any mode other then standalone is chosen, EZ-OTG will be in
Table 13. Crystal Pins coprocessor mode. The device will power up with the appropriate
communication interface enabled according to its boot pins and
Pin Name Pin Number
wait idle until a coprocessor communicates with it. See the BIOS
XTALIN G3 documentation for greater detail on the boot process.
XTALOUT G2

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 CY7C67200

Operational Modes Standalone Mode

There are two modes of operation: Coprocessor and Stand- In standalone mode, there is no external processor connected to
alone. EZ-OTG. Instead, EZ-OTG’s own internal 16-bit CPU is the main
processor and firmware is typically downloaded from an
Coprocessor Mode EEPROM. Optionally, firmware may also be downloaded via
EZ-OTG can act as a coprocessor to an external host processor. USB. Refer to Table 14 for booting into standalone mode.
In this mode, an external host processor drives EZ-OTG and is After booting into standalone mode (GPIO[31:30] = ‘11’), the fol-
the main processor rather then EZ-OTG’s own 16-bit internal lowing pins are affected:
CPU. An external host processor may interface to EZ-OTG
through one of the following three interfaces in coprocessor ■ GPIO[31:30] are configured as output pins to examine the
mode: EEPROM contents.

■ HPI mode, a 16-bit parallel interface with up to 16 MBytes ■ GPIO[28:27] are enabled for debug UART mode.
transfer rate ■ GPIO[29] is configured as OTGID for OTG applications on
■ HSS mode, a serial interface with up to 2M baud transfer rate PORT1A.
❐ If OTGID is logic 1 then PORT1A (OTG) is configured as a
■ SPI mode, a serial interface with up to 2 Mbits/s transfer rate. USB peripheral.
At bootup GPIO[31:30] determine which of these three interfaces ❐ If OTGID is logic 0 then PORT1A (OTG) is configured as a
are used for coprocessor mode. Refer to Table 14 for details. USB host.
Bootloading begins from the selected interface after POR + 3 ms ■ Ports 1B, 2A, and 2B default as USB peripheral ports.
of BIOS bootup.
■ All other pins remain INPUT pins.

Minimum Hardware Requirements for Standalone Mode – Peripheral Only

Figure 5. Minimum Standalone Hardware Configuration – Peripheral Only

EZ-OTG
CY7C67200
Reset
VReg VCC, AVCC, nRESET
Logic
BoostVCC
VBus
D+ DPlus
Standard-B
or Mini-B D- DMinus
GND
SHIELD
Bootstrap Options
Vcc Vcc

10k 10k
GPIO[30] SCL*
GPIO[31] SDA*

Int. 16k x8
Code / Data
Bootloading Firmware
VCC
A0 Up to 64k x8 VCC
A1 EEPROM WP
A2 SCL
Reserved
GND SDA 22pf
XIN
GND, AGND, 12MHz
BoostGND
XOUT
22pf
*Bootloading begins after POR + 3ms BIOS bootup * Parallel Resonant
Fundamental Mode
*GPIO[31:30] 31 30
500uW
Up to 2k x8 SCL SDA
20-33pf ±5%
>2k x8 to 64k x8 SDA SCL

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 CY7C67200

Power Savings and Reset Description Upon wakeup, code begins executing within 200 ms, the time it
takes the PLL to stabilize.
The EZ-OTG modes and reset conditions are described in this
section. Table 15. wakeup Sources[5, 6]
Wakeup Source (if enabled) Event
Power Savings Mode Description
USB Resume D+/D– Signaling
EZ-OTG has one main power savings mode, Sleep. For detailed
information on Sleep mode; See section “Sleep”. OTGVBUS Level
Sleep mode is used for USB applications to support USB OTGID Any Edge
suspend and non USB applications as the main chip power down HPI Read
mode. HSS Read
In addition, EZ-OTG is capable of slowing down the CPU clock SPI Read
speed through the CPU Speed register [0xC008] without
affecting other peripheral timing. Reducing the CPU clock speed IRQ0 (GPIO 24) Any Edge
from 48 MHz to 24 MHz reduces the overall current draw by
around 8 mA while reducing it from 48 MHz to 3 MHz reduces Power-On Reset (POR) Description
the overall current draw by approximately 15 mA. The length of the power-on-reset event can be defined by (VCC
ramp to valid) + (Crystal start up). A typical application might
Sleep utilize a 12-ms power-on-reset event = ~7 ms + ~5 ms, respec-
Sleep mode is the main chip power down mode and is also used tively.
for USB suspend. Sleep mode is entered by setting the Sleep
Enable (bit 1) of the Power Control register [0xC00A]. During Reset Pin
Sleep mode (USB Suspend) the following events and states are The Reset pin is active low and requires a minimum pulse dura-
true: tion of sixteen 12-MHz clock cycles (1.3 ms). A reset event re-
stores all registers to their default POR settings. Code execution
■ GPIO pins maintain their configuration during sleep (in then begins 200 ms later at 0xFF00 with an immediate jump to
suspend). 0xE000, the start of BIOS.
■ External Memory Address pins are driven low. Note It should be noted that for up to 3 ms after BIOS starts
■ XTALOUT is turned off. executing, GPIO[24:19] and GPIO[15:8] will be driven as outputs
for a test mode. If these pins need to be used as inputs, a series
■ Internal PLL is turned off. resistor is required (10 ohm to 48 ohm is recommended). Refer
to BIOS documentation for addition details.
■ Firmware must disable the charge pump (OTG Control register
[0xC098]) causing OTGVBUS to drop below 0.2 V. Otherwise USB Reset
OTGVBUS will only drop to VCC – (2 schottky diode drops).
A USB Reset affects registers 0xC090 and 0xC0B0, all other
■ Booster circuit is turned off. registers remain unchanged.
■ USB transceivers is turned off.
Memory Map
■ CPU suspends until a programmable wakeup event.
Memory map information is presented in this section.
External (Remote) Wakeup Source
Mapping
There are several possible events available to wake EZ-OTG
The EZ-OTG has just over 24 KB of addressable memory
from Sleep mode as shown in Table 15. These may also be used
mapped from 0x0000 to 0xFFFF. This 24 KB contains both
as remote wakeup options for USB applications. See section
program and data space and is byte addressable. Figure 6.
“Power Control Register [0xC00A] [R/W]” on page 15.
shows the various memory region address locations.

Notes
5. Read data will be discarded (dummy data).
6. HPI_INT will assert on a USB Resume.registers

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 CY7C67200

Internal Memory Registers

Of the internal memory, 15 KB is allocated for user’s program
and data code. The lower memory space from 0x0000 to 0x04A2 Some registers have different functions for a read vs. a write
is reserved for interrupt vectors, general purpose registers, USB access or USB host vs. USB device mode. Therefore, registers
control registers, the stack, and other BIOS variables. The upper of this type have multiple definitions for the same address.
internal memory space contains EZ-OTG control registers from The default register values listed in this data sheet may be
0xC000 to 0xC0FF and the BIOS ROM itself from 0xE000 to altered to some other value during BIOS initialization. Refer to
0xFFFF. For more information on the reserved lower memory or the BIOS documentation for Register initialization information.
the BIOS ROM, refer to the Programmers documentation and
the BIOS documentation. Processor Control Registers
During development with the EZ-OTG toolset, the lower area of There are eight registers dedicated to general processor control.
User's space (0x04A4 to 0x1000) should be left available to load Each of these registers is covered in this section and is summa-
the GDB stub. The GDB stub is required to allow the toolset rized in Table 16.
debug access into EZ-OTG.
Figure 6. Memory Map Table 16. Processor Control Registers
Internal Memory Register Name Address R/W
CPU Flags Register 0xC000 R
HW INTs
Register Bank Register 0xC002 R/W
0x0000 - 0x00FF
SW INTs Hardware Revision Register 0xC004 R
0x0100 - 0x011F Primary Registers CPU Speed Register 0xC008 R/W
0x0120 - 0x013F Swap Registers Power Control Register 0xC00A R/W
0x0140 - 0x0148 HPI Int / Mailbox Interrupt Enable Register 0xC00E R/W
0x014A - 0x01FF LCP Variables
Breakpoint Register 0xC014 R/W
0x0200- 0x02FF USB Registers USB Diagnostic Register 0xC03C W

0x0300- 0x030F Slave Setup Packet

0x0310- 0x03FF BIOS Stack
0x0400- 0x04A2 USB Slave & OTG
USER SPACE
0x04A4- 0x3FFF
~15K

0xC000- 0xC0FF Control Registers

0xE000- 0xFFFF BIOS

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CPU Flags Register [0xC000] [R]

Figure 7. CPU Flags Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write – – – – – – – –
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
...Reserved Global Negative Overflow Carry Zero
Interrupt Flag Flag Flag Flag
Field Enable
Read/Write – – – R R R R R
Default 0 0 0 X X X X X

Register Description was either larger than the destination operand size (for addition)
The CPU Flags register is a read only register that gives or smaller than the destination operand should allow for
processor flags status. subtraction.
1: Overflow occurred
Global Interrupt Enable (Bit 4)
0: Overflow did not occur
The Global Interrupt Enable bit indicates if the Global Interrupts
are enabled. Carry Flag (Bit 1)
1: Enabled The Carry Flag bit indicates if an arithmetic operation resulted in
0: Disabled a carry for addition, or borrow for subtraction.
1: Carry/Borrow occurred
Negative Flag (Bit 3)
0: Carry/Borrow did not occur
The Negative Flag bit indicates if an arithmetic operation results
in a negative answer. Zero Flag (Bit 0)
1: MS result bit is ‘1’ The Zero Flag bit indicates if an instruction execution resulted in
0: MS result bit is not ‘1’ a ‘0’.
1: Zero occurred
Overflow Flag (Bit 2)
0: Zero did not occur
The Overflow Flag bit indicates if an overflow condition has
occurred. An overflow condition can occur if an arithmetic result

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Bank Register [0xC002] [R/W]

Figure 8. Bank Register
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 1

Bit # 7 6 5 4 3 2 1 0
Field ...Address Reserved
Read/Write R/W R/W R/W – – – – –
Default 0 0 0 X X X X X

Register Description
.

Table 17. Bank Register Example

The Bank register maps registers R0–R15 into RAM. The eleven Register Hex Value Binary Value
MSBs of this register are used as a base address for registers
R0–R15. A register address is automatically generated by: Bank 0x0100 0000 0001 0000 0000
1. Shifting the four LSBs of the register address left by 1 R14 0x000E << 1 = 0x001C 0000 0000 0001 1100
2. ORing the four shifted bits of the register address with the 12 RAM 0x011C 0000 0001 0001 1100
MSBs of the Bank Register Location
3. Forcing the LSB to zero
Address (Bits [15:4])
For example, if the Bank register is left at its default value of
0x0100, and R2 is read, then the physical address 0x0102 will The Address field is used as a base address for all register
be read. See Table 17 for details. addresses to start from.
Reserved
All reserved bits must be written as ‘0’.

Hardware Revision Register [0xC004] [R]

Figure 9. Revision Register

Bit # 15 14 13 12 11 10 9 8
Field Revision...
Read/Write R R R R R R R R
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
Field ...Revision
Read/Write R R R R R R R R
Default X X X X X X X X

Register Description Revision (Bits [15:0])

The Hardware Revision register is a read-only register that The Revision field contains the silicon revision number.
indicates the silicon revision number. The first silicon revision is
represented by 0x0101. This number is increased by one for
each new silicon revision.

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CPU Speed Register [0xC008] [R/W]

Figure 10. CPU Speed Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Reserved CPU Speed
Read/Write - - - - R/W R/W R/W R/W
Default 0 0 0 0 1 1 1 1

Register Description
The CPU Speed register allows the processor to operate at a user selected speed. This register only affects the CPU; all other
peripheral timing is still based on the 48-MHz system clock (unless otherwise noted).

CPU Speed (Bits[3:0])

The CPU Speed field is a divisor that selects the operating speed of the processor as defined in Table 18.
Table 18. CPU Speed Definition
CPU Speed [3:0] Processor Speed
0000 48 MHz/1
0001 48 MHz/2
0010 48 MHz/3
0011 48 MHz/4
0100 48 MHz/5
0101 48 MHz/6
0110 48 MHz/7
0111 48 MHz/8
1000 48 MHz/9
1001 48 MHz/10
1010 48 MHz/11
1011 48 MHz/12
1100 48 MHz/13
1101 48 MHz/14
1110 48 MHz/15
1111 48 MHz/16

Reserved
All reserved bits must be written as ‘0’.

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Power Control Register [0xC00A] [R/W]

Figure 11. Power Control Register

Bit # 15 14 13 12 11 10 9 8
Reserved Host/Device 2 Reserved Host/Device 1 OTG Reserved HSS SPI
Field Wake Enable Wake Enable Wake Enable Wake Enable Wake Enable
Read/Write – R/W – R/W R/W – R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
HPI Reserved GPI Reserved Boost 3V Sleep Halt
Field Wake Enable Wake Enable OK Enable Enable
Read/Write R/W – – R/W – R R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description SPI Wake Enable (Bit 8)

The Power Control register controls the power-down and The SPI Wake Enable bit enables or disables a wakeup condition
wakeup options. Either the sleep mode or the halt mode options to occur on a falling SPI_nSS input transition. The processor
can be selected. All other writable bits in this register can be used may take several hundreds of microseconds before being opera-
as a wakeup source while in sleep mode. tional after wakeup. Therefore, the incoming data byte that
causes the wakeup will be discarded.
Host/Device 2 Wake Enable (Bit 14)
1: Enable wakeup on falling SPI nSS input transition
The Host/Device 2 Wake Enable bit enables or disables a
wakeup condition to occur on an Host/Device 2 transition. This 0: Disable SPI_nSS interrupt
wake up from the SIE port does not cause an interrupt to the
on-chip CPU. HPI Wake Enable (Bit 7)

1: Enable wakeup on Host/Device 2 transition. The HPI Wake Enable bit enables or disables a wakeup
condition to occur on an HPI interface read.
0: Disable wakeup on Host/Device 2 transition.
1: Enable wakeup on HPI interface read
Host/Device 1 Wake Enable (Bit 12) 0: Disable wakeup on HPI interface read
The Host/Device 1 Wake Enable bit enables or disables a
wakeup condition to occur on an Host/Device 1 transition. This GPI Wake Enable (Bit 4)
wakeup from the SIE port does not cause an interrupt to the The GPI Wake Enable bit enables or disables a wakeup
on-chip CPU. condition to occur on a GPIO(25:24) transition.
1: Enable wakeup on Host/Device 1 transition 1: Enable wakeup on GPIO(25:24) transition
0: Disable wakeup on Host/Device 1 transition 0: Disable wakeup on GPIO(25:24) transition

OTG Wake Enable (Bit 11) Boost 3V OK (Bit 2)

The OTG Wake Enable bit enables or disables a wakeup The Boost 3V OK bit is a read only bit that returns the status of
condition to occur on either an OTG VBUS_Valid or OTG ID the OTG Boost circuit.
transition (IRQ20). 1: Boost circuit not ok and internal voltage rails are below 3.0 V
1: Enable wakeup on OTG VBUS valid or OTG ID transition 0: Boost circuit ok and internal voltage rails are at or above 3.0 V
0: Disable wakeup on OTG VBUS valid or OTG ID transition Sleep Enable (Bit 1)
HSS Wake Enable (Bit 9) Setting this bit to ‘1’ immediately initiates SLEEP mode. While in
The HSS Wake Enable bit enables or disables a wakeup SLEEP mode, the entire chip is paused achieving the lowest
condition to occur on an HSS Rx serial input transition. The standby power state. All operations are paused, the internal
processor may take several hundreds of microseconds before clock is stopped, the booster circuit and OTG VBUS charge
being operational after wakeup. Therefore, the incoming data pump are all powered down, and the USB transceivers are
byte that causes the wakeup will be discarded. powered down. All counters and timers are paused but will retain
their values. SLEEP mode exits by any activity selected in this
1: Enable wakeup on HSS Rx serial input transition register. When SLEEP mode ends, instruction execution
0: Disable wakeup on HSS Rx serial input transition resumes within 0.5 ms.
1: Enable Sleep Mode
0: No Function

Halt Enable (Bit 0)

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 CY7C67200

Setting this bit to ‘1’ immediately initiates HALT mode. While in waking interrupt is serviced (you may want to follow the HALT
HALT mode, only the CPU is stopped. The internal clock still runs instruction with two NOPs).
and all peripherals still operate, including the USB engines. The 1: Enable Halt Mode
power savings using HALT in most cases will be minimal, but in
applications that are very CPU intensive the incremental savings 0: No Function
may provide some benefit.
Reserved
The HALT state is exited when any enabled interrupt is triggered.
Upon exiting the HALT state, one or two instructions immediately All reserved bits must be written as ‘0’.
following the HALT instruction may be executed before the

Interrupt Enable Register [0xC00E] [R/W]

Figure 12. Interrupt Enable Register [7]

Bit # 15 14 13 12 11 10 9 8
Reserved OTG SPI Reserved Host/Device 2 Host/Device 1
Interrupt Interrupt Interrupt Interrupt
Field Enable Enable Enable Enable
Read/Write – – – R/W R/W – R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
HSS In Mailbox Out Mailbox Reserved UART GPIO Timer 1 Timer 0
Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
Field Enable Enable Enable Enable Enable Enable Enable
Read/Write R/W R/W R/W – R/W R/W R/W R/W
Default 0 0 0 1 0 0 0 0

Register Description Host/Device 1 Interrupt Enable (Bit 8)

The Interrupt Enable Register allows control of the hardware The Host/Device 1 Interrupt Enable bit enables or disables all of
interrupt vectors. the following Host/Device 1 hardware interrupts: Host 1 USB
Done, Host 1 USB SOF/EOP, Host 1 WakeUp/Insert/Remove,
OTG Interrupt Enable (Bit 12) Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB,
The OTG Interrupt Enable bit enables or disables the OTG Device 1 Endpoint n.
ID/OTG4.4 V Valid hardware interrupt. 1: Enable Host 1 and Device 1 interrupt
1: Enable OTG interrupt 0: Disable Host 1 and Device 1 interrupt
0: Disable OTG interrupt
HSS Interrupt Enable (Bit 7)
SPI Interrupt Enable (Bit 11) The HSS Interrupt Enable bit enables or disables the following
The SPI Interrupt Enable bit enables or disables the following High-speed Serial Interface hardware interrupts: HSS Block
three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA Done, and HSS RX Full.
Block Done. 1: Enable HSS interrupt
1: Enable SPI interrupt 0: Disable HSS interrupt
0: Disable SPI interrupt
In Mailbox Interrupt Enable (Bit 6)
Host/Device 2 Interrupt Enable (Bit 9) The In Mailbox Interrupt Enable bit enables or disables the HPI:
The Host/Device 2 Interrupt Enable bit enables or disables all of Incoming Mailbox hardware interrupt.
the following Host/Device 2 hardware interrupts: Host 2 USB 1: Enable MBXI interrupt
Done, Host 2 USB SOF/EOP, Host 2 WakeUp/Insert/Remove,
Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB, 0: Disable MBXI interrupt
Device 2 Endpoint n. Out Mailbox Interrupt Enable (Bit 5)
1: Enable Host 2 and Device 2 interrupt The Out Mailbox Interrupt Enable bit enables or disables the HPI:
0: Disable Host 2 and Device 2 interrupt Outgoing Mailbox hardware interrupt.
1: Enable MBXO interrupt
0: Disable MBXO interrupt
Note
7. Errata: Host/Device 1 SIE events will still trigger an interrupt when only the Host/Device 2 SIE Interrupt Enable is set and vise versa. For more information, see the
Errata on page 84.

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UART Interrupt Enable (Bit 3) Timer 1 Interrupt Enable (Bit 1)

The UART Interrupt Enable bit enables or disables the following The Timer 1 Interrupt Enable bit enables or disables the TImer1
UART hardware interrupts: UART TX and UART RX. Interrupt Enable. When this bit is reset, all pending Timer 1 inter-
1: Enable UART interrupt rupts are cleared.

0: Disable UART interrupt 1: Enable TM1 interrupt

0: Disable TM1 interrupt
GPIO Interrupt Enable (Bit 2)
The GPIO Interrupt Enable bit enables or disables the General Timer 0 Interrupt Enable (Bit 0)
Purpose IO Pins Interrupt (See the GPIO Control Register). The Timer 0 Interrupt Enable bit enables or disables the TImer0
When GPIO bit is reset, all pending GPIO interrupts are also Interrupt Enable. When this bit is reset, all pending Timer 0 inter-
cleared. rupts are cleared.
1: Enable GPIO interrupt 1: Enable TM0 interrupt
0: Disable GPIO interrupt 0: Disable TM0 interrupt

Reserved
All reserved bits must be written as ‘0’.

Breakpoint Register [0xC014] [R/W]

Figure 13. Breakpoint Register

Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description
The Breakpoint Register holds the breakpoint address. When the program counter match this address, the INT127 interrupt occurs.
To clear this interrupt, a zero value must be written to this register.

Address (Bits [15:0])

The Address field is a 16-bit field containing the breakpoint address.

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 CY7C67200

USB Diagnostic Register [0xC03C] [R/W]

Figure 14. USB Diagnostic Register

Bit # 15 14 13 12 11 10 9 8
Reserved Port 2A Reserved Port 1A Reserved...
Diagnostic Diagnostic
Field Enable Enable
Read/Write - R/W - R/W - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
...Reserved Pull-down LS Pull-up FS Pull-up Reserved Force Select
Field Enable Enable Enable
Read/Write - R/W R/W R/W - R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description FS Pull-up Enable (Bit 4)

The USB Diagnostic Register provides control of diagnostic The FS Pull-up Enable bit enables or disables a full-speed
modes. It is intended for use by device characterization tests, not pull-up resistor (pull up on D+) for testing.
for normal operations. This register is Read/Write by the on-chip 1: Enable full-speed pull-up resistor on D+
CPU but is write-only via the HPI port.
0: Pull-up resistor is not connected on D+
Port 2A Diagnostic Enable (Bit 15)
Force Select (Bits [2:0])
The Port 2A Diagnostic Enable bit enables or disables Port 2A
for the test conditions selected in this register. The Force Select field bit selects several different test condition
states on the data lines (D+/D–). See Table 19 for details.
1: Apply any of the following enabled test conditions: J/K, DCK,
SE0, RSF, RSL, PRD Table 19. Force Select Definition
0: Do not apply test conditions Force Select [2:0] Data Line State
Port 1A Diagnostic Enable (Bit 15) 1xx Assert SE0
The Port 1A Diagnostic Enable bit enables or disables Port 1A 01x Toggle JK
for the test conditions selected in this register. 001 Assert J
1: Apply any of the following enabled test conditions: J/K, DCK, 000 Assert K
SE0, RSF, RSL, PRD
0: Do not apply test conditions Reserved
Pull-down Enable (Bit 6) All reserved bits must be written as ‘0’.
The Pull-down Enable bit enables or disables full-speed Timer Registers
pull-down resistors (pull down on both D+ and D–) for testing.
There are three registers dedicated to timer operations. Each of
1: Enable pull-down resistors on both D+ and D– these registers are discussed in this section and are summarized
0: Disable pull-down resistors on both D+ and D– in Table 20.

LS Pull-up Enable (Bit 5) Table 20. Timer Registers

The LS Pull-up Enable bit enables or disables a low-speed Register Name Address R/W
pull-up resistor (pull up on D–) for testing. Watchdog Timer Register 0xC00C R/W
1: Enable low-speed pull-up resistor on D– Timer 0 Register 0xC010 R/W
0: Pull-up resistor is not connected on D– Timer 1 Register 0xC012 R/W

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 CY7C67200

Watchdog Timer Register [0xC00C] [R/W]

Figure 15. Watchdog Timer Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
...Reserved Timeout Period Lock WDT Reset
Field Flag Select Enable Enable Strobe
Read/Write R/W R/W R/W R/W R/W R/W R/W W
Default 0 0 0 0 0 0 0 0

Register Description Lock Enable (Bit 2)

The Watchdog Timer register provides status and control over The Lock Enable bit does not allow any writes to this register until
the Watchdog timer. The Watchdog timer can also interrupt the a reset. In doing so the Watchdog timer can be set up and
processor. enabled permanently so that it can only be cleared on reset (the
WDT Enable bit is ignored).
Timeout Flag (Bit 5)
1: Watchdog timer permanently set
The Timeout Flag bit indicates if the Watchdog timer has expired.
The processor can read this bit after exiting a reset to determine 0: Watchdog timer not permanently set
if a Watchdog timeout occurred. This bit is cleared on the next WDT Enable (Bit 1)
external hardware reset.
The WDT Enable bit enables or disables the Watchdog timer.
1: Watchdog timer expired
1: Enable Watchdog timer operation
0: Watchdog timer did not expire
0: Disable Watchdog timer operation
Period Select (Bits [4:3])
Reset Strobe (Bit 0)
The Period Select field is defined in Table 21. If this time expires
before the Reset Strobe bit is set, the internal processor is reset. The Reset Strobe is a write-only bit that resets the Watchdog
timer count. It must be set to ‘1’ before the count expires to avoid
Table 21. Period Select Definition a Watchdog trigger
Period Select[4:3] WDT Period Value 1: Reset Count
00 1.4 ms
Reserved
01 5.5 ms
All reserved bits must be written as ‘0’.
10 22.0 ms
11 66.0 ms

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 CY7C67200

Timer n Register [R/W]

■ Timer 0 Register 0xC010
■ Timer 1 Register 0xC012
Figure 16. Timer n Register
Bit # 15 14 13 12 11 10 9 8
Field Count...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1

Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1

Register Description
The Timer n Register sets the Timer n count. Both Timer 0 and Timer 1 decrement by one every 1-µs clock tick. Each can provide an
interrupt to the CPU when the timer reaches zero.

Count (Bits [15:0])

The Count field sets the Timer count.

General USB Registers

There is one set of registers dedicated to general USB control. This set consists of two identical registers, one for Host/Device Port
1 and one for Host/Device Port 2. This register set has functions for both USB host and USB peripheral options and is covered in this
section and summarized in Table 22. USB Host-only registers are covered in Section “USB Host Only Registers” on page 22 and USB
Device-only registers are covered in Section “USB Device Only Registers” on page 30.
Table 22. USB Registers [8]
Register Name Address (SIE1/SIE2) R/W
USB n Control Register 0xC08A/0xC0AA R/W

USB n Control Register [R/W]

■ USB 1 Control Register 0xC08A
■ USB 2 Control Register 0xC0AA
Figure 17. USB n Control Register

Bit # 15 14 13 12 11 10 9 8
Reserved Port A Port A Reserved LOA Mode Reserved
Field D+ Status D– Status Select
Read/Write - - R R - R/W R/W -
Default X X X X 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Port A Reserved Port A Suspend Reserved Port A
Field Resistors Enable Force D± State Enable SOF/EOP Enable
Read/Write R/W - - R/W R/W R/W - R/W
Default 0 0 0 0 0 0 0 0

Note
8. Errata: Writing to the SIE2 Control register via HPI can corrupt the SIE1 control register. Writing to the SIE1 Control register via HPI can corrupt the SIE2 control
register. For more information, see the Errata on page 84.

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Register Description
The USB n Control register is used in both host and device mode. It monitors and controls the SIE and the data lines of the USB ports.
This register can be accessed by the HPI interface.

Port A D+ Status (Bit 13) Port A Force D± State (Bits [4:3])

The Port A D+ Status bit is a read-only bit that indicates the value The Port A Force D± State field controls the forcing state of the
of DATA+ on Port A. D+ D– data lines for Port A. This field forces the state of the Port
1: D+ is high A data lines independent of the Port Select bit setting. See
Table 24 for details.
0: D+ is low
Table 24. Port A Force D± State
Port A D– Status (Bit 12)
The Port A D– Status bit is a read-only bit that indicates the value Port A Force D± State
Function
of DATA– on Port A. MSB LSB
1: D– is high 0 0 Normal Operation
0: D– is low 0 1 Force USB Reset, SE0 State
1 0 Force J-State
LOA (Bit 10)
1 1 Force K-State
The LOA bit selects the speed of Port A.
1: Port A is set to Low-speed mode Suspend Enable (Bit 2)
0: Port A is set to Full-speed mode The Suspend Enable bit enables or disables the suspend feature
on both ports. When suspend is enabled the USB transceivers
Mode Select (Bit 9) are powered down and can not transmit or received USB packets
The Mode Select bit sets the SIE for host or device operation. but can still monitor for a wakeup condition.
When set for device operation only one USB port is supported. 1: Enable suspend
The active port is selected by the Port Select bit in the Host n 0: Disable suspend
Count Register.
1: Host mode Port A SOF/EOP Enable (Bit 0)
0: Device mode The Port A SOF/EOP Enable bit is only applicable in host mode.
In Device mode this bit must be written as ‘0’. In host mode this
Port A Resistors Enable (Bit 7) bit enables or disables SOFs or EOPs for Port A. Either SOFs or
The Port A Resistors Enable bit enables or disables the EOPs will be generated depending on the LOA bit in the USB n
pull-up/pull-down resistors on Port A. When enabled, the Mode Control Register when Port A is active.
Select bit and LOA bit of this register sets the pull-up/pull-down 1: Enable SOFs or EOPs
resistors appropriately. When the Mode Select is set for Host 0: Disable SOFs or EOPs
mode, the pull-down resistors on the data lines (D+ and D–) are
enabled. When the Mode Select is set for Device mode, a single Reserved
pull-up resistor on either D+ or D–, determined by the LOA bit,
will be enabled. See Table 23 for details. All reserved bits must be written as ‘0’.

1: Enable pull-up/pull-down resistors

0: Disable pull-up/pull-down resistors

Table 23. USB Data Line Pull-up and Pull-down Resistors

Port n
Mode
L0A Resistors Function
Select Enable
X X 0 Pull up/Pull down on D+ and
D– Disabled
X 1 1 Pull down on D+ and D–
Enabled
1 0 1 Pull up on USB D– Enabled
0 0 1 Pull up on USB D+ Enabled

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 CY7C67200

USB Host Only Registers

There are twelve sets of dedicated registers to USB host only operation. Each set consists of two identical registers (unless otherwise
noted); one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized in Table 25.
Table 25. USB Host Only Register
Address
Register Name R/W
(Host 1/Host 2)
Host n Control Register 0xC080/0xC0A0 R/W
Host n Address Register 0xC082/0xC0A2 R/W
Host n Count Register 0xC084/0xC0A4 R/W
Host n Endpoint Status Register 0xC086/0xC0A6 R
Host n PID Register 0xC086/0xC0A6 W
Host n Count Result Register 0xC088/0xC0A8 R
Host n Device Address Register 0xC088/0xC0A8 W
Host n Interrupt Enable Register 0xC08C/0xC0AC R/W
Host n Status Register 0xC090/0xC0B0 R/W
Host n SOF/EOP Count Register 0xC092/0xC0B2 R/W
Host n SOF/EOP Counter Register 0xC094/0xC0B4 R
Host n Frame Register 0xC096/0xC0B6 R

Host n Control Register [R/W]

■ Host 1 Control Register 0xC080
■ Host 2 Control Register 0xC0A0
Figure 18. Host n Control Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Preamble Sequence Sync ISO Reserved Arm
Field Enable Select Enable Enable Enable
Read/Write R/W R/W R/W R/W - - - R/W
Default 0 0 0 0 0 0 0 0

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Register Description 1: The next enabled packet will be transferred after the SOF or
The Host n Control register allows high-level USB transaction EOP packet is transmitted
control. 0: The next enabled packet will be transferred as soon as the SIE
is free
Preamble Enable (Bit 7)
The Preamble Enable bit enables or disables the transmission of ISO Enable (Bit 4)
a preamble packet before all low-speed packets. This bit should The ISO Enable bit enables or disables an Isochronous trans-
only be set when communicating with a low-speed device. action.
1: Enable Preamble packet 1: Enable Isochronous transaction
0: Disable Preamble packet 0: Disable Isochronous transaction

Sequence Select (Bit 6) Arm Enable (Bit 0)

The Sequence Select bit sets the data toggle for the next packet. The Arm Enable bit arms an endpoint and starts a transaction.
This bit has no effect on receiving data packets; sequence This bit is automatically cleared to ‘0’ when a transaction is
checking must be handled in firmware. complete.
1: Send DATA1 1: Arm endpoint and begin transaction
0: Send DATA0 0: Endpoint disarmed

Sync Enable (Bit 5) Reserved

The Sync Enable bit synchronizes the transfer with the SOF All reserved bits must be written as ‘0’.
packet in full-speed mode and the EOP packet in low-speed
mode.

Host n Address Register [R/W]

■ Host 1 Address Register 0xC082
■ Host 2 Address Register 0xC0A2
Figure 19. Host n Address Register
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description Address (Bits [15:0])

The Host n Address register is used as the base pointer into The Address field sets the address pointer into internal RAM or
memory space for the current host transactions. ROM.

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 CY7C67200

Host n Count Register [R/W]

■ Host 1 Count Register 0xC084
■ Host 2 Count Register 0xC0A4
Figure 20. Host n Count Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - - - - - R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description Count (Bits [9:0])

The Host n Count register is used to hold the number of bytes The Count field sets the value for the current transaction data
(packet length) for the current transaction. The maximum packet packet length. This value is retained when switching between
length is 1023 bytes in ISO mode. The Host Count value is used host and device mode, and back again.
to determine how many bytes to transmit, or the maximum
number of bytes to receive. If the number of received bytes is Reserved
greater then the Host Count value then an overflow condition will All reserved bits must be written as ‘0’.
be flagged by the Overflow bit in the Host n Endpoint Status
register.

Host n Endpoint Status Register [R]

■ Host 1 Endpoint Status Register 0xC086
■ Host 2 Endpoint Status Register 0xC0A6

Figure 21. Host n Endpoint Status Register

Bit # 15 14 13 12 11 10 9 8
Reserved Overflow Underflow Reserved
Field Flag Flag
Read/Write - - - - R R - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Stall NAK Length Reserved Sequence Timeout Error ACK
Flag Flag Exception Status Flag Flag Flag
Field Flag
Read/Write R R R - R R R R
Default 0 0 0 0 0 0 0 0

Register Description 0: Overflow condition did not occur

The Host n Endpoint Status register is a read-only register that Underflow Flag (Bit 10)
provides status for the last USB transaction.
The Underflow Flag bit indicates that the received data in the last
Overflow Flag (Bit 11) data transaction was less then the maximum length specified in
The Overflow Flag bit indicates that the received data in the last the Host n Count register. The Underflow Flag should be
data transaction exceeded the maximum length specified in the checked in response to a Length Exception signified by the
Host n Count Register. The Overflow Flag should be checked in Length Exception Flag set to ‘1’.
response to a Length Exception signified by the Length 1: Underflow condition occurred
Exception Flag set to ‘1’. 0: Underflow condition did not occur
1: Overflow condition occurred

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 CY7C67200

Stall Flag (Bit 7) Timeout Flag (Bit 2)

The Stall Flag bit indicates that the peripheral device replied with The Timeout Flag bit indicates if a timeout condition occurred for
a Stall in the last transaction. the last transaction. A timeout condition can occur when a device
1: Device returned Stall either takes too long to respond to a USB host request or takes
too long to respond with a handshake.
0: Device did not return Stall
1: Timeout occurred
NAK Flag (Bit 6) 0: Timeout did not occur
The NAK Flag bit indicates that the peripheral device replied with
a NAK in the last transaction. Error Flag (Bit 1)

1: Device returned NAK The Error Flag bit indicates a transaction failed for any reason
other than the following: Timeout, receiving a NAK, or receiving
0: Device did not return NAK a STALL. Overflow and Underflow are not considered errors and
do not affect this bit. CRC5 and CRC16 errors will result in an
Length Exception Flag (Bit 5) Error flag along with receiving incorrect packet types.
The Length Exception Flag bit indicates the received data in the 1: Error detected
data stage of the last transaction does not equal the maximum
Host Count specified in the Host n Count register. A Length 0: No error detected
Exception can either mean an overflow or underflow and the
Overflow and Underflow flags (bits 11 and 10, respectively) ACK Flag (Bit 0)
should be checked to determine which event occurred. The ACK Flag bit indicates two different conditions depending on
1: An overflow or underflow condition occurred the transfer type. For non-Isochronous transfers, this bit repre-
sents a transaction ending by receiving or sending an ACK
0: An overflow or underflow condition did not occur packet. For Isochronous transfers, this bit represents a
successful transaction that will not be represented by an ACK
Sequence Status (Bit 3) packet.
The Sequence Status bit indicates the state of the last received 1: For non-Isochronous transfers, the transaction was ACKed.
data toggle from the device. Firmware is responsible for For Isochronous transfers, the transaction was completed
monitoring and handling the sequence status. The Sequence bit successfully.
is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to
‘0’ when an error is detected in the transaction and the Error bit 0: For non-Isochronous transfers, the transaction was not
will be set. ACKed. For Isochronous transfers, the transaction was not
completed successfully.
1: DATA1
0: DATA0

Host n PID Register [W]

■ Host 1 PID Register 0xC086
■ Host 2 PID Register 0xC0A6
Figure 22. Host n PID Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field PID Select Endpoint Select
Read/Write W W W W W W W W
Default 0 0 0 0 0 0 0 0

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 CY7C67200

Register Description Table 26. PID Select Definition (continued)

The Host n PID register is a write-only register that provides the PID TYPE PID Select [7:4]
PID and Endpoint information to the USB SIE to be used in the
next transaction. PREAMBLE 1100 (C Hex)
NAK 1010 (A Hex)
PID Select (Bits [7:4])
STALL 1110 (E Hex)
The PID Select field defined as in Table 26. ACK and NAK tokens
are automatically sent based on settings in the Host n Control DATA0 0011 (3 Hex)
register and do not need to be written in this register. DATA1 1011 (B Hex)
Table 26. PID Select Definition Endpoint Select (Bits [3:0])
PID TYPE PID Select [7:4] The Endpoint field allows addressing of up to 16 different
set-up 1101 (D Hex) endpoints.

IN 1001 (9 Hex) Reserved

OUT 0001 (1 Hex) All reserved bits must be written as ‘0’.
SOF 0101 (5 Hex)

Host n Count Result Register [R]

■ Host 1 Count Result Register 0xC088
■ Host 2 Count Result Register 0xC0A8
Figure 23. Host n Count Result Register
Bit # 15 14 13 12 11 10 9 8
Field Result...
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Result
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0

Register Description Result (Bits [15:0])

The Host n Count Result register is a read-only register that The Result field contains the differences in bytes between the
contains the size difference in bytes between the Host Count received packet and the value specified in the Host n Count
Value specified in the Host n Count register and the last packet register. If an overflow condition occurs, Result [15:10] is set to
received. If an overflow or underflow condition occurs, that is the ‘111111’, a 2’s complement value indicating the additional byte
received packet length differs from the value specified in the Host count of the received packet. If an underflow condition occurs,
n Count register, the Length Exception Flag bit in the Host n Result [15:0] indicates the excess byte count (number of bytes
Endpoint Status register will be set. The value in this register is not used).
only valid when the Length Exception Flag bit is set and the Error
Flag bit is not set; both bits are in the Host n Endpoint Status Reserved
register. All reserved bits must be written as ‘0’.

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 CY7C67200

Host n Device Address Register [W]

■ Host 1 Device Address Register 0xC088
■ Host 2 Device Address Register 0xC0A8
Figure 24. Host n Device Address Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Address
Read/Write - W W W W W W W
Default 0 0 0 0 0 0 0 0

Register Description Address (Bits [6:0])

The Host n Device Address register is a write-only register that The Address field contains the value of the USB address for the
contains the USB Device Address that the host wishes to next device that the host is going to communicate with. This
communicate with. value must be written by firmware.

Reserved
All reserved bits must be written as ‘0’.

Host n Interrupt Enable Register [R/W]

■ Host 1 Interrupt Enable Register 0xC08C
■ Host 2 Interrupt Enable Register 0xC0AC

Figure 25. Host n Interrupt Enable Register

Bit # 15 14 13 12 11 10 9 8
VBUS ID Interrupt Reserved SOF/EOP Reserved
Field Interrupt Enable Enable Interrupt Enable
Read/Write R/W R/W - - - - R/W -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Reserved Port A Reserved Port A Connect Reserved Done
Wake Interrupt Enable Change Interrupt Enable
Field Interrupt Enable
Read/Write - R/W - R/W - - - R/W
Default 0 0 0 0 0 0 0 0

Register Description 0: Disable VBUS interrupt

The Host n Interrupt Enable register allows control over ID Interrupt Enable (Bit 14)
host-related interrupts.
The ID Interrupt Enable bit enables or disables the OTG ID
In this register a bit set to ‘1’ enables the corresponding interrupt interrupt. When enabled this interrupt triggers on both the rising
while ‘0’ disables the interrupt. and falling edge of the OTG ID pin (only supported in Port 1A).
VBUS Interrupt Enable (Bit 15) This bit is only available for Host 1 and is a reserved bit in Host 2.

The VBUS Interrupt Enable bit enables or disables the OTG 1: Enable ID interrupt
VBUS interrupt. When enabled this interrupt triggers on both the 0: Disable ID interrupt
rising and falling edge of VBUS at the 4.4 V status (only
supported in Port 1A). This bit is only available for Host 1 and is SOF/EOP Interrupt Enable (Bit 9)
a reserved bit in Host 2. The SOF/EOP Interrupt Enable bit enables or disables the
1: Enable VBUS interrupt SOF/EOP timer interrupt.

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 CY7C67200

1: Enable SOF/EOP timer interrupt 1: Enable Connect Change interrupt

0: Disable SOF/EOP timer interrupt 0: Disable Connect Change interrupt

Port A Wake Interrupt Enable (Bit 6) Done Interrupt Enable (Bit 0)

The Port A Wake Interrupt Enable bit enables or disables the The Done Interrupt Enable bit enables or disables the USB
remote wakeup interrupt for Port A. Transfer Done interrupt. The USB Transfer Done triggers when
1: Enable remote wakeup interrupt for Port A either the host responds with an ACK, or a device responds with
any of the following: ACK, NAK, STALL, or Timeout. This
0: Disable remote wakeup interrupt for Port A interrupt is used for both Port A and Port B.
Port A Connect Change Interrupt Enable (Bit 4) 1: Enable USB Transfer Done interrupt
The Port A Connect Change Interrupt Enable bit enables or 0: Disable USB Transfer Done interrupt
disables the Connect Change interrupt on Port A. This interrupt
triggers when either a device is inserted (SE0 state to J state) or Reserved
a device is removed (J state to SE0 state). All reserved bits must be written as ‘0’.

Host n Status Register [R/W]

■ Host 1 Status Register 0xC090
■ Host 2 Status Register 0xC0B0
Figure 26. Host n Status Register
Bit # 15 14 13 12 11 10 9 8
VBUS ID Interrupt Reserved SOF/EOP Reserved
Field Interrupt Flag Flag Interrupt Flag
Read/Write R/W R/W - - - - R/W -
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
Reserved Port A Reserved Port A Connect Reserved Port A Reserved Done
Wake Interrupt Change SE0 Interrupt Flag
Field Flag Interrupt Flag Status
Read/Write - R/W - R/W - R/W - R/W
Default X X X X X X X X

Register Description The ID Interrupt Flag bit indicates the status of the OTG ID
The Host n Status register provides status information for host interrupt (only for Port 1A). When enabled this interrupt triggers
operation. Pending interrupts can be cleared by writing a ‘1’ to on both the rising and falling edge of the OTG ID pin. This bit is
the corresponding bit. This register can be accessed by the HPI only available for Host 1 and is a reserved bit in Host 2.
interface. 1: Interrupt triggered

VBUS Interrupt Flag (Bit 15) 0: Interrupt did not trigger

The VBUS Interrupt Flag bit indicates the status of the OTG SOF/EOP Interrupt Flag (Bit 9)
VBUS interrupt (only for Port 1A). When enabled this interrupt The SOF/EOP Interrupt Flag bit indicates the status of the
triggers on both the rising and falling edge of VBUS at 4.4 V. This SOF/EOP Timer interrupt. This bit triggers ‘1’ when the
bit is only available for Host 1 and is a reserved bit in Host 2. SOF/EOP timer expires.
1: Interrupt triggered 1: Interrupt triggered
0: Interrupt did not trigger 0: Interrupt did not trigger
ID Interrupt Flag (Bit 14)

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 CY7C67200

Port A Wake Interrupt Flag (Bit 6) Port A SE0 Status (Bit 2)

The Port A Wake Interrupt Flag bit indicates remote wakeup on The Port A SE0 Status bit indicates if Port A is in an SE0 state or
Port A. not. Together with the Port A Connect change Interrupt Flag bit,
1: Interrupt triggered it can be determined whether a device was inserted (non-SE0
condition) or removed (SE0 condition).
0: Interrupt did not trigger
1: SE0 condition
Port A Connect Change Interrupt Flag (Bit 4) 0: Non-SE0 condition
The Port A Connect Change Interrupt Flag bit indicates the
status of the Connect Change interrupt on Port A. This bit Done Interrupt Flag (Bit 0)
triggers ‘1’ on either a rising edge or falling edge of a USB Reset The Done Interrupt Flag bit indicates the status of the USB
condition (device inserted or removed). Together with the Port A Transfer Done interrupt. The USB Transfer Done triggers when
SE0 Status bit, it can be determined whether a device was either the host responds with an ACK, or a device responds with
inserted or removed. any of the following: ACK, NAK, STALL, or Timeout. This
1: Interrupt triggered interrupt is used for both Port A and Port B.

0: Interrupt did not trigger 1: Interrupt triggered

0: Interrupt did not trigger

Host n SOF/EOP Count Register [R/W]

■ Host 1 SOF/EOP Count Register 0xC092
■ Host 2 SOF/EOP Count Register 0xC0B2

Figure 27. Host n SOF/EOP Count Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - R/W R/W R/W R/W R/W R/W
Default 0 0 1 0 1 1 1 0

Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 0 0 0 0 0

Register Description Count (Bits [13:0])

The Host n SOF/EOP Count register contains the SOF/EOP The Count field sets the SOF/EOP counter duration.
Count Value that is loaded into the SOF/EOP counter. This value
is loaded each time the SOF/EOP counter counts down to zero. Reserved
The default value set in this register at power-up is 0x2EE0, All reserved bits must be written as ‘0’.
which will generate a 1-ms time frame. The SOF/EOP counter is
a down counter decremented at a 12-MHz rate. When this
register is read, the value returned is the programmed SOF/EOP
count value.

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 CY7C67200

Host n SOF/EOP Counter Register [R]

■ Host 1 SOF/EOP Counter Register 0xC094
■ Host 2 SOF/EOP Counter Register 0xC0B4

Figure 28. Host n SOF/EOP Counter Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved Counter...
Read/Write - - R R R R R R
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
Field ...Counter
Read/Write R R R R R R R R
Default X X X X X X X X

Register Description Counter (Bits [13:0])

The Host n SOF/EOP Counter register contains the current value The Counter field contains the current value of the SOF/EOP
of the SOF/EOP down counter. This value can be used to down counter.
determine the time remaining in the current frame.

Host n Frame Register [R]

■ Host 1 Frame Register 0xC096
■ Host 2 Frame Register 0xC0B6

Figure 29. Host n Frame Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved Frame...
Read/Write - - - - - R R R
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Frame
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0

Register Description Reserved

The Host n Frame register maintains the next frame number to All reserved bits must be written as ‘0’.
be transmitted (current frame number + 1). This value is updated
after each SOF transmission. This register resets to 0x0000 after USB Device Only Registers
each CPU write to the Host n SOF/EOP Count register (Host 1: There are ten sets of USB Device Only registers. All sets consist
0xC092, Host 2: 0xC0B2). of at least two registers, one for Device Port 1 and one for Device
Port 2. In addition, each Device port has eight possible
Frame (Bits [10:0])
endpoints. This gives each endpoint register set eight registers
The Frame field contains the next frame number to be trans- for each Device Port for a total of 16 registers per set. The USB
mitted. Device Only registers are covered in this section and summa-
rized in Table 27.
Table 27. USB Device Only Registers
Address
Register Name R/W
(Device 1/Device 2)
Device n Endpoint n Control Register 0x02n0 R/W
Device n Endpoint n Address Register 0x02n2 R/W

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 CY7C67200

Table 27. USB Device Only Registers (continued)

Address
Register Name R/W
(Device 1/Device 2)
Device n Endpoint n Count Register 0x02n4 R/W
Device n Endpoint n Status Register 0x02n6 R/W
Device n Endpoint n Count Result Register 0x02n8 R/W
Device n Interrupt Enable Register 0xC08C/0xC0AC R/W
Device n Address Register 0xC08E/0xC0AE R/W
Device n Status Register 0xC090/0xCB0 R/W
Device n Frame Number Register 0xC092/0xC0B2 R
Device n SOF/EOP Count Register 0xC094/0xC0B4 W

Device n Endpoint n Control Register [R/W]

■ Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280]
■ Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290]
■ Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0]
■ Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0]
■ Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0]
■ Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0]
■ Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0]
■ Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0]
Figure 30. Device n Endpoint n Control Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
IN/OUT Sequence Stall ISO NAK Direction Enable Arm
Ignore Select Enable Enable Interrupt Select Enable
Field Enable Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X

Register Description Sequence Select (Bit 6)

The Device n Endpoint n Control register provides control over a The Sequence Select bit determines whether a DATA0 or a
single EP in device mode. There are a total of eight endpoints for DATA1 will be sent for the next data toggle. This bit has no effect
each of the two ports. All endpoints have the same definition for on receiving data packets, sequence checking must be handled
their Device n Endpoint n Control register. in firmware.

IN/OUT Ignore Enable (Bit 6) 1: Send a DATA1

The IN/OUT Ignore Enable bit forces endpoint 0 (EP0) to ignore 0: Send a DATA0
all IN and OUT requests. This bit must be set so that EP0 only Stall Enable (Bit 5)
excepts Setup packets at the start of each transfer. This bit must
be cleared to except IN/OUT transactions. This bit only applies The Stall Enable bit sends a Stall in response to the next request
to EP0. (unless it is a setup request, which are always ACKed). This is a
sticky bit and continues to respond with Stalls until cleared by
1: Ignore IN/OUT requests firmware.
0: Do not ignore IN/OUT requests 1: Send Stall

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 CY7C67200

0: Do not send Stall is set incorrectly, the setup will be ACKed and the Set-up Status
Flag will be set (refer to the setup bit of the Device n Endpoint n
ISO Enable (Bit 4) Status register for details).
The ISO Enable bit enables and disables an Isochronous trans- 1: OUT transfer (host to device)
action. This bit is only valid for EPs 1–7 and has no function for
EP0. 0: IN transfer (device to host)

1: Enable Isochronous transaction Enable (Bit 1)

0: Disable Isochronous transaction The Enable bit must be set to allow transfers to the endpoint. If
Enable is set to ‘0’ then all USB traffic to this endpoint is ignored.
NAK Interrupt Enable (Bit 3) If Enable is set ‘1’ and Arm Enable (bit 0) is set ‘0’ then NAKs will
The NAK Interrupt Enable bit enables and disables the gener- automatically be returned from this endpoint (except setup
ation of an Endpoint n interrupt when the device responds to the packets, which are always ACKed as long as the Enable bit is
host with a NAK. The Endpoint n Interrupt Enable bit in the set).
Device n Interrupt Enable register must also be set. When a NAK 1: Enable transfers to an endpoint
is sent to the host, the corresponding EP Interrupt Flag in the
Device n Status register will be set. In addition, the NAK Flag in 0: Do not allow transfers to an endpoint
the Device n Endpoint n Status register will be set. Arm Enable (Bit 0)
1: Enable NAK interrupt The Arm Enable bit arms the endpoint to transfer or receive a
0: Disable NAK interrupt packet. This bit is cleared to ‘0’ when a transaction is complete.

Direction Select (Bit 2) 1: Arm endpoint

The Direction Select bit needs to be set according to the 0: Endpoint disarmed
expected direction of the next data stage in the next transaction. Reserved
If the data stage direction is different from what is set in this bit,
it will get NAKed and either the IN Exception Flag or the OUT All reserved bits must be written as ‘0’.
Exception Flag will be set in the Device n Endpoint n Status
register. If a setup packet is received and the Direction Select bit Device n Endpoint n Address Register [R/W]

■ Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282]

■ Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292]
■ Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2]
■ Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2]
■ Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2]
■ Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2]
■ Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2]
■ Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2]

Figure 31. Device n Endpoint n Address Register

Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X

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 CY7C67200

Register Description
The Device n Endpoint n Address register is used as the base pointer into memory space for the current Endpoint transaction. There
are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Address
register.

Address (Bits [15:0])

The Address field sets the base address for the current transaction on a signal endpoint.

Device n Endpoint n Count Register [R/W]

■ Device n Endpoint 0 Count Register [Device 1: 0x0204 Device 2: 0x0284]
■ Device n Endpoint 1 Count Register [Device 1: 0x0214 Device 2: 0x0294]
■ Device n Endpoint 2 Count Register [Device 1: 0x0224 Device 2: 0x02A4]
■ Device n Endpoint 3 Count Register [Device 1: 0x0234 Device 2: 0x02B4]
■ Device n Endpoint 4 Count Register [Device 1: 0x0244 Device 2: 0x02C4]
■ Device n Endpoint 5 Count Register [Device 1: 0x0254 Device 2: 0x02D4]
■ Device n Endpoint 6 Count Register [Device 1: 0x0264 Device 2: 0x02E4]
■ Device n Endpoint 7 Count Register [Device 1: 0x0274 Device 2: 0x02F4]

Figure 32. Device n Endpoint n Count Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - - - - - R/W R/W
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X

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 CY7C67200

Register Description
The Device n Endpoint n Count register designates the maximum packet size that can be received from the host for OUT transfers
for a single endpoint. This register also designates the packet size to be sent to the host in response to the next IN token for a single
endpoint. The maximum packet length is 1023 bytes in ISO mode. There are a total of eight endpoints for each of the two ports. All
endpoints have the same definition for their Device n Endpoint n Count register.

Count (Bits [9:0])

The Count field sets the current transaction packet length for a single endpoint.

Reserved
All reserved bits must be written as ‘0’.

Device n Endpoint n Status Register [R/W]

■ Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286]
■ Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296]
■ Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6]
■ Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6]
■ Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6]
■ Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6]
■ Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6]
■ Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6]

Figure 33. Device n Endpoint n Status Register

Bit # 15 14 13 12 11 10 9 8
Reserved Overflow Underflow OUT IN
Field Flag Flag Exception Flag Exception Flag
Read/Write - - - - R/W R/W R/W R/W
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
Stall NAK Length Setup Sequence Timeout Error ACK
Field Flag Flag Exception Flag Flag Flag Flag Flag Flag
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X

Register Description 1: Overflow condition occurred

The Device n Endpoint n Status register provides packet status 0: Overflow condition did not occur
information for the last transaction received or transmitted. This
register is updated in hardware and does not need to be cleared Underflow Flag (Bit 10)
by firmware. There are a total of eight endpoints for each of the The Underflow Flag bit indicates that the received data in the last
two ports. All endpoints have the same definition for their Device data transaction was less then the maximum length specified in
n Endpoint n Status register. the Device n Endpoint n Count register. The Underflow Flag
The Device n Endpoint n Status register is a memory-based should be checked in response to a Length Exception signified
register that must be initialized to 0x0000 before USB Device by the Length Exception Flag set to ‘1’.
operations are initiated. After initialization, this register must not 1: Underflow condition occurred
be written to again.
0: Underflow condition did not occur
Overflow Flag (Bit 11)
OUT Exception Flag (Bit 9)
The Overflow Flag bit indicates that the received data in the last
data transaction exceeded the maximum length specified in the The OUT Exception Flag bit indicates when the device received
Device n Endpoint n Count register. The Overflow Flag should an OUT packet when armed for an IN.
be checked in response to a Length Exception signified by the 1: Received OUT when armed for IN
Length Exception Flag set to ‘1’. 0: Received IN when armed for IN

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 CY7C67200

IN Exception Flag (Bit 8) Enable bit settings as long as the Device n EP n Control register
The IN Exception Flag bit indicates when the device received an Enable bit is set.
IN packet when armed for an OUT. 1: Setup packet was received
1: Received IN when armed for OUT 0: Setup packet was not received
0: Received OUT when armed for OUT Sequence Flag (Bit 3)
Stall Flag (Bit 7) The Sequence Flag bit indicates whether the last data toggle
The Stall Flag bit indicates that a Stall packet was sent to the received was a DATA1 or a DATA0. This bit has no effect on
host. receiving data packets; sequence checking must be handled in
firmware.
1: Stall packet was sent to the host
1: DATA1 was received
0: Stall packet was not sent
0: DATA0 was received
NAK Flag (Bit 6)
Timeout Flag (Bit 2)
The NAK Flag bit indicates that a NAK packet was sent to the
host. The Timeout Flag bit indicates whether a timeout condition
occurred on the last transaction. On the device side, a timeout
1: NAK packet was sent to the host can occur if the device sends a data packet in response to an IN
0: NAK packet was not sent request but then does not receive a handshake packet in a
predetermined time. It can also occur if the device does not
Length Exception Flag (Bit 5) receive the data stage of an OUT transfer in time.
The Length Exception Flag bit indicates the received data in the 1: Timeout occurred
data stage of the last transaction does not equal the maximum 0: Timeout condition did not occur
Endpoint Count specified in the Device n Endpoint n Count
register. A Length Exception can either mean an overflow or Error Flag (Bit 2)
underflow and the Overflow and Underflow flags (bits 11 and 10,
respectively) should be checked to determine which event The Error Flag bit is set if a CRC5 and CRC16 error occurs, or if
occurred. an incorrect packet type is received. Overflow and Underflow are
not considered errors and do not affect this bit.
1: An overflow or underflow condition occurred
1: Error occurred
0: An overflow or underflow condition did not occur
0: Error did not occur
Setup Flag (Bit 4)
ACK Flag (Bit 0)
The Setup Flag bit indicates that a setup packet was received.
In device mode setup packets are stored at memory location The ACK Flag bit indicates whether the last transaction was
0x0300 for Device 1 and 0x0308 for Device 2. Setup packets are ACKed.
always accepted regardless of the Direction Select and Arm 1: ACK occurred
0: ACK did not occur

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 CY7C67200

Device n Endpoint n Count Result Register [R/W]

■ Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288]
■ Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298]
■ Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8]
■ Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8]
■ Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8]
■ Device n Endpoint 5 Count Result Register [Device 1: 0x0258 Device 2: 0x02D8]
■ Device n Endpoint 6 Count Result Register [Device 1: 0x0268 Device 2: 0x02E8]
■ Device n Endpoint 7 Count Result Register [Device 1: 0x0278 Device 2: 0x02F8]

Figure 34. Device n Endpoint n Count Result Register

Bit # 15 14 13 12 11 10 9 8
Field Result...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
Field ...Result
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X

Register Description Result (Bits [15:0])

The Device n Endpoint n Count Result register contains the size The Result field contains the differences in bytes between the
difference in bytes between the Endpoint Count specified in the received packet and the value specified in the Device n Endpoint
Device n Endpoint n Count register and the last packet received. n Count register. If an overflow condition occurs, Result [15:10]
If an overflow or underflow condition occurs, that is the received is set to ‘111111’, a 2’s complement value indicating the
packet length differs from the value specified in the Device n additional byte count of the received packet. If an underflow
Endpoint n Count register, the Length Exception Flag bit in the condition occurs, Result [15:0] indicates the excess byte count
Device n Endpoint n Status register will be set. The value in this (number of bytes not used).
register is only considered when the Length Exception Flag bit is
set and the Error Flag bit is not set; both bits are in the Device n Reserved
Endpoint n Status register. All reserved bits must be written as ‘0’.
The Device n Endpoint n Count Result register is a memory
based register that must be initialized to 0x0000 before USB
Device operations are initiated. After initialization, this register
must not be written to again.

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 CY7C67200

Device n Interrupt Enable Register [R/W]

■ Device 1 Interrupt Enable Register 0xC08C
■ Device 2 Interrupt Enable Register 0xC0AC

Figure 35. Device n Interrupt Enable Register

Bit # 15 14 13 12 11 10 9 8
VBUS ID Interrupt Reserved SOF/EOP Reserved SOF/EOP Reset
Interrupt Enable Timeout Interrupt Interrupt
Field Enable Interrupt Enable Enable Enable
Read/Write R/W R/W - - R/W - R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
EP7 Interrupt EP6 Interrupt EP5 Interrupt EP4 Interrupt EP3 Interrupt EP2 Interrupt EP1 Interrupt EP0 Interrupt
Field Enable Enable Enable Enable Enable Enable Enable Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description SOF/EOP Interrupt Enable (Bit 9)

The Device n Interrupt Enable register provides control over The SOF/EOP Interrupt Enable bit enables or disables the
device-related interrupts including eight different endpoint inter- SOF/EOP received interrupt.
rupts. 1: Enable SOF/EOP Received interrupt
VBUS Interrupt Enable (Bit 15) 0: Disable SOF/EOP Received interrupt
The VBUS Interrupt Enable bit enables or disables the OTG Reset Interrupt Enable (Bit 8)
VBUS interrupt. When enabled this interrupt triggers on both the
rising and falling edge of VBUS at the 4.4 V status (only The Reset Interrupt Enable bit enables or disables the USB
supported in Port 1A). This bit is only available for Device 1 and Reset Detected interrupt
is a reserved bit in Device 2. 1: Enable USB Reset Detected interrupt
1: Enable VBUS interrupt 0: Disable USB Reset Detected interrupt
0: Disable VBUS interrupt
EP7 Interrupt Enable (Bit 7)
ID Interrupt Enable (Bit 14) The EP7 Interrupt Enable bit enables or disables an endpoint
The ID Interrupt Enable bit enables or disables the OTG ID seven (EP7) Transaction Done interrupt. An EPx Transaction
interrupt. When enabled this interrupt triggers on both the rising Done interrupt triggers when any of the following responses or
and falling edge of the OTG ID pin (only supported in Port 1A). events occur in a transaction for the device’s given Endpoint:
This bit is only available for Device 1 and is a reserved bit in send/receive ACK, send STALL, Timeout occurs, IN Exception
Device 2. Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also be
1: Enable ID interrupt set so that NAK responses triggers this interrupt.
0: Disable ID interrupt 1: Enable EP7 Transaction Done interrupt
SOF/EOP Timeout Interrupt Enable (Bit 11) 0: Disable EP7 Transaction Done interrupt
The SOF/EOP Timeout Interrupt Enable bit enables or disables EP6 Interrupt Enable (Bit 6)
the SOF/EOP Timeout Interrupt. When enabled this interrupt
triggers when the USB host fails to send a SOF or EOP packet The EP6 Interrupt Enable bit enables or disables an endpoint six
within the time period specified in the Device n SOF/EOP Count (EP6) Transaction Done interrupt. An EPx Transaction Done
register. In addition, the Device n Frame register counts the interrupt triggers when any of the following responses or events
number of times the SOF/EOP Timeout Interrupt triggers occur in a transaction for the device’s given Endpoint:
between receiving SOF/EOPs. send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt
1: SOF/EOP timeout occurred Enable bit in the Device n Endpoint Control register can also be
0: SOF/EOP timeout did not occur set so that NAK responses triggers this interrupt.
1: Enable EP6 Transaction Done interrupt
0: Disable EP6 Transaction Done interrupt

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 CY7C67200

EP5 Interrupt Enable (Bit 5) EP2 Interrupt Enable (Bit 2)

The EP5 Interrupt Enable bit enables or disables an endpoint five The EP2 Interrupt Enable bit enables or disables an endpoint two
(EP5) Transaction Done interrupt. An EPx Transaction Done (EP2) Transaction Done interrupt. An EPx Transaction Done
interrupt triggers when any of the following responses or events interrupt triggers when any of the following responses or events
occur in a transaction for the device’s given Endpoint: occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also be Enable bit in the Device n Endpoint Control register can also be
set so that NAK responses triggers this interrupt. set so that NAK responses triggers this interrupt.
1: Enable EP5 Transaction Done interrupt 1: Enable EP2 Transaction Done interrupt
0: Disable EP5 Transaction Done interrupt 0: Disable EP2 Transaction Done interrupt

EP4 Interrupt Enable (Bit 4) EP1 Interrupt Enable (Bit 1)

The EP4 Interrupt Enable bit enables or disables an endpoint The EP1 Interrupt Enable bit enables or disables an endpoint
four (EP4) Transaction Done interrupt. An EPx Transaction Done one (EP1) Transaction Done interrupt. An EPx Transaction Done
interrupt triggers when any of the following responses or events interrupt triggers when any of the following responses or events
occur in a transaction for the device’s given Endpoint: occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also be Enable bit in the Device n Endpoint Control register can also be
set so that NAK responses triggers this interrupt. set so that NAK responses triggers this interrupt.
1: Enable EP4 Transaction Done interrupt 1: Enable EP1 Transaction Done interrupt
0: Disable EP4 Transaction Done interrupt 0: Disable EP1 Transaction Done interrupt

EP3 Interrupt Enable (Bit 3) EP0 Interrupt Enable (Bit 0)

The EP3 Interrupt Enable bit enables or disables an endpoint The EP0 Interrupt Enable bit enables or disables an endpoint
three (EP3) Transaction Done interrupt. An EPx Transaction zero (EP0) Transaction Done interrupt. An EPx Transaction
Done interrupt triggers when any of the following responses or Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given Endpoint: events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Timeout occurs, IN Exception send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, the NAK Interrupt Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control register can also be Enable bit in the Device n Endpoint Control register can also be
set so that NAK responses triggers this interrupt. set so that NAK responses triggers this interrupt.
1: Enable EP3 Transaction Done interrupt 1: Enable EP0 Transaction Done interrupt
0: Disable EP3 Transaction Done interrupt 0: Disable EP0 Transaction Done interrupt

Reserved
All reserved bits must be written as ‘0’.

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 CY7C67200

Device n Address Register [W]

■ Device 1 Address Register 0xC08E
■ Device 2 Address Register 0xC0AE
Figure 36. Device n Address Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Address
Read/Write - W W W W W W W
Default 0 0 0 0 0 0 0 0

Register Description
The Device n Address register holds the device address assigned by the host. This register initializes to the default address 0 at reset
but must be updated by firmware when the host assigns a new address. Only USB data sent to the address contained in this register
will be responded to, all others are ignored.
Address (Bits [6:0])
The Address field contains the USB address of the device assigned by the host.
Reserved
All reserved bits must be written as ‘0’.
Device n Status Register [R/W]
■ Device 1 Status Register 0xC090
■ Device 2 Status Register 0xC0B0
Figure 37. Device n Status Register
Bit # 15 14 13 12 11 10 9 8
VBUS ID Interrupt Reserved SOF/EOP Reset
Field Interrupt Flag Flag Interrupt Flag Interrupt Flag
Read/Write R/W R/W - - - - R/W R/W
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
EP7 Interrupt EP6 Interrupt EP5 Interrupt EP4 Interrupt EP3 Interrupt EP2 Interrupt EP1 Interrupt EP0 Interrupt
Field Flag Flag Flag Flag Flag Flag Flag Flag
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X

Register Description ID Interrupt Flag (Bit 14)

The Device n Status register provides status information for The ID Interrupt Flag bit indicates the status of the OTG ID
device operation. Pending interrupts can be cleared by writing a interrupt (only for Port 1A). When enabled this interrupt triggers
‘1’ to the corresponding bit. This register can be accessed by the on both the rising and falling edge of the OTG ID pin. This bit is
HPI interface. only available for Device 1 and is a reserved bit in Device 2.
VBUS Interrupt Flag (Bit 15) 1: Interrupt triggered
The VBUS Interrupt Flag bit indicates the status of the OTG 0: Interrupt did not trigger
VBUS interrupt (only for Port 1A). When enabled this interrupt SOF/EOP Interrupt Flag (Bit 9)
triggers on both the rising and falling edge of VBUS at 4.4 V. This
bit is only available for Device 1 and is a reserved bit in Device 2. The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP
received interrupt has triggered.
1: Interrupt triggered
1: Interrupt triggered
0: Interrupt did not trigger

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 CY7C67200

0: Interrupt did not trigger 0: Interrupt did not trigger

Reset Interrupt Flag (Bit 8) EP3 Interrupt Flag (Bit 3)

The Reset Interrupt Flag bit indicates if the USB Reset Detected The EP3 Interrupt Flag bit indicates if the endpoint three (EP3)
interrupt has triggered. Transaction Done interrupt has triggered. An EPx Transaction
1: Interrupt triggered Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given EP:
0: Interrupt did not trigger send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
EP7 Interrupt Flag (Bit 7) Enable bit in the Device n Endpoint Control register is set, this
The EP7 Interrupt Flag bit indicates if the endpoint seven (EP7) interrupt also triggers when the device NAKs host requests.
Transaction Done interrupt has triggered. An EPx Transaction 1: Interrupt triggered
Done interrupt triggers when any of the following responses or
events occur in a transaction for the device’s given EP: 0: Interrupt did not trigger
send/receive ACK, send STALL, Timeout occurs, IN Exception EP2 Interrupt Flag (Bit 2)
Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control register is set, this The EP2 Interrupt Flag bit indicates if the endpoint two (EP2)
interrupt also triggers when the device NAKs host requests. Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt triggers when any of the following responses or
1: Interrupt triggered events occur in a transaction for the device’s given EP:
0: Interrupt did not trigger send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
EP6 Interrupt Flag (Bit 6) Enable bit in the Device n Endpoint Control register is set, this
The EP6 Interrupt Flag bit indicates if the endpoint six (EP6) interrupt also triggers when the device NAKs host requests.
Transaction Done interrupt has triggered. An EPx Transaction 1: Interrupt triggered
Done interrupt triggers when any of the following responses or 0: Interrupt did not trigger
events occur in a transaction for the device’s given EP:
send/receive ACK, send STALL, Timeout occurs, IN Exception EP1 Interrupt Flag (Bit 1)
Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control register is set, this The EP1 Interrupt Flag bit indicates if the endpoint one (EP1)
interrupt also triggers when the device NAKs host requests. Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt triggers when any of the following responses or
1: Interrupt triggered events occur in a transaction for the device’s given EP:
0: Interrupt did not trigger send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
EP5 Interrupt Flag (Bit 5) Enable bit in the Device n Endpoint Control register is set, this
The EP5 Interrupt Flag bit indicates if the endpoint five (EP5) interrupt also triggers when the device NAKs host requests.
Transaction Done interrupt has triggered. An EPx Transaction 1: Interrupt triggered
Done interrupt triggers when any of the following responses or 0: Interrupt did not trigger
events occur in a transaction for the device’s given EP:
send/receive ACK, send STALL, Timeout occurs, IN Exception EP0 Interrupt Flag (Bit 0)
Error, or OUT Exception Error. In addition, if the NAK Interrupt The EP0 Interrupt Flag bit indicates if the endpoint zero (EP0)
Enable bit in the Device n Endpoint Control register is set, this Transaction Done interrupt has triggered. An EPx Transaction
interrupt also triggers when the device NAKs host requests. Done interrupt triggers when any of the following responses or
1: Interrupt triggered events occur in a transaction for the device’s given EP:
0: Interrupt did not trigger send/receive ACK, send STALL, Timeout occurs, IN Exception
Error, or OUT Exception Error. In addition, if the NAK Interrupt
EP4 Interrupt Flag (Bit 4) Enable bit in the Device n Endpoint Control register is set, this
interrupt also triggers when the device NAKs host requests.
The EP4 Interrupt Flag bit indicates if the endpoint four (EP4)
Transaction Done interrupt has triggered. An EPx Transaction 1: Interrupt triggered
Done interrupt triggers when any of the following responses or 0: Interrupt did not trigger
events occur in a transaction for the device’s given EP:
send/receive ACK, send STALL, Timeout occurs, IN Exception Reserved
Error, or OUT Exception Error. In addition, if the NAK Interrupt All reserved bits must be written as ‘0’.
Enable bit in the Device n Endpoint Control register is set, this
interrupt also triggers when the device NAKs host requests.
1: Interrupt triggered

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 CY7C67200

Device n Frame Number Register [R]

■ Device 1 Frame Number Register 0xC092
■ Device 2 Frame Number Register 0xC0B2
Figure 38. Device n Frame Number Register

Bit # 15 14 13 12 11 10 9 8
SOF/EOP SOF/EOP Reserved Frame...
Field Timeout Flag Timeout Interrupt Counter
Read/Write R R R R - R R R
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Frame
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0

Register Description The SOF/EOP Timeout Interrupt Counter field increments by 1

The Device n Frame Number register is a read only register that from 0 to 7 for each SOF/EOP Timeout Interrupt. This field resets
contains the Frame number of the last SOF packet received. This to 0 when a SOF/EOP is received. This field is only updated
register also contains a count of SOF/EOP Timeout occurrences. when the SOF/EOP Timeout Interrupt Enable bit in the Device n
Interrupt Enable register is set.
SOF/EOP Timeout Flag (Bit 15)
Frame (Bits [10:0])
The SOF/EOP Timeout Flag bit indicates when an SOF/EOP
Timeout Interrupt occurs. The Frame field contains the frame number from the last
received SOF packet in full speed mode. This field has no
1: An SOF/EOP Timeout interrupt occurred function for low-speed mode. If a SOF Timeout occurs, this field
0: An SOF/EOP Timeout interrupt did not occur contains the last received Frame number.

SOF/EOP Timeout Interrupt Counter (Bits [14:12])

Device n SOF/EOP Count Register [W]
■ Device 1 SOF/EOP Count Register 0xC094
■ Device 2 SOF/EOP Count Register 0xC0B4
Figure 39. Device n SOF/EOP Count Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - R R R R R R
Default 0 0 1 0 1 1 1 0

Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R R R R R R R R
Default 1 1 1 0 0 0 0 0

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 CY7C67200

Register Description The Count field contains the current value of the SOF/EOP down
The Device n SOF/EOP Count register must be written with the counter. At power-up and reset, this value is set to 0x2EE0 and
time expected between receiving a SOF/EOPs. If the SOF/EOP for expected 1-ms SOF/EOP intervals, this SOF/EOP count
counter expires before an SOF/EOP is received, an SOF/EOP should be increased slightly.
Timeout Interrupt can be generated. The SOF/EOP Timeout Reserved
Interrupt Enable and SOF/EOP Timeout Interrupt Flag are
located in the Device n Interrupt Enable and Status registers, All reserved bits must be written as ‘0’.
respectively.
OTG Control Registers
The SOF/EOP count must be set slightly greater than the
expected SOF/EOP interval. The SOF/EOP counter decrements There is one register dedicated for OTG operation. This register
at a 12-MHz rate. Therefore in the case of an expected 1-ms is covered in this section and summarized in Table 28.
SOF/EOP interval, the SOF/EOP count must be set slightly Table 28. OTG Registers
greater then 0x2EE0.
Register Name [9] Address R/W
Count (Bits [13:0]) OTG Control Register C098H R/W

OTG Control Register [0xC098] [R/W]

Figure 40. OTG Control Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved VBUS Receive Charge Pump VBUS D+ D–
Pull-up Disable Enable Discharge Pull-up Pull-up
Enable Enable Enable Enable
Read/Write - - R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field D+ D– Reserved OTG Data ID VBUS Valid
Pull-down Pull-down Status Status Flag
Enable Enable
Read/Write R/W R/W - - - R R R
Default 0 0 0 0 0 X X X

Register Description 0: OTG VBus charge pump disabled

The OTG Control register allows control and monitoring over the VBUS Discharge Enable (Bit 10)
OTG port on Port1A.
The VBUS Discharge Enable bit enables or disables a 2K-ohm
VBUS Pull-up Enable (Bit 13) discharge pull-down resistor onto OTG VBus.
The VBUS Pull-up Enable bit enables or disables a 500 ohm 1: 2K-ohm pull-down resistor enabled
pull-up resistor onto OTG VBus. 0: 2K-ohm pull-down resistor disabled
1: 500 ohm pull-up resistor enabled
D+ Pull-up Enable (Bit 9)
0: 500 ohm pull-up resistor disabled
The D+ Pull-up Enable bit enables or disables a pull-up resistor
Receive Disable (Bit 12) on the OTG D+ data line.
The Receive Disable bit enables or powers down (disables) the 1: OTG D+ dataline pull-up resistor enabled
OTG receiver section. 0: OTG D+ dataline pull-up resistor disabled
1: OTG receiver powered down and disabled
D– Pull-up Enable (Bit 8)
0: OTG receiver enabled
The D– Pull-up Enable bit enables or disables a pull-up resistor
Charge Pump Enable (Bit 11) on the OTG D– data line.
The Charge Pump Enable bit enables or disables the OTG VBus 1: OTG D– dataline pull-up resistor enabled
charge pump. 0: OTG D– dataline pull-up resistor disabled
1: OTG VBus charge pump enabled
Note
9. Errata: The VBUS interrupt in the Host/Device Status Registers [0xC090 and 0xC0B0] and OTG Control Register [0xC098] triggers multiple times whenever VBUS
is turned on. It should only trigger once when VBUS rises above 4.4 V and once when VBUS falls from above 4.4 V to 0 V. For more information, see the Errata on
page 84.

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 CY7C67200

D+ Pull-down Enable (Bit 7) 0: OTG VBus is less than 0.8 V

The D+ Pull-down Enable bit enables or disables a pull-down ID Status (Bit 1)
resistor on the OTG D+ data line.
The ID Status bit is a read only bit that indicates the state of the
1: OTG D+ dataline pull-down resistor enabled OTG ID pin on Port A.
0: OTG D+ dataline pull-down resistor disabled 1: OTG ID Pin is not connected directly to ground (>10K ohm)
D– Pull-down Enable (Bit 6) 0: OTG ID Pin is connected directly ground (< 10 ohm)
The D– Pull-down Enable bit enables or disables a pull-down VBUS Valid Flag (Bit 0)
resistor on the OTG D– data line.
The VBUS Valid Flag bit indicates whether OTG VBus is greater
1: OTG D– dataline pull-down resistor enabled than 4.4 V. After turning on VBUS, firmware should wait at least
0: OTG D– dataline pull-down resistor disabled 10 µs before this reading this bit.

OTG Data Status (Bit 2) 1: OTG VBus is greater then 4.4 V

0: OTG VBus is less then 4.4 V
The OTG Data Status bit is a read only bit and indicates the TTL
logic state of the OTG VBus pin. Reserved
1: OTG VBus is greater than 2.4 V All reserved bits must be written as ‘0’.
GPIO Registers
There are seven registers dedicated for GPIO operations. These seven registers are covered in this section and summarized in
Table 29.
Table 29. GPIO Registers
Register Name Address R/W
GPIO Control Register 0xC006 R/W
GPIO0 Output Data Register 0xC01E R/W
GPIO0 Input Data Register 0xC020 R
GPIO0 Direction Register 0xC022 R/W
GPIO1 Output Data Register 0xC024 R/W
GPIO1 Input Data Register 0xC026 R
GPIO1 Direction Register 0xC028 R/W

GPIO Control Register [0xC006] [R/W]

Figure 41. GPIO Control Register

Bit # 15 14 13 12 11 10 9 8
Write Protect Reserved Reserved SAS Mode
Field Enable Enable Select
Read/Write R/W - R - R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
HSS Reserved SPI Reserved Interrupt 0 Interrupt 0
Field Enable Enable Polarity Select Enable
Read/Write R/W - R/W - - - R/W R/W
Default 0 0 0 0 0 0 0 0

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 CY7C67200

Register Description Table 30. Mode Select Definition (continued)

The GPIO Control register configures the GPIO pins for various Mode Select
interface options. It also controls the polarity of the GPIO GPIO Configuration
[10:8]
interrupt on IRQ0 (GPIO24).
000 GPIO – General Purpose Input Output
Write Protect Enable (Bit 15)
HSS Enable (Bit 7)
The Write Protect Enable bit enables or disables the GPIO write
The HSS Enable bit routes HSS to GPIO[15:12].
protect. When Write Protect is enabled, the GPIO Mode Select
[15:8] bits are read-only until a chip reset. 1: HSS is routed to GPIO
1: Enable Write Protect 0: HSS is not routed to GPIOs. GPIO[15:12] are free for other
purposes.
0: Disable Write Protect
SPI Enable (Bit 5)
SAS Enable (Bit 11)
The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS Enable
The SAS Enable bit, when in SPI mode, reroutes the SPI port
bit is set, it overrides and routes the SPI_nSSI pin to GPIO15.
SPI_nSSI pin to GPIO[15] rather then GPIO[9].
1: SPI is routed to GPIO[11:8]
1: Reroute SPI_nss to GPIO[15]
0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for other
0: Leave SPI_nss on GPIO[9]
purposes.
Mode Select (Bits [10:8])
Interrupt 0 Polarity Select (Bit 1)
The Mode Select field selects how GPIO[15:0] and GPIO[24:19]
The Interrupt 0 Polarity Select bit selects the polarity for IRQ0.
are used as defined in Table 30.
1: Sets IRQ0 to rising edge
Table 30. Mode Select Definition
0: Sets IRQ0 to falling edge
Mode Select GPIO Configuration Interrupt 0 Enable (Bit 0)
[10:8]
111 Reserved The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO
110 SCAN – (HW) Scan diagnostic. For produc- bit on the interrupt Enable register must also be set in order for
tion test only. Not for normal operation this for this interrupt to be enabled.
101 HPI – Host Port Interface 1: Enable IRQ0
100 Reserved 0: Disable IRQ0
011 Reserved Reserved
010 Reserved All reserved bits must be written as ‘0’.
001 Reserved

GPIO 0 Output Data Register [0xC01E] [R/W]

Figure 42. GPIO 0 Output Data Register

Bit # 15 14 13 12 11 10 9 8
Field GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

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 CY7C67200

Register Description
The GPIO 0 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15 to
GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data written,
not the data on pins configured as inputs (see Input Data Register).
Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.

Reserved
All reserved bits must be written as ‘0’.

GPIO 1 Output Data Register [0xC024] [R/W]

Figure 43. GPIO n Output Data Register

Bit # 15 14 13 12 11 10 9 8
Field GPIO31 GPIO30 GPIO29 Reserved GPIO24
Read/Write R/W R/W R/W - - - - R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved
Read/Write R/W R/W R/W R/W R/W - - -
Default 0 0 0 0 0 0 0 0

Register Description
The GPIO 1 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15 to
GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data written,
not the data on pins configured as inputs (see Input Data Register).
Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.
Reserved
All reserved bits must be written as ‘0’.

GPIO 0 Input Data Register [0xC020] [R]

Figure 44. GPIO 0 Input Data Register

Bit # 15 14 13 12 11 10 9 8
Field GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0

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 CY7C67200

Register Description
The GPIO 0 Input Data register reads the input data of the GPIO pins. The GPIO 0 Input Data register reads from GPIO15 to GPIO0
while the GPIO 1 Input Data register reads from GPIO31 to GPIO19.
Every bit represents the voltage of that GPIO pin.

GPIO 1 Input Data Register [0xC026] [R]

Figure 45. GPIO 1 Input Data Register

Bit # 15 14 13 12 11 10 9 8
Field GPIO31 GPIO30 GPIO29 Reserved GPIO24
Read/Write R R R - - - - R
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved
Read/Write R R R R R - - -
Default 0 0 0 0 0 0 0 0

Register Description
The GPIO 1 Input Data register reads the input data of the GPIO pins. The GPIO 0 Input Data register reads from GPIO15 to GPIO0
while the GPIO 1 Input Data register reads from GPIO31 to GPIO19.
Every bit represents the voltage of that GPIO pin.

GPIO 0 Direction Register [0xC022] [R/W]

Figure 46. GPIO 0 Direction Register

Bit # 15 14 13 12 11 10 9 8
Field GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

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 CY7C67200

Register Description
The GPIO 0 Direction register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction register controls
GPIO15 to GPIO0 while the GPIO 1 Direction register controls GPIO31 to GPIO19.
When any bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register is set to
‘0’, the corresponding GPIO data pin becomes an input.

Reserved
All reserved bits must be written as ‘0’.

GPIO 1 Direction Register [0xC028] [R/W]

Figure 47. GPIO 1 Direction Register

Bit # 15 14 13 12 11 10 9 8
Field GPIO31 GPIO30 GPIO29 Reserved GPIO24
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description
The GPIO 1 Direction register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction register controls
GPIO15 to GPIO0 while the GPIO 1 Direction register controls GPIO31 to GPIO19.
When any bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register is set to
‘0’, the corresponding GPIO data pin becomes an input.

Reserved
All reserved bits must be written as ‘0’.

HSS Registers
There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized in Table 31.
Table 31. HSS Registers
Register Name Address R/W
HSS Control Register 0xC070 R/W
HSS Baud Rate Register 0xC072 R/W
HSS Transmit Gap Register 0xC074 R/W
HSS Data Register 0xC076 R/W
HSS Receive Address Register 0xC078 R/W
HSS Receive Length Register 0xC07A R/W
HSS Transmit Address Register 0xC07C R/W
HSS Transmit Length Register 0xC07E R/W

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 CY7C67200

HSS Control Register [0xC070] [R/W]

Figure 48. HSS Control Register

Bit # 15 14 13 12 11 10 9 8
HSS RTS CTS XOFF XOFF CTS Receive Done
Enable Polarity Select Polarity Select Enable Enable Interrupt Interrupt
Field Enable Enable
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Transmit Receive One Transmit Packet Receive Receive Receive
Done Interrupt Done Interrupt Stop Bit Ready Mode Overflow Packet Ready Ready
Field Enable Enable Select Flag Flag Flag
Read/Write R/W R/W R/W R R/W R/W R R
Default 0 0 0 0 0 0 0 0

Register Description Receive Interrupt Enable (Bit 9)

The HSS Control register provides high-level status and control The Receive Interrupt Enable bit enables or disables the Receive
over the HSS port. Ready and Receive Packet Ready interrupts.

HSS Enable (Bit 15) 1: Enable the Receive Ready and Receive Packet Ready inter-
rupts
The HSS Enable bit enables or disables HSS operation.
0: Disable the Receive Ready and Receive Packet Ready inter-
1: Enables HSS operation rupts
0: Disables HSS operation
Done Interrupt Enable (Bit 8)
RTS Polarity Select (Bit 14) The Done Interrupt Enable bit enables or disables the Transmit
The RTS Polarity Select bit selects the polarity of RTS. Done and Receive Done interrupts.
1: RTS is true when LOW 1: Enable the Transmit Done and Receive Done interrupts
0: RTS is true when HIGH 0: Disable the Transmit Done and Receive Done interrupts

CTS Polarity Select (Bit 13) Transmit Done Interrupt Flag (Bit 7)
The CTS Polarity Select bit selects the polarity of CTS. The Transmit Done Interrupt Flag bit indicates the status of the
Transmit Done Interrupt. It will set when a block transmit is
1: CTS is true when LOW finished. To clear the interrupt, a ‘1’ must be written to this bit.
0: CTS is true when HIGH 1: Interrupt triggered
XOFF (Bit 12) 0: Interrupt did not trigger
The XOFF bit is a read-only bit that indicates if an XOFF has Receive Done Interrupt Flag (Bit 6)
been received. This bit is automatically cleared when an XON is
received. The Receive Done Interrupt Flag bit indicates the status of the
Receive Done Interrupt. It will set when a block transmit is
1: XOFF received finished. To clear the interrupt, a ‘1’ must be written to this bit.
0: XON received 1: Interrupt triggered
XOFF Enable (Bit 11) 0: Interrupt did not trigger
The XOFF Enable bit enables or disables XON/XOFF software
handshaking. One Stop Bit (Bit 5)

1: Enable XON/XOFF software handshaking The One Stop Bit bit selects between one and two stop bits for
transmit byte mode. In receive mode, the number of stop bits
0: Disable XON/XOFF software handshaking may vary and does not need to be fixed.
CTS Enable (Bit 10) 1: One stop bit
The CTS Enable bit enables or disables CTS/RTS hardware 0: Two stop bits
handshaking.
1: Enable CTS/RTS hardware handshaking
0: Disable CTS/RTS hardware handshaking

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 CY7C67200

Transmit Ready (Bit 4) Receive Packet Ready Flag (Bit 1)

The Transmit Ready bit is a read only bit that indicates if the HSS The Receive Packet Ready Flag bit is a read only bit that
Transmit FIFO is ready for the CPU to load new data for trans- indicates if the HSS receive FIFO is full with eight bytes.
mission. 1: HSS receive FIFO is full
1: HSS transmit FIFO ready for loading 0: HSS receive FIFO is not full
0: HSS transmit FIFO not ready for loading
Receive Ready Flag (Bit 0)
Packet Mode Select (Bit 3) The Receive Ready Flag is a read only bit that indicates if the
The Packet Mode Select bit selects between Receive Packet HSS receive FIFO is empty.
Ready and Receive Ready as the interrupt source for the RxIntr 1: HSS receive FIFO is not empty (one or more bytes is reading
interrupt. for reading)
1: Selects Receive Packet Ready as the source 0: HSS receive FIFO is empty
0: Selects Receive Ready as the source

Receive Overflow Flag (Bit 2)

The Receive Overflow Flag bit indicates if the Receive FIFO
overflowed when set. This flag can be cleared by writing a ‘1’ to
this bit.
1: Overflow occurred
0: Overflow did not occur
HSS Baud Rate Register [0xC072] [R/W]

Figure 49. HSS Baud Rate Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved Baud...
Read/Write - - - R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Baud
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 1 0 1 1 1

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 CY7C67200

Register Description
The HSS Baud Rate register sets the HSS Baud Rate. At reset, the default value is 0x0017 which sets the baud rate to 2.0 MHz.

Baud (Bits [12:0])

The Baud field is the baud rate divisor minus one, in units of 1/48 MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts a
constraint on the Baud Value as follows: (24 – 1) < Baud > (5000 – 1)

Reserved
All reserved bits must bit written as ‘0’.

HSS Transmit Gap Register [0xC074] [R/W]

Figure 50. HSS Transmit Gap Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field Transmit Gap Select
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 1 0 0 1

Register Description
The HSS Transmit Gap register is only valid in block transmit mode. It allows for a programmable number of stop bits to be inserted
thus overwriting the One Stop Bit in the HSS Control register. The default reset value of this register is 0x0009, equivalent to two stop
bits.

Transmit Gap Select (Bits [7:0])

The Transmit Gap Select field sets the inactive time between transmitted bytes. The inactive time = (Transmit Gap Select – 7) * bit
time. Therefore an Transmit Gap Select Value of 8 is equal to having one Stop bit.

Reserved
All reserved bits must be written as ‘0’.

HSS Data Register [0xC076] [R/W]

Figure 51. HSS Data Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
Field Data
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X

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 CY7C67200

Register Description
The HSS Data register contains data received on the HSS port (not for block receive mode) when read. This receive data is valid
when the Receive Ready bit of the HSS Control register is set to ‘1’. Writing to this register initiates a single byte transfer of data. The
Transmit Ready Flag in the HSS Control register must read ‘1’ before writing to this register (this avoids disrupting the previous/current
transmission).
Data (Bits [7:0])
The Data field contains the data received or to be transmitted on the HSS port.
Reserved
All reserved bits must be written as ‘0’.

HSS Receive Address Register [0xC078] [R/W]

Figure 52. HSS Receive Address Register

Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description
The HSS Receive Address register is used as the base pointer address for the next HSS block receive transfer.
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block receive transfer.

HSS Receive Counter Register [0xC07A] [R/W]

Figure 53. HSS Receive Counter Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved Counter...
Read/Write - - - - - - R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Counter
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

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 CY7C67200

Register Description
The HSS Receive Counter register designates the block byte length for the next HSS receive transfer. This register must be loaded
with the word count minus one to start the block receive transfer. As each byte is received this register value is decremented. When
read, this register indicates the remaining length of the transfer.

Counter (Bits [9:0])

The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When the
transfer is complete this register returns 0x03FF until reloaded.

Reserved
All reserved bits must be written as ‘0’.

HSS Transmit Address Register [0xC07C] [R/W]

Figure 54. HSS Transmit Address Register

Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description
The HSS Transmit Address register is used as the base pointer address for the next HSS block transmit transfer.

Address (Bits [15:0])

The Address field sets the base pointer address for the next HSS block transmit transfer.

HSS Transmit Counter Register [0xC07E] [R/W]

Figure 55. HSS Transmit Counter Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved Counter...
Read/Write - - - - - - R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Counter
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

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 CY7C67200

Register Description HPI Registers

The HSS Transmit Counter register designates the block byte There are five registers dedicated to HPI operation. In addition,
length for the next HSS transmit transfer. This register must be there is an HPI status port which can be address over HPI. Each
loaded with the word count minus one to start the block transmit of these registers is covered in this section and are summarized
transfer. As each byte is transmitted this register value is decre- in Table 32.
mented. When read, this register indicates the remaining length
of the transfer. Table 32. HPI Registers

Counter (Bits [9:0]) Register Name Address R/W

The Counter field value is equal to the word count minus one HPI Breakpoint Register 0x0140 R
giving a maximum value of 0x03FF (1023) or 2048 bytes. When Interrupt Routing Register 0x0142 R
the transfer is complete this register returns 0x03FF until SIE1msg Register 0x0144 W
reloaded.
SIE2msg Register 0x0148 W
Reserved HPI Mailbox Register 0xC0C6 R/W
All reserved bits must be written as ‘0’.

HPI Breakpoint Register [0x0140] [R]

Figure 56. HPI Breakpoint Register

Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0

Register Description
The HPI Breakpoint register is a special on-chip memory location, which the external processor can access using normal HPI memory
read/write cycles. This register is read-only by the CPU but is read/write by the HPI port. The contents of this register have the same
effect as the Breakpoint register [0xC014]. This special Breakpoint register is used by software debuggers which interface through
the HPI port instead of the serial port.
When the program counter matches the Breakpoint Address, the INT127 interrupt triggers. To clear this interrupt, a zero value must
be written to this register.

Address (Bits [15:0])

The Address field is a 16-bit field containing the breakpoint address.

Interrupt Routing Register [0x0142] [R]

Figure 57. Interrupt Routing Register

Bit # 15 14 13 12 11 10 9 8
VBUS to HPI ID to HPI SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Swap 1
Field Enable Enable HPI Enable CPU Enable HPI Enable CPU Enable Enable Enable
Read/Write R R R R R R R R
Default 0 0 0 1 0 1 0 0

Bit # 7 6 5 4 3 2 1 0
Resume2 to Resume1 to Reserved Done2 to HPI Done1 to HPI Reset1 to HPI HPI Swap 0
Field HPI Enable HPI Enable Enable Enable Enable Enable
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

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 CY7C67200

Register Description 0: Do not route signal to CPU

The Interrupt Routing register allows the HPI port to take over Reset2 to HPI Enable (Bit 9)
some or all of the SIE interrupts that usually go to the on-chip
CPU. This register is read-only by the CPU but is read/write by The Reset2 to HPI Enable bit routes the USB Reset interrupt that
the HPI port. By setting the appropriate bit to ‘1’, the SIE interrupt occurs on Device 2 to the HPI port instead of the on-chip CPU.
is routed to the HPI port to become the HPI_INTR signal and also 1: Route signal to HPI port
readable in the HPI Status register. The bits in this register select
where the interrupts are routed. The individual interrupt enable 0: Do not route signal to HPI port
is handled in the SIE interrupt enable register. HPI Swap 1 Enable (Bit 8)
VBUS to HPI Enable (Bit 15) Both HPI Swap bits (bits 8 and 0) must be set to identical values.
The VBUS to HPI Enable bit routes the OTG VBUS interrupt to When set to ‘00’, the most significant data byte goes to
the HPI port instead of the on-chip CPU. HPI_D[15:8] and the least significant byte goes to HPI_D[7:0].
This is the default setting. By setting to ‘11’, the most significant
1: Route signal to HPI port data byte goes to HPI_D[7:0] and the least significant byte goes
0: Do not route signal to HPI port to HPI_D[15:8].

ID to HPI Enable (Bit 14) Resume2 to HPI Enable (Bit 7)

The ID to HPI Enable bit routes the OTG ID interrupt to the HPI The Resume2 to HPI Enable bit routes the USB Resume
port instead of the on-chip CPU. interrupt that occurs on Host 2 to the HPI port instead of the
on-chip CPU.
1: Route signal to HPI port
1: Route signal to HPI port
0: Do not route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP2 to HPI Enable (Bit 13)
Resume1 to HPI Enable (Bit 6)
The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt
to the HPI port. The Resume1 to HPI Enable bit routes the USB Resume
interrupt that occurs on Host 1 to the HPI port instead of the
1: Route signal to HPI port on-chip CPU.
0: Do not route signal to HPI port 1: Route signal to HPI port
SOF/EOP2 to CPU Enable (Bit 12) 0: Do not route signal to HPI port
The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2 Done2 to HPI Enable (Bit 3)
interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can
be routed to both the on-chip CPU and the HPI port the firmware The Done2 to HPI Enable bit routes the Done interrupt for
must ensure only one of the two (CPU, HPI) resets the interrupt. Host/Device 2 to the HPI port instead of the on-chip CPU.
1: Route signal to CPU 1: Route signal to HPI port
0: Do not route signal to CPU 0: Do not route signal to HPI port

SOF/EOP1 to HPI Enable (Bit 11) Done1 to HPI Enable (Bit 2)

The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt The Done1 to HPI Enable bit routes the Done interrupt for
to the HPI port. Host/Device 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port 1: Route signal to HPI port
0: Do not route signal to HPI port 0: Do not route signal to HPI port

SOF/EOP1 to CPU Enable (Bit 10) Reset1 to HPI Enable (Bit 1)

The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1 The Reset1 to HPI Enable bit routes the USB Reset interrupt that
interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt can occurs on Device 1 to the HPI port instead of the on-chip CPU.
be routed to both the on-chip CPU and the HPI port the firmware 1: Route signal to HPI port
must ensure only one of the two (CPU, HPI) resets the interrupt.
0: Do not route signal to HPI port
1: Route signal to CPU

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 CY7C67200

HPI Swap 0 Enable (Bit 0)

Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to ‘00’, the most significant data byte goes to HPI_D[15:8]
and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant data byte goes to
HPI_D[7:0] and the least significant byte goes to HPI_D[15:8].

SIEXmsg Register [W] [10]

• SIE1msg Register 0x0144
• SIE2msg Register 0x0148

Figure 58. SIEXmsg Register

Bit # 15 14 13 12 11 10 9 8
Field Data...
Read/Write W W W W W W W W
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
Field ...Data
Read/Write W W W W W W W W
Default X X X X X X X X

Register Description
The SIEXmsg register allows an interrupt to be generated on the HPI port. Any write to this register causes the SIEXmsg flag in the
HPI Status Port to go high and also causes an interrupt on the HPI_INTR pin. The SIEXmsg flag is automatically cleared when the
HPI port reads from this register.

Data (Bits [15:0])

The Data field[15:0] simply must have any value written to it to cause SIExmsg flag in the HPI Status Port to go high.

HPI Mailbox Register [0xC0C6] [R/W]

Figure 59. HPI Mailbox Register

Bit # 15 14 13 12 11 10 9 8
Field Message...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Message
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description
The HPI Mailbox register provides a common mailbox between the CY7C67200 and the external host processor.
If enabled, the HPI Mailbox RX Full interrupt triggers when the external host processor writes to this register. When the CY7C67200
reads this register the HPI Mailbox RX Full interrupt automatically gets cleared.
If enabled, the HPI Mailbox TX Empty interrupt triggers when the external host processor reads from this register. The HPI Mailbox
TX Empty interrupt is automatically cleared when the CY7C67200 writes to this register.
In addition, when the CY7C67200 writes to this register, the HPI_INTR signal on the HPI port asserts signaling the external processor
that there is data in the mailbox to read. The HPI_INTR signal deasserts when the external host processor reads from this register.

Message (Bits [15:0])

The Message field contains the message that the host processor wrote to the HPI Mailbox register.
Note
10. Errata: The SIE1msg and SIE2msg Registers [0x0144 and 0x0148] are not initialized at power up. For more information, see the Errata on page 84.

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 CY7C67200

HPI Status Port [] [HPI: R]

Figure 60. HPI Status Port

Bit # 15 14 13 12 11 10 9 8
VBUS ID Reserved SOF/EOP2 Reserved SOF/EOP1 Reset2 Mailbox In
Field Flag Flag Flag Flag Flag Flag
Read/Write R R - R - R R R
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
Resume2 Resume1 SIE2msg SIE1msg Done2 Done1 Reset1 Mailbox Out
Field Flag Flag Flag Flag Flag Flag
Read/Write R R R R R R R R
Default X X X X X X X X

Register Description 0: Interrupt did not trigger

The HPI Status Port provides the external host processor with Mailbox In Flag (Bit 8)
the MailBox status bits plus several SIE status bits. This register
is not accessible from the on-chip CPU. The additional SIE status The Mailbox In Flag bit is a read-only bit that indicates if a
bits are provided to aid external device driver firmware devel- message is ready in the incoming mailbox. This interrupt clears
opment, and are not recommended for applications that do not when on-chip CPU reads from the HPI Mailbox register.
have an intimate relationship with the on-chip BIOS. 1: Interrupt triggered
Reading from the HPI Status Port does not result in a CPU HPI 0: Interrupt did not trigger
interface memory access cycle. The external host may continu-
ously poll this register without degrading the CPU or DMA perfor- Resume2 Flag (Bit 7)
mance. The Resume2 Flag bit is a read-only bit that indicates if a USB
VBUS Flag (Bit 15) resume interrupt occurs on either Host/Device 2.

The VBUS Flag bit is a read-only bit that indicates whether OTG 1: Interrupt triggered
VBus is greater than 4.4 V. After turning on VBUS, firmware 0: Interrupt did not trigger
should wait at least 10 µs before this reading this bit.
Resume1 Flag (Bit 6)
1: OTG VBus is greater then 4.4 V
The Resume1 Flag bit is a read-only bit that indicates if a USB
0: OTG VBus is less then 4.4 V resume interrupt occurs on either Host/Device 1.
ID Flag (Bit 14) 1: Interrupt triggered
The ID Flag bit is a read-only bit that indicates the state of the 0: Interrupt did not trigger
OTG ID pin.
SIE2msg (Bit 5)
SOF/EOP2 Flag (Bit 12) The SIE2msg Flag bit is a read-only bit that indicates if the
The SOF/EOP2 Flag bit is a read-only bit that indicates if a CY7C67200 CPU has written to the SIE2msg register. This bit is
SOF/EOP interrupt occurs on either Host/Device 2. cleared on an HPI read.
1: Interrupt triggered 1: The SIE2msg register has been written by the CY7C67200
0: Interrupt did not trigger CPU
0: The SIE2msg register has not been written by the CY7C67200
SOF/EOP1 Flag (Bit 10) CPU
The SOF/EOP1 Flag bit is a read-only bit that indicates if a
SOF/EOP interrupt occurs on either Host/Device 1. SIE1msg (Bit 4)

1: Interrupt triggered The SIE1msg Flag bit is a read-only bit that indicates if the
CY7C67200 CPU has written to the SIE1msg register. This bit is
0: Interrupt did not trigger cleared on an HPI read.
Reset2 Flag (Bit 9) 1: The SIE1msg register has been written by the CY7C67200
CPU
The Reset2 Flag bit is a read-only bit that indicates if a USB
Reset interrupt occurs on either Host/Device 2. 0: The SIE1msg register has not been written by the CY7C67200
CPU
1: Interrupt triggered

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 CY7C67200

Done2 Flag (Bit 3) 1: Interrupt triggered

In host mode the Done2 Flag bit is a read-only bit that indicates 0: Interrupt did not trigger
if a host packet done interrupt occurs on Host 2. In device mode
this read only bit indicates if any of the endpoint interrupts occurs Reset1 Flag (Bit 1)
on Device 2. Firmware needs to determine which endpoint The Reset1 Flag bit is a read-only bit that indicates if a USB
interrupt occurred. Reset interrupt occurs on either Host/Device 1.
1: Interrupt triggered 1: Interrupt triggered
0: Interrupt did not trigger 0: Interrupt did not trigger
Done1 Flag (Bit 2) Mailbox Out Flag (Bit 0)
In host mode the Done 1 Flag bit is a read-only bit that indicates The Mailbox Out Flag bit is a read-only bit that indicates if a
if a host packet done interrupt occurs on Host 1. In device mode message is ready in the outgoing mailbox. This interrupt clears
this read-only bit indicates if any of the endpoint interrupts occurs when the external host reads from the HPI Mailbox register.
on Device 1. Firmware needs to determine which endpoint
interrupt occurred. 1: Interrupt triggered
0: Interrupt did not trigger

SPI Registers
There are 12 registers dedicated to SPI operation. Each register is covered in this section and summarized in Table 33.
Table 33. SPI Registers
Register Name Address R/W
SPI Configuration Register 0xC0C8 R/W
SPI Control Register 0xC0CA R/W
SPI Interrupt Enable Register 0xC0CC R/W
SPI Status Register 0xC0CE R
SPI Interrupt Clear Register 0xC0D0 W
SPI CRC Control Register 0xC0D2 R/W
SPI CRC Value 0xC0D4 R/W
SPI Data Register 0xC0D6 R/W
SPI Transmit Address Register 0xC0D8 R/W
SPI Transmit Count Register 0xC0DA R/W
SPI Receive Address Register 0xC0DC R/W
SPI Receive Count Register 0xC0DE R/W

SPI Configuration Register [0xC0C8] [R/W]

Figure 61. SPI Configuration Register

Bit # 15 14 13 12 11 10 9 8
3Wire Phase SCK Polarity Scale Select Reserved
Field Enable Select Select
Read/Write R/W R/W R/W R/W R/W R/W R/W -
Default 1 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Master Master SS SS Delay Select
Field Active Enable Enable Enable
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 1 1 1 1 1

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 CY7C67200

Register Description
The SPI Configuration register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.

3Wire Enable (Bit 15) Master Active Enable (Bit 7)

The 3Wire Enable bit indicates if the MISO and MOSI data lines The Master Active Enable bit is a read-only bit that indicates if
are tied together allowing only half duplex operation. the master state machine is active or idle. This field only applies
1: MISO and MOSI data lines are tied together to master mode.

0: Normal MISO and MOSI Full Duplex operation (not tied 1: Master state machine is active
together) 0: Master state machine is idle

Phase Select (Bit 14) Master Enable (Bit 6)

The Phase Select bit selects advanced or delayed SCK phase. The Master Enable bit sets the SPI interface to master or slave.
This field only applies to master mode. This bit is only writable when the Master Active Enable bit reads
1: Advanced SCK phase ‘0’, otherwise value will not change.

0: Delayed SCK phase 1: Master SPI interface

0: Slave SPI interface
SCK Polarity Select (Bit 13)
This SCK Polarity Select bit selects the polarity of SCK. SS Enable (Bit 5)

1: Positive SCK polarity The SS Enable bit enables or disables the master SS output.

0: Negative SCK polarity 1: Enable master SS output

0: Disable master SS output (three-state master SS output, for
Scale Select (Bits [12:9]) single SS line in slave mode)
The Scale Select field provides control over the SCK frequency,
based on 48 MHz. See Table 34 for a definition of this field. This SS Delay Select (Bits [4:0])
field only applies to master mode. When the SS Delay Select field is set to ‘00000’ this indicates
manual mode. In manual mode SS is controlled by the SS
Table 34. Scale Select Field Definition for SCK Frequency Manual bit of the SPI Control register. When the SS Delay Select
field is set between ‘00001’ to ‘11111’, this value indicates the
Scale Select [12:9] SCK Frequency
count in half bit times of auto transfer delay for: SS LOW to SCK
0000 12 MHz active, SCK inactive to SS HIGH, SS HIGH time. This field only
0001 8 MHz applies to master mode.
0010 6 MHz
0011 4 MHz
0100 3 MHz
0101 2 MHz
0110 1.5 MHz
0111 1 MHz
1000 750 KHz
1001 500 KHz
1010 375 KHz
1011 250 KHz
1100 375 KHz
1101 250 KHz
1110 375 KHz
1111 250 KHz

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SPI Control Register [0xC0CA] [R/W]

Figure 62. SPI Control Register

Bit # 15 14 13 12 11 10 9 8
SCK FIFO Byte Full Duplex SS Read Transmit Receive
Field Strobe Init Mode Manual Enable Ready Data Ready
Read/Write W W R/W R/W R/w R/W R R
Default 0 0 0 0 0 0 0 1

Bit # 7 6 5 4 3 2 1 0
Transmit Receive Transmit Bit Length Receive Bit Length
Field Empty Full
Read/Write R R R/W R/W R/W R/W R/w R/W
Default 1 0 0 0 0 0 0 0

Register Description Read Enable (Bit 10)

The SPI Control register controls the SPI port. Fields apply to The Read Enable bit initiates a read phase for a master mode
both master and slave mode unless otherwise noted. transfer or set the slave to receive (in slave mode).

SCK Strobe (Bit 15) 1: Initiates a read phase for a master transfer or sets a slave to
receive. In master mode this bit is sticky and remains set until the
The SCK Strobe bit starts the SCK strobe at the selected read transfer begins.
frequency and polarity (set in the SPI Configuration register), but
not phase. This bit feature can only be enabled when in master 0: Initiates the write phase for slave operation
mode and must be during a period of inactivity. This bit is Transmit Ready (Bit 9)
self-clearing.
The Transmit Ready bit is a read-only bit that indicates if the
1: SCK Strobe Enable transmit port is ready to empty and ready to be written.
0: No Function 1: Ready for data to be written to the port. The transmit FIFO is
FIFO Init (Bit 14) not full.

The FIFO Init bit initializes the FIFO and clear the FIFO Error 0: Not ready for data to be written to the port
Status bit. This bit is self-clearing. Receive Data Ready (Bit 8)
1: FIFO Init Enable The Receive Data Ready bit is a read-only bit that indicates if the
0: No Function receive port has data ready.

Byte Mode (Bit 13) 1: Receive port has data ready to read

The Byte Mode bit selects between PIO (byte mode) and DMA 0: Receive port does not have data ready
(block mode) operation. Transmit Empty (Bit 7)
1: Set PIO (byte mode) operation The Transmit Empty bit is a read-only bit that indicates if the
0: Set DMA (block mode) operation transmit FIFO is empty.

Full Duplex (Bit 12) 1: Transmit FIFO is empty

The Full Duplex bit selects between full-duplex and half-duplex 0: Transmit FIFO is not empty
operation. Receive Full (Bit 6)
1: Enable full duplex. Full duplex is not allowed and will not set The Receive Full bit is a read-only bit that indicates if the receive
if the 3Wire Enable bit of the SPI Configuration register is set to FIFO is full.
‘1’
1: Receive FIFO is full
0: Enable half-duplex operation
0: Receive FIFO is not full
SS Manual (Bit 11)
Transmit Bit Length (Bits [5:3])
The SS Manual bit activates or deactivates SS if the SS Delay
Select field of the SPI Control register is all zeros and is The Transmit Bit Length field controls whether a full byte or
configured as master interface. This field only applies to master partial byte is to be transmitted. If Transmit Bit Length is ‘000’, a
mode. full byte is transmitted. If Transmit Bit Length is ‘001’ to ‘111’, the
value indicates the number of bits that will be transmitted.
1: Activate SS, master drives SS line asserted LOW
0: Deactivate SS, master drives SS line deasserted HIGH

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 CY7C67200

Receive Bit Length (Bits [2:0])

The Receive Bit Length field controls whether a full byte or partial byte will be received. If Receive Bit Length is ‘000’ then a full byte
will be received. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that will be received.

SPI Interrupt Enable Register [0xC0CC] [R/W]

Figure 63. SPI Interrupt Enable Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
...Reserved Receive Transmit Transfer
Field Interrupt Enable Interrupt Enable Interrupt Enable
Read/Write - - - - - R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description 1: Enables byte mode transmit interrupt

The SPI Interrupt Enable register controls the SPI port. 0: Disables byte mode transmit interrupt

Receive Interrupt Enable (Bit 2) Transfer Interrupt Enable (Bit 0)

The Receive Interrupt Enable bit enables or disables the byte The Transfer Interrupt Enable bit enables or disables the block
mode receive interrupt (RxIntVal). mode interrupt (XfrBlkIntVal).
1: Enable byte mode receive interrupt 1: Enables block mode interrupt
0: Disable byte mode receive interrupt 0: Disables block mode interrupt

Transmit Interrupt Enable (Bit 1) Reserved

The Transmit Interrupt Enable bit enables or disables the byte All reserved bits must be written as ‘0’.
mode transmit interrupt (TxIntVal).

SPI Status Register [0xC0CE] [R]

Figure 64. SPI Status Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
FIFO Error Reserved Receive Transmit Transfer
Field Flag Interrupt Flag Interrupt Flag Interrupt Flag
Read/Write R - - - - R R R
Default 0 0 0 0 0 0 0 0

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 CY7C67200

Register Description The Receive Interrupt Flag is a read only bit that indicates if a
The SPI Status register is a read only register that provides byte mode receive interrupt has triggered.
status for the SPI port. 1: Indicates a byte mode receive interrupt has triggered
0: Indicates a byte mode receive interrupt has not triggered
FIFO Error Flag (Bit 7)
The FIFO Error Flag bit is a read only bit that indicates if a FIFO Transmit Interrupt Flag (Bit 1)
error occurred. When this bit is set to ‘1’ and the Transmit Empty The Transmit Interrupt Flag is a read only bit that indicates a byte
bit of the SPI Control register is set to ‘1’, then a Tx FIFO mode transmit interrupt has triggered.
underflow has occurred. Similarly, when set with the Receive Full
1: Indicates a byte mode transmit interrupt has triggered
bit of the SPI Control register, a Rx FIFO overflow has
occured.This bit automatically clear when the SPI FIFO Init 0: Indicates a byte mode transmit interrupt has not triggered
Enable bit of the SPI Control register is set.
Transfer Interrupt Flag (Bit 0)
1: Indicates FIFO error
The Transfer Interrupt Flag is a read only bit that indicates a
0: Indicates no FIFO error block mode interrupt has triggered.
Receive Interrupt Flag (Bit 2) 1: Indicates a block mode interrupt has triggered
0: Indicates a block mode interrupt has not triggered

SPI Interrupt Clear Register [0xC0D0] [W]

Figure 65. SPI Interrupt Clear Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Reserved Transmit Transfer
Field Interrupt Clear Interrupt Clear
Read/Write - - - - - - W W
Default 0 0 0 0 0 0 0 0

Register Description Transfer Interrupt Clear (Bit 0)

The SPI Interrupt Clear register is a write-only register that allows The Transfer Interrupt Clear bit is a write-only bit that will clear
the SPI Transmit and SPI Transfer Interrupts to be cleared. the block mode interrupt. This bit is self clearing.
Transmit Interrupt Clear (Bit 1) 1: Clear the block mode interrupt
The Transmit Interrupt Clear bit is a write-only bit that clears the 0: No function
byte mode transmit interrupt. This bit is self-clearing. Reserved
1: Clear the byte mode transmit interrupt All reserved bits must be written as ‘0’.
0: No function
SPI CRC Control Register [0xC0D2] [R/W]

Figure 66. SPI CRC Control Register

Bit # 15 14 13 12 11 10 9 8
CRC Mode CRC CRC Receive One in Zero in Reserved...
Field Enable Clear CRC CRC CRC
Read/Write R/W R/W R/W R/W R/W R R -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

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 CY7C67200

Register Description 1: Clear CRC with all ones

The SPI CRC Control register provides control over the CRC 0: No Function
source and polynomial value.
Receive CRC (Bit 11)
CRC Mode (Bits [15:14) The Receive CRC bit determines whether the receive bit stream
The CRCMode field selects the CRC polynomial as defined in or the transmit bit stream is used for the CRC data input in full
Table 35. duplex mode. This bit is a don’t care in half-duplex mode.
1: Assigns the receive bit stream
Table 35. CRC Mode Definition 0: Assigns the transmit bit stream

CRCMode One in CRC (Bit 10)

CRC Polynomial
[9:8] The One in CRC bit is a read-only bit that indicates if the CRC
00 MMC 16-bit: X^16 + X^12 + X^5 + 1 value is all zeros or not.
(CCITT Standard) 1: CRC value is not all zeros
01 CRC7 7-bit: X^7+ X^3 + 1 0: CRC value is all zeros
10 MST 16-bit: X^16+ X^15 + X^2 + 1
Zero in CRC (Bit 9)
11 Reserved, 16-bit polynomial 1.
The Zero in CRC bit is a read-only bit that indicates if the CRC
CRC Enable (Bit 13) value is all ones or not.
The CRC Enable bit enables or disables the CRC operation. 1: CRC value is not all ones
1: Enables CRC operation 0: CRC value is all ones
0: Disables CRC operation Reserved
CRC Clear (Bit 12) All reserved bits must be written as ‘0’.
The CRC Clear bit will clear the CRC with a load of all ones. This
bit is self clearing and always reads ‘0’.

SPI CRC Value Register [0xC0D4] [R/W]

Figure 67. SPI CRC Value Register

Bit # 15 14 13 12 11 10 9 8
Field CRC...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1

Bit # 7 6 5 4 3 2 1 0
Field ...CRC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 1 1 1 1 1

Register Description
The SPI CRC Value register contains the CRC value.

CRC (Bits [15:0])

The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value will be a seven bit value [6:0]. Therefore bits [15:7] are
invalid in CRC7 mode.

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SPI Data Register [0xC0D6] [R/W]

Figure 68. SPI Data Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default X X X X X X X X

Bit # 7 6 5 4 3 2 1 0
Field Data
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X

Register Description
The SPI Data register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO byte
mode. This receive data is valid when the receive bit of the SPI Interrupt Value is set to ‘1’ (RxIntVal triggers) or the Receive Data
Ready bit of the SPI Control register is set to ‘1’. Writing to this register in PIO byte mode will initiate a transfer of data, the number of
bits defined by Transmit Bit Length field in the SPI Control register.

Data (Bits [7:0])

The Data field contains data received or to be transmitted on the SPI port.

Reserved
All reserved bits must be written as ‘0’.

SPI Transmit Address Register [0xC0D8] [R/W]

Figure 69. SPI Transmit Address Register

Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description
The SPI Transmit Address register is used as the base address for the SPI transmit DMA.

Address (Bits [15:0])

The Address field sets the base address for the SPI transmit DMA.

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SPI Transmit Count Register [0xC0DA] [R/W]

Figure 70. SPI Transmit Count Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - - - - R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description
The SPI Transmit Count register designates the block byte length for the SPI transmit DMA transfer.

Count (Bits [10:0])

The Count field sets the count for the SPI transmit DMA transfer.

Reserved
All reserved bits must be written as ‘0’.

SPI Receive Address Register [0xC0DC [R/W]

Figure 71. SPI Receive Address Register

Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description
The SPI Receive Address register is issued as the base address for the SPI Receive DMA.

Address (Bits [15:0])

The Address field sets the base address for the SPI receive DMA.

SPI Receive Count Register [0xC0DE] [R/W]

Figure 72. SPI Receive Count Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - - - - R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

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 CY7C67200

Register Description
The SPI Receive Count register designates the block byte length for the SPI receive DMA transfer.

Count (Bits [10:0])

The Count field sets the count for the SPI receive DMA transfer.

Reserved
All reserved bits must be written as ‘0’.

UART Registers
There are three registers dedicated to UART operation. Each of these registers is covered in this section and summarized in Table 36.
Table 36. UART Registers
Register Name Address R/W
UART Control Register 0xC0E0 R/W
UART Status Register 0xC0E2 R
UART Data Register 0xC0E4 R/W

UART Control Register [0xC0E0] [R/W]

Figure 73. UART Control Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
...Reserved Scale Baud UART
Field Select Select Enable
Read/Write - - - R/W R/W R/W R/W R/W
Default 0 0 0 0 0 1 1 1

Register Description Baud Select (Bits [3:1])

The UART Control register enables or disables the UART Refer to Table 37 for a definition of this field.
allowing GPIO7 (UART_TXD) and GPIO6 (UART_RXD) to be
freed up for general use. This register must also be written to set Table 37. UART Baud Select Definition
the baud rate, which is based on a 48-MHz clock. Baud Rate Baud Rate
Baud Select [3:1]
w/DIV8 = 0 w/DIV8 = 1
Scale Select (Bit 4)
000 115.2K baud 14.4K baud
The Scale Select bit acts as a prescaler that will divide the baud
rate by eight. 001 57.6K baud 7.2K baud
1: Enable prescaler 010 38.4K baud 4.8K baud
0: Disable prescaler 011 28.8K baud 3.6K baud
100 19.2K baud 2.4K baud
101 14.4K baud 1.8K baud
110 9.6K baud 1.2K baud
111 7.2K baud 0.9K baud

UART Enable (Bit 0)

The UART Enable bit enables or disables the UART.
1: Enable UART
0: Disable UART. This allows GPIO6 and GPIO7 to be used for
general use

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 CY7C67200

Reserved
All reserved bits must be written as ‘0’.

UART Status Register [0xC0E2] [R]

Figure 74. UART Status Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Receive Full Transmit Full
Read/Write - - - - - - R R
Default 0 0 0 0 0 0 0 0

Register Description
The UART Status register is a read-only register that indicates the status of the UART buffer.
Receive Full (Bit 1) Transmit Full (Bit 0)
The Receive Full bit indicates whether the receive buffer is full. The Transmit Full bit indicates whether the transmit buffer is full.
It can be programmed to interrupt the CPU as interrupt #5 when It can be programmed to interrupt the CPU as interrupt #4 when
the buffer is full. This can be done though the UART bit of the the buffer is empty. This can be done though the UART bit of the
Interrupt Enable register (0xC00E). This bit will automatically be Interrupt Enable register (0xC00E). This bit will automatically be
cleared when data is read from the UART Data register. set to ‘1’ after data is written by EZ-Host to the UART Data
1: Receive buffer full register (to be transmitted). This bit will automatically be cleared
to ‘0’ after the data is transmitted.
0: Receive buffer empty
1: Transmit buffer full (transmit busy)
0: Transmit buffer is empty and ready for a new byte of data
UART Data Register [0xC0E4] [R/W]

Figure 75. UART Data Register

Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0

Bit # 7 6 5 4 3 2 1 0
Field Data
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0

Register Description
The UART Data register contains data to be transmitted or received from the UART port. Data written to this register will start a data
transmission and also causes the UART Transmit Empty Flag of the UART Status register to set. When data received on the UART
port is read from this register, the UART Receive Full Flag of the UART Status register will be cleared.

Data (Bits [7:0])

The Data field is where the UART data to be transmitted or received is located

Reserved
All reserved bits must be written as ‘0’.

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 CY7C67200

Pin Diagram
The following describes the CY7C67200 48-pin FBGA.

Figure 76. EZ-OTG Pin Diagram

A1 A2 A3 A4 A5 A6
GND GPIO1/D1 GPIO3/D3 VCC nRESET Reserved

B1 B2 B3 B4 B5 B6
AGND GPIO0/D0 GPIO4/D4 GPIO6/D6/RX GPIO7/D7/TX GND

C1 C2 C3 C4 C5 C6

OTGVBUS DM2A GPIO2/D2 GPIO5/D5 GPIO8/D8/ GPIO9/D9/

MISO nSSI
D1 D2 D3 D4 D5 D6
CSWITCHA CSWITCHB DP2A GPIO11/D1/ GPIO10/D10/ VCC
MOSI SCK
E1 E2 E3 E4 E5 E6
BOOSTGND VSWITCH DP1A GPIO14/D14/ GPIO13/D13/ GPIO12/D12/
RTS RXD TXD
F1 F2 F3 F4 F5 F6
BOOSTVCC DM1A GPIO30/SDA GPIO29/ GPIO19/A0 GPIO15/D15/
OTGID CTS/nSSI

G1 G2 G3 G4 G5 G6
AVCC XTALOUT XTALIN GPIO23/nRD/ GPIO21/nCS/ GND
nWAIT nRESET

H1 H2 H3 H4 H5 H6
GND VCC GPIO31/SCL GPIO24/INT/ GPIO22/nWR GPIO20/A1
IRQ0

Pin Descriptions
Table 38. Pin Descriptions
Pin Name Type Description
H3 GPIO31/SCK IO GPIO31: General Purpose IO
SCK: I2C EEPROM SCK
F3 GPIO30/SDA IO GPIO30: General Purpose IO
SDA: I2C EEPROM SDA
F4 GPIO29/OTGID IO GPIO29: General Purpose IO
OTGID: Input for OTG ID pin. When used as OTGID, this pin must be
tied high through an external pull-up resistor. Assuming VCC = 3.0 V,
a 10K to 40K resistor must be used.
H4 GPIO24/INT/IRQ0 [11] IO GPIO24: General Purpose IO
INT: HPI INT
IRQ0: Interrupt Request 0. See Register 0xC006. This pin is also one
of two possible GPIO wakeup sources.
G4 GPIO23/nRD IO GPIO23: General Purpose IO
nRD: HPI nRD

Note
11. Errata: Part does not service USB ISRs when GPIO24 pin (also labeled as HPI_INT and IORDY) is low and any IDE register is read. For more information, see
the Errata on page 84.

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 CY7C67200

Table 38. Pin Descriptions (continued)

Pin Name Type Description
H5 GPIO22/nWR IO GPIO22: General Purpose IO
nWR: HPI nWR
G5 GPIO21/nCS IO GPIO21: General Purpose IO
nCS: HPI nCS
H6 GPIO20/A1 IO GPIO20: General Purpose IO
A1: HPI A1
F5 GPIO19/A0 IO GPIO19: General Purpose IO
A0: HPI A0
F6 GPIO15/D15/CTS/ IO GPIO15: General Purpose IO
nSSI D15: D15 for HPI
CTS: HSS CTS
nSSI: SPI nSSI
E4 GPIO14/D14/RTS IO GPIO14: General Purpose IO
D14: D14 for HPI
RTS: HSS RTS
E5 GPIO13/D13/RXD IO GPIO13: General Purpose IO
D13: D13 for HPI
RXD: HSS RXD (Data is received on this pin)
E6 GPIO12/D12/TXD IO GPIO12: General Purpose IO
D12: D12 for HPI
TXD: HSS TXD (Data is transmitted from this pin)
D4 GPIO11/D11/MOSI IO GPIO11: General Purpose IO
D11: D11 for HPI
MOSI: SPI MOSI
D5 GPIO10/D10/SCK IO GPIO10: General Purpose IO
D10: D10 for HPI
SCK: SPI SCK
C6 GPIO9/D9/nSSI IO GPIO9: General Purpose IO
D9: D9 for HPI
nSSI: SPI nSSI
C5 GPIO8/D8/MISO IO GPIO8: General Purpose IO
D8: D8 for HPI
MISO: SPI MISO
B5 GPIO7/D7/TX IO GPIO7: General Purpose IO
D7: D7 for HPI
TX: UART TX (Data is transmitted from this pin)
B4 GPIO6/D6/RX IO GPIO6: General Purpose IO
D6: D6 for HPI
RX: UART RX (Data is received on this pin)
C4 GPIO5/D5 IO GPIO5: General Purpose IO
D5: D5 for HPI
B3 GPIO4/D4 IO GPIO4: General Purpose IO
D4: D4 for HPI
A3 GPIO3/D3 IO GPIO3: General Purpose IO
D3: D3 for HPI
C3 GPIO2/D2 IO GPIO2: General Purpose IO
D2: D2 for HPI
A2 GPIO1/D1 IO GPIO1: General Purpose IO
D1: D1 for HPI
B2 GPIO0/D0 IO GPIO0: General Purpose IO
D0: D0 for HPI
F2 DM1A IO USB Port 1A D–
E3 DP1A IO USB Port 1A D+
C2 DM2A IO USB Port 2A D–

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 CY7C67200

Table 38. Pin Descriptions (continued)

Pin Name Type Description
D3 DP2A IO USB Port 2A D+
G3 XTALIN Input Crystal Input or Direct Clock Input
G2 XTALOUT Output Crystal output. Leave floating if direct clock source is used.
A5 nRESET Input Reset
A6 Reserved – Tie to Gnd for normal operation.
F1 BOOSTVCC Power Booster Power Input: 2.7 V to 3.6 V
E2 VSWITCH Analog Output Booster Switching Output
E1 BOOSTGND Ground Booster Ground
C1 OTGVBUS Analog IO USB OTG Vbus
D1 CSWITCHA Analog Charge Pump Capacitor
D2 CSWITCHB Analog Charge Pump Capacitor
G1 AVCC Power USB Power
B1 AGND Ground USB Ground
H2, D6, A4 VCC Power Main VCC
G6, B6, A1, H1 GND Ground Main Ground

Absolute Maximum Ratings Operating Conditions

This section lists the absolute maximum ratings. Stresses above TA (Ambient Temperature Under Bias) ......... –40°C to +85°C
those listed can cause permanent damage to the device.
Exposure to maximum rated conditions for extended periods can Supply Voltage (VCC, AVCC) .........................+3.0 V to +3.6 V
affect device operation and reliability. Supply Voltage (BoostVCC)[12] ......................+2.7 V to +3.6 V
Storage Temperature .................................. –40°C to +125°C Ground Voltage................................................................. 0 V
Ambient Temperature with Power Supplied.. –40°C to +85°C FOSC (Oscillator or Crystal Frequency).... 12 MHz ± 500 ppm
Supply Voltage to Ground Potential................0.0 V to +3.6 V ................................................................... Parallel Resonant
DC Input Voltage to Any General Purpose Input Pin.... 5.5 V
DC Voltage Applied to XTALIN ........... –0.5 V to VCC + 0.5 V
Static Discharge Voltage (per MIL-STD-883, Method 3015) >
2000 V
Max Output Current, per Input Output. ......................... 4 mA

Crystal Requirements (XTALIN, XTALOUT)

Table 39. Crystal Requirements
Crystal Requirements, (XTALIN, XTALOUT) Min Typical Max Unit
Parallel Resonant Frequency 12 MHz
Frequency Stability –500 +500 PPM
Load Capacitance 20 33 pF
Driver Level 500 µW
Start-up Time 5 ms
Mode of Vibration: Fundamental

Note
12. The on-chip voltage booster circuit boosts BoostVCC to provide a nominal 3.3 V VCC supply.

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 CY7C67200

DC Characteristics
Table 40. DC Characteristics[13]
Parameter Description Conditions Min. Typ. Max. Unit
VCC, AVCC Supply Voltage 3.0 3.3 3.6 V
BoosVCC Supply Voltage 2.7 – 3.6 V
VIH Input HIGH Voltage 2.0 – 5.5 V
VIL Input LOW Voltage – – 0.8 V
II Input Leakage Current 0< VIN < VCC –10.0 – +10.0 A
VOH Output Voltage HIGH IOUT = 4 mA 2.4 – – V
VOL Output LOW Voltage IOUT = –4 mA – – 0.4 V
IOH Output Current HIGH – – 4 mA
IOL Output Current LOW – – 4 mA
CIN Input Pin Capacitance Except D+/D– – – 10 pF
D+/D– – – 15 pF
VHYS Hysteresis on nReset Pin 250 – – mV
ICC[14, 15] Supply Current 2 transceivers powered – 80 100 mA
ICCB [14, 15]
Supply Current with Booster Enabled 2 transceivers powered – 135 180 mA
ISLEEP Sleep Current USB Peripheral: includes 1.5K – 210 500 A
internal pull up
Without 1.5K internal pull up – 5 30 A
ISLEEPB Sleep Current with Booster Enabled USB Peripheral: includes 1.5K – 210 500 A
internal pull up
Without 1.5K internal pull up – 5 30 A

Table 41. DC Characteristics: Charge Pump

Parameter Description Conditions Min. Typ. Max. Unit
VA_VBUS_OUT Regulated OTGVBUS Voltage 8 mA< ILOAD < 10 mA 4.4 – 5.25 V
TA_VBUS_RISE VBUS Rise Time ILOAD = 10 mA – 100 ms
IA_VBUS_OUT Maximum Load Current 8 – 10 mA
CDRD_VBUS OUTVBUS Bypass Capacitance 4.4 V< VBUS < 5.25 V 1.0 – 6.5 pF
VA_VBUS_LKG OTGVBUS Leakage Voltage OTGVBUS not driven – – 200 mV
VDRD_DATA_LKG Dataline Leakage Voltage – – 342 mV
ICHARGE Charge Pump Current Draw ILOAD = 8 mA – 20 20 mA
ILOAD = 0 mA – 0 1 mA
ICHARGEB Charge Pump Current Draw with ILOAD = 8 mA – 30 45 mA
Booster Active
ILOAD = 0 mA – 0 5 mA
IB_DSCHG_IN B-Device (SRP Capable) 0 V< VBUS < 5.25 V – – 8 mA
Discharge Current
VA_VBUS_VALID A-Device VBUS Valid 4.4 – – V

Notes
13. All tests were conducted with Charge pump off.
14. ICC and ICCB values are the same regardless of USB host or peripheral configuration.
15. There is no appreciable difference in ICC and ICCB values when only one transceiver is powered.

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 CY7C67200

Table 41. DC Characteristics: Charge Pump (continued)

Parameter Description Conditions Min. Typ. Max. Unit
VA_SESS_VALID A-Device Session Valid 0.8 – 2.0 V
VB_SESS_VALID B-Device Session Valid 0.8 – 4.0 V
VA_SESS_END B-Device Session End 0.2 – 0.8 V
E Efficiency When Loaded ILOAD = 8 mA, VCC = 3.3 V 75 – %
RPD Data Line Pull Down 14.25 – 24.8 
RA_BUS_IN A-device VBUS Input Impedance VBUS is not being driven 40 – 100 k
to GND
RB_SRP_UP B-device VBUS SRP Pull Up Pull-up voltage = 3.0 V 281 – – 
RB_SRP_DWN B-device VBUS SRP Pull Down 656 – – 

USB Transceiver
USB 2.0-compatible in full- and low-speed modes.
This product was tested as compliant to the USB-IF specification under the test identification number (TID) of 100390449 and is listed
on the USB-IF’s integrators list.

AC Timing Characteristics
Reset Timing
tRESET
nRESET

tIOACT
nRD or nWRL or nWRH

Reset Timing

Parameter Description Min. Typ. Max. Unit

tRESET nRESET Pulse Width 16 – – clocks[16]
tIOACT nRESET HIGH to nRD or nWRx Active 200 – – µs

Note
16. Clock is 12 MHz nominal.

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 CY7C67200

Clock Timing
tCLK
tLOW
XTALIN

tHIGH tFALL tRISE

Clock Timing
Parameter Description Min. Typ. Max. Unit
fCLK Clock Frequency – 12.0 – MHz
vXINH[17] Clock Input High 1.5 3.0 3.6 V
(XTALOUT left floating)
tCLK Clock Period 83.17 83.33 83.5 ns
tHIGH Clock High Time 36 – 44 ns
tLOW Clock Low Time 36 – 44 ns
tRISE Clock Rise Time – – 5.0 ns
tFALL Clock Fall Time – – 5.0 ns
Duty Cycle 45 – 55 %

I2C EEPROM Timing

1. I2C EEPROM Bus Timing - Serial I/O

tLOW tHIGH
tR tF

SCL
tSU.DAT tBUF
tSU.STA tHD.DAT tSU.STO
tHD.STA

SDA IN
tAA tDH

SDA OUT

Parameter Description Min. Typical Max. Unit

fSCL Clock Frequency – – 400 kHz
tLOW Clock Pulse Width Low 1300 – – ns
tHIGH Clock Pulse Width High 600 – – ns
tAA Clock Low to Data Out Valid 900 – – ns
tBUF Bus Idle Before New Transmission 1300 – – ns
tHD.STA Start Hold Time 600 – – ns
tSU.STA Start Setup Time 600 – – ns
tHD.DAT Data In Hold Time 0 – – ns
tSU.DAT Data In Setup Time 100 – – ns
tR Input Rise Time – – 300 ns
tF Input Fall Time – – 300 ns
tSU.STO Stop Setup Time 600 – – ns
tDH Data Out Hold Time 0 – – ns
Note
17. vXINH is required to be 3.0 V to obtain an internal 50/50 duty cycle clock.

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 CY7C67200

Figure 77. HPI (Host Port Interface) Write Cycle Timing

tCYC

tASU tWP tAH

ADDR [1:0]

tCSSU tCSH
nCS

nWR

nRD

Dout [15:0]
tDSU tWDH

Parameter Description Min. Typical Max. Unit

tASU Address Setup –1 – – ns
tAH Address Hold –1 – – ns
tCSSU Chip Select Setup –1 – – ns
tCSH Chip Select Hold –1 – – ns
tDSU Data Setup 6 – – ns
tWDH Write Data Hold 2 – – ns
tWP Write Pulse Width 2 – – T[18]
tCYC Write Cycle Time 6 – – T[18]

Note
18. T = system clock period = 1/48 MHz.

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 CY7C67200

HPI (Host Port Interface) Read Cycle Timing

tCYC

tASU tRP tAH

ADDR [1:0]

tCSSU tCSH
nCS

nWR tRDH

nRD

Din [15:0]

tACC tRDH

Parameter Description Min. Typ. Max. Unit

tASU Address Setup –1 – – ns
tAH Address Hold –1 – – ns
tCSSU Chip Select Setup –1 – – ns
tCSH Chip Select Hold –1 – – ns
tACC Data Access Time, from HPI_nRD falling – – 1 T[18]
tRDH Read Data Hold, relative to the earlier of HPI_nRD 0 – 7 ns
rising or HPI_nCS rising
tRP Read Pulse Width 2 – – T[18]
tCYC Read Cycle Time 6 – – T[18]

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 CY7C67200

HSS BYTE Mode Transmit

qt_clk

CPU_A[2:0] CPU may start another BYTE

transmit right after TxRdy
goes high
CPUHSS_cs

CPU_wr
BT BT

TxRdy flag

HSS_TxD start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit

start of last data bit to TxRdy high:

TxRdy low to start bit delay: 0 min, 4 T max. programmable
Byte transmit 0 min, BT max when starting from IDEL. 1 or 2 stop bits.
triggered by a (T is qt_clk period)
For back to back transmit, new START Bit 1 stop bit shown.
CPU write to the begins immediately following previous STOP bit.
HSS_TxData register (BT = bit period)

qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate relationship between CPU operations
and HSS port operations.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.

HSS Block Mode Transmit

BT

HSS_TxD

t GAP

BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.
The BLOCK mode STOP bit time, tGAP = (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS
Transmit Gap register 90xC074].
The default tGAP is 2 BT.
BT = bit time = 1/baud rate.

HSS BYTE and BLOCK Mode Receive

BT +/- 5%
received byte added to
BT +/- 5% receive FIFO during the final data bit time

HSS_RxD start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit

10 BT +/- 5%

Receive data arrives asynchronously relative to the internal clock.

Incoming data bit rate may deviate from the programmed baud rate clock by as much as ±5% (with HSS_RATE value of 23 or higher).
BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag.
BLOCK mode received bytes are written directly to the memory system.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.

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 CY7C67200

Hardware CTS/RTS Handshake

tCTShold tCTShold
tCTSsetup tCTSsetup

HSS_RTS

HSS_CTS

HSS_TxD

Start of transmission delayed until HSS_CTS goes high Start of transmission not delayed by HSS_CTS

tCTSset-up: HSS_CTS setup time before HSS_RTS = 1.5T min.

tCTShold: HSS_CTS hold time after START bit = 0 ns min.
T = 1/48 MHz.
When RTS/CTS hardware handshake is enabled, transmission can be held off by deasserting HSS_CTS at least 1.5T before
HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit.
HSS_RTS is deasserted in the third data bit time.
An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit.

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 CY7C67200

Register Summary
Table 42. Register Summary
R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low
R 0x0140 HPI Breakpoint Address... 0000 0000
...Address 0000 0000
R 0x0142 Interrupt Routing VBUS to HPI ID to HPI SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Swap 1 0001 0100
Enable Enable HPI Enable CPU Enable HPI Enable CPU Enable Enable Enable
Resume2 to Resume1 to Reserved Done2 to HPI Done1 to HPI Reset1 to HPI HPI Swap 0 0000 0000
HPI Enable HPI Enable Enable Enable Enable Enable
W 1: 0x0144 SIEXmsg Data... xxxx xxxx
2: 0x0148
...Data xxxx xxxx
R/W 0x02n0 Device n Endpoint n Control Reserved xxxx xxxx
IN/OUT Sequence Stall ISO NAK Interrupt Direction Enable ARM xxxx xxxx
Ignore Enable Select Enable Enable Enable Select Enable
R/W 0x02n2 Device n Endpoint n Address Address... xxxx xxxx
...Address xxxx xxxx
R.W 0x02n4 Device n Endpoint n Count Reserved Count... xxxx xxxx
...Count xxxx xxxx
R/W 0x02n6 Device n Endpoint n Status Reserved Overflow Underflow OUT IN xxxx xxxx
Flag Flag Exception Flag Exception Flag
Stall NAK Length Set-up Sequence Timeout Error ACK xxxx xxxx
Flag Flag Exception Flag Flag Status Flag Flag Flag
R/W 0x02n8 Device n Endpoint n Count Re- Result... xxxx xxxx
sult
...Result xxxx xxxx
R 0xC000 CPU Flags Reserved... 0000 0000
...Reserved Global Inter- Negative Overflow Carry Zero 000x xxxx
rupt Enable Flag Flag Flag Flag
R/W 0xC002 Bank Address... 0000 0001
...Address Reserved 000x xxxx
R 0xC004 Hardware Revision Revision... xxxx xxxx
...Revision xxxx xxxx
R/W 0xC006 GPIO Control Write Protect UD Reserved SAS Mode 0000 0000
Enable Enable Select
HSS Reserved SPI Reserved Interrupt 0 Interrupt 0 0000 0000
Enable Enable Polarity Select Enable
R/W 0xC008 CPU Speed Reserved... 0000 0000
.Reserved CPU Speed 0000 000F
R/W 0xC00A Power Control Reserved Host/Device 2 Reserved Host/Device 1 OTG Reserved HSS SPI 0000 0000
Wake Enable Wake Enable Wake Enable Wake Enable Wake Enable
HPI Reserved GPI Reserved Boost 3V Sleep Halt 0000 0000
Wake Enable Wake Enable OK Enable Enable
R/W 0xC00C Watchdog Timer Reserved... 0000 0000
...Reserved Timeout Period Lock WDT Reset 0000 0000
Flag Select Enable Enable Strobe
R/W 0xC00E Interrupt Enable Reserved OTG SPI Reserved Host/Device 2 Host/Device 1 0000 0000
Interrupt Interrupt Interrupt Interrupt
Enable Enable Enable Enable
HSS Interrupt In Mailbox Out Mailbox Reserved UART GPIO Timer 1 Timer 0 0001 0000
Enable Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
Enable Enable Enable Enable Enable Enable
R/W 0xC098 OTG Control Reserved VBUS Receive Charge Pump VBUS Dis- D+ D– 0000 0000
Pull-up Enable Disable Enable charge Enable Pull-up Enable Pull-up Enable
D+ D– Reserved OTG Data Sta- ID VBUS Valid 0000 0XXX
Pull-down Pull-down tus Status Flag
Enable Enable
R/W 0: 0xC010 Timer n Count... 1111 1111
1: 0xC012
...Count 1111 1111
R/W 0xC014 Breakpoint Address... 0000 0000
...Address 0000 0000
R/W 1: 0xC018 Extended Page n Map Address...
2: 0xC01A
...Address
R/W 0xC01E GPIO 0 Output Data GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 0000 0000
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 0000 0000
R 0xC020 GPIO 0 Input Data GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 0000 0000
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 0000 0000
R/W 0xC022 GPIO 0 Direction GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 0000 0000
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 0000 0000

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 CY7C67200

Table 42. Register Summary (continued)

R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low
R/W 0xC024 GPIO 1 Output Data GPIO31 GPIO30 GPIO29 Reserved GPIO24 0000 0000
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved 0000 0000
R 0xC026 GPIO 1 Input Data GPIO31 GPIO30 GPIO29 Reserved GPIO24 0000 0000
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved 0000 0000
R/W 0xC028 GPIO 1 Direction GPIO31 GPIO30 GPIO29 Reserved GPIO24 0000 0000
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 Reserved 0000 0000
R/W 0xC03C USB Diagnostic Reserved Port 2A Diag- Reserved Port 1A Diag- Reserved... 0000 0000
nostic Enable nostic Enable
...Reserved Pull-down LS Pull-up FS Pull-up Reserved Force Select 0000 0000
Enable Enable Enable
R/W 0xC070 HSS Control HSS RTS CTS XOFF XOFF CTS Receive Inter- Done Interrupt 0000 0000
Enable Polarity Select Polarity Select Enable Enable rupt Enable Enable
Transmit Done Receive Done One Transmit Packet Receive Receive Pack- Receive 0000 0000
Interrupt Flag Interrupt Flag Stop Bit Ready Mode Select Overflow Flag et Ready Flag Ready Flag
R/W 0xC072 HSS Baud Rate Reserved HSS Baud... 0000 0000
...Baud 0001 0111
R/W 0xC074 HSS Transmit Gap Reserved 0000 0000
Transmit Gap Select 0000 1001
R/W 0xC076 HSS Data Reserved xxxx xxxx
Data xxxx xxxx
R/W 0xC078 HSS Receive Address Address... 0000 0000
...Address 0000 0000
R/W 0xC07A HSS Receive Counter Reserved Counter... 0000 0000
...Counter 0000 0000
R/W 0xC07C HSS Transmit Address Address.. 0000 0000
...Address 0000 0000
R/W 0xC07E HSS Transmit Counter Reserved Counter... 0000 0000
...Counter 0000 0000
R/W 0xC080 Host n Control Reserved 0000 0000
0xC0A0
Preamble Sequence Sync ISO Reserved Arm 0000 0000
Enable Select Enable Enable Enable
R/W 0xC082 Host n Address Address... 0000 0000
0xC0A2
...Address 0000 0000
R/W 0xC084 Host n Count Reserved Port Select Reserved Count... 0000 0000
0xC0A4
...Count 0000 0000
R 0xC086 Host n PID Reserved Overflow Underflow Reserved 0000 0000
0xC0A6 Flag Flag
Stall NAK Length Reserved Sequence Timeout Error ACK 0000 0000
Flag Flag Exception Flag Status Flag Flag Flag
W 0xC086 Host n EP Status Reserved 0000 0000
0xC0A4
PID Select Endpoint Select 0000 0000
R 0xC088 Host n Count Result Result... 0000 0000
0xC0A8
...Result 0000 0000
W 0xC088 Host n Device Address Reserved... 0000 0000
0xC0A8
...Reserved Address 0000 0000
R/W 0xC08A USB n Control Reserved Port A Port A Reserved LOA Mode Reserved xxxx 0000
0xC0AA D+ Status D– Status Select
Port A Reserved Port A Suspend Reserved Port A 0000 0000
Resistors Force D± Enable SOF/EOP
Enable State Enable
R/W 0xC08C Host 1 Interrupt Enable VBUS ID Reserved SOF/EOP Reserved 0000 0000
Interrupt Interrupt Interrupt
Enable Enable Enable
Reserved Port A Reserved Port A Con- Reserved Done 0000 0000
Wake Interrupt nect Change Interrupt
Enable Interrupt Enable
Enable
R/W 0xC08C Device 1 Interrupt Enable VBUS ID Reserved SOF/EOP Reserved SOF/EOP Reset 0000 0000
Interrupt Interrupt Timeout Inter- Interrupt Interrupt
Enable Enable rupt Enable Enable Enable

EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 0000 0000
Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
Enable Enable Enable Enable Enable Enable Enable Enable
R/W 0xC08E Device n Address Reserved... 0000 0000
0xC0AE
...Reserved Address 0000 0000

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 CY7C67200

Table 42. Register Summary (continued)

R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low
R/W 0xC090 Host 1 Status VBUS ID Reserved SOF/EOP Reserved xxxx xxxx
Interrupt Interrupt Interrupt
Flag Flag Flag
Reserved Port A Reserved Port A Con- Reserved Port A Reserved Done xxxx xxxx
Wake Interrupt nect SE0 Interrupt
Flag Change Status Flag
Interrupt Flag
R/W 0xC090 Device 1 Status VBUS ID Reserved SOF/EOP Reset xxxx xxxx
Interrupt Interrupt Interrupt Interrupt
Flag Flag Flag Flag
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 xxxx xxxx
Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
Flag Flag Flag Flag Flag Flag Flag Flag
R/W 0xC092 Host n SOF/EOP Count Reserved Count... 0010 1110
0xC0B2
...Count 1110 0000
R 0xC092 Device n Frame Number SOF/EOP SOF/EOP Reserved Frame... 0000 0000
0xC0B2 Timeout Timeout
Flag Interrupt Count
...Frame 0000 0000
R 0xC094 Host n SOF/EOP Counter Reserved Counter...
0xC0B4
...Counter
W 0xC094 Device n SOF/EOP Count Reserved Count...
0xC0B4
...Count
R 0xC096 Host n Frame Reserved Frame... 0000 0000
0xC0B6
...Frame 0000 0000
R/W 0xC0AC Host 2 Interrupt Enable Reserved SOF/EOP Reserved 0000 0000
Interrupt
Enable
Reserved Port A Reserved Port A Con- Reserved Done 0000 0000
Wake Interrupt nect Change Interrupt
Enable Interrupt Enable
Enable
R/W 0xC0AC Device 2 Interrupt Enable Reserved SOF/EOP Wake SOF/EOP Reset 0000 0000
Timeout Inter- Interrupt Interrupt Interrupt
rupt Enable Enable Enable Enable
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 0000 0000
Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt
Enable Enable Enable Enable Enable Enable Enable Enable
R/W 0xC0B0 Host 2 Status Reserved SOF/EOP Reserved xxxx xxxx
Interrupt Flag
Reserved Port A Reserved Port A Con- Reserved Port A Reserved Done xxxx xxxx
Wake Interrupt nect Change SE0 Interrupt
Flag Interrupt Flag Status Flag
R/W 0xC0B0 Device 2 Status Reserved SOF/EOP Wake SOF/EOP Reset xxxx xxxx
Timeout Interrupt Interrupt Interrupt
Interrupt Flag Flag Flag
Enable
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 xxxx xxxx
Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag
R/W 0xC0C6 HPI Mailbox Message... 0000 0000
...Message 0000 0000
R/W 0xC0C8 SPI Configuration 3Wire Phase SCK Scale Select Reserved 1000 0000
Enable Select Polarity Select
Master Master SS SS Delay Select 0001 1111
Active Enable Enable Enable
R/W 0xC0CA SPI Control SCK FIFO Byte FullDuplex SS Read Transmit Receive 0000 0001
Strobe Init Mode Manual Enable Ready Data Ready
Transmit Receive Transmit Bit Length Receive Bit Length 1000 0000
Empty Full
R/W 0xC0CC SPI Interrupt Enable Reserved... 0000 0000
...Reserved Receive Transmit Transfer 0000 0000
Interrupt Interrupt Interrupt
Enable Enable Enable
R 0xC0CE SPI Status Reserved... 0000 0000
FIFO Error Reserved Receive Transmit Transfer 0000 0000
Flag Interrupt Flag Interrupt Flag Interrupt Flag
W 0xC0D0 SPI Interrupt Clear Reserved... 0000 0000
...Reserved Transmit Transmit 0000 0000
Interrupt Clear Interrupt Clear
R/W 0xC0D2 SPI CRC Control CRC Mode CRC Enable CRC Clear Receive CRC One in CRC Zero in CRC Reserved... 0000 0000
...Reserved 0000 0000
R/W 0xC0D4 SPI CRC Value CRC.. 1111 1111
...CRC 1111 1111

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 CY7C67200

Table 42. Register Summary (continued)

R/W Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low
R/W 0xC0D6 SPI Data Port t Reserved xxxx xxxx
Data xxxx xxxx
R/W 0xC0D8 SPI Transmit Address Address... 0000 0000
...Address 0000 0000
R/W 0xC0DA SPI Transmit Count Reserved Count... 0000 0000
...Count 0000 0000
R/W 0xC0DC SPI Receive Address Address... 0000 0000
...Address 0000 0000
R/W 0xC0DE SPI Receive Count Reserved Count... 0000 0000
...Count 0000 0000
R/W 0xC0E0 UART Control Reserved... 0000 0000
...Reserved Scale Baud UART 0000 0111
Select Select Enable
R 0xC0E2 UART Status Reserved... 0000 0000
...Reserved Receive Transmit 0000 0000
Full Full
R/W 0xC0E4 UART Data Reserved 0000 0000
Data 0000 0000
R HPI Status Port VBUS ID Reserved SOF/EOP2 Reserved SOF/EOP1 Reset2 Mailbox In
Flag Flag Flag Flag Flag Flag
Resume2 Resume1 SIE2msg SIE1msg Done2 Done1 Reset1 Mailbox Out
Flag Flag Flag Flag Flag Flag

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 CY7C67200

Ordering Information
Table 43. Ordering Information
Ordering Code Package Type Pb-Free Temperature Range
CY7C67200-48BAXI 48-pin FBGA X –40 to 85 °C
CY7C67200-48BAXIT 48-pin FBGA, Tape and reel X –40 to 85 °C
CY3663 Development Kit

Ordering Code Definitions

CY 7 C 67 XXX - XX XXXX I T

Tape and Reel

Thermal Rating: I = Industrial

Package Type:
BAX: Ball Grid Array Pb-free

48-pin Count

Part number

Family Code: USB

Technology Code: CMOS

Marketing Code: Cypress products

Company Code: CY = Cypress

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 CY7C67200

Package Diagram
Figure 78. 48-ball FBGA (7.00 mm × 7.00 mm × 1.2 mm) BA48 Package Outline

51-85096 *J

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 CY7C67200

Acronyms Document Conventions

Table 44. Acronyms Used in this Document Units of Measure
Acronym Description Table 45. Units of Measure
AC alternating current Symbol Unit of Measure
AEC Automotive Electronics Council °C degree Celsius
CPU central processing unit MHz megahertz
CRC cyclic redundancy check µA microampere
DC direct current µF microfarad
DMA direct memory access µs microsecond
EEPROM electronically erasable programmable read only µW microwatt
memory
mA milliampere
EOP end of packet
ms millisecond
XRAM external ram memory
mV millivolt
FIFO first in first out
mW milliwatt
GPIO general purpose input/output
ns nanosecond
HSS high speed serial
ppm parts per million
HPI host port interface
pF picofarad
IDE integrated device electronics
V volt
I2C inter-integrated circuit
W watt
KVM keyboard-video-mouse
OTG on-the-go protocol
PLL phase locked loop
POR power-on reset
PIO programmed input/output
PWM pulse width modulation
RAM random access memory
ROM read only memory
SPI serial peripheral interface
SIE serial-interface-engine
SE0 single ended zero
SOF start of frame
SRAM static random access memory
TQFP thin quad flat pack
TTL transistor-transistor logic
UART universal asynchronous receiver/transmitter
USB universal serial bus
WDT watchdog timer

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 CY7C67200

Errata
This section describes the errata for the CY7C67200. Details include errata trigger conditions, scope of impact, available workaround,
and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number Device Characteristics

CY7C67200 All Packages

CY7C67200 Qualification Status

In Production

CY7C67200 Errata Summary

The following table defines the errata applicability to available CY7C67200 family devices. An “X” indicates that the errata pertains to
the selected device.
Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description.

Silicon
Items CY7C67200 Fix Status
Revision
<xref>1. HPI Write to SIE Registers X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>2. IDE Register Read When GPIO24 Pin is Low X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>3. UART Does Not Recognize Framing Errors X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>4. UART Does Not Override GPIO Control Regis- X A No fix is currently planned for future silicon
ter versions. Use workaround.
<xref>5. VBUS Interrupt (VBUS Valid) Requires De- X A No fix is currently planned for future silicon
bouncing versions. Use workaround.
<xref>6. Coupled SIE Interrupt Enable Bits X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>7. Un-Initialized SIExmsg Registers X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>8. BIOS USB Peripheral Mode: Descriptor Length X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>9. Peripheral Short Packet Issue X A Will be fixed in future silicon revision. Use
workaround.
<xref>10. Data Toggle Corruption Issue X A Will be fixed in future silicon revision. Use
workaround.

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 CY7C67200

1. HPI Write to SIE Registers

■ Problem Definition
Writing to the SIE2 Control register via HPI can corrupt the SIE1 control register.
Writing to the SIE1 Control register via HPI can corrupt the SIE2 control register.
■ Parameters Affected
SIE control registers
■ Trigger Condition(S)
When an external processor accesses the SIE1 or SIE2 register at the same time the internal CY16 CPU is also accessing the
opposite SIE, the SIE accessed by the CY16 CPU will be corrupted.
For example, the external processor writes a value of 0x80 to the SIE2 register 0xC0B0 while the internal CY16 is doing a read/write
to the SIE1 register 0xC08C, the SIE1 register 0xC08C, will be corrupted with the value 0x80.
■ Scope of Impact
If the internal CPU and external CPU access the SIEs at the same time, contention will occur resulting in incorrect data in one of
the SIE registers.
■ Workaround
1. Use the LCP COMM_WRITE_CTRL_REG to handle the writing to SIE registers.
2. Use download code to handle SIE WRITE commands.
3. Avoid accessing SIE register from the external CPU. For example: Route all the SIE interrupts to the software mailbox
interrupt registers 0x144 and 0x148. This requires user to create download code.
■ Fix Status
Use workaround. No fix is currently planned for future silicon revisions. An implementation example is included in the Cypress
Windows CE driver.

2. IDE Register Read When GPIO24 Pin is Low

■ Problem Definition
Part does not service USB ISRs when GPIO24 pin (also labeled as HPI_INT and IORDY) is low and any IDE register is read.
■ Parameters Affected
USB ISRs do not get serviced.
■ Trigger Conditions
The IDE registers (0xC050 through 0xC06E) should not be read unless IDE is being used. Debuggers that read all memory
locations while single stepping can cause this situation to manifest itself.
■ Scope of Impact
If debugging and using this pin, your application will appear to hang.
■ Workaround
When running in stand-alone mode, avoid using the GPIO24 pin if possible.
■ Fix Status
Other workarounds being investigated. No fix is currently planned for future silicon revisions.

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 CY7C67200

3. UART Does Not Recognize Framing Errors

■ Problem Definition
The UART is not designed to recognize framing errors.
■ Parameters Affected
UART serial communications.
■ Trigger Conditions
Some platforms can cause EZ-OTG to see a string of NULL characters and cause the UART to get out of sync.
■ Scope of Impact
This can cause the UART to lose connection with the host during serial communications. One example of this is if the UART is
used as the debug port to the PC. This problem has occurred on, but is not limited to, Dell machines running WinXP or Win2k.
■ Workaround
For general use, there is no workaround. If this problem is experienced while debugging, try running the debugger on a different
Host (PC/OS). Otherwise the USB port can be used for the debugging interface.
■ Fix Status
No fix is currently planned for future silicon versions.

4. UART Does Not Override GPIO Control Register

■ Problem Definition
When the UART is enabled, the GPIO Control Register still has control over GPIO 6 (UART RX pin). When enabled, the UART
should override the GPIO Control Register, which defaults to setting the pin as an input.
■ Parameters Affected
UART serial communications.
■ Trigger Conditions
Enabling UART
■ Scope of Impact
GPIO 6 UART RX pin is controlled by GPIO Control Register and defaults to an input. The UART mode does not override the GPIO
control register for this pin and can be inadvertently configured as an output.
■ Workaround
Ensure the GPIO Control Register is written appropriately to set GPIO6 as an input when the UART is enabled.
■ Fix Status
No fix is currently planned for future silicon versions.

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 CY7C67200

5. VBUS Interrupt (VBUS Valid) Requires Debouncing

■ Problem Definition
The VBUS interrupt in the Host/Device Status Registers [0xC090 and 0xC0B0] and OTG Control Register [0xC098] triggers multiple
times whenever VBUS is turned on. It should only trigger once when VBUS rises above 4.4 V and once when VBUS falls from
above 4.4 V to 0 V.
■ Parameters Affected
Electrical.
■ Trigger Conditions
VBUS turned on.
■ Scope of Impact
Host/Device Registers and OTG Control Register trigger multiple times.
■ Workaround
When reading the status of this interrupt, a software debounce should be implemented.
■ Fix Status
No fix is currently planned for future silicon versions.

6. Coupled SIE Interrupt Enable Bits

■ Problem Definition
Host/Device 1 SIE events will still trigger an interrupt when only the Host/Device 2 SIE Interrupt Enable is set and vise versa.
■ Parameters Affected
Host/Device SIE Interrupts.
■ Trigger Conditions
Setting only 1 Host/Device SIE Interrupt Enable.
■ Scope of Impact
The Host/Device global Interrupt Enable bits can not be used to disable each Host/Device SIE independently. These bits are found
in the Interrupt Enable Register (0xC00E).
■ Workaround
If an SIE Interrupt is desired, both Host/Device 1 and Host/Device 2 Interrupt Enable bits should be set in the global Interrupt Enable
Register (0xC00E). To properly mask an SIE Interrupt to a single SIE, the lower level Host/Device Interrupt Enable Registers
(0xC08C and 0xC0AC) must be used. For example, setting the Host/Device 2 IE Register to 0x0000 will prevent any Host/Device
2 events from generating a Host/Device Interrupt. To disable all SIE interrupts, both Host/Device Interrupt Enable bits in the Interrupt
Enable Register should be cleared.
■ Fix Status
No fix is currently planned for future silicon versions. Examples provided in the Development Kit Software.

Document Number: 38-08014 Rev. *K Page 87 of 93

 CY7C67200

7. Un-Initialized SIExmsg Registers

■ Problem Definition
The SIE1msg and SIE2msg Registers [0x0144 and 0x0148] are not initialized at power up.
■ Parameters Affected
HPI interrupts.
■ Trigger Conditions
Power-up initialization.
■ Scope of Impact
If using the HPI interface in coprocessor mode, random data will be written to the SIE1msg and SIE2msg Registers [0x0144 and
0x0148] at power up. This will cause two improper HPI interrupts (HPI_INTR) to occur, one for each of the two SIExmsg Registers.
■ Workaround
The external processor should clear the SIExmsg Registers [0x0144 and 0x0148] shortly after nRESET is de-asserted and prior
to the expected processing of proper HPI interrupts (generally 10ms after nRESET is de-asserted.)
■ Fix Status
No fix is currently planned for future silicon versions.

8. BIOS USB Peripheral Mode: Descriptor Length

■ Problem Definition
The BIOS will not properly return a descriptor or set of descriptors if the length is a multiple of the control endpoint’s maximum
packet size.
■ Parameters Affected
Control Endpoint maximum packet size.
■ Trigger Conditions
Get Descriptor requests.
■ Scope of Impact
If the descriptor length is a multiple of the maximum packet size, the BIOS will respond with a STALL instead of a zero-length data
packet for the final IN request.
■ Workaround
If the requested descriptor length is a multiple of the maximum packet size, then either the maximum packet size or the descriptor
length needs to change. A descriptor length can be increased by simply adding a padded byte to the end of a descriptor and
increasing the descriptor Length byte by one. Section 9.5 (Descriptor) of the USB2.0 specification allows a descriptor length to be
larger than the value defined in the specification.
■ Fix Status
No fix is currently planned for future silicon versions.

Document Number: 38-08014 Rev. *K Page 88 of 93

 CY7C67200

9. Peripheral Short Packet Issue

■ Problem Definition
When a SIE is configured as a peripheral, the SUSBx_RECEIVE function does not invoke the callback function when it receives
a short packet.
■ Parameters Affected
SIEx Endpoint x Interrupt (Interrupt 32-47).
■ Trigger Conditions
This issue is seen when a SIE is configured as a peripheral during an OUT data transfer when the host sends a zero length or
short packet. If this occurs the BIOS will behave as if a full packet was received and will continue to accept data until the Device n
Endpoint n Count Register value is satisfied.
■ Scope of Impact
All peripheral functions are susceptible to this as it is a normal occurrence with USB traffic.
■ Workaround
To fix this problem the SIEx Endpoint x Interrupt must be replaced for any peripheral endpoint that is configured as an OUT endpoint.
1. Acquire the file called susb1.s from Cypress Support or by downloading a newer version of the frameworks that has had
this fix applied and includes susb1.s.
2. Modify fwxcfg.h in your project to have the following flags and define/undef the fix for the endpoints you are using:
#define FIX_USB1_EP1
#define FIX_USB1_EP2
#undef FIX_USB1_EP3
#undef FIX_USB1_EP4
#undef FIX_USB1_EP5
#undef FIX_USB1_EP6
#undef FIX_USB1_EP7

#undef FIX_USB2_EP1
#undef FIX_USB2_EP2
#undef FIX_USB2_EP3
#undef FIX_USB2_EP4
#undef FIX_USB2_EP5
#undef FIX_USB2_EP6
#undef FIX_USB2_EP7

3. Add the new susb1.s to the included assembly source files in the make file.
For example: ASM_SRC := startup.s isrs.s susb1.s

4. Add usb_init somewhere in the startup code. This will likely be in fwxmain.c as demonstrated below:

void fwx_program_init(void)
{
void usb_init(); /* define the prototype */
usb_init();
fwx_init(); /* Initialize everything in the base framework. */
}

5. Build the project using the modified make file.

■ Fix Status
The ROM version of the BIOS will be updated during any future silicon rolls. No current roll of the part currently exists.
10.Data Toggle Corruption Issue

Document Number: 38-08014 Rev. *K Page 89 of 93

 CY7C67200

■ Problem Definition
When a SIE is configured as a peripheral, data toggle corruption as specified in the USB 2.0 spec, section 8.6.4, does not work as
specified.
■ Parameters Affected
SIEx Endpoint x Interrupt (Interrupt 32-47).
■ Trigger Conditions
This issue is seen when a SIE is configured as a peripheral and the host sends an incorrect data toggle. According to the USB
specification, when an incorrect data toggle is seen from the host the peripheral should throw away the data but increment the data
toggle bit to re-synchronize the data toggle bits. In the current ROM BIOS the SIEx Endpoint x Interrupt will ignore the data toggle
error and accept the data.
■ Scope of Impact
All peripheral functions are susceptible to this as it is a normal occurrence with USB traffic.
■ Workaround
To fix this problem the SIEx Endpoint x Interrupt must be replaced for any endpoint that is configured as an OUT endpoint.
1. Acquire the file called susb1.s from Cypress Support or by downloading a newer version of the frameworks that has this
included.
2. Modify fwxcfg.h in your project to have the following flags and define/undef the fix for the endpoints you are using:
#define FIX_USB1_EP1
#define FIX_USB1_EP2
#undef FIX_USB1_EP3
#undef FIX_USB1_EP4
#undef FIX_USB1_EP5
#undef FIX_USB1_EP6
#undef FIX_USB1_EP7

#undef FIX_USB2_EP1
#undef FIX_USB2_EP2
#undef FIX_USB2_EP3
#undef FIX_USB2_EP4
#undef FIX_USB2_EP5
#undef FIX_USB2_EP6
#undef FIX_USB2_EP7

3. Add the new susb1.s to the included assembly source files in the make file.
For example: ASM_SRC := startup.s isrs.s susb1.s
4. Add usb_init somewhere in the startup code. This will likely be in fwxmain.c as demonstrated below:

void fwx_program_init(void)
{
void usb_init(); /* define the prototype */

usb_init();

fwx_init(); /* Initialize everything in the base framework. */

}

5. Build the project using the modified make file.

■ Fix Status
The ROM version of the BIOS will be updated during any future silicon rolls. No current roll of the part currently exists.

Document Number: 38-08014 Rev. *K Page 90 of 93

 CY7C67200

Document History Page

Document Title: CY7C67200, EZ-OTG™ Programmable USB On-The-Go Host/Peripheral Controller
Document Number: 38-08014
Orig. of Submission
Revision ECN Description of Change
Change Date
** 111872 MUL 03/22/02 New data sheet.
*A 116988 MUL 08/23/02 Preliminary data sheet
*B 124954 MUL 04/10/03 Added Memory Map Section and Ordering Information Section
Moved Functional Register Map Tables into Register section
General Clean-up
Changed from “Preliminary” to “Preliminary Confidential“
*C 126211 MUL 05/23/03 Added Interface Description Section and Power Savings and Reset Section
Added Char Data
General Clean-up
Removed DRAM, MDMA, and EPP
Added “Programmable” to the title page
*D 127334 KKV 05/29/03 Corrected font to enable correct symbol display
*E 129394 MUL 10/07/03 Final Data Sheet
Changed Memory Map Section
Added USB OTG Logo
General Clean-up
*F 472875 ARI See ECN Removed “power consumption” bullet from the Features bullet list.
Corrected number GPIO[31:20] to read GPIO[31:30] in Section “Standalone
Mode”.
Made sentence into a Note in Section “Reset Pin” and repeated the note in
Section “Host Port Interface (HPI)”.
Corrected the Host/Device 1 Interrupt Enable (Bit 8) Information in Section
“Interrupt Enable Register [0xC00E] [R/W]”.
Corrected data on Write Protect Enable (Bit 15) Section “GPIO Control Register
[0xC006] [R/W]” to read “the GPIO Mode Select [15:8] bits are read only until
a chip reset“.
Re-wrote the Register Description in Section “SIEXmsg Register [W] [10]”.
Put document on 2-column template and corrected grammar. Put the figure
captions at the top of the figures per new template specifications.
Added Static Discharge Voltage information in Section “Absolute Maximum
Ratings”
Added compliance statement and TID in Section “USB Transceiver”.
*G 567317 KKVTMP See ECN Added the lead free information on the Ordering Information Section. Imple-
mented the new template with no numbers on the headings.
*H 3378752 NMMA 09/21/11 Updated template and styles according to current Cypress standards.
Updated pin description in Ordering Information table.
Added Acronyms and Units of Measure.
Added Ordering Code Definitions.
*I 3997630 PRJI 05/11/2013 Added Errata.

Document Number: 38-08014 Rev. *K Page 91 of 93

 CY7C67200

Document History Page (continued)

Document Title: CY7C67200, EZ-OTG™ Programmable USB On-The-Go Host/Peripheral Controller
Document Number: 38-08014
Orig. of Submission
Revision ECN Description of Change
Change Date
*J 4082823 PRJI 07/31/2013 Added Errata footnotes (Note 1, 2, 7, 8, 9, 10, 11).
Updated Interface Descriptions:
Updated UART Interface:
Added Note 1 and referred the same note in the heading.
Updated I2C EEPROM Interface:
Added Note 2 and referred the same note in the heading.
Updated Registers:
Updated Processor Control Registers:
Updated Interrupt Enable Register [0xC00E] [R/W]:
Added Note 7 and referred the same note in the heading.
Updated General USB Registers:
Added Note 8 and referred the same note in the heading.
Updated OTG Control Registers:
Added Note 9 and referred the same note in the heading.
Updated HPI Registers:
Updated SIEXmsg Register [W] [10]:
Added Note 10 and referred the same note in the heading.
Updated Pin Descriptions:
Added Note 11 and referred the same note in “GPIO24/INT/IRQ0” pin.
Updated to new template.
Completing Sunset Review.
*K 5514428 RAJV 11/08/2016 Updated Package Diagram:
spec 51-85096 – Changed revision from *I to *J.
Updated to new template.
Completing Sunset Review.

Document Number: 38-08014 Rev. *K Page 92 of 93

 CY7C67200

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Document Number: 38-08014 Rev. *K Revised November 8, 2016 Page 93 of 93