Computer Organization and Architecture Test 3

Number of Questions: 35 Section Marks: 30

Directions for questions 1 to 35: Select the correct alterna- 6. Consider the following instruction:
tive from the given choices. ADD R1, (R2, R3)
1. A computer ‘A’ uses the following 32-bit floating point Here R1, R2, R3 are registers
representation of real numbers. The Sum of data present in the R2 and R3 is stored in a
32-bit register R1.
S Mantissa Exponent Which of the following mode best reflects the mode of
31 30 87 0 second operand?
(A) Indexed mode
Computer ‘B’ uses the following floating point repre- (B) Base Register mode
sentation scheme. (C) Base with index mode
(D) Base with index and offset mode
S Mantissa Exponent
31 30 76 0
7. Consider an instruction format with fields containing
zeros:
Which of the following statement is TRUE with regard
0000 0000 0000 0000 0000 0000 0000 0000
to computer B’s method of representing floating-point
Opcode Destination Source Immediate value
numbers over computer A’s method?
Register Register
(A) Both range and precision are decreased.
(B) The range is decreased but the precision is in- What is the maximum possible number of operations,
creased. registers with the given instruction format?
(C) The range is increased but the precision is de- (A) 4, 8 (B) 4, 16
creased. (C) 16, 256 (D) 16, 65536
(D) Both range and precision remain same. 8. A 64 M-bit DRAM organized as 4 M addresses of 16-bit
2. The minimum number of control bits required to exe- words each. A memory system is built using 128 M
cute a microprogram which has 50 control signals is addresses of 256-bit words each. How many DRAM
_______. chips that are required for this memory system?
(A) 5 (B) 6 (A) 16 (B) 32
(C) 50 (D) 100 (C) 128 (D) 512
3. Consider the following instructions: 9. Consider a hypothetical 64-bit micro-processor having
BEQ R0, R1, L1 64-bit instructions composed of two fields: Opcode:
The opcode is BEQ, which means Branch if Equal. 2-bytes. Immediate operand or an operand address:
The instruction checks the equality of R0, R1 and if remaining bytes.
both are equal jump to L1. Which of the following cor- What is the maximum directly addressable memory ca-
rectly specifies given instruction but with much greater pacity (in bytes)?
branching distance? (A) 216 (B) 248
64
(A) compare R0, R1 if zero jump to L1 (C) 2 (D) 224
(B) LOAD R0 Branch if equal R1, L1 10. Consider a machine with a byte addressable main mem-
(C) Branch if not equal R0, R1, L2 Jump L1 L2: ory of 4 GB and a block size of 16 bytes. Assume that a
(D) Branch if not Equal R0, R1, L1 Jump L2 L1: direct mapped cache consisting of 32 lines is used with
this machine. How many bytes of main memory can be
4. Consider a loop branch that branches 100 times in a stored in the cache?
row, then it is not taken once. Assume that the predic- (A) 4096 (B) 220
tion bit for this branch remains in the prediction buffer. (C) 512 (D) 736
The prediction accuracy for this branch by using 1-bit
11. Consider a dynamic RAM that must be given a refresh
branch history table prediction scheme (in percentage)
cycle 64 times per ms. Each refresh operation requires
is _______.
150 ns; a memory cycle requires 250 ns. What percent-
(A) 90 (B) 95
age of the memory’s total operating time is given to
(C) 98 (D) 99 refreshes?
5. The biased exponent value for double precision floating (A) 1% (B) 3%
point numbers is ________. (C) 5% (D) 10%
(A) 1023 (B) 1024 12. A DMA module is transferring characters to memory
(C) 256 (D) 255 using cycle stealing, from a device transmitting at
 Computer Organization and Architecture Test 3 | 3.27

9600 bps. The processor is fetching instructions at the whenever needed, LRU replacement policy can be
rate of 1 million instructions per second (1 MIPS). By used. What is the percentage of cache utilization for
how much the processor is slowed down due to the Direct mapped, Associative and 2-way set-Associative
DMA activity? respectively, if the processor accesses the following
(A) 0.0012% (B) 0.01% elements?
(C) 0.001% (D) 0.12% M0, 0, M0, 1, M0, 2, M0, 3, M0, 4, M0, 5, M0, 6, M0, 7, M1, 0,
13. Match list-A with list-B and select the correct answer M1, 1, M1, 2, M1, 3, M1, 4, M1, 5, M1, 6, M1, 7.
using the code given below the list: (A) 50%, 100%, 50% (B) 50%, 50%, 50%
(C) 100%, 100%, 100% (D) 100%, 100%, 50%
List–A List–B
18. Consider the given program structure, which is in Main
a. Cache 1. Printer
memory:
b. DMA I/O 2. Disk
c. Interrupt I/O 3. High speed RAM START 20

(A) a–1, b–2, c–3 (B) a–2, b–3, c–1

26
(C) a–3, b–2, c–1 (D) a–3, b–1, c–2
14. The speed gained by a ‘p’ segment pipeline executing
168 Inner loop
‘q’ tasks is: executes
( q + p − 1) p+q 30 times Outer
(A) (B) loop
pq pq − 1 242 executes
10 times
pq p+q
(C) (D)
p + q −1 pq + 1 1203

15. The IEEE 32-bit floating point format of –6 is:

1503 END
(A) 1 10000001 10000000000000000000000
(B) 1 00000010 00000000000000000000000
(C) 1 00000001 10000000000000000000000 The memory addresses are in decimal. The program
(D) 1 10000001 00000000000000000000000 consists of two loops along with start and end state-
ments. All the instructions in the program are executed
16. Consider below code segment:
in sequential manner. The program is to be run on a
LOAD R1, M[1000]
computer that has an instruction cache of size 1 K words
LOAD R2, M[1002]
organized in a direct-mapped manner. The main mem-
ADD R3, R1, R2
ory size is 64 K words with block size of 128 words.
STORE R3, M[1008]
Let the cycle time of main memory is 10 ns and cycle
LOAD R4, M[1004]
time of the cache is 1 ns.
ADD R5, R1, R4
Then the total time needed for reading instructions
STORE R5, M[1010]
from main memory to the cache during the execution
Assume that this program is executed on a pipe-
of the program (in nano seconds) is _______.
lined processor with 5 stages: FI (Fetch Instruction),
(A) 1280 (B) 4864
RD(Read registers while Decoding), EX (Execute the
(C) 48640 (D) 61440
operation or calculate the address), MEM (Access an
operand in data memory), WR (write result into a reg- 19. A pipelined processor has two branch delay slots, An
ister). optimizing compiler can fill one of these slots 75% of
The first operand of each instruction will be the desti- the time and can fill the second slot only 20% of the
nation. What is the minimum number of stalls that will time. What is the ratio of improvement in performance
be there in the reordered code of given code if the pro- achieved by this optimization to without optimization,
cessor uses forwarding also? assuming that 10% of the instructions executed are
(A) 0 (B) 1 branch instructions?
(C) 2 (D) 3 (A) 1.102 (B) 1.086
(C) 0.9 (D) 1.105
17. Consider a 2 × 8 two-dimensional array of elements,
M. Assume that each element in the array occupies 20. Consider a system with a 4 KB, 4-way set associa-
one word and the array elements are stored in column- tive cache memory with 128 lines, a 1024 word array
major order in the main memory from location 2000 where each element is a 32-bit word. When a program
to location 2015. The cache consists of 8 blocks and accesses this array with a scale of D, it means start-
each block will have just two words. Assume also that ing with the first element, the program accesses every
3.28 | Computer Organization and Architecture Test 3

Dth element. For example, for D = 1, the program EX: Execution or address calculation
accesses every element, for D = 2, the program accesses MEM: Data memory access
every second element and so on. Assuming a cache that WB: Write back
is initially empty and a program makes one pass over The following code executed on this pipeline:
this array with a scale of D, what is the miss rate gener-
ated for D = 8? Instruction Operation

1 1 ADD R1, R2, R3 R1 ← R2 + R3

(A) (B)
2 4 SUB R4, R1, R5 R4 ←R1 - R5
1 1 LOAD R6, 200(R1) R6 ← M[200 + R1]
(C) (D)
8 16 ADD R7, R1, R6 R7 ← R1 + R6

21. A computer has 32-bit instructions and 12-bit addresses. Use forwarding to resolve data hazards. Then the num-
If there are 240 two-address instructions, how many ber of stalls that will occur because of data hazards in
one-address operations can be formulated? given code is _____.
(A) 4096 (B) 65536 (A) 0 (B) 1
(C) 8192 (D) 131072 (C) 2 (D) 3
22. Consider a pipelined processor with a 5-stage pipeline. 26. Consider a floating point representation: c.re where c
Assume that all instructions take 5 cycles. The dynamic represents coefficient register of size 10 in which MSB
instruction count by type, as a percentage of the total, is bit is used to represent sign, r represents radix and e
as follows: represents contents of exponent register of size 5, in
10% store instructions which MSB is used to represent sign. Then the contents
20% load instructions of coefficient and exponent registers for the number
30% branch instructions +1001.110 will be:
40% ALU instructions (A) 0100111000, 00100 (B) 0001001110, 00100
What is the ideal speed-up due to pipelining for this (C) 1001110000, 10100 (D) 1001110000, 10101
processor? 27. Consider a 32-bit microprocessor, with a 16-bit exter-
(A) 2.5 (B) 5 nal data bus, driven by an 8 MHz input clock. Assume
(C) 10 (D) 50 that this microprocessor has a bus cycle whose mini-
23. For the data given in Q. No. 22, let stalls due to data mum duration equals four input clock cycles. What is
hazards occur only under two reasons. the minimum data transfer rate across the bus that this
A stall of two cycles occur when a load instruction is microprocessor can sustain, in bytes?
followed by an ALU instruction that uses the result of (A) 2 MB/sec (B) 4 MB/sec
load. This scenario exists for 40% of the load instruc- (C) 6 MB/sec (D) 8 MB/sec
tions. 28. Consider a bus structure in which a single internal bus
A stall of three cycles occur when a branch instruction connects the ALU and all processor registers.
is preceded by an ALU operation whose result is used Which of the following represents the correct sequence
as a branch condition. This scenario exists for 50% of of micro-operations to add a number to the accumula-
the branch instructions. What is the decrease in the tor when the number is an indirect address operand?
ideal speed up of pipelining only due to data hazards? (A) t1: MAR ← (IR(address))
(A) 50% (B) 75.6% t2: MBR ← memory
(C) 18.9% (D) 37.8% t3: Y ← (MBR)
24. Given t4: Z ← (AC) + (Y)
x = (0100 0110 1101 1000 0000 0000 0000 0000)2 and t5: AC ← (Z)
y = (1011 1110 1110 0000 0000 0000 0000 0000)2, (B) t1: MAR ← (IR(address))
representing single precision IEEE 754 floating point t2: MBR ← memory
numbers. Then the respective values of x + y and x * y t3: Z ← (AC) + (MBR)
in decimal (approximately) are: t4: AC ← (Z)
(A) 27647.5625 and –12096 (C) t1: MBR ← (IR(address))
(B) 27647.5625 and –24192 t2: Z ← (AC) + (MBR)
(C) 13823.75 and 24192 t3: AC ← (Z)
(D) 13823.75 and –24192 (D) t1: MAR ← (IR(address))
25. A 5-stage pipeline has the following stages: t2: MBR ← memory
IF: Instruction fetch t3: MAR ← (MBR)
ID: Instruction decode and register file read t4: MBR ← memory
 Computer Organization and Architecture Test 3 | 3.29

t5: Y ← (MBR) 32. Consider a computer with the following characteristics:

t6: AC ← (AC) + (Y) Total main memory: 1 MB; word size is 1 byte; Block
t7: AC ← (Z) size of 16 bytes; and cache size of 64 kbytes; for the
29. For the data given in Q. No. 28, what is the number main memory address F0010, what will be the cache
of clock cycles required for above operation if each line bits for a direct mapped cache?
micro-operation takes one clock cycle? (A) 1111 (B) 0000
(C) 0000 0000 0001 (D) 000000001000
(A) 5 (B) 4
(C) 3 (D) 7 33. Consider a system in which a data transfer over a bus
takes 500 ns. Transfer of bus control in either direction,
30. The access time of a cache memory is 100 ns and that
from processor to I/O device or vice versa, takes 250 ns.
of main memory is 1 ms. 80% of the memory requests
One of the I/O devices has a data transfer rate of 50 kb/s
are for read and others are for write. Hit ratio for read
and employs DMA. Data is transferred one byte at a
only accesses is 0.9. A write-through procedure is used.
time. Suppose we employ DMA in a cycle-stealing
The average access time of the system for both read and
mode. When transferring a block of 128 bytes, it would
write requests is:
tie up the bus for (in micro seconds) _______.
(A) 160 ns (B) 200 ns (A) 250 (B) 0.2
(C) 360 ns (D) 720 ns (C) 128 (D) 0.4
31. Consider a new instruction named branch-on-bit-set. 34. A PC relative mode branch instruction is 2 bytes long.
The instruction The address of the instruction, in decimal, is 356029.
“bbs reg, pos, label” Determine the branch target address if the signed dis-
jumps to label if bit in position ‘pos’ of register oper- placement in the instruction is –31.
and ‘reg’ is one. A register is 32 bits wide and the bits (A) 356029 (B) 356030
are numbered 0 to 31, bit in position 0 being the least (C) 356031 (D) 356000
significant. Consider the following emulation of this 35. Consider a system employing interrupt driven I/O for
instruction on a processor that does not have branch- a particular device that transfers data on an average of
on-bit-set implemented. 10 KB/sec on a continuous basis. Assume that inter-
result ← reg & mark rupt processing takes 100 ms (i.e., the time to jump to
Branch to label if result is non-zero. the ISR, execute it and return to the main program).
The variable ‘result’ is temporary register. For correct Determine what fraction of processor time is consumed
emulation the variable mask must be generated by: by this I/O device if it interrupts for every byte.
(A) mask ← 0xf (B) mask ← pos (A) 1 (B) 10
(C) mask ← 0xffff >> pos (D) mask ← 0x1<< pos (C) 100 (D) 0.8

Answer Keys
1. B 2. B 3. C 4. C 5. A 6. C 7. C 8. D 9. B 10. C
11. A 12. D 13. C 14. C 15. A 16. A 17. C 18. D 19. B 20. B
21. B 22. B 23. D 24. A 25. B 26. A 27. B 28. D 29. D 30. C
31. D 32. C 33. D 34. D 35. A

Hints and Explanations

1. The range of a floating point number depends on expo- BNE R0, R1, L2
nent size. As exponent size in ‘B’ decreases, the range Jump L1, L2:
also decreases. We get much greater branching distance by using 1-ad-
The precision specifies number of digits after decimal dress instruction: Jump L1.
point, which increases in ‘B’ computer. Choice (B) We can’t use zero-address as we need to specify the
2. Using Vertical Microprogramming, there will be 6-con- opcode ‘jump’
trol bits to provide 50 control signals. By using the instruction ‘Jump L1’ the address space
( 26 = 64 > 50) Choice (B) is more so we can specify much greater branching
distance. Choice (C)
3. Given instruction BEQ R0, R1, L1.
This instruction can be replaced by following instruc- 4. Branch history table is a small memory, which contains a
tions, to achieve greater branching distance: bit that says whether the branch was recently taken or not.
3.30 | Computer Organization and Architecture Test 3

In the given problem, the loop executes 100 times but 12. The DMA is transmitting at a rate of 9600 bits per
in the 101th time the loop is not taken. 9600
But it will be incorrectly predicted by 1-bit branch his- second i.e., it is transmitting = 1200 characters
8
tory table prediction as the loop is taken for 100 times. per second. The processor is processing at a rate of
In the 1st iteration also the predictor specifies incorrect 1 million instructions per second i.e., It will take
branch prediction as the bit is set to ‘not taken’ in the 1
exit stage of last execution of the program. = 1m second to process a single instruction.
106
∴ 2 wrong predictions, out of 101 predictions.
A single character will be processed by DMA in
∴ Prediction Accuracy percentage
1
=
99
× 100 = 98% Choice (C) ≈ 833 ms
101 1200
∴ Slow down of processor due to DMA
5. In Double precision floating point format,
1
Number of bits for exponent = 11 = × 100 = 0.12% Choice (D)
833
∴ Biased exponent = 2k–1 – 1,
Where k is the number of bits used for exponent. 13. Cache is high speed RAM, DMA I/O is used with disk,
Here k = 11, hence Biased exponent Interrupt I/O is used with printer. Choice (C)
= 210 – 1 = 1023. Choice (A) 14. Without pipelining, execution time = pq
with pipelining, execution time = p + q – 1
6. If we assume R2 as Base register, R3 as Index register,
pq
then the mode will be Base with index mode. ∴ speed up = Choice (C)
Choice (C) p + q −1

7. Number of bits in opcode = 4 15. IEEE 32-bit floating point representation will be in the
⇒ Number of operations possible = 24 = 16 form of:
Number of bits in src/dest. Registers = 8 8 bits 23-bits
∴ Number of registers = 28 = 256 Choice (C) Biased
fraction
exponent
8. Each DRAM has 4M addresses of 16-bit words.
⇒ DRAM capacity = 4M × 16 Sign bit
Memory system capacity = 128M × 256 6 = 110
128 M × 256 For –6 sign bit is 1.
∴ Number of chips required = = 512
4 M × 16 6 = 110 = 1.10 × 2010
Choice (D) Exponent = 010
9. Instruction size = 64-bits Biased exponent = 127 + 2 = 129 = 10000001
Opcode size = 2B = 16-bits Fraction = 10000000000000000000000
Hence IEEE 32-bit floating point representation of
Operand/Address field = 64 – 16 = 48-bits.
–6 is:
The 48-bits can be used to specify a particular address.
110000001
∴ Maximum directly addressable memory = 248
10000000000000000000000 Choice (A)
Choice (B)
16. In given code stalls occur before the ADD instructions.
10. Number of lines in cache = 32 2 stalls are there in given code. To minimize stalls, we
There are 32 lines in cache. Each line will have 16 bytes. reorder the code. In the reordered code place LOAD R4,
∴ Total bytes of memory in cache M[1004] before ADD R3, R1, R2.
= 16 × 32 = 512 bytes Choice (C) The resultant code will be:
11. The DRAM has given a refresh cycle 64 times per ms. LOAD R1, M[1000]
Time required for one refresh operation = 150 ns LOAD R2, M[1002]
In 1 ms, the time required to refresh is 64 × 150 ns LOAD R4, M[1004]
= 9600 ns ADD R3, R1, R2
∴ The fraction of time devoted to memory refresh is ADD R5, R1, R4
9600 × 10 −9 STORE R3, M[1008]
= 0.0096 STORE R5, M[1010]
10 −3
No stalls in the reordered code. Choice (A)
∴ Approximate percentage of the memory’s total
operating time given to refreshes is 1%. 17. The Array M2×8 is stored in column-major order in the
Choice (A) main memory, i.e.,
 Computer Organization and Architecture Test 3 | 3.31

Main memory
Cache memory The cache memory is shown below with main memory
w0
block addresses.
L0
w1 Start
w2
. L1 0 1024 20
w3 I0
. . .
. . 127 1151 26
. . .
.. 128 1152
. I1 168
.
. . 255 1279 1203
2000
. M0, 0 . .
. B0 . . 256 1280 I2 242
. M1, 0 w14 L7 383 1407
. M0, 1 w15
. B1 384 1408 I3
. M1, 1
. 511 1535
. .
. . . 512 I4
. . .
. . . 1503
.
639
end
640 I5
2015 M0, 7
B7
M1, 7 767
768 I6
.
. 895
.
. 896 I7
1023
In direct mapping, B0 is placed in L0, B1 in L1, B2 in
L2, ..., B7 in L7 to access the elements M0, 0 – M0, 7
The remaining elements are already in cache. All those
accesses will be hits. Hence the sequence of reads from the main memory
As all the 8-blocks used, cache utilization is 100%. blocks into cache line is:
In Associative mapping, each block of main memory
Line: 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 0, 1, 0, 1, ...0, 1, 0, 1, 2, 3
will be placed at anywhere in the cache lines. Also
8-accesses will be misses and the remaining will be
hits. No need of replacement and all lines of cache will Pass 1 outer loop Pass 2 Pass 10
be used.
i.e., in pass1 of outer loop the lines 0, 1, 2, 3, 4, 5, 6,
∴ Cache utilization = 100%
7, 0, 1 will be accessed. In pass 2 0, 1 are accessed for
In 2-way set-Associative mapping, two blocks will
(0 – 127), (128 – 255) and again 0, 1 are accessed for
be treated as a single set. There will be 4-sets.
(1024 – 1151), (1152 – 1279).
Cache memory In last pass 0, 1, 0, 1, 2, 3 lines will be accessed.
∴ Total time for reading the blocks of main memory
L0L1 Set 0
into the cache
L2L3 Set 1 = (10 + 9 × 4 + 2) × 128 × 10
= 61440 n sec. Choice (D)
L4L5 Set 2 19. Let the number of instruction be 100.
Without optimization, time required to execute 100
L6L7 Set 3
Instructions = 100 + 10 × 2 = 100 + 20 = 120
All the four sets are used. Set 0 consists B0, B4, set 1 With optimization time required
contains B1, B5. Like this all sets are used. Hence cache = (120 – 0.75 ×10 – 0.20 × 10) = 110.5
utilization is 100%. Choice (C) ∴ Improvement using optimization
18. Given main memory size = 64 K = 216 words =
120
= 1.086. Choice (B)
Block size = 128 = 27 words 110.5
Cache size = 1 K = 210 words 20. Number of lines in cache = 128
Word field size = 7 As the cache is a 4-way set associative, each set con-
210 tains 4-blocks.
Number of lines = 7 = 23 128
2 ∴ Number of sets = = 32
∴ Line field size = 3 4
⇒ Tag = 16 – (7 + 3) = 6 So there will be 32 misses.
3.32 | Computer Organization and Architecture Test 3

But the program accesses every 8th word. Exponent = 125 – 127 = –2
32 Mantissa =1.110 0000 0000 0000 0000 0000
∴ Number of misses = =4 ∴ y = –1.110 0000 0000 0000 0000 0000 × 2–2
8
= –0.4375
1
Hence miss rate = Choice (B) x + y = 27648 – 0.4375 = 27647.5625
4 x * y = 27648 * 0.4375 = –12096 Choice (A)
21. Instruction size = 32-bits 25. Given code:
Two address instruction format will be I1: ADD R1, R2, R3
I2:SUB R4, R1, R5
opcode address1 address2
I3:LOAD R6, 200(R1)
8 12 12
I4:ADD R7, R1, R6
There will be 28 possible combinations of operations. I2, I3, I4 are dependent on I1. I4 dependent on I3.
Two address instructions = 240 The execution chart is shown below:
Operations for single address instructions 1 2 3 4 5 6 7 8 9 10
= 256 – 240 = 16 I1 IF ID EX MEM WB
I2 IF ID EX MEM WB
Single address instruction format will be I3 IF ID EX MEM WB
I4 IF Stall ID EX MEM WB
opcode address

12 bits ∴ R1 can be forwarded to I2, I3 and I4, but R6 (in I3)

cannot be forwarded to I4 immediately, so one stall
Total one address operations = 16 × 2 = 65536.
12
occurs. Choice (B)
Choice (B)
26. Given number +1001.110
22. The ideal speed up of a pipelined processor is equal to
the number of stages in the pipeline. Then c = 0 1 0 0 1 1 1 0 0 0
∴ As there are 5-stages the speed will be 5.
Choice (B) sign fraction

23. Ideal speed up = 5 e= 0 0 1 0 0

Speed up due to Data hazards
Pipeline Depth sign exponent
1 + (load frequency × load penalty) The decimal point will be at 4th position from left.
+ (branch frequency × branch penalty) Choice (A)
=
5 27. Input clock frequency = 8 MHz
1 + (0.2 × 0.4 × 2) + (0.3 × 0.5 × 3) 1
clock cycle = = 125 ns
5 8 MHz
= = 3.11
1 + 0.16 + 0.45 Given that bus cycle = 4 × clock cycle
5 − 3.11 = 4 × 125 = 500 ns
∴ Speed up = × 100 = 37.8% Choice (D) Data bus width = 16-bits = 2 B
5
∴ 2 B can be transferred for every 500 ns.
24. Given x = 0100 0110 1101 1000 0000 0000 0000 0000 2B
y = 1011 1110 1110 0000 0000 0000 0000 0000 ∴ Transfer rate = = 4 MB/sec Choice (B)
500 ns
IEEE 754 floating point representation numbers has the
following format: 28. As the number is an indirect address operand, the effec-
Sign Biased exponent Mantissa
tive address will present in the given address location.
So we refer two times to get the actual operand from
1 8 23
memory. Hence the correct sequence of micro-opera-
For x, sign bit = 0 ⇒ sign = + tion is Choice (D)
Biased exponent = 100 01101 = 141 29. As there are 7 micro-operations and each micro-oper-
Exponent = 141 – 127 (Bias) = 14 ation takes one clock cycle, the total number of clock
Mantissa = 1.101 1000 0000 0000 0000 0000 cycles for addition with an indirect address operand = 7.
∴ x = +1.101 1000 0000 0000 0000 0000 × 214 Choice (D)
= +27648 30. Access time of cache = 100 ns
For y, sign bit =1 ⇒ sign = – Access time of main memory = 1 ms = 103 ns
Biased exponent = 011 1110 1 = 125
 Computer Organization and Architecture Test 3 | 3.33

Read requests = 80% word size = 4

Write requests = 20% 216
Number of blocks in cache = = 212
Hit ratio for read only access = 0.9 24
Write-through means main memory is updated while ∴ Line = 12
updating cache memory. tag + line = 20 – 4 = 16
Average access time of the system Tag = 16 – 12 = 4
= 0.8(0.9 × 100 + 0.1(100 + 1000)) + 0.2 × 1000 Given address F0010:
= 160 + 200 = 360 ns Choice (C)
1111 000000000001 000
31. The instruction “bbs reg, pos, label” jumps to label it F0010 =
tag line word
bit in position ‘pos’ of register operand ‘reg’ is one.
To implement this instruction as ∴ Line address = 0000 0000 0001 Choice (C)
result ← reg & mask 33. The time required to transfer one byte is:
We are performing ‘and’ operation between ‘reg’ and = 250 + 500 + 250
‘mask’. = 1000 ns = 1 μs.
The mask must be ‘1’ to check a position value of ‘reg’. To transfer 128 bytes, we require 128 μs.
And it is left shifted POS number of times to align that Choice (D)
1 to the required position of reg. 34. Instructions size = 2 B
For example, Current instructions address = 356029
Reg = A091 = 1010 0000 1001 0001 PC always points to the address of the next instruction.
POS = 2 i.e., 356029 + 2 = 356031
Using bbs, we won’t jump to label as 2nd bit is zero us- In PC-relative addressing mode, the content of PC is
ing mask ← ox1 << POS added to the displacement, which is given as -31.
← ox1 << 2 So the branch target address
← ox 0100 = 356031 - 31 = 356000 Choice (D)
Now we perform AND between reg and mask. As the
35. Data transferred = 10 kB/sec
result is zero we won’t jump to label. Choice (D)
= 10000 Bytes/sec
32. Main memory = 1 MB = 2 B 20
Given that interrupts are generated for every 1 Byte.
Word size = 1 B
There will be 10000 interrupts and rate of interrupts
Block size = 16 B = 24 B
1
Cache size = 64 KB = 216 B = = 100 ms
For Direct mapped cache: 10000
∴ Fraction of processor time consumed by this I/O
tag line word
100
= =1 Choice (A)
20 100