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ams OSRAM Group
Datasheet
DS001046

AS7343
14-Channel Multi-Spectral Sensor

v4-00 • 2022-Dec-19
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Content Guide

Content Guide

1 General Description ...................... 3 9.1 I²C Address ................................................. 18

9.2 I²C Write Transaction.................................. 19
1.1 Key Benefits & Features............................... 3 9.3 I²C Read Transaction ................................. 19
1.2 Applications .................................................. 4 9.4 Timing Characteristics ................................ 19
1.3 Block Diagram .............................................. 4 9.5 Timing Diagrams ........................................ 20
2 Ordering Information .................... 5 10 Register Description .................... 21
3 Pin Assignment ............................. 6 10.1 Register Overview ...................................... 21
10.2 Detailed Register Description ..................... 24
3.1 Pin Diagram .................................................. 6
3.2 Pin Description ............................................. 6 11 Application Information............... 49
4 Absolute Maximum Ratings ......... 8 11.1 Schematic ................................................... 49
11.2 PCB Pad Layout ......................................... 49
5 Electrical Characteristics.............. 9 11.3 Application Optical Requirements .............. 50
6 Optical Characteristics ............... 10 12 Package Drawings & Markings ... 51
7 Typical Operating 13 Tape & Reel Information.............. 52
Characteristics ............................ 14
14 Soldering & Storage Information 54
8 Functional Description................ 15
14.1 Storage Information .................................... 55
8.1 Device Architecture .................................... 16
8.2 Sensor Array............................................... 17 15 Revision Information ................... 56
8.3 GPIO........................................................... 17 16 Legal Information ......................... 57
8.4 Interrupt (INT) ............................................. 17
8.5 LED Driver (LDR) ....................................... 17
9 I²C Interface.................................. 18

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General Description

1 General Description
The ams OSRAM AS7343 is a 14-channel highly versitile, multi-purpose spectral sensor enabling new
consumer, commercial, industrial and laboratory applications. It is optimized for reflective,
transmissive and emissive measurements including color matching, fluid or reagent analysis, lateral
flow test applications and spectral identification in the visible range.

The spectral response is defined by individual channels covering approximately 380 nm to 1000 nm
with 11 channels centered in the visible spectrum (VIS), plus one near-infrared (NIR) and a clear
channel.

AS7343 integrates high-precision optical filters onto standard CMOS silicon via deposited interference
filter technology. A built-in aperture controls the light entering the sensor array to increase accuracy. A
programmable digital GPIO and LED driver enable light source and trigger/sync control. Device control
and spectral data access is implemented through a serial I²C interface. The device is available in an
ultra-low profile package with dimensions of 3.1 mm x 2 mm x 1 mm.

1.1 Key Benefits & Features

The benefits and features of AS7343, 14-Channel Multi-Spectral Sensor, are listed below:

Figure 1:
Added Value of Using AS7343

Benefits Features

Highly versatile multi-purpose spectral ● 14 channels between 380 nm and 1000 nm

sensor ● Reflective, transmissive and emissive applications
● Enables ultra-low light operation
Highest sensitivity ● Enables operation behind dark glass or additional
external filters
● 1.8 V VDD operation
Low power consumption and minimum I2C
● Configurable sleep mode
traffic
● Interrupt-driven device
● On chip interference filter technology
Ultra-high integration ● Integrated LED driver and 6 integrated ADCs
● 3.1 mm x 2 mm x 1 mm package outline

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General Description

1.2 Applications
● Emissive light measurement
● Transmissive and reflective measurements such as fluid or color measurements
● Photoelectric smoke detectors

1.3 Block Diagram

The functional blocks of this device are shown below:

Figure 2 :
Functional Blocks of AS7343

1.8V VLED
VDD
LED
PGND (opt.)
GND AS7343 LDR
1.8V
14CH
Spectral
Sensor
SCL 380-1000nm
MCU SDA
INT GPIO Trig/Sync

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Ordering Information

2 Ordering Information

Ordering Code Package Delivery Form Delivery Quantity I2C Slave Address

AS7343-DLGT OLGA-8 Tape & Reel 13-inch 10000 pcs/reel 0x39

AS7343-DLGM OLGA-8 Tape & Reel 7-inch 500 pcs/reel 0x39
AS7343B-DLGT OLGA-8 Tape & Reel 13-inch 10000 pcs/reel 0x29

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Pin Assignment

3 Pin Assignment

3.1 Pin Diagram

Figure 3:
Pin Assignment of AS7343 (TOP VIEW)

VDD 1 8 SDA

SCL 2 7 INT
TOP VIEW

GND 3 6 GPIO

LDR 4 5 PGND

3.2 Pin Description

Figure 4:
Pin Description of AS7343

Pin Number Pin Name Pin Type(1) Description

1 VDD P Positive supply voltage terminal
Serial interface clock signal line for I²C interface.
2 SCL DI
Connect pull up resistor to 1.8 V.
3 GND P Ground. All voltages referenced to GND
4 LDR A_I/O LED current sink input. If not used leave pin unconnected.
5 PGND P Ground. All voltages referenced to GND
General purpose input/output. Default output open drain. If not
6 GPIO D_I/O
used leave pin unconnected.

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Pin Assignment

Pin Number Pin Name Pin Type(1) Description

Interrupt. Open drain output active low. Connect pull up resistor
7 INT DO_OD
to 1.8 V. If not used leave pin unconnected.
Serial interface data signal line for I²C interface.
8 SDA D_I/O
Connect pull up resistor to 1.8 V.

(1) Explanation of abbreviations:

DI Digital Input
D_I/O Digital Input/Output
DO_OD Digital Output, open drain
P Power pin
A_I/O Analog pin

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Absolute Maximum Ratings

4 Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only. Functional operation of the device at these or any other
conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. All voltages with respect
to GND/PGND. Device parameters are guaranteed at VDD=1.8 V and TA=25 °C unless otherwise
noted.

Figure 5:
Absolute Maximum Ratings of AS7343

Symbol Parameter Min Max Unit Comments

Electrical Parameters
VDD / VGND Supply Voltage to Ground -0.3 1.98 V Applicable for pin VDD
VANA_MAX Analog Pins -0.3 3.6 V Applicable for pin LDR
Applicable for pins
VDIG_MAX Digital Pins -0.3 3.6 V
SCL,SDA,GPIO and INT
Input Current (latch-up
ISCR ± 100 mA AEC-Q100-004E
immunity)
IO Output Terminal Current -1 20 mA
Electrostatic Discharge
ESDHBM Electrostatic Discharge HBM ± 2000 V JS-001-2017
ESDCDM Electrostatic Discharge CDM ± 500 V JS-002-2018
Temperature Ranges and Storage Conditions
TA Operating Ambient Temperature -30 85 °C
TSTRG Storage Temperature Range -40 85 °C
TBODY Package Body Temperature 260 °C IPC/JEDEC J-STD-020(1)
Relative Humidity (non-
RHNC 5 85 %
condensing)
MSL Moisture Sensitivity Level 3 Maximum floor life time of 168h

(1) The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.” The lead finish for Pb-
free leaded packages is “Matte Tin” (100% Sn).

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Electrical Characteristics

5 Electrical Characteristics
All limits are guaranteed. The parameters with Min and Max values are guaranteed with production
tests or SQC (Statistical Quality Control) methods. All voltages with respect to GND/PGND. Device
parameters are guaranteed at VDD=1.8 V and TA=25 °C unless otherwise noted.

Figure 6:
Electrical Characteristics of AS7343

Symbol Parameter Conditions Min Typ Max Unit

VDD Supply voltage 1.7 1.8 1.98 V
Operating free-air
TA -30 25 85 °C
temperature(1)
Power Consumption
VDD=1.8 V; TA =25 °C
210 280 µA
Active mode(3)
VDD=1.8 V; TA =25 °C
IDD Supply current(2) 40 60 µA
Idle mode(4)
VDD=1.8 V; TA =25 °C
0.7 5 µA
Sleep mode(5)
Digital Pins
SCL,SDA input high
VIH 1.26 V
voltage
SCL,SDA input low
VIL 0.54 V
voltage
INT, SDA output low
VOL 6 mA sink current 0.4 V
voltage
CI Input pin capacitance 10 pF
Leakage current into
Ileak -5 5 µA
SCL,SDA,INT pins
GPIO
Maximum capacitive
CLOAD 20 pF
load GPIO
LED Driver
I_LDR= 4 mA ; LED_HALF = “0” 240
mV
I_LDR= 4 mA ; LED_HALF = “1” 130
V_LDR LDR compliance voltage
I LDR 134 mA ; LED_HALF = “0” 280
mV
I LDR 134 mA ; LED_HALF = “1” 180

(1) While the device is operational across the temperature range, functionality will vary with temperature.
(2) Supply current values are shown at the VDD pin and do not include current through pin LDR.
(3) Active state occurs during active integration. (PON = “1” ; SP_EN = “1”) If wait is enabled (WEN = “1”), supply current is
lower during the wait period.
(4) Idle state occurs when PON = “1” and all functions are disabled.
(5) Sleep state occurs when PON = “0” and I2C bus is idle. If I2C traffic is active device automatically enters idle mode.

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Optical Characteristics

6 Optical Characteristics
All limits are guaranteed. The parameters with Min and Max values are guaranteed with production
tests or SQC (Statistical Quality Control) methods. All voltages with respect to GND/PGND. Device
parameters are guaranteed at VDD=1.8 V and TA=25 °C unless otherwise noted.

Figure 7:
AS7343 Optical Channel Summary

Peak Wavelength [nm](1)(2) Full Width Half Maximum [nm]

Channel
(min) λp (typ) (max) (typ)
F1 395 405 415 30
F2 415 425 435 22
FZ 440 450 460 55
F3 465 475 485 30
F4 505 515 525 40
FY 545 555 565 100
F5 540 550 560 35
FXL 590 600 610 80
F6 630 640 650 50
F7 680 690 700 55
F8 735 745 755 60
NIR 845 855 865 54

(1) Parameter measured on a production ongoing sample bases on glass using diffused light. The table above is valid for
full sensor response including diffuser, package and photodiode response.
(2) Peak wavelength is validated by smoothed/averaged monochromator measurement data.

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Optical Characteristics

Figure 8:
Optical Characteristics of Spectral Channels, AGAIN: 1024x, Integration Time: 27.8 ms

Symbol Parameter Conditions Min Typ Max Unit

Irradiance LED_396 nm ; Ee= 155 mW/m²

Re_F1 responsivity 4311 5749 7186 counts
channel F1 LED_408 nm ; Ee= 155 mW/m²

Irradiance LED_408 nm ; Ee= 155 mW/m²

Re_F2 responsivity 1317 1756 2196 counts
channel F2 LED_448 nm ; Ee= 155 mW/m²

Irradiance LED_428 nm ; Ee= 155 mW/m²

Re_FZ responsivity 1627 2169 2711 counts
channel FZ LED_480 nm ; Ee= 155 mW/m²

Irradiance LED_448 nm ; Ee= 155 mW/m²

Re_F3 responsivity 577 770 962 counts
channel F3 LED_500 nm ; Ee= 155 mW/m²

Irradiance LED_500 nm ; Ee= 155 mW/m²

Re_F4 responsivity 2356 3141 3926 counts
channel F4 LED_534 nm ; Ee= 155 mW/m²

Irradiance LED_534 nm ; Ee= 155 mW/m²

Re_FY responsivity 2810 3747 4684 counts
channel FY LED_593 nm ; Ee= 155 mW/m²

Irradiance LED_531 nm ; Ee= 155 mW/m²

Re_F5 responsivity 1180 1574 1967 counts
channel F5 LED_594 nm ; Ee= 155 mW/m²

Irradiance LED_593 nm ; Ee= 155 mW/m²

Re_FXL responsivity 3582 4776 5970 counts
channel FXL LED_628 nm ; Ee= 155 mW/m²

Irradiance LED_618 nm ; Ee= 155 mW/m²

Re_F6 responsivity 2502 3336 4170 counts
channel F6 LED_665 nm ; Ee= 155 mW/m²

Irradiance LED_685 nm ; Ee= 155 mW/m²

Re_F7 responsivity 4095 5435 6774 counts
channel F7 LED_715 nm ; Ee= 155 mW/m²

Irradiance LED_715 nm ; Ee= 155 mW/m²

Re_F8 responsivity 648 864 1080 counts
channel F8 LED_766 nm ; Ee= 155 mW/m²

Irradiance LED_849 nm ; Ee= 155 mW/m²

Re_NIR responsivity 7936 10581 13226 counts
channel NIR LED_903 nm ; Ee= 155 mW/m²

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Optical Characteristics

Figure 9:
Optical Characteristics of Broadband Channels, AGAIN: 1024x, FD_GAIN: 64x, Integration
Time: 27.8 ms

Symbol Parameter Conditions Min Typ Max Unit

Irradiance LED_593 nm ; Ee= 155 mW/m²

Re_FD responsivity LED_766 nm ; Ee= 155 mW/m² 3233 4311 5389 counts
channel Flicker FD_GAIN=64x

Irradiance LED_396 nm ; Ee= 155 mW/m²

Re_VIS responsivity LED_766 nm ; Ee= 155 mW/m² 749 999 1248 counts
channel VIS 2 VIS PDs read-out

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Optical Characteristics

Figure 10:
Optical Characteristics of AS7343, AGAIN: 128x, Integration Time: 11 ms (unless otherwise
noted)

Symbol Parameter Conditions Min Typ Max Unit

Ee = 0 μW/cm2
Dark ADC count AGAIN: 512x
Dark_1(1) 0 5 counts
value Integration time:
98 ms
AGAIN: 0.5x 7.49 7.9 8.28
AGAIN: 1x 15 15.8 16.5
AGAIN: 2x 30 31.6 33.2 See
AGAIN: 4x 61 64 67 note (3)

AGAIN: 8x 117 124 130

AGAIN: 16x 235 247 259
(2) Optical gain ratios,
Gain
relative to 64x gain AGAIN: 32x 0.475 0.5 0.525
ratio
setting
AGAIN: 64x 1
AGAIN: 128x 1.9 2 2.1
AGAIN: 256x 3.9 4.1 4.3
AGAIN: 512x 8.1 8.6 9.1
AGAIN: 1024x 15.2 16.9 18.6
AGAIN: 2048x 28.2 34.75 41.3
White LED, 2700 K
ADC % full
Integration time: 0.05
noise(4) scale
100 ms
Typical integration ASTEP = 599
tint 50 ms
time(5) ATIME = 29
Integration time step
tASTEP ASTEP = 999 2.78 ms
size
hca Half cone angle On the sensor 40 deg

(1) The typical 3-sigma distribution is between 0 and 1 counts for AGAIN setting of 16x.
(2) The gain ratios are relative to 64x gain setting and are calculated relative to the response with integration time: 11 ms
and AGAIN: 128x.
(3) ADC noise is calculated as the standard deviation of relative to full scale.
(4) Integration time, in milliseconds, is equal to: (ATIME + 1) x (ASTEP + 1) x 2.78 µs
(5) AGAIN ratio 0.5x to 16x is multiplied by 1000 for easier readability

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Typical Operating Characteristics

7 Typical Operating Characteristics

Figure 11:
Spectral Responsivity

F1 F2 FZ F3 F4 FY F5
FXL F6 F7 F8 VIS NIR
0.9
spectral responsivity scaled to Si response

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0
350 400 450 500 550 600 650 700 750 800 850 900 950 1000
wavelength / λ [nm]

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Functional Description

8 Functional Description
Upon power-up (POR), the device initializes. During initialization (typically 200 μs), the device will
deterministically send NAK on I²C and cannot accept I²C transactions. All communication with the
device must be delayed and all outputs from the device must be ignored including interrupts. After
initialization, the device enters the SLEEP state. In this operational state, the internal oscillator and
other circuitry are not active, resulting in ultra-low power consumption. If an I²C transaction occurs
during this state, the I²C core wakes up temporarily to service the communication. Once the Power ON
bit, “PON”, is enabled, the device enters the IDLE state in which the internal oscillator and attendant
circuitry are active, but power consumption remains low. Whenever the spectral measurement is
enabled (SP_EN = “1”) the device enters the ACTIVE state. If the spectral measurement is disabled
(SP_EN = “0”) the device returns to the IDLE state. The figure below describes a simplified state
diagram and the typical supply currents in each state.

If Sleep after Interrupt is enabled (SAI = “1” in register 0xC7), the state machine will enter SLEEP
when an interrupt occurs. Entering SLEEP does not automatically change any of the register settings
(e.g. PON bit is still high, but the normal operational state is over-ridden by SLEEP state). SLEEP
state is terminated when the SAI_ACTIVE bit is cleared (the status bit is in register 0xBC and the clear
status bit is in register 0xFA).

Figure 12:
Simplified State Diagram

Power On

VDD > VDD_POR

SLEEP
PON = 0"

PON = 1"

IDLE
SP_EN = 0"

SP_EN = 1"

ACTIVE
Spectral/Flicker

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Functional Description

8.1 Device Architecture

The device features six independent 16-bit ADCs. Gain and integration time of the six ADCs can be
adjusted with the I2C interface. A wait time can be programed to automatically set a delay between two
consecutive spectral measurements and to reduce overall power consumption. Once a measurement
is started, the device is automatically processing the channels and storing the measurement data on
chip.

Figure 13:
Simplified Block Diagram

VDD LDR
GND SYNC input
automatic
LED
measurement engine Driver PGND
GPIO

CH0 ADC Data 1

SCL
CH1 ADC Data 2 I2C
SMUX

CH2 ADC Data 3 Interface SDA

CH3 ADC .
CH4 ADC .
interrupt INT
handling
CH5 ADC Data 18
18 x 16bit
6 x 16bit
DATA
ADC
Register

256 byte RC-

5x5 PD array OTP
Flicker PD FIFO osc
on chip IF Filter

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Functional Description

8.2 Sensor Array

The device features a 5x5-photodiode array. On top and below the photodiode array there are two
photodiodes with dedicated functions such as flicker detection (“FD”) and near- infrared response
(“NIR”). The photodiode “C” represents a photodiode without filter and is responsive in the visible
spectral range. (“VIS”).

Figure 14:
Sensor Array

520µm

NIR FD

C F F6 C
F3 5

X F2 F7
F4 L
F1
FY F8

780µm
520µm

F8 FY FZ
F1
X F4
F7 F2 L

F F3
C F6 5 C

FD NIR

8.3 GPIO
The GPIO can be used synchronization input to start/stop the spectral measurement. It also allows
synchronizing the LED driver (LDR) with an external start/stop signal. Default state of the GPIO is
“output”.

8.4 Interrupt (INT)

The interrupt (INT) can be used to define thresholds and read-out the device only when the channel
threshold has been reached. The pin is active low.

8.5 LED Driver (LDR)

The LED driver is programmable and can be used to drive external LEDs. It is also possible to
synchronize the LED driver with an external start/stop signal via pin GPIO.

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I²C Interface

9 I²C Interface
The device uses I²C serial communication protocol for communication. The device supports 7-bit chip
addressing and both standard and full-speed clock frequency modes. Read and Write transactions
comply with the standard set by Philips (now NXP). Internal to the device, an 8-bit buffer stores the
register address location of the desired byte to read or write. This buffer auto-increments upon each
byte transfer and is retained between transaction events (i.e. valid even after the master issues a
STOP command and the I²C bus is released). During consecutive Read transactions, the
future/repeated I²C Read transaction may omit the memory address byte normally following the chip
address byte; the buffer retains the last register address +1. All 16-bit fields have a latching scheme
for reading and writing. In general, it is recommended to use I²C bursts whenever possible, especially
in this case when accessing two bytes of one logical entity. When reading these fields, the low byte
must be read first, and it triggers a 16-bit latch that stores the 16-bit field. The high byte must be read
immediately afterwards. When writing to these fields, the low byte must be written first, immediately
followed by the high byte. Reading or writing to these registers without following these requirements
will cause errors.

9.1 I²C Address

Figure 15:
AS7343 I²C Slave Address

Device I2C Address

AS7343 0x39

AS7343B 0x29

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I²C Interface

9.2 I²C Write Transaction

A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS WRITE,
DATA BYTE(S), and STOP (P). Following each byte (9th clock pulse) the slave places an
ACKNOWLEDGE/NOT- ACKNOWLEDGE (A/N) on the bus. If the slave transmits N, the master may
issue a STOP.

Figure 16:
I2C Byte Write

S DW A WA A reg_data A P

WA++

9.3 I²C Read Transaction

A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS,
RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but the final byte the
master places an ACK on the bus (9th clock pulse). Termination of the Read transaction is indicated by
a NACK being placed on the bus by the master, followed by STOP.

Figure 17:
I2C Read

S DW A WA A Sr DR A data N P

RA++

9.4 Timing Characteristics

Figure 18:
I²C Timing Characteristics

Symbol Parameter Min Typ Max Unit

fSCL I²C clock frequency 1 MHz

Bus free time between start and stop
tBUF 1.3
condition
µs
Hold time after (repeated) start condition.
tHD;STA 0.6
After this period, the first clock is generated.

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I²C Interface

Symbol Parameter Min Typ Max Unit

tSU;STA Repeated start condition setup time 0.6

tSU;STO Stop condition setup time 0.6
tLOW SCL clock low period 1.3
tHIGH SCL clock high period 0.6
tHD;DAT Data hold time 0
tSU;DAT Data setup time 100
ns
tF Clock/data fall time 300
tR Clock/data rise time 300

9.5 Timing Diagrams

Figure 19:
I²C Slave Timing Diagram

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Register Description

10 Register Description
The device is controlled and monitored by registers accessed through the I²C serial interface. These
registers provide device control functions and can be read to determine device status and acquire
device data.

The register set is summarized below. The values of all registers and fields that are listed as reserved
or are not listed must not be changed at any time. Two-byte fields are always latched with the low byte
followed by the high byte. The “Name” column illustrates the purpose of each register by highlighting
the function associated to each bit. The bits are shown from MSB (D7) to LSB (D0). GRAY fields are
reserved and their values must not be changed at any time.

In order to access registers from 0x58 to 0x66 bit REG_BANK in register CFG0 (0xBF) needs to be
set to “1”. For register access of registers 0x80 and above bit REG_BANK needs to be set to “0”.

10.1 Register Overview

Figure 20:
Register Overview

Addr Name <D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0>

0x58 AUXID AUXID [3:0]

0x59 REVID REVID [2:0]
0x5A ID ID [7:0]
0x66 CFG12 SP_TH_CH [2:0]
SMUXE
0x80 ENABLE FDEN WEN SP_EN PON
N
0x81 ATIME ATIME [7:0]
0x83 WTIME WTIME [7:0]
0x84 SP_TH_L_LSB [7:0]
SP_TH_L
0x85 SP_TH_L_MSB [7:0]
0x86 SP_TH_H_LSB [7:0]
SP_TH_H
0x87 SP_TH_H_MSB [7:0]
0x93 STATUS ASAT AINT FINT SINT
ASAT_
0x94 ASTATUS AGAIN_STATUS [3:0]
STATUS
0x95 DATA_0_L [7:0]
DATA_0
0x96 DATA_0_H [7:0]
0x97 DATA_1_L [7:0]
DATA_1
0x98 DATA_1_H [7:0]
0x99 DATA_2 DATA_2_L [7:0]

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Register Description

Addr Name <D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0>

0x9A DATA_2_H [7:0]

0x9B DATA_3_L [7:0]
DATA_3
0x9C DATA_3_H [7:0]
0x9D DATA_4_L [7:0]
DATA_4
0x9E DATA_4_H [7:0]
0x9F DATA_5_L [7:0]
DATA_5
0xA0 DATA_5_H [7:0]
0xA1 DATA_6_L [7:0]
DATA_6
0xA2 DATA_6_H [7:0]
0xA3 DATA_7_L [7:0]
DATA_7
0xA4 DATA_7_H [7:0]
0xA5 DATA_8_L [7:0]
DATA_8
0xA6 DATA_8_H [7:0]
0xA7 DATA_9_L [7:0]
DATA_9
0xA8 DATA_9_H [7:0]
0xA9 DATA_10_L [7:0]
DATA_10
0xAA DATA_10_H [7:0]
0xAB DATA_11_L [7:0]
DATA_11
0xAC DATA_11_H [7:0]
0xAD DATA_12_L [7:0]
DATA_12
0xAE DATA_12_H [7:0]
0xAF DATA_13_L [7:0]
DATA_13
0xB0 DATA_13_H [7:0]
0xB1 DATA_14_L [7:0]
DATA_14
0xB2 DATA_14_H [7:0]
0xB3 DATA_15_L [7:0]
DATA_15
0xB4 DATA_15_H [7:0]
0xB5 DATA_16_L [7:0]
DATA_16
0xB6 DATA_16_H [7:0]
0xB7 DATA_17_L [7:0]
DATA_17
0xB8 DATA_17_H [7:0]
ASAT_ ASAT_ FDSAT FDSAT_
0x90 STATUS 2 AVALID
DIG ANA _ANA DIG
INT_SP
0x91 STATUS 3 INT_SP_H
_L
SINT SINT
0xBB STATUS 5
_FD _SMUX
FIFO_ FD_TRI SP_TRI SAI_ INT_BUS
0xBC STATUS 4 OVTEMP
OV G G ACT Y

LOW_ REG_
0xBF CFG 0 WLONG
POWER BANK

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Register Description

Addr Name <D7> <D6> <D5> <D4> <D3> <D2> <D1> <D0>

0xC6 CFG1 AGAIN[4:0]

0xC7 CFG3 SAI
SMUX_
0xF5 CFG6
CMD[4:3]
0xC9 CFG8 FIFO_TH [7:6]
SIEN SIEN
0xCA CFG9
_FD _SMUX
0x65 CFG10 FD_PERS [2:0]
0xCF PERS APERS [3:0]
GPIO_ GPIO_ GPIO_ GPIO_
0x6B GPIO
INV IN_EN OUT IN
0xD4 ASTEP [7:0]
ASTEP
0xD5 ASTEP [15:8]
FD_FIF
0xD6 CFG20 auto_SMUX
O_8b
LED_AC
0xCD LED LED_DRIVE [6:0]
T
AGC_GAIN_
0xD7 AGC_FD_GAIN_MAX [7:4]
MAX
0xDE AZ_CONFIG AT_NTH_ITERATION [7:0]
0xE0 FD_TIME_1 FD_TIME [7:0]
0xE2 FD_TIME_2 FD_GAIN [7:3] FD_TIME [10:8]
FIFO_W
0xDF FD_CFG0 RITE_F
D
FD_ FD_
FD_STATU FD_ FD_ FD_ FD_
0xE3 120HZ_ 100Hz_
S VALID SAT 120Hz 100Hz
VALID VALID
0xF9 INTENAB ASIEN SP_IEN FIEN SIEN
SW_ SP_MAN FIFO_ CLEAR_
0xFA CONTROL
RESET _AZ CLR SAI_ACT
ASTATU
0xFC FIFO_MAP FIFO_WRITE_CH5_DATA – FIFO_WRITE_CH0_DATA [6:1]
S
0xFD FIFO_LVL FIFO_LVL [7:0]
0xFE FDATA _L[7:0]
FDATA
0xFF FDATA_H [15:8]

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Register Description

10.2 Detailed Register Description

For easier readability, the detailed register description is done in groups of registers related to
dedicated device functions. This is not necessarily related to its register address.

Explanation of register access abbreviations:

RW = read or write
R = read only
W = write only
SC = self-clearing after access

10.2.1 Enable and Configuration Registers

The following registers are needed to power up and configure the device. To operate the device set bit
PON = “1” first (register 0x80) after that configure the device and enable interrupts before setting
SP_EN = “1”. Changing configuration while SP_EN = “1” may result in invalid results.

ENABLE Register (Address 0x80)

Figure 21:
ENABLE Register

Addr: 0x80 ENABLE

Bit Bit Name Default Access Bit Description

7 Reserved 0 RW Reserved
Flicker Detection Enable.
6 FDEN 0 RW 0: Flicker Detection disabled
1: Flicker Detection enabled
5 Reserved 0 RW Reserved
SMUX Enable.
1: Starts SMUX command
4 SMUXEN 0 RW
Note: This bit gets cleared automatically as soon as
SMUX operation is finished
Wait Enable.
0: Wait time between two consecutive spectral
3 WEN 0 RW measurements disabled
1: Wait time between two consecutive spectral
measurements enabled
2 Reserved 0 RW Reserved
Spectral Measurement Enable.
1 SP_EN 0 RW 0: Spectral Measurement Disabled
1: Spectral Measurement Enabled

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Register Description

Addr: 0x80 ENABLE

Bit Bit Name Default Access Bit Description

Power ON.
0: AS7343 disabled
0 PON 0 RW 1: AS7343 enabled
Note: When bit is set, internal oscillator is activated,
allowing timers and ADC channels to operate.

GPIO Register (Address 0x6B)

Figure 22:
GPIO Register

Addr: 0x6B GPIO

Bit Bit Name Default Access Bit Description

7:4 Reserved 0 Reserved
GPIO Invert.
3 GPIO_INV 0 RW
If set, the GPIO output is inverted.
GPIO Input Enable.
2 GPIO_IN_EN 0 RW
If set, the GPIO pin accepts a non-floating input.
GPIO Output.
1 GPIO_OUT 1 RW
If set, the output state of the GPIO is active directly.
GPIO Input.
0 GPIO_IN 0 R Indicates the status of the GPIO input if
GPIO_IN_EN is set.

LED Register (Address 0xCD)

Figure 23:
LED Register

Addr: 0xCD LED

Bit Bit Name Default Access Bit Description

LED Control.
7 LED_ACT 0 RW 0: External LED connected to pin LDR off
1: External LED connected to pin LDR on
LED Driving Strength.
000 0000: 4 mA
000 0001: 6 mA
6:0 LED_DRIVE 000 0100 RW
000 0010: 8 mA
000 0011: 10 mA
000 0100: 12 mA

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Register Description

Addr: 0xCD LED

Bit Bit Name Default Access Bit Description

……
111 1110: 256 mA
111 1111: 258 mA

INTENAB Register (Address 0xF9)

Figure 24:
INTENAB Register

Addr: 0xF9 INTENAB

Bit Bit Name Default Access Bit Description

Spectral and Flicker Detect Saturation Interrupt
Enable.
7 ASIEN 0 RW
When asserted permits saturation interrupts to be
generated.
6:4 Reserved Reserved
Spectral Interrupt Enable.
3 SP_IEN 0 RW When asserted permits interrupts to be generated,
subject to the spectral thresholds and persistence
filter. Bit is mirrored in the ENABLE register.
FIFO Buffer Interrupt Enable.
2 F_IEN 0 RW When asserted permits interrupt to be generated
when FIFO_LVL exceeds the FIFO threshold
condition.
1 Reserved 0 Reserved
System Interrupt Enable.
0 SIEN RW When asserted permits system interrupts to be
generated. Indicates that flicker detection status has
changed or SMUX operation has finished.

CONTROL Register (Address 0xFA)

Figure 25:
CONTROL Register

Addr: 0xFA CONTROL

Bit Bit Name Default Access Bit Description

7:4 Reserved 0 Reserved
Software Reset
3 SW_RESET 0 RW
When set the device will force a power on reset.
2 SP_MAN_AZ 0 RW Spectral Engine Manual Autozero.

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Register Description

Addr: 0xFA CONTROL

Bit Bit Name Default Access Bit Description

Starts a manual autozero of the spectral engines.
Set SP_EN = 0 before starting a manual autozero for
it to work.
FIFO Buffer Clear.
1 FIFO_CLR 0 RW Clears all FIFO data, FINT, FIFO_OV, and
FIFO_LVL.
Clear Sleep-After-Interrupt Active.
0 CLEAR_SAI_ACT 0 RW Clears SAI_ACTIVE, ends sleep, and restarts device
operation.

10.2.2 ADC Timing Configuration / Integration Time

The integration time is set using the ATIME (0x81) and ASTEP (0xD4, 0xD5) registers. The integration
time, in milliseconds, is equal to:

Equation 1: Setting the integration time

𝑡𝑖𝑛𝑡 = (𝐴𝑇𝐼𝑀𝐸 + 1) × (𝐴𝑆𝑇𝐸𝑃 + 1) × 2.78 µ𝑠

It is not allowed that both settings –ATIME and ASTEP – are set to “0”.

The integration time also defines the full-scale ADC value, which is equal to:

Equation 2: ADC full scale value1

𝐴𝐷𝐶𝑓𝑢𝑙𝑙𝑠𝑐𝑎𝑙𝑒 = (𝐴𝑇𝐼𝑀𝐸 + 1) × (𝐴𝑆𝑇𝐸𝑃 + 1)

ATIME Register (Address 0x81)

Figure 26:
ATIME Register

Addr: 0x81 ATIME

Bit Bit Name Default Access Bit Description

Integration Time.
Sets the number of integration steps from 1 to 255.

7:0 ATIME 0x00 RW Value Integration Time

0 ASTEP
n ASTEP x (n+1)

1
The maximum ADC count is 65535. Any ATIME/ASTEP field setting resulting in higher ADC full-scale values would result in a
full-scale of 65535.

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Register Description

Addr: 0x81 ATIME

Bit Bit Name Default Access Bit Description

255 ASTEP x 256

ASTEP Register (Address 0xD4, 0xD5)

Figure 27:
ASTEP Register

Addr: 0xD4, 0xD5 ASTEP

Bit Bit Name Default Access Bit Description

Integration Time Step Size.
Sets the integration time per step in increments of
2.78 µs. The default value is 999.
7:0 ASTEP 0xCA VALUE STEP SIZE
0 2.78 µs
n 2.78 µs x (n+1)
999 RW
599 1.67 ms
999 2.78 ms
15:8 ASTEP 0xCB 17999 50 ms
65534 182 ms
65535 Reserved, do not use

WTIME Register (Address 0x83)

If wait is enabled (WEN = “1” register 0x80), each new measurement is started based on WTIME. It is
necessary for WTIME to be sufficiently long for spectral integration and any other functions to be
completed within the period. The device will warn the user if the timing is configured incorrectly. If
WTIME is too short, then SP_TRIG in register STATUS4 (ADDR: 0xBC) will be set to “1”.

Figure 28:
WTIME Register

Addr: 0x83 WTIME

Bit Bit Name Default Access Bit Description

Spectral Measurement Wait Time.
8-bit value to specify the delay between two
consecutive spectral measurements.
7:0 WTIME 0x00 RW
Value Wait Cycles Wait Time
0x00 1 2.78 ms

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Register Description

Addr: 0x83 WTIME

Bit Bit Name Default Access Bit Description

0x01 2 5.56 ms
n n 2.78 ms x (n+1)
0xff 256 711 ms

FD_TIME Register (Address 0xE0, 0xE2)

The register FD_Time_1 and FD_Time_2 can be used to configure the integration time and gain (ADC
5) of the flicker detection independently from the other ADCs. The FD_TIME register is an 11-bit
register with the MSB in register 0xDA (bit 10:8) and the LSB in register 0xD8 (bit 7:0). The bit FDEN
(register 0x80) must be set to “1” in order to use the FD_TIME registers. If the bit FDEN is not set,
ADC5 runs automatically with the same gain and integration time as ADC0 to ADC4.

Equation 3: Calculating the flicker detection integration time

𝑡𝑖𝑛𝑡_𝐹𝐷 = 𝐹𝐷_𝑇𝐼𝑀𝐸 × 2.78 µ𝑠

Figure 29:
FD_Time_1 Register

Addr: 0xE0 FD_TIME_1

Bit Bit Name Default Access Bit Description

LSB of flicker detection integration time. Note: must
7:0 FD_TIME [7:0] 0110 0111 RW
not be changed during FDEN = 1 and PON = 1.

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Register Description

Figure 30:
FD_Time_2 Register

Addr: 0xE2 FD_TIME_2

Bit Bit Name Default Access Bit Description

Flicker Detection Gain Setting (ADC5)

VALUE GAIN
0 0.5x
1 1x
2 2x
3 4x
4 8x
7:3 FD_GAIN 9 RW 5 16x
6 32x
7 64x
8 128x
9 256x
10 512x
11 1024x
12 2048x
MSB of flicker detection integration time. Note: must
2:0 FD_TIME [10:8] 1 RW
not be changed during FDEN = 1 and PON = 1.

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Register Description

10.2.3 ADC Configuration

The following registers provide configuration for the 6 integrated ADCs (CH0 to CH5). It is possible to
adjust the gain and setup the auto zero compensation for the ADCs.

CFG1 Register (Address 0xC6)

Figure 31:
CFG1 Register

Addr: 0xC6 CFG1

Bit Bit Name Default Access Bit Description

7:5 Reserved 0 Reserved
Spectral Engines Gain Setting.
Sets the spectral sensitivity.
VALUE GAIN
0 0.5x
1 1x
2 2x
3 4x
4 8x
4:0 AGAIN 9 RW
5 16x
6 32x
7 64x
8 128x
9 256x
10 512x
11 1024x
12 2048x

CFG10 Register (Address 0x65)

Figure 32:
CFG10 Register

Addr: 0x65 CFG10

Bit Bit Name Default Access Bit Description

7:3 Reserved Reserved Reserved Reserved

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Register Description

Addr: 0x65 CFG10

Bit Bit Name Default Access Bit Description

Flicker Detect Persistence.
Sets the number of consecutive flicker detect results
that must be different before the flicker detect status
2:0 FD_PERS 2 RW will be changed. Flicker detection interrupts on SINT
are affected by this setting. Flicker detect
persistence is equal to 2(𝐹𝐷𝑃𝐸𝑅𝑆 −1)
Setting “0” equals to every time.

AZ_CONFIG Register (Address 0xDE)

The following register configures how often the spectral engine offsets are reset (auto zero) to
compensate for changes of the device temperature. The typical time auto zero needs to be completed
is 15 ms.

Figure 33:
AZ_CONFIG Register

Addr: 0xDE AZ_CONFIG

Bit Bit Name Default Access Bit Description

AUTOZERO FREQUENCY.
Sets the frequency at which the device performs auto
zero of the spectral engines.
Note: If FDEN = “1” auto zero is also done for ADC 5.
The flicker detection measurement will be interrupted
and restarted in this case.
VALUE AUTOZERO FREQUENCY
7:0 AZ_NTH_ITERATION 255 RW 0 Never (not recommended)
1 Every integration cycle
2 Every 2 cycles
… Every “AZ_NTH_ITERATION” cycle
254 Every 254 cycles
255 Only before first measurement cycle

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Register Description

AGC_GAIN_MAX Register (Address 0xD7)

Figure 34:
AGC_GAIN_MAX Register

Addr: 0xD7 AGC_GAIN_MAX

Bit Bit Name Default Access Bit Description

Flicker Detection AGC Gain Max.
Sets the maximum gain for flicker detection to
7:4 AGC_FD_GAIN_MAX 9 RW 2 𝐴𝐺𝐶_𝐹𝐷_𝐺𝐼𝐴𝑁_𝑀𝐴𝑋
Default value is 9 (256x). The range can be set from
0 (0.5x) to 10 (2048x).
3:0 Reserved 9 Reserved Reserved

CFG8 Register (Address 0xC9)

Figure 35:
CFG8 Register

Addr: 0xC9 CFG8

Bit Bit Name Default Access Bit Description

FIFO Threshold.
Sets a threshold on the FIFO level that triggers the
first FIFO buffer interrupt (FINT).
VALUE FIFO_LVL
7:6 FIFO_TH 2 RW 0 1
1 4
2 8
3 16
5:0 Reserved 0 Reserved

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Register Description

10.2.4 Device Identification

The following registers provided device identification. Device ID, revision ID and auxiliary ID are read
only.

AUXID Register (Address 0x58)

Figure 36:
AUXID Register

Addr: 0x58 AUXID

Bit Bit Name Default Access Bit Description

7:4 Reserved Reserved
3:0 AUXID 0000 R Auxiliary Identification

REVID Register (Address 0x59)

Figure 37:
REVID Register

Addr: 0x59 REVID

Bit Bit Name Default Access Bit Description

7:3 Reserved Reserved
2:0 REV_ID 000 R Revision Number Identification

ID Register (Address 0x5A)

Figure 38:
ID Register

Addr: 0x5A ID

Bit Bit Name Default Access Bit Description

Part Number Identification
7:0 ID 10000001 R
Value 10000001

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Register Description

10.2.5 Spectral Interrupt Configuration

The spectral interrupt threshold registers provide 16-bit values to be used as the high and low
thresholds for comparison to the 16-bit CH0_DATA values (ADC CH0). If SP_IEN (register 0xF9) is
enabled and CH0_DATA is not between the two thresholds for the number of consecutive
measurements specified in APERS (register 0xBD) an interrupt is set.

SP_TH_L_LSB Register (Address 0x84)

Figure 39:
SP_TH_L_LSB Register

Addr: 0x84 SP_TH_L_LSB

Bit Bit Name Default Access Bit Description

Spectral Low Threshold LSB
7:0 SP_TH_L_LSB 0x00 RW This register provides the low byte of the low
interrupt threshold (CH0).

SP_TH_L_MSB Register (Address 0x85)

Figure 40:
SP_TH_L_MSB Register

Addr: 0x85 SP_TH_L_MSB

Bit Bit Name Default Access Bit Description

Spectral Low Threshold MSB
This register provides the high byte of the low
interrupt threshold (CH0).
Both SP_TH_L registers are combined to a 16-bit
threshold. If the value captured by channel 0 is
below the low threshold and the APERS value is
reached the bit SP_IEN is set and an interrupt is
generated.
7:0 SP_TH_L_MSB 0x00 RW
There is an 8-bit data latch implemented that stores
the written low byte until the high byte is written.
Both bytes will be applied at the same time to avoid
an invalid threshold.
Note: The LSB register cannot be changed without
writing to the MSB register. It is recommended to
write to SP_TH_L_LSB and SP_TH_L_MSB within
one I2C command.

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Register Description

SP_TH_H_LSB Register (Address 0x86)

Figure 41:
SP_TH_H_LSB Register

Addr: 0x86 SP_TH_H_LSB

Bit Bit Name Default Access Bit Description

Spectral High Threshold LSB
7:0 SP_TH_H_LSB 0x00 RW This register provides the low byte of the high
interrupt threshold (CH0).

SP_TH_H_MSB Register (Address 0x87)

Figure 42:
SP_TH_H_MSB Register

Addr: 0x87 SP_TH_H_MSB

Bit Bit Name Default Access Bit Description

Spectral High Threshold MSB
This register provides the high byte of the high
interrupt threshold (CH0).
7:0 SP_TH_H_MSB 0x00 RW Both SP_TH_H registers are combined to a 16-bit
threshold. If the value captured by channel 0 is
above the high threshold and the APERS value is
reached the bit SP_IEN is set and an interrupt is
generated.

CFG12 Register (Address 0x66)

Figure 43:
CFG12 Register

Addr: 0x66 CFG12

Bit Bit Name Default Access Bit Description

7:3 Reserved 0 Reserved
Spectral Threshold Channel.
Sets the channel used for interrupts and persistence,
if enabled, to determine device status and gain
settings.

2:0 SP_TH_CH 0 RW VALUE CHANNEL

0 CH0
1 CH1
2 CH2

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Register Description

Addr: 0x66 CFG12

Bit Bit Name Default Access Bit Description

3 CH3
4 CH4
5 CH5

10.2.6 Device Status Registers

The following registers provide status of the device and indicate details about saturation, interrupts,
over temperature, device execution and ambient light flicker detection.

STATUS Register (Address 0x93)

The primary status register for AS7343 indicates if there are saturation or interrupt events that need to
be handled by the user. This register is self-clearing, meaning that writing a “1” to any bit in the
register clears that status bit. In this way, the user should read the STATUS register, handle all
indicated event(s) and then write the register value back to STATUS to clear the handled events.
Writing “0” will not clear those bits if they have a value of “1”, which means that new events that
occurred since the last read of the STATUS register will not be accidentally cleared. In case channel
saturation has happened (ASAT or FDSAT) it is recommended to discard the measurement results
and re-configure device configuration such as AGAIN and Integration Time to avoid saturation.

Figure 44:
STATUS Register

Addr: 0x93 STATUS

Bit Bit Name Default Access Bit Description

Spectral and Flicker Detect Saturation.
7 ASAT 0 R, SC If ASIEN is set, indicates Spectral saturation. Check
STATUS2 register to distinguish between analog or
digital saturation.
6:4 Reserved 0 R Reserved
Spectral Channel Interrupt.
3 AINT 0 R, SC If SP_IEN is set, indicates that a spectral event that
met the programmed thresholds and persistence
(APERS) occurred.
FIFO Buffer Interrupt.
If FIEN is set, indicates that the FIFO_LVL fulfills the
2 FINT 0 R, SC threshold condition. If cleared by writing 1, the
interrupt will be asserted again as more data is
collected. To fully clear this interrupt, all data must
be read from the FIFO buffer.
1 Reserved 0 R Reserved
0 SINT 0 R, SC System Interrupt.

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Register Description

Addr: 0x93 STATUS

Bit Bit Name Default Access Bit Description

If SIEN is set, indicates that system interrupt is set.
Refer to Status5 register.

STATUS 2 Register (Address 0x90)

Figure 45:
STATUS 2 Register

Addr: 0x90 STATUS 2

Bit Bit Name Default Access Bit Description

7 Reserved 0 Reserved
Spectral Valid.
6 AVALID 0 R Indicates that the spectral measurement has been
completed
5 Reserved 0 Reserved
Digital Saturation.
4 ASAT_DIGITAL 0 R Indicates that the maximum counter value has been
reached. Maximum counter value depends on
integration time set in the ATIME register.
Analog Saturation.
3 ASAT_ANALOG 0 R Indicates that the intensity of ambient light has
exceeded the maximum integration level for the
spectral analog circuit.
2 Reserved 0 R Reserved
Flicker Detect Analog Saturation.
1 FDSAT_ANALOG 0 R Indicates that the intensity of ambient light has
exceeded the maximum integration level for the
analog circuit for flicker detection.
Flicker Detect Digital Saturation.
0 FDSAT_DIGITAL 0 R Indicates that the maximum counter value has been
reached during flicker detection.

STATUS 3 Register (Address 0x91)

Figure 46:
STATUS 3 Register

Addr: 0x91 STATUS 3

Bit Bit Name Default Access Bit Description

7:6 Reserved 0 Reserved
5 INT_SP_H 0 R Spectral Interrupt High.

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Register Description

Addr: 0x91 STATUS 3

Bit Bit Name Default Access Bit Description

Indicates that a spectral interrupt occurred because
the data exceeded the high threshold.
Spectral Interrupt Low.
4 INT_SP_L 0 R Indicates that a spectral interrupt occurred because
the data is below the low threshold.
3:0 Reserved 0 Reserved

STATUS 5 Register (Address 0xBB)

Figure 47:
STATUS 5 Register

Addr: 0xBB STATUS 5

Bit Bit Name Default Access Bit Description

7:4 Reserved 0 Reserved
Flicker Detect Interrupt.
3 SINT_FD 0 R If SIEN_FD is set, indicates that the FD_STATUS
register status has changed
SMUX Operation Interrupt.
2 SINT_SMUX 0 R Indicates that SMUX command execution has
finished.
1:0 Reserved 0 Reserved

STATUS 4 Register (Address 0xBC)

Figure 48:
STATUS 4 Register

Addr: 0xBC STATUS 4

Bit Bit Name Default Access Bit Description

FIFO Buffer Overflow.
7 FIFO_OV 0 R Indicates that the FIFO buffer overflowed and
information has been lost. Bit is automatically
cleared when the FIFO buffer is read
6 Reserved 0 R Reserved
Over Temperature Detected.
5 OVTEMP 0 R Indicates the device temperature is too high. Write 1
to clear this bit.
Flicker Detect Trigger Error.
4 FD_TRIG 0 R Indicates that there is a timing error that prevents
flicker detect from working correctly.

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Register Description

Addr: 0xBC STATUS 4

Bit Bit Name Default Access Bit Description

3 Reserved 0 Reserved
Spectral Trigger Error.
2 SP_TRIG 0 R Indicates that there is a timing error. The WTIME is
too short for the selected ATIME.
Sleep after Interrupt Active.
1 SAI_ACTIVE 0 R Indicates that the device is in SLEEP due to an
interrupt. To exit SLEEP mode, clear this bit.
Initialization Busy.
0 INT_BUSY 0 R Indicates that the device is initializing. This bit will
remain 1 for about 300 μs after power on. Do not
interact with the device until initialization is complete.

FD_STATUS Register (Address 0xE3)

Figure 49:
FD_STATUS Register

Addr: 0xE3 FD_STATUS

Bit Bit Name Default Access Bit Description

7:6 Reserved Reserved
Flicker Detection Measurement Valid.
FD_MEASUREMENT_
5 0 R Indicates that flicker detection measurement is
VALID
complete. Write 1 to this bit to clear this field.
Flicker Saturation Detected.
FD_SATURATION_ Indicates that saturation occurred during the last
4 0 R
DETECTED flicker detection measurement, and the result may
not be valid. Write 1 to this bit to clear this field.
Flicker Detection 120 Hz Flicker Valid.
FD_120HZ_FLICKER_
3 0 R Indicates that the 120 Hz flicker detection calculation
VALID
is valid. Write 1 to this bit to clear this field.
Flicker Detection 100 Hz Flicker Valid.
FD_100HZ_FLICKER_
2 0 R Indicates that the 100 Hz flicker detection calculation
VALID
is valid. Write 1 to this bit to clear this field.
Flicker Detected at 120 Hz.
1 FD_120HZ_FLICKER 0 R Indicates if an ambient light source is flickering at
120 Hz.
Flicker Detected at 100 Hz.
0 FD_100HZ_FLICKER 0 R Indicates if an ambient light source is flickering at
100 Hz.

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Register Description

10.2.7 Spectral Data and Status

The ASTATUS register provides saturation and gain status associated to each set of spectral data.
Reading the ASTATUS register (0x94) latches all 36 spectral data bytes to that status read. Reading
these bytes consecutively (0x94 to 0xB8) ensures that the data is concurrent. All spectral data are
stored as 16-bit values. If flicker detection is enabled, spectral channel five (CH5 ADC) is used for the
flicker detection function. The ASTATUS and spectral data registers are read only.

ASTATUS Register (Address 0x94)

Figure 50:
ASTATUS Register

Addr: 0x94 ASTATUS

Bit Bit Name Default Access Bit Description

Saturation Status.
7 ASAT_STATUS 0 R, SC Indicates if the latched data is affected by analog or
digital saturation.
6:4 Reserved 0 R Reserved
Gain Status.
3:0 AGAIN_STATUS 0 R, SC Indicates the gain applied for the spectral data
latched to this ASTATUS read.

DATA Register (Address 0x95/0xB8)

Figure 51:
DATA_N_L Register

Addr: 0x95/97/99..B7 DATA_N_L

Bit Bit Name Default Access Bit Description

7:0 DATA_N_L 0 R Spectral Data – low byte

Figure 52:
DATA_N_H Register

Addr: 0x96/98/9A..B8 DATA_N_H

Bit Bit Name Default Access Bit Description

7:0 DATA_N_H 0 R Spectral Data – high byte

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Register Description

10.2.8 Miscellaneous Configuration

CFG0 Register (Address 0xBF)

Figure 53:
CFG0 Register

Addr: 0xBF CFG0

Bit Bit Name Default Access Bit Description

7:6 Reserved 0 Reserved
Low Power Idle.
5 LOW_POWER 0 RW When asserted, the device will automatically run in a
low power mode whenever all functions are in wait
states or disabled.
Register Bank Access
0: Register access to register 0x80 and above
4 REG_BANK 0 RW 1: Register access to register 0x20 to 0x7F
Note: Bit needs to be set to access registers 0x20 to
0x7F. If registers 0x80 and above needs to be
accessed bit needs to be set to “0”.
3 Reserved 0 Reserved
Trigger Long.
2 WLONG 0 RW
Increases the WTIME setting by a factor of 16.
1:0 Reserved 0 Reserved

CFG3 Register (Address 0xC7)

Figure 54:
CFG3 Register

Addr: 0xC7 CFG3

Bit Bit Name Default Access Bit Description

7:5 Reserved 0 Reserved
Sleep After Interrupt.
If set, the oscillator is turned off whenever an
4 SAI 0 RW interrupt is active. SAI_ACTIVE is set in this event.
To activate the oscillator again, clear all interrupts
and clear the SAI_ACTIVE bit.
3:0 Reserved 0xC Reserved

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Register Description

CFG6 Register (Address 0xF5)

Figure 55:
CFG6 Register

Addr: 0xF5 CFG6

Bit Bit Name Default Access Bit Description

SMUX Command.
Selects the SMUX command to execute when
setting SMUXEN gets set. Do not change during
ongoing SMUX operation.
VALUE SMUX_CMD

4:3 SMUX_CMD 2 RW 0 ROM code initialization of SMUX

Read SMUX configuration to RAM
1
from SMUX chain
Write SMUX configuration from
2
RAM to SMUX chain
3 Reserved, do not use

CFG9 Register (Address 0xCA)

Figure 56:
CFG9 Register

Addr: 0xCA CFG9

Bit Bit Name Default Access Bit Description

7 Reserved 0 Reserved
System Interrupt Flicker Detection.
6 SIEN_FD 0 RW Enables system interrupt when flicker detection
status change has occurred.
5 Reserved Reserved
System Interrupt SMUX Operation.
4 SIEN_SMUX 0 RW Enables system interrupt when SMUX command has
finished
3:0 Reserved Reserved

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Register Description

CFG20 Register (Address 0xD6)

Figure 57:
CFG20 Register

Addr: 0xD6 CFG20

Bit Bit Name Default Access Bit Description

Enable 8-bit FIFO Mode for Flicker Detection.
0: Disabled
7 FD_FIFO_8b 0 RW 1: Enabled
Note: FD_TIME must be smaller than 256, else
flicker data might be larger than 8 bit. In that case
flicker data gets saturated to 0xFF.
Automatic Channel Read-Out
0: 6 Channel
FZ, FY, FXL, NIR, 2xVIS, FD
1: Reserved;
2: Automatic 12 channel
Cycle 1: FZ, FY, FXL, NIR, 2xVIS, FD
Cycle 2: F2, F3, F4, F6, 2xVIS, FD
3: Automatic 18 channel
Cycle 1: FZ, FY, FXL, NIR, 2xVIS, FD
6:5 auto_smux 0 RW
Cycle 2: F2, F3, F4, F6, 2xVIS, FD
Cycle 3: F1, F7, F8, F5, 2xVIS, FD
Note: the bit “auto_smux” should only be changed
before a measurement is started.
Once a measurement is started the device is
automatically processing the channels as per
definition above and storing the measurement
results in the eighteen data registers.
2xVIS: per default the “Top Left” and “Bot Right”
VIS/CLEAR PD is read-out.
4:0 Reserved Reserved

PERS Register (Address 0xCF)

Figure 58:
PERS Register

Addr: 0xCF PERS

Bit Bit Name Default Access Bit Description

7:4 Reserved 0 Reserved
3:0 APERS 0 RW Spectral Interrupt Persistence.

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Register Description

Addr: 0xCF PERS

Bit Bit Name Default Access Bit Description

Defines a filter for the number of consecutive
occurrences that spectral data must remain outside
the threshold range between SP_TH_L and
SP_TH_H before an interrupt is generated. The
spectral data channel used for the persistence filter
is set by SP_TH_CHANNEL. Any sample that is
inside the threshold range resets the counter to 0.
VALUE CHANNEL
Every spectral cycle generates an
0
interrupt
1 1
2 2
3 3
4 5
5 10
… 5 x (APERS – 3)
14 55
15 60

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Register Description

10.2.9 FIFO Buffer Data and Status

The FIFO buffer is used to poll spectral data with fewer I²C read and write transactions. The FIFO
buffer is 256 bytes of RAM containing 128 two-byte datasets. If the FIFO overflows (i.e. 129 datasets
before host reads data from the FIFO buffer), an overflow flag will be set and new data will be lost.
The Host acquires data by reading addresses: 0xFE – 0xFF. The register address pointer
automatically wraps from 0xFF to 0xFE as data are read. Data can be read one byte at a time or in
blocks, (there is no block-read length limit). When reading single bytes, the internal FIFO read pointer
and the FIFO Buffer Level, FIFO_LVL, are updated each time register 0xFF is read. For block-reads,
the internal FIFO read pointer and the FIFO Buffer Level, FIFO_LVL update for each two-byte entry. If
the FIFO continues to be accessed after FIFO_LVL = 0, the device will return 0 for all data. The FINT
interrupt indicates when there is valid data in the FIFO buffer. The amount of unread data is indicated
by the FIFO_LVL.

FIFO_MAP Register (Address 0xFC)

Figure 59:
FIFO_MAP Register

Addr: 0xFC FIFO_MAP

Bit Bit Name Default Access Bit Description

7 Reserved 0 Reserved
FIFO Write CH5 Data.
If set, CH5 data is written to the FIFO Buffer. (two
6 FIFO_WRITE_CH5_DATA 0 RW bytes per sample)
Note: If flicker detection is enabled, this bit is
ignored. Refer to register 0xD7 for FDEN=”1”.
FIFO Write CH4 Data.
5 FIFO_WRITE_CH4_DATA 0 RW If set, CH4 data is written to the FIFO Buffer. (two
bytes per sample)
FIFO Write CH3 Data.
4 FIFO_WRITE_CH3_DATA 0 RW If set, CH3 data is written to the FIFO Buffer. (two
bytes per sample)
FIFO Write CH2 Data.
3 FIFO_WRITE_CH2_DATA 0 RW If set, CH2 data is written to the FIFO Buffer. (two
bytes per sample)
FIFO Write CH1 Data.
2 FIFO_WRITE_CH1_DATA 0 RW If set, CH1 data is written to the FIFO Buffer. (two
bytes per sample)
FIFO Write CH0 Data.
1 FIFO_WRITE_CH0_DATA 0 RW If set, CH0 data is written to the FIFO Buffer. (two
bytes per sample)
FIFO Write Status.
0 FIFO_WRITE_ASTATUS 0 RW If set, ASTATUS (one byte per sample) is written
to the FIFO Buffer.

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Register Description

FIFO_CFG0 Register (Address 0xDF)

Figure 60:
FIFO_CFG0 Register

Addr: 0xDF FIFO_CFG0

Bit Bit Name Default Access Bit Description

FIFO Write Flicker Detection
If set flicker raw data is written into FIFO (one byte
7 FIFO_WRITE_FD 0 RW per sample)
Note: This bit is ignored if flicker detection is
disabled. Refer to register 0xFC for FDEN=”0”.
6:0 Reserved 0100001 Reserved, do not change

FIFO_LVL Register (Address 0xFD)

Figure 61:
FIFO_LVL Register

Addr: 0xFD FIFO_LVL

Bit Bit Name Default Access Bit Description

FIFO Buffer Level.
Indicates the number of entries (each are 2 bytes)
7:0 FIFO_LVL 0 R available in the FIFO buffer waiting for readout. The
FIFO RAM is 256 byte, the FIFO_LVL range is from
0 entries to 128 entries.

FDATA Register (Address 0xFE and 0xFF)

Figure 62:
FDATA_L Register

Addr: 0xFE FDATA_L

Bit Bit Name Default Access Bit Description

7:0 FDATA 0 R FIFO Buffer Data

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Register Description

Figure 63:
FDATA_H Register

Addr: 0xFF FDATA_H

Bit Bit Name Default Access Bit Description

15:8 FDATA 0 R FIFO Buffer Data

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Application Information

11 Application Information

11.1 Schematic
Figure 64:
Application Example

VDD
1.8V R1
22R
VDD
C1 C2
4.7uF 1uF
PGND GPIO
GND AS7343
Vbus
1.8V
14CH
R2 R3 R4 Spectral
2k2 2k2 10k
SCL Sensor LDR
SCL
SDA 380-1000nm
SDA
INT
INT

11.2 PCB Pad Layout

Figure 65:
Recommended PCB Pad Layout

(1) All dimensions are in millimeters.

(2) Dimension tolerances are 0.05 mm unless otherwise noted.
(3) This drawing is subject to change without notice.

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Application Information

11.3 Application Optical Requirements

For optimal performance, an achromatic diffuser shall be placed above the device aperture. The
recommended solution is a bulk diffuser that meets the minimum recommended scattering
characteristic shown below. For more details refer to the optical design guide or contact ams OSRAM.

Figure 66:
Diffuser Characteristics

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Package Drawings & Markings

12 Package Drawings & Markings

Figure 67:
OLGA8 Package Outline Drawing

RoHS Green

(1) All dimensions are in millimeters. Angles in degrees.

(2) Dimensioning and tolerance conform to ASME Y14.5M-1994.
(3) This package contains no lead (Pb).
(4) This drawing is subject to change without notice.

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Tape & Reel Information

13 Tape & Reel Information

Figure 68:
AS7343 OLGA8 Tape Dimensions

(1) All dimensions are in millimeters. Angles in degrees.

(2) This drawing is subject to change without notice.

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Tape & Reel Information

Figure 69:
AS7343 OLGA8 Reel Dimensions

(1) All dimensions are in millimeters. Angles in degrees.

(2) This drawing is subject to change without notice.

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Soldering & Storage Information

14 Soldering & Storage Information

The module has been tested and has demonstrated an ability to be reflow soldered to a PCB
substrate. The solder reflow profile describes the expected maximum heat exposure of components
during the solder reflow process of product on a PCB. Temperature is measured on top of component.
The components should be limited to a maximum of three passes through this solder reflow profile.

Figure 70:
Solder Reflow Profile Graph

Figure 71:
Solder Reflow Profile

Parameter Reference Device

Average temperature gradient in preheating 2.5 °C/s

Soak time tsoak 2 to 3 minutes
Time above 217 °C (T1) t1 Max 60 s
Time above 230 °C (T2) t2 Max 50 s
Time above Tpeak – 10 °C (T3) t3 Max 10 s
Peak temperature in reflow Tpeak 260 °C
Temperature gradient in cooling Max −5 °C/s

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Soldering & Storage Information

14.1 Storage Information

14.1.1 Moisture Sensitivity

Optical characteristics of the device can be adversely affected during the soldering process by the
release and vaporization of moisture that has been previously absorbed into the package.

To ensure the package contains the smallest amount of absorbed moisture possible, each device is
baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope
called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping,
handling, and storage before use.

14.1.2 Shelf Life

The calculated shelf life of the device in an unopened moisture barrier bag is 24 months from the date
code on the bag when stored under the following conditions:
● Shelf Life: 24 months
● Ambient Temperature: <40 °C
● Relative Humidity: <90%

Rebaking of the devices will be required if the devices exceed the 24 months shelf life or the Humidity
Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture
region.

14.1.3 Floor Life

The module has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of
devices removed from the moisture barrier bag is 168 hours from the time the bag was opened,
provided that the devices are stored under the following conditions:
● Floor Life: 168 hours
● Ambient Temperature: <30°C
● Relative Humidity: <60%

If the floor life or the temperature/humidity conditions have been exceeded, the devices must be
rebaked prior to solder reflow or dry packing.

14.1.4 Rebaking Instructions

When the shelf life or floor life limits have been exceeded, rebake at 50 °C for 12 hours.

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Revision Information

15 Revision Information

Document Status Product Status Definition

Product Preview Pre-Development Information in this datasheet is based on product ideas in the planning phase
of development. All specifications are design goals without any warranty and
are subject to change without notice

Preliminary Datasheet Pre-Production Information in this datasheet is based on products in the design, validation or
qualification phase of development. The performance and parameters shown
in this document are preliminary without any warranty and are subject to
change without notice

Datasheet Production Information in this datasheet is based on products in ramp-up to full production
or full production which conform to specifications in accordance with the terms
of ams-OSRAM AG standard warranty as given in the General Terms of Trade

Datasheet Discontinued Information in this datasheet is based on products which conform to

(discontinued) specifications in accordance with the terms of ams-OSRAM AG standard
warranty as given in the General Terms of Trade, but these products have
been superseded and should not be used for new designs

Changes from previous version to current revision v4-00 Page

Bit “auto_smux” (REG CFG20, ADDR 0xD6) – cycle 3 channel order updated 44
Increased shelf life to 24 months 55

● Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
● Correction of typographical errors is not explicitly mentioned.

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Legal Information

16 Legal Information
Copyrights & Disclaimer
Copyright ams-OSRAM AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights
reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written
consent of the copyright owner.
Devices sold by ams-OSRAM AG are covered by the warranty and patent indemnification provisions appearing in its General
Terms of Trade. ams-OSRAM AG makes no warranty, express, statutory, implied, or by description regarding the information
set forth herein. ams-OSRAM AG reserves the right to change specifications and prices at any time and without notice.
Therefore, prior to designing this product into a system, it is necessary to check with ams-OSRAM AG for current information.
This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual
environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by ams-OSRAM AG for each application. This product is provided
by ams-OSRAM AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of
merchantability and fitness for a particular purpose are disclaimed.
ams-OSRAM AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury,
property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages,
of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or
liability to recipient or any third party shall arise or flow out of ams-OSRAM AG rendering of technical or other services.

RoHS Compliant & ams Green Statement

RoHS Compliant: The term RoHS compliant means that ams-OSRAM AG products fully comply with current RoHS directives.
Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories
(per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials.
Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free
processes.
ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free
of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material).
Important Information: The information provided in this statement represents ams-OSRAM AG knowledge and belief as of the
date that it is provided. ams-OSRAM AG bases its knowledge and belief on information provided by third parties, and makes no
representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. ams-OSRAM AG has taken and continues to take reasonable steps to provide representative and accurate information
but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams-OSRAM AG
and ams-OSRAM AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

Headquarters Please visit our website at www.ams.com

ams-OSRAM AG Buy our products or get free samples online at www.ams.com/Products
Tobelbader Strasse 30 Technical Support is available at www.ams.com/Technical-Support
8141 Premstaetten Provide feedback about this document at www.ams.com/Document-Feedback
Austria, Europe For sales offices, distributors and representatives go to www.ams.com/Contact
Tel: +43 (0) 3136 500 0 For further information and requests, e-mail us at ams_sales@ams.com

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