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Clock Tree Synthesis

CTS (clock tree synthesis) balances clock skew and minimizes insertion delay by connecting all sequential circuit clock pins to a single source with buffers/inverters. It requires placement data, a CTS spec defining buffers/constraints, and clock/sink information. CTS builds a buffer tree to reduce skew and balance loads across levels. Key steps are clustering pins, fixing drive strengths, reducing insertion delay, balancing loads, and post-conditioning. The goal is to meet skew and timing targets while satisfying DRV constraints like transition, capacitance, and fan-out.

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2K views7 pages

Clock Tree Synthesis

CTS (clock tree synthesis) balances clock skew and minimizes insertion delay by connecting all sequential circuit clock pins to a single source with buffers/inverters. It requires placement data, a CTS spec defining buffers/constraints, and clock/sink information. CTS builds a buffer tree to reduce skew and balance loads across levels. Key steps are clustering pins, fixing drive strengths, reducing insertion delay, balancing loads, and post-conditioning. The goal is to meet skew and timing targets while satisfying DRV constraints like transition, capacitance, and fan-out.

Uploaded by

kaushik vk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CLOCK TREE SYNTHESIS

What is cts ?
CTS is the process of connecting the clocks to all clock pin of sequential circuits by
using inverters/buffers in order to balance the skew and to minimize the insertion delay.
All the clock pins are driven by a single clock source. Clock balancing is important for
meeting all the design constraints.

Checklist before CTS:


● The clock source are identified with the create_clock or create_generated_clock
commands.
● The placement of standard cells and optimization is done. {NOTE: use
check_legality –verbose command to verify that the placement is legalized. If
cells are not legalize the qor is not good and it might have long run time during
CTS stage}
● Power ground nets- pre-routed
● Congestion- acceptable
● Timing – acceptable
● Estimated max tran/cap – no violations
● High fan-out nets such as scan enable, reset are synthesized with buffers.

Inputs required for CTS:


● Placement def
● CTS spec
● Target latency and skew if specify (SDC)
● Buffer or inverters for building the clock tree
● The source of clock and all the sinks where the clock is going to feed (all sink
pins).
● Clock tree DRC (max Tran, max cap, max fan-out, max no. of buffer levels)
● NDR (Nondefault routing) rules (because clock nets are more prone to cross-talk
effect)
● Routing metal layers used for clocks.

What CTS Spec File contains ?


1. Inverters or buffers to be defined which will be used to balance the clock tree.
2. CTS Exceptions (End points of clock tree).
3. Skew group information.
4. Contains target Skew, max target transition and other timing constraints as per clock
tree.
5. Top layer and bottom layer route info. VIA’s information which will be used during
clock route.
6 Clock related info (Generated clocks {Eg. Clock divider, Clock multiplier etc}).
7 NDR Rule definition.

Output of CTS:

1) CTS def
2) Latency and skew report
3) Clock structure report
4) Timing Qor report

CTS target:

1. Skew
2. Insertion delay

CTS goal:

1. Max Tran
2. Max cap
3. Max fan-out
4. A buffer tree is built to balance the loads and minimize skew, there are levels of
buffer in the clock tree between the clock source and clock sinks.

Why do we need buffer tree ?


It is build to reduce skew and balance load

Algorithms used by tool to insert buffer tree


1. H-Tree (most preferred)
2. X-Tree
3. Geometric Matching algorithm (GMA)
4. PI structure
5. Fish bone

Steps to follow in CTS :


There are following steps which need to be performed during the Clock Tree Synthesis:
● Clustering
● DRV Fixing
● Insertion Delay Reduction
● Power Reduction
● Balancing
● Post-Conditioning

1. Clustering
Depending on the geometry locations, the skew groups are being created as per the
description in SPEC file.

2. DRV Fixing
At this stage, DRVs (max_tran, max_cap, max_length, max_fanout) are fixed.

3. Insertion Delay Reduction


At this stage, insertion delay is getting minimized as much as possible, which is one of
our main goals for the Clock Tree Synthesis.

4. Power Reduction
As we know clock is a major power consumer, so we need to analyze and fix it in such a
way that power consumption will be less.

5. Balancing
The main balancing happens at this stage with the help of different clock buffers and
inverters.

6. Post-conditioning
At this stage, again DRVs will be checked and if required then it will be fixed

Checks after CTS:


● In latency report check is skew is minimum? And insertion delay is balanced or
not.
● In qor report check is timing (especially HOLD) met, if not why?
● In utilization report check Standard cell utilization is acceptable or not?
● Check global route congestion?
● Check placement legality of cells.
● Check whether the timing violations are related to the constrained paths or not
like not defining false paths, asynchronous paths, half-cycle paths, multi-cycle
paths in the design.
Clock Tree Power Consumption
As we know that clock network is the heaviest switching element in the design.
Clock tree power depends upon below two factors:
o Latency
o Transition

1. Latency: If latency is less then less buffer in the design. So less power consumption.

2. Transition: If transition is good then less power consumption. Transition is being


blamed always for the losses happening in the design w.r.t the trade-off.

Clock Tree Exceptions


There are following clock tree exceptions:
Stop Pin – No buffer/inverter insertion beyond this point (Don’t touch scenario)
Ignore Pin (Float Pins) – it is like stop pins but delay on the clock pin, macro internal delay.
Exclude Pin –CTS ignores the targets and only fix the clock tree DRC (CTS goals).
Through Pin – by these pin clock tree tracing the continuous against the default
behavior. Clock which are traversed through divider clock sequential elements clock
pins are considered as non-stop pins.

Why clock routes are given more priority than signal nets:
Clock is propagated after placement because the exact location of cells
and modules are needed for the clock propagation for the estimation of
accurate delay, skew and insertion delay. Clock is propagated before
routing of signals nets and clock is the only signal nets switches frequently
which act as sources for dynamic power dissipation.
Analyze the Clock Tree
▪ Report Timing (both Setup and Hold)

▪ If timing not met then check clocks be grouped (balanced together)

▪ Report Insertion Delay & Skew and verify that the targets are achieved

▪ Report DRV targets (Fanout, Capacitance and Transition)

▪ Check the intended Leaf Cell (Clock Sinks) is reached

▪ Check the Clock Tree Exceptions are not in the Clock Tree

▪ Report the pre-existing cells, such as Clock Gating Cells

▪ Do Quality-of-Report (QoR)

▪ Check Clock Tree converges either with itself or with another Clock Tree

▪ Clock Tree has timing relationship with other Clock Trees for inter Clock

Skew balancing

▪ Check Design Rule Constraints

▪ Check Routing Constraints

▪ Report Power and Area

POST CTS OPTIMIZATION


1. We do timing optimization after CTS because real values of metal will be known,
hence timing will change accordingly. Sowe do timing optimization based on
synthesized clock tree.
2. Optimize with useful skew
3. DRV Fixes like tran/cap/Fout violation
4. After DRV fixes again few timing violations emerges to tool again does timing
optimization
STAGES IN CTS

1. CLOCK_OPT -FROM BUILD CLOCK -TO ROUTE_CLOCK

Build_clock —--> During this stage we synthesize and optimize all scenarios
Logical connectivity established.
Route_clock —---> Does detail route of all synthesised clock nets.
Physical connectivity established.
What steps design undergoes during cts ?

I. Check NDR
II. Check clk cell spacing
III. Remove existing cts by removing Buff/inv
IV. CTS initialization
V. Creating DRC
VI. PDC check
VII. Grid cell creation
VIII. Setting target skew and latency
● Clock cell relocation (if needed)
● DRC fixing beyond exceptions
buff/inv added
● Path based global latency and skew opt
● Area recovery
● Final drc fix
● Target latency delay insertion
● Local skew optimization
● All reports

2. Clock_opt -from final_opto -to final_opto


Optimize further timing, logical DRc, area, power , routability etc

Output of CTS:
1. CTS def
2. Latency and skew report
3. Clock structure report
4. Timing Qor report

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