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Interupts in Pic16f87 Microcontroller

This document discusses interrupts in the PIC16F88 microcontroller. It lists 13 different interrupt sources for the chip, including external interrupts, timer interrupts, USART interrupts, and more. It then describes the 5 registers used to control and process interrupts - INTCON, PIE1, PIR1, PIE2, and PIR2. Each register contains bits used to enable or disable interrupts and flags to indicate interrupt occurrences. Interrupts can be enabled or disabled at the primary level for all interrupts or secondary level individually.

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Muhammed Razi M
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25 views12 pages

Interupts in Pic16f87 Microcontroller

This document discusses interrupts in the PIC16F88 microcontroller. It lists 13 different interrupt sources for the chip, including external interrupts, timer interrupts, USART interrupts, and more. It then describes the 5 registers used to control and process interrupts - INTCON, PIE1, PIR1, PIE2, and PIR2. Each register contains bits used to enable or disable interrupts and flags to indicate interrupt occurrences. Interrupts can be enabled or disabled at the primary level for all interrupts or secondary level individually.

Uploaded by

Muhammed Razi M
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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INTERUPTS IN PIC16F88

MICROCONTROLLER

1
Interrupt :- It is a disturbance signal ,
which disturbs the normal processing of a
controller or a processor . Also, it act as a
request from the device which generates it.
Once a processor or a
controller accepts an interrupt it stopes the
current executing program and it will provide
service for the received request . I.e., the
processor will now run the program requested
by the interrupted device. That program we
will call as Interrupt Service Routine (ISR).

Interrupts in pic 16F88 are :-

1. External Interrupt - I.e., INT interrupt, our


controller can receive this interrupt from an
external world with the help of a signal called
INT.
2. Port B change Interrupt – Whenever there is
a change in port RB4 to RB7 this interrupt will
be generated.
2
3. Timer 0 Overflow Interrupt - Whenever the
timer 0 falls off its value from FFH to 00H this
interrupt is generated.
4. Timer 1 Overflow Interrupt - Whenever the
timer 1 falls off its value from FFFFH to
0000H this interrupt is generated.(it is a 16bit
timer).
5. Timer 2 Overflow Interrupt - Whenever the
timer 2 falls off its value from FFH to 00H this
interrupt is generated.
6. USART Interrupt - (universal synchronous /
asynchronous receiver / transmitter) It is a
serial port interrupt. Whenever a transmission
section of the USART successfully transfer the
data. Then, the transmit interrupt is generated
and whenever the receiver section of the
USART successfully receives the data from
some external world receive interrupt will be
generated.
7. Parallel Slave Port (PSP) – When a 8bit
asynchronous bidirectional data transfer
between the controller and external device
occur this interrupt is generated.
8. ADC Interrupt – Whenever ADC
successfully finishes the converts of selected
3
analog signal to digital it will generate an
ADC interrupt.
9. Synchronous Serial Port Interrupt –
Whenever synchronous serial port initial
successful transferring or receiving of data it
will generate this interrupt.
10. CCP 1 Interrupt - Capture / Compare / PWM
1 generates an interrupt whenever the
corresponding process finishes.
11. CCP 2 Interrupt - Capture / Compare / PWM
2 generates an interrupt whenever the
corresponding process finishes.
12. SSP bus Collision – Synchronous Serial Port
bus may collide while transferring the data
between two different devices at that time this
interrupt is generated.
13. EEPROM Write Operation Interrupt –
Whenever we finish a write operation on any
location of that EEPROM this interrupt is
generated.
14. Comparator Interrupt – Whenever the
comparator compares two input values if both
are matched then it will generates an interrupt.

4
All the interrupts in PIC 16f8788 can
either enabled or disabled at the primary level or
at the secondary level. I.e., all interrupts in PIC
16f8788 are maskable.
All Interrupts in PIC can be enabled or
disabled at a time that is called primary level
enabling or disabling of interrupts. We can also
enable or disable the interrupts individually that
we call secondary level enabling or disabling
interrupt.

Registers Used for Interrupts :-


In order to process interrupts in PIC
microcontroller we took the help of 5 internal
registers.
1. Interrupt Control Register (INTCON).
2. Peripheral Interrupt Enable 1(PIE 1).
3. Peripheral Interrupt Register 1(PIR 1).
4. Peripheral Interrupt Enable 2(PIE 2).
5. Peripheral Interrupt Register 2(PIR 2).

5
INTCON Register :-
The INTCON register is a readable and
writable register, which contains various enable
and flag bits for the TMR0 register overflow, RB
port change and external RB0/INT pin interrupt.

GIE: Global Interrupt Enable bit


1-Enables all unmasked interrupts
0-Disables all interrupts
PIE: Peripheral Interrupt Enable bit
1-Enables all unmasked peripheral interrupts
0-Disables all peripheral interrupts
TMR0IE: TMR0 Overflow Interrupt Enable bit
1-Enables the TMR0 interrupt
0-Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

6
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1-TMR0 register has overflowed (must be cleared
in software)
0-TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred
(must be cleared in software)
0 = The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed
state; a mismatch condition will continue to set the
bit. Reading PORTB will end the mismatch
condition and allow the bit to be cleared (must be
cleared in software).
0 = None of the RB7:RB4 pins have changed state

PIE1 Register :-
The PIE1 register contains the individual
enable bits for the peripheral interrupts.

7
PSPIE: Parallel Slave Port Read/Write Interrupt
Enable bit(1)
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
Note: PSPIE is reserved on PIC16F873A/876A
devices; always maintain this bit clear.
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART to receive interrupt
0 = Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART to transmit interrupt
0 = Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable
bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
8
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable
bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

PIR1 Register :-
The PIR1 register contains the individual
flag bits for the peripheral interrupts.

PSPIF: Parallel Slave Port Read/Write Interrupt


Flag bit(1)
1 = A read or a write operation has taken place
0 = No read or write has occurred
9
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt
Flag bit
CCP1IF: CCP1 Interrupt Flag bit
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared
in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in
software)
0 = TMR1 register did not overflow

10
PIE2 Register :-
The PIE2 register contains the individual
enable bits for the CCP2 peripheral interrupt, the
SSP bus collision interrupts, EEPROM writes
operation interrupt, and the comparator interrupt.

CMIE: Comparator Interrupt Enable bit


1 = Enables the comparator interrupt
0 = Disable the comparator interrupt
EEIE: EEPROM Write Operation Interrupt
Enable bit
1 = Enable EEPROM write interrupt
0 = Disable EEPROM write interrupt
BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt
0 = Disable bus collision interrupt
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt

11
PIR2 Register :-
The PIR2 register contains the flag bits for
the CCP2 interrupt, the SSP bus collision interrupt,
EEPROM write operation interrupt and the
comparator interrupt.

CMIF: Comparator Interrupt Flag bit


1 = The comparator input has changed (must be
cleared in software)
0 = The comparator input has not changed
EEIF: EEPROM Write Operation Interrupt Flag
bit
1 = The write operation completed (must be
cleared in software)
0 = The write operation is not complete or has not
been started
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP when
configured for I2C Master mode
0 = No bus collision has occurred
CCP2IF: CCP2 Interrupt Flag bit
12

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