DEPARTMENT OF ELECTRONICS

AND
COMMUNICATION ENGINEERING

III SEMESTER LAB MANUAL

(2022 Scheme)
Digital System Design Using
Verilog BEC302
(Integrated Professional Core Course)

Prepared By:

Mr. Chetan B V, Assistant Professor, ECE

Mr. Santhosha B G, Assistant Professor, ECE

Lab Instructor:
Mr. Rakesh A, Technical Staff, ECE

Approved by
Dr. Praveen J
IQAC Director, Professor and Head, ECE
 Contents
Sl Page
Topic/Title
No. No.
1 Vision and Mission – Institute and Department 3
2 PEOs, PSOs and POs 4-5
3 University Syllabus of the Course 6-9
4 Course Objectives, Outcomes and CO-PO mapping 9-10
5 List of experiments 11
6 Lab programs/experiments 12-54

2
 Vision and Mission of the Institute

Vision
To develop technologically competent, humane and socially responsible
engineers and managers to meet the ever-growing challenges of the Global
Environment.

Mission
• To provide quality technical and management education by applying best
practices in teaching, learning and with the state-of-the-art infrastructural
facilities.
• To mould engineers and managers with appropriate pedagogy to develop
leadership qualities and skills by imbibing professional ethics to make them
industry ready.
• To develop student-centric institution which evolves and fosters the talents of
budding engineers, managers and entrepreneurs and prepare them to make a
positive contribution to the society.
• To promote Research and Consultancy through collaboration with industries
and Government Organizations.

Vision and Mission of the Department

Vision
To excel in creating technically competent and socially responsible Electronics &
Communication Engineers capable of contributing to the emerging technology.

Mission
M1: Imparting effective technical education to excel in Electronics &
Communication Engineering.
M2: Adapting appropriate pedagogy to imbibe professionalism in students.
M3: Inculcating Research culture and there by bridging the gap between
Academia and Industry.

3
 Program Educational Objectives (PEOs)

The Department of Electronics & Communication Engineering is committed to

educate and train the students to be effective and efficient Electronics &
Communication Engineers with the following specific objectives.
PEO1: To deliver Engineering Skills and Knowledge by integrating basic
engineering concepts with core Electronics and Communication Engineering to
solve the problems of the society.
PEO2: To exhibit technical competency by developing solutions in diverse areas
of Electronics and Communication Engineering.
PEO3: To be receptive to emerging technologies and attain professional
competency through pursuing Research and life-long learning.

Program Specific Outcomes (PSOs)

Graduates of Electronics & Communication Engineering are able to

PSO1: Design Analog and Digital Systems using emerging Technologies.
PSO2: Build different models by applying Technical knowledge in
Communication, Networking, Signal Processing, VLSI and Embedded Systems
along with Programming and Simulation tools for a variety of applications.

Program Outcomes (POs)

Graduates of Electronics & Communication Engineering by the time of

graduation will demonstrate:
PO1: Engineering knowledge: Apply the knowledge of mathematics, science,
engineering fundamentals, and an engineering specialization to the solution of
complex engineering problems.
PO2: Problem analysis: Identify, formulate, research literature, and analyze
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences.
PO3: Design/development of solutions: Design solutions for complex
engineering problems and design system components or processes that meet
the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.
4
PO4: Conduct investigations of complex problems: Use research-based
knowledge and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid
conclusions.
PO5: Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and
modeling to complex engineering activities with an understanding of the
limitations.
PO6: The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
PO7: Environment and sustainability: Understand the impact of the
professional engineering solutions in societal and environmental contexts, and
demonstrate the knowledge of, and need for sustainable development.
PO8: Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
PO9: Individual and team work: Function effectively as an individual, and as a
member or leader in diverse teams, and in multidisciplinary settings.
PO10: Communication: Communicate effectively on complex engineering
activities with the engineering community and with society at large, such as,
being able to comprehend and write effective reports and design documentation,
make effective presentations, and give and receive clear instructions.
PO11: Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply these to
one’s own work, as a member and leader in a team, to manage projects and in
multidisciplinary environments.
PO12: Life-long learning: Recognize the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest context of
technological change.

5
6
7
8
Course objectives:
This course will enable students to:
• Impart the concepts of simplifying Boolean expression using K-map techniques and Quine-
McCluskey minimization techniques.
• Impart the concepts of designing and analyzing combinational logic circuits.
• Impart design methods and analysis of sequential logic circuits.
• Impart the concepts of Verilog HDL-data flow and behavioral models for the design of digital
systems.

Course outcomes:
After studying this course, student will be able to

COs STATEMENTS
Simplify Boolean functions using K-map and Quine-McCluskey minimization
C202.1
technique.
C202.2 Analyse and design for combinational logic circuits.
Analyse the concepts of Flip-Flops and to design the synchronous sequential
C202.3
circuits using Flip-Flops.
C202.4 Model Combinational circuits and sequential circuits using Verilog descriptions

9
CO-PO mapping
Program
Course
Program Outcomes Specific
Outcomes
Outcomes

COs PO-1 PO-2 PO-3 PO-4 PO-5 PO-6 PO-7 PO-8 PO-9 PO-10 PO-11 PO-12 PSO-1 PSO-2

C202.1 3 2 2 - - - - - - - - 2 2 -

C202.2 2 2 2 - - - - - - - - 2 2 -

C202.3 3 2 2 - - - - - - - - 2 2 -

C202.4 2 2 2 - 2 - - - - - - 2 - 2

Sum 10 8 8 - 2 - - - - - - 8 6 2

Average 2.5 2 2 2 2 2 2

10
 List of Lab Experiments

Sl. Page
Experiment
No. No
To simplify the given Boolean expressions and realize using
1 12
Verilog program.
To realize Adder/Subtractor (Full/half) circuits using Verilog
2 14
data flow description.
3 To realize 4-bit ALU using Verilog program 17
To realize the following Code converters using Verilog Behavioral
description
4 20
a) Gray to binary and vice versa b) Binary to excess3 and vice
versa
To realize using Verilog Behavioral description: 8:1 mux, 8:3
5 25
encoder, Priority encoder
To realize using Verilog Behavioral description: 1:8 Demux, 3:8
6 33
decoder, 2-bit Comparator
To realize using Verilog Behavioral description:
7 39
Flip-flops: a) JK type b) SR type c) T type and d) D type
To realize Counters - up/down (BCD and binary) using Verilog
8 47
Behavioral description
Verilog Program to interface a Stepper motor to the FPGA/CPLD
9 50
and rotate the motor in the specified direction (by N steps).
Verilog programs to interface Switches and LEDs to the
10 54
FPGA/CPLD and demonstrate its working.

11
1. To simplify the given Boolean expressions and realize using Verilog
program.
Design Block:
module exp3(
input a,
input b,
input c,
output y
);
assign y= (a & b) | (b & c);
endmodule

Stimulus Block:
module exp3_tb;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
exp3 uut (
.a(a),
.b(b),
.c(c),
.y(y)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
#100;

12
 a = 0;
b = 1;
c = 0;
// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 1;
c = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
$finish;
end

endmodule

Result:

13
2. To realize Adder/Subtractor (Full/half) circuits using Verilog data flow
description
Half Adder
module ha1(
input a,b,
output s,c
);
assign s = a ^ b;
assign c = a & b;
endmodule

Stimulus Block
module ha1_tb;
// Inputs
reg a;
reg b;
// Outputs
wire s;
wire c;
// Instantiate the Unit Under Test (UUT)
ha1 uut (
.a(a),
.b(b),
.s(s),
.c(c)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100;
a = 0;
b = 1;

14
 // Wait 100 ns for global reset to finish
#100;
a = 1;
b = 0;
// Wait 100 ns for global reset to finish
#100;
a = 1;
b = 1;
// Wait 100 ns for global reset to finish
#100;
$finish;
end
endmodule

RESULT:

Full Adder
module fa(
input a,
input b,
input cin,
output sum,
output cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule

15
RESULT:

Half Subtractor
RESULT:

Full Subtractor
RESULT:

16
3. To realize 4-bit ALU using Verilog program
Block Diagram

Function Table

Inputs Output
Action
enable opcode result ack
0 xxx 3’bZ 0 High Impedance with ack = 0
1 000 a+b 1 Addition
1 001 a-b 1 Subtraction
1 010 a+1 1 Increment accumulator by 1
1 011 a-1 1 Decrement accumulator by 1
1 100 a 1 True value of ‘a’
1 101 ~a 1 Complement of ‘a’
1 110 a|b 1 a OR b (Bitwise)
1 111 a&b 1 a AND b (Bitwise)
1 Invalid 3’bZ 0 High Impedance with ack = 0

Design Block:

module alu(
input [3:0] a,
input [3:0] b,
input enable,
input [2:0] opcode,
output reg [4:0] result,
output reg ack
);
always @*
begin
ack = 0;
if (enable)
case (opcode)
0: begin result = a + b; ack = 1; end

17
 1: begin result = a - b; ack = 1; end
2: begin result = a + 1; ack = 1; end
3: begin result = a - 1; ack = 1; end
4: begin result = a ; ack = 1; end
5: begin result = ~ a ; ack = 1; end
6: begin result = a | b ; ack = 1; end
7: begin result = a & b ; ack = 1; end
default: result = 3'bz;
endcase
else
result = 3'bz;
end
endmodule

Stimulus Block:
module alu_3_tb;
reg [3:0] a, b;
reg enable;
reg [2:0] opcode;
wire [4:0] result;
wire ack;
// Instantiate the Unit Under Test (UUT)
alu uut (
.a(a),
.b(b),
.enable(enable),
.opcode(opcode),
.result(result),
.ack(ack)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;

18
 enable = 0;
opcode = 0;
#100;
a = 4;
b = 3;
enable = 1;
opcode = 0;
#100;
opcode = 1;
#100;
opcode = 2;
#100;
opcode = 3;
#100;
opcode = 4;
#100;
opcode = 5;
#100;
opcode = 6;
#100;
opcode = 7;
#100;
opcode = 3'bxxx;
#100;
$finish;
end
endmodule

RESULT:

19
4. To realize the following Code converters using Verilog Behavioral
description
a) Gray to binary and vice versa
module binarytogray (b3, b2, b1, b0, g3, g2, g1, g0);
input b3, b2, b1, b0;
output g3, g2, g1, g0;
reg g3, g2, g1, g0;
always @(b3, b2, b1, b0)
begin
g0=b1^b0;
g1=b2^b1;
g2=b3^b2;
g3=b3;
end
endmodule

module graytobinary (g3, g2, g1, g0, b3, b2, b1, b0);
input g3, g2, g1, g0;
output b3, b2, b1,b0;
reg b3, b2, b1,b0;
always @(g3, g2, g1, g0)
begin
b3=g3;
b2=b3^g2;
b1=b2^g1;
b0=b1^g0;
end
endmodule

b) Binary to excess3
module bin_to_excess3(
input [3:0] b, output reg [3:0] ex3);
always@*
ex3 = b + 3;

20
 endmodule

Stimulus Block
module bin_to_excess3_tb;
// Inputs
reg [3:0] b;
// Outputs
wire [3:0] ex3;
// Instantiate the Unit Under Test (UUT)
bin_to_excess3 uut (
.b(b),
.ex3(ex3)
);
initial begin
b = 0;
#100;
b = 1;
#100;
b = 2;
#100;
b = 3;
#100
b = 4;
#100;
b = 5;
#100;
b = 6;
#100;
b = 7;
#100;
b = 8;
#100;
b = 9;
#100;

21
 b = 10;
#100;
b = 11;
#100;
b = 12;
#100;
$finish;
end
endmodule

Excess3 to Binary
module ex3tobin(
input [3:0] e,
output reg[3:0] b
);
always@*
b = e - 3;
endmodule

Stimulus Block
module exc3tobin_tb;
// Inputs
reg [3:0] e;
// Outputs
wire [3:0] b;
// Instantiate the Unit Under Test (UUT)
ex3tobin uut (
.e(e),
.b(b)
);
initial begin
e = 3;
#100;
e = 4;

22
 #100;
e = 5;
#100;
e = 6;
#100;
e = 7;
#100;
e = 8;
#100;
e = 9;
#100;
e = 10;
#100;
e = 11;
#100;
e = 12;
#100;
e = 13;
#100;
e = 14;
#100;
e = 15;
#100;
$finish;
end
endmodule

RESULT:
Binary to Gray

23
Gray to Binary

Binary to excess3

Excess3 to Binary

24
5. To realize using Verilog Behavioral description: 8:1 mux, 8:3 encoder,
Priority encoder
a. 8 to 1 Multiplexer using CASE statement
Block Diagram

Truth Table

Design Block:
module mux_case (
input [7:0] i,
input e,
input [2:0] sel,
output reg y
);
always @*
if (e)
y = 1'bz;
else
case (sel)
0 : y = i[0];
1 : y = i[1];

25
 2 : y = i[2];
3 : y = i[3];
4 : y = i[4];
5 : y = i[5];
6 : y = i[6];
7 : y = i[7];
default : y = 1'bz;
endcase
endmodule

Stimulus Block:
module mux_case_tb;
// Inputs
reg [7:0] i;
reg [2:0] sel;
reg e;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux_case uut (.i(i), .sel(sel), .e(e), .y(y));
initial
begin
i = 8'b10101010;
e = 1;
sel = 0;
#100;
e = 0;
sel = 0;
#100;
sel = 1;
#100;
sel = 2;
#100;
sel = 3;

26
 #100;
sel = 4;
#100;
sel = 5;
#100;
sel = 6;
#100;
sel = 7;
#100;
sel = 3'bz;
#100;
$finish;
end
endmodule

RESULTS:

b. 8 to 3 Encoder without priority

Block Diagram:

Truth table:

27
Design Block:
module encoder ( input [7:0] a, input e, output reg [2:0] y );
always @*
if (e)
y = 3'bzzz;
else
case (a)
1: y = 0;
2: y = 1;
4: y = 2;
8: y = 3;
16: y = 4;
32: y = 5;
64: y = 6;
128: y = 7;
default: y = 3'bzzz;
endcase
endmodule

Stimulus Block:
module encoder_tb;
// Inputs
reg [7:0] a;
reg e;
// Outputs
wire [2:0] y;
// Instantiate the Unit Under Test (UUT)
encoder uut (.a(a), .e(e), .y(y) );
initial begin
a = 0;
e = 1;
#50;
a = 1;
e = 0;

28
 #50;
a = 2;
#50;
a = 4;
#50;
a = 8;
#50;
a = 16;
#50;
a = 32;
#50;
a = 64;
#50;
a = 128;
#50;
a = 120;
#50;
$finish;
end
endmodule

RESULTS:

c. 8 to 3 Encoder with Priority

Block Diagram:

29
Truth table:

Design Block:
module encoder_with_priority(
input [7:0] a,
input e,
output reg [2:0] y
);
always @*
if (e)
y = 3'bz;
else
if (a[7])
y = 7;
else if (a[6])
y = 6;
else if (a[5])
y = 5;
else if (a[4])
y = 4;
else if (a[3])
y = 3;
else if (a[2])
y = 2;
else if (a[1])
y = 1;
else if (a[0])
30
 y = 0;
else
y = 3'bz;
endmodule

Stimulus Block:
module encoder_with_priority_tb;
// Inputs
reg [7:0] a;
reg e;
// Outputs
wire [2:0] y;
// Instantiate the Unit Under Test (UUT)
encoder_with_priority uut (.a(a), .e(e), .y(y) );
initial begin
a = 0;
e = 1;
#100;
e = 0;
a = 128;
#100;
a = 64;
#100;
a = 32;
#100;
a = 16;
#100;
a = 8;
#100;
a = 4;
#100;
a = 2;
#100;
a = 1;

31
 #100;
a = 127;
#100;
a = 129;
#100;
a = 12;
#100;
a = 120;
#100;
a = 28;
#100;
a = 0;
#100;
$finish;
end
endmodule

RESULTS:

32
6. To realize using Verilog Behavioral description: 1:8 Demux, 3:8 decoder,
2-bit Comparator
1) 1:8 Demux

module demux_1_8(y,s,a);
output reg [7:0]y;
input [2:0]s;
input a;
always @*
begin
y=0;
case(s)
3'd0: y[0]=a;
3'd1: y[1]=a;
3'd2: y[2]=a;
3'd3: y[3]=a;
3'd4: y[4]=a;
3'd5: y[5]=a;
3'd6: y[6]=a;
3'd7: y[7]=a;
endcase
end
endmodule

33
Stimulus Block
module test_demux;
reg [2:0]s;
reg a;
wire [7:0]y;
demux_1_8 mydemux(.y(y), .a(a), .s(s));
initial begin
a=1;
s=3'd5;
#30;
a=0;
s=3'd1;
#30;
a=1;
s=3'd1;
#30;
s=3'd6;
#30;
s=3'd0;
#30;
$finish;
end
endmodule

RESULTS

2) 3:8 Decoder
Design Block:
module decoder3_to_8( in,out, en);
input [2:0] in;
34
 input en;
output [7:0] out;
reg [7:0] out;
always @( in or en)
begin
if (en)
begin
out=8'd0;
case (in)
3'b000: out[0]=1'b1;
3'b001: out[1]=1'b1;
3'b010: out[2]=1'b1;
3'b011: out[3]=1'b1;
3'b100: out[4]=1'b1;
3'b101: out[5]=1'b1;
3'b110: out[6]=1'b1;
3'b111: out[7]=1'b1;
default: out=8'd0;
endcase
end
else
out=8'd0;
end
endmodule

Stimulus Block
module decoder_tb;
wire [7:0] out;
reg en;
reg [2:0] in;
integer i;
decoder3_to_8 dut (in,out,en);
initial begin
$monitor( "en=%b, in=%d, out=%b ", en, in, out);

35
 for ( i=0; i<16; i=i+1)
begin
{en,in} = i;
#5;
end
end
endmodule

RESULTS:

3) 2-bit Comparator
Design Block:
module comp2(
input [1:0] a, b,
output reg equal, greater1, lower
);
always @ (a or b)
begin
if (a < b)
begin
greater1 = 0; equal = 0; lower = 1;
end
else if (a == b)
begin
greater1 = 0; equal = 1; lower = 0;
end
else
begin

36
 greater1 = 1; equal = 0; lower = 0;
end
end
endmodule

Stimulus Block
module comp2_tb;
// Inputs
reg [1:0] a;
reg [1:0] b;
// Outputs
wire equal;
wire greater1;
wire lower;
// Instantiate the Unit Under Test (UUT)
comp2 uut (
.a(a),
.b(b),
.equal(equal),
.greater1(greater1),
.lower(lower)
);
initial begin
// Initialize Inputs
a = 0; b = 0;
#100;
#100; a = 2; b = 1;
#100; a = 1; b = 2;
#100; a = 3; b = 3;
end
initial begin
#100
$monitor("a = %b, b = %b, lower = %b, greater1 = %b, equal = %b",
a, b, lower, greater1, equal);

37
 end
endmodule

RESULTS:

38
7. To realize using Verilog Behavioral description: Flip-flops: a) SR type b)
JK type c) T type and d) D type

a. S R Flip Flop
Block diagram:

Truth Table:

Design Block:
module sr_ff (input [1:0] sr,
input clk, rst ,
output reg q, qb
);
always @ ( posedge clk)
if (rst)
begin
q = 1'b0; // reset
qb = ~q;
end
else
begin
case (sr)
39
 0 : q = q; // no change
1 : q = 0; // reset
2 : q = 1; // set
3 : q = 1'bX; // invalid output
endcase
qb = ~q;
end
endmodule

Stimulus Block:
module sr_ff_tb;
// Inputs
reg [1:0] sr;
reg clk;
reg rst;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
sr_ff uut (
.sr(sr),
.clk(clk),
.rst(rst),
.q(q),
.qb(qb)
);
// Generation of clk signal
initial clk = 1'b0;
always #5 clk = ~clk;
initial begin
// Initialize Inputs
rst = 1;
sr = 0;
#50;

40
 rst = 0;
sr = 0;
#50;
sr = 1;
#50;
sr = 2;
#50;
sr = 3;
#50;
$finish;
end
endmodule

RESULTS:

b. J K Flip Flop

Block diagram:

Truth Table:

41
Design Block:
module jk_ff (input [1:0] jk,
input clk, rst,
output reg q, qb
);
always @ ( posedge clk)
if (rst)
begin
q = 1'b0; // reset
qb = ~q;
end
else
begin
case (jk)
0 : q = q; // no change
1 : q = 0; // reset
2 : q = 1; // set
3 : q = ~q; // toggle
endcase
qb = ~q;
end
endmodule

Stimulus Block:
module jk_ff_tb;
// Inputs
reg [1:0] jk;
reg clk;
reg rst;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
jk_ff uut (

42
 .jk (jk),
.clk (clk),
.rst (rst),
.q (q),
.qb (qb)
);
// Generation of clk signal
initial clk = 1'b0;
always #5 clk = ~clk;
initial begin
// Initialize Inputs
rst = 1;
jk = 0;
#50;
rst = 0;
jk = 0;
#50;
jk = 1;
#50;
jk = 2;
#50;
jk = 3;
#50;
$finish;
end
endmodule

RESULTS:

43
c. D Flip Flop
Block diagram:

Truth Table:

Design Block:
module d_ff ( input d, input clk, input rst,
output reg q, qb);
always @ ( posedge clk)
if (rst)
begin
q = 0;
qb = ~q;
end
else
begin
q = d;
qb= ~q;
end
endmodule
Stimulus Block:
module d_ff_tb;
// Inputs
reg d;
reg clk;

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 reg rst;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
d_ff uut (.d (d),
.clk (clk),
.rst (rst),
.q (q),
.qb (qb) );
//Generation of clk signal
initial clk = 0;
always #5 clk = ~clk;
initial begin
rst = 1;
d = 0;
#50;
rst = 0;
d = 0;
#50; d = 1;
#50;
$finish;
end
endmodule

RESULTS:

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8. To realize Counters - up/down (BCD and binary) using Verilog Behavioral
description
i) Binary Up-Down Counter
Block Diagram:

dir
rst binary_up_down q [3:0]
clk

Design Block:
module binary_up_down(
input clk,
input rst,
input dir,
output reg [3:0] q
);
initial
q = 0;
always @ (posedge clk)
if (rst)
q = 0;
else
if (dir)
q = q + 1;
else
q = q - 1;
endmodule

Stimulus Block:
module binary_up_down_tb;
// Inputs
reg clk;
reg rst;
reg dir;

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 // Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
binary_up_down uut (
.clk(clk),
.rst(rst),
.dir(dir),
.q(q)
);
initial
begin
rst = 1;
dir = 1;
#100;
rst = 0;
#300;
dir = 0;
#250;
$finish;
end
initial
clk = 0;
always
#10 clk = ~clk;
endmodule

Results:

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ii) BCD Up-Down Counter
Block Diagram:

dir
rst bcd_up_down q [3:0]
clk

Design Block:
module bcd_up_down(
input clk,
input rst,
input dir,
output reg [3:0] q
);
initial
q = 0;
always @ (posedge clk)
if (rst)
q = 0;
else
if (dir)
q = (q==9) ? 0 : q + 1;
else
q = (q == 0)? 9 : q - 1;
endmodule

Stimulus Block:
module bcd_up_down_tb;
// Inputs
reg clk;
reg rst;
reg dir;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)

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 bcd_up_down uut (
.clk(clk),
.rst(rst),
.dir(dir),
.q(q)
);
initial
begin
rst = 1;
dir = 1;
#100;
rst = 0;
#300;
dir = 0;
#250;
$finish;
end

initial
clk = 0;

always
#10 clk = ~ clk;
endmodule

Results:

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9 Verilog Program to interface a Stepper motor to the FPGA/CPLD and
rotate the motor in the specified direction (by N steps).
//Stepper rotation in clkwise(dir = 1) and anticlockwise direction(dir = 0)
Block Diagram:

B
STEPPER
CPLD MOTOR STEPPER
C MOTOR
INTERFACE

Fig. Connections of CPLD with Stepper Motor Interface and Stepper Motor

Fig. Cross section of a typical Stepper Motor

Stepper Motor Excitation Sequences:

1. Full Step Excitation
a. Single phase excitation
b. Two phase excitation
2. Half Step Excitation

Table. Single Phase Full Step Excitation (1.80 Rotation per step)
Clockwise rotation Anti-Clockwise rotation
Steps Sequence Steps Sequence
D C B A D C B A
1 0 0 0 1 1 1 0 0 0
2 0 0 1 0 2 0 1 0 0
3 0 1 0 0 3 0 0 1 0
4 1 0 0 0 4 0 0 0 1

50
 Table. Two Phase Full Step Excitation (1.80 Rotation per step)
Clockwise rotation Anti-Clockwise rotation
Steps Sequence Steps Sequence
D C B A D C B A
1 0 0 1 1 1 1 0 0 1
2 0 1 1 0 2 1 1 0 0
3 1 1 0 0 3 0 1 1 0
4 1 0 0 1 4 0 0 1 1

Table. Half Step Excitation (0.90 Rotation per step)

Clockwise rotation Anti-Clockwise rotation
Steps Sequence Steps Sequence
D C B A D C B A
1 0 0 1 1 1 1 0 0 1
2 0 0 0 1 2 1 0 0 0
3 0 1 1 0 3 0 1 0 0
4 0 0 1 0 4 0 1 0 0
5 1 1 0 0 5 0 1 1 0
6 0 1 0 0 6 0 0 1 0
7 1 0 0 1 7 0 0 1 1
8 1 0 0 0 8 0 0 0 1

Calculation of the steps for required rotation angle:

Full step excitation
Step angle = 1.80
No. of steps = Required rotation angle in Degrees / Step angle
Eg: 1. For 3600 rotation,
No. of steps = 360 / 1.8 = 200
2. For 1800 rotation,
No. of steps = 180 / 1.8 = 100

a. Stepper Motor Continuous Rotation in Clockwise and Anticlockwise

Direction.
module stepper_motor_clk_aclk(
input clk,dir,
output reg [3:0] d_out
):

51
 reg [15:0] clk_div:
always @ (posedge clk)
clk_div = clk_div+ l:
always @ (posedge clk_div [15])
begin
if (dir == l'bl)
case (d_out)
4'b0111: d_out = 4'b1011;
4'b1011 : d_out = 4'b1101:
4'b1101 : d_out = 4'b1110:
4'b1110 : d_out = 4'b0111;
default : d_out =4'b0111:
endcase
else if (dir == 1'b0)
case (d_out)
4'b1110 : d_out = 4'b1101:
4'b1101 : d_out =4'b1011:
4'b1011 : d_out = 4'b0111:
4'b0111 : d_out = 4'b1110;
default :d_out = 4'bl110:
endcase
end
endmodule

b. Stepper Motor Rotation in 180o Clockwise and 360o Anticlockwise

Direction.

module stepper_motor_180clk_360aclk (

input clk,

output reg [3:0] d_out

);

reg [15:0] clk_div ;

integer count = 0;

52
always @ (posedge clk)

clk_div = clk_div + 1;

always @ (posedge clk_div [15])

begin

if (count < 100)

case (d_out)

4'b0111 : d_out = 4'b1011;

4'b1011 : d_out = 4'b1101;

4'b1101 : d_out = 4'b1110;

4'b1110 : d_out = 4'b0111;

default : d_out = 4'b0111;

endcase

else if (count < 300)

case (d_out)

4'b1110 : d_out = 4'b1101;

4'b1101 : d_out = 4'b1011;

4'b1011 : d_out = 4'b0111;

4'b0111 : d_out = 4'b1110;

default : d_out = 4'b1110;

endcase

count = count + 1;

end

endmodule

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10. Verilog programs to interface Switches and LEDs to the
FPGA/CPLD and demonstrate its working.
Block Diagram:

Switch LED
(Push
Button)

Design Block:

module switch_led_interface ( output led, input switch);

assign led = ~ switch;
endmodule

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