MCP6271/1R/2/3/4/5

170 µA, 2 MHz Rail-to-Rail Op Amp

Features Description
• Gain Bandwidth Product: 2 MHz (typical) The Microchip Technology Inc. MCP6271/1R/2/3/4/5
• Supply Current: IQ = 170 µA (typical) family of operational amplifiers (op amps) provide wide
• Supply Voltage: 2.0V to 6.0V bandwidth for the current. This family has a 2 MHz
• Rail-to-Rail Input/Output Gain Bandwidth Product (GBWP) and a 65° Phase
Margin. This family also operates from a single supply
• Extended Temperature Range: –40°C to +125°C
voltage as low as 2.0V, while drawing 170 µA (typical)
• Available in Single, Dual and Quad Packages quiescent current. The MCP6271/1R/2/3/4/5 supports
• Parts with Chip Select (CS) rail-to-rail input and output swing, with a Common-
- Single (MCP6273) mode input voltage range of VDD + 300 mV to VSS –
- Dual (MCP6275) 300 mV. This family of op amps is designed with Micro-
chip’s advanced CMOS process.
Applications The MCP6275 has a Chip Select input (CS) for dual op
• Automotive amps in an 8-pin package and is manufactured by
• Portable Equipment cascading two op amps (the output of op amp A
• Photodiode Amplifier connected to the non-inverting input of op amp B). The
CS input puts the device in low power mode.
• Analog Filters
• Notebooks and PDAs The MCP6271/1R/2/3/4/5 family operates over the
Extended Temperature Range of –40°C to +125°C,
• Battery Powered Systems
with a power supply range of 2.0V to 6.0V.
Available Tools
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Circuit Designer & Simulator
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes

Package Types
MCP6271 MCP6271 MCP6271R MCP6272
PDIP, SOIC, MSOP SOT-23-5 SOT-23-5 PDIP, SOIC, MSOP
NC 1 8 NC VOUT 1 5 VDD VOUT 1 5 VSS VOUTA 1 8 VDD
VIN– 2 – 7 VDD VSS 2 VDD 2 VINA– 2 –+ 7 VOUTB
+ – + –
VIN+ 3 + 6 VOUT VIN+ 3 4 VIN– VIN+ 3 4 VIN– VINA+ 3 –+ 6 VINB–
VSS 4 5 NC VSS 4 5 VINB+

MCP6273 MCP6273 MCP6274 MCP6275

PDIP, SOIC, MSOP SOT-23-6 PDIP, SOIC, TSSOP PDIP, SOIC, MSOP
NC 1 8 CS VOUT 1 6 VDD VOUTA 1 14 VOUTD VOUTA/VINB+ 1 8 VDD
VIN– 2 – 7 VDD VSS 2 +– 5 CS VINA– 2 – + + – 13 VIND– VINA– 2 –+ 7 VOUTB
VIN+ 3 + 6 VOUT VIN+ 3 4 VIN– VINA+ 3 12 VIND+ VINA+ 3 +– 6 VINB–
VSS 4 5 NC VDD 4 11 VSS VSS 4 5 CS
VINB+ 5 10 VINC+
VINB– 6 –+ +– 9 VINC–
VOUTB 7 8 VOUTC

 2019 Microchip Technology Inc. DS20001810G-page 1

MCP6271/1R/2/3/4/5
NOTES:

DS20001810G-page 2  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
1.0 ELECTRICAL † Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
CHARACTERISTICS device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
Absolute Maximum Ratings † indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
VDD – VSS ........................................................................7.0V periods may affect device reliability.
Current at Input Pins ....................................................±2 mA †† See Section 4.1.2 “Input Voltage and Current Limits”.
Analog Inputs (VIN+ and VIN–) †† .. VSS – 1.0V to VDD + 1.0V
All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ................................... –65°C to +150°C
Junction Temperature (TJ) .........................................+150°C
ESD Protection On All Pins (HBM/MM)   4 kV/400V

DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT  VDD/2, VL = VDD/2, RL = 10 kto VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Input Offset (Note 1)
Input Offset Voltage VOS –3.0 — +3.0 mV VCM = VSS
Input Offset Voltage VOS –5.0 — +5.0 mV TA = –40°C to +125°C, VCM = VSS
(Extended Temperature)
Input Offset Temperature Drift VOS/TA — ±1.7 — µV/°C TA = –40°C to +125°C, VCM = VSS
Power Supply Rejection Ratio PSRR 70 90 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current IB — ±1.0 — pA Note 2
At Temperature IB — 50 200 pA TA= +85°C (Note 2)
At Temperature IB — 2 5 nA TA= +125°C (Note 2)
Input Offset Current IOS — ±1.0 — pA Note 3
13
Common-mode Input Impedance ZCM — 10 ||6 — ||pF Note 3
Differential Input Impedance ZDIFF — 1013||3 — ||pF Note 3
Common-mode (Note 4)
Common-mode Input Voltage Range VCMR VSS  0.15 — VDD + 0.15 V VDD = 2.0V (Note 5)
VCMR VSS  0.30 — VDD + 0.30 V VDD = 5.5V (Note 5)
Common-mode Rejection Ratio CMRR 70 85 — dB VCM = –0.3V to 2.5V, VDD = 5V
(Note 6)
Common-mode Rejection Ratio CMRR 65 80 — dB VCM = –0.3V to 5.3V, VDD = 5V
(Note 6)
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 90 110 — dB VOUT = 0.2V to VDD – 0.2V,
VCM = VSS (Note 1)
Note 1: The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6275’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6275’s VOUTA/VINB+ pin.
4: The MCP6275’s VINB– pin (op amp B) has a Common-mode input voltage range (VCMR) of VSS + 100 mV to
VDD – 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s VOUTA/VINB+ pin (op amp B)
has a voltage range specified by VOH and VOL.
5: Set by design and characterization.
6: Does not apply to op amp B of the MCP6275.
7: All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 2.0V and 5.5V.

 2019 Microchip Technology Inc. DS20001810G-page 3

MCP6271/1R/2/3/4/5
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT  VDD/2, VL = VDD/2, RL = 10 kto VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD  15 mV 0.5V input overdrive (Note 4)
Output Short Circuit Current ISC — ±25 — mA
Power Supply
Supply Voltage VDD 2.0 — 6.0 V
Quiescent Current per Amplifier IQ 100 170 240 µA IO = 0
Note 1: The MCP6275’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6275’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6275’s VOUTA/VINB+ pin.
4: The MCP6275’s VINB– pin (op amp B) has a Common-mode input voltage range (VCMR) of VSS + 100 mV to
VDD – 100 mV. CMRR is not measured for op amp B of the MCP6275. The MCP6275’s VOUTA/VINB+ pin (op amp B)
has a voltage range specified by VOH and VOL.
5: Set by design and characterization.
6: Does not apply to op amp B of the MCP6275.
7: All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 2.0V and 5.5V.

AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT  VDD/2, VL = VDD/2, RL = 10 kto VL, CL = 60 pF and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 2.0 — MHz
Phase Margin PM — 65 — ° G = +1 V/V
Slew Rate SR — 0.9 — V/µs
Noise
Input Noise Voltage Eni — 4.6 — µVP-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni — 20 — nV/Hz f = 1 kHz
Input Noise Current Density ini — 3 — fA/Hz f = 1 kHz

CS VIL VIH

tOFF
tON

High-Z High-Z
VOUT

-0.7 µA -0.7 µA
(typical) -170 µA (typical)
ISS (typical)

0.7 µA 0.7 µA
(typical) 10 nA (typical)
(typical)
ICS

FIGURE 1-1: Timing Diagram for the Chip

Select (CS) pin on the MCP6273 and MCP6275.

DS20001810G-page 4  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.0V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA –40 — +125 °C
Operating Temperature Range TA –40 — +125 °C Note
Storage Temperature Range TA –65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 JA — 256 — °C/W
Thermal Resistance, 6L-SOT-23 JA — 230 — °C/W
Thermal Resistance, 8L-PDIP JA — 85 — °C/W
Thermal Resistance, 8L-SOIC JA — 163 — °C/W
Thermal Resistance, 8L-MSOP JA — 206 — °C/W
Thermal Resistance, 14L-PDIP JA — 70 — °C/W
Thermal Resistance, 14L-SOIC JA — 120 — °C/W
Thermal Resistance, 14L-TSSOP JA — 100 — °C/W
Note: The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.

MCP6273/MCP6275 CHIP SELECT SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 10 kto VDD/2, CL = 60 pF and CS is tied low.
Parameters Sym Min Typ Max Units Conditions

CS Low Specifications
CS Logic Threshold, Low VIL VSS — 0.2VDD V
CS Input Current, Low ICSL — 0.01 — µA CS = VSS
CS High Specifications
CS Logic Threshold, High VIH 0.8VDD — VDD V
CS Input Current, High ICSH — 0.7 2 µA CS = VDD
GND Current per Amplifier ISS — –0.7 — µA CS = VDD
Amplifier Output Leakage — — 0.01 — µA CS = VDD
Dynamic Specifications (Note 1)
CS Low to Valid Amplifier tON — 4 10 µs CS Low  0.2 VDD, G = +1 V/V,
Output, Turn on Time VIN = VDD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output tOFF — 0.01 — µs CS High  0.8 VDD, G = +1 V/V,
High-Z VIN = VDD/2, VOUT = 0.1 VDD/2
Hysteresis VHYST — 0.6 — V VDD = 5V
Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6275. The dynamic
specification is tested at the output of op amp B (VOUTB).

 2019 Microchip Technology Inc. DS20001810G-page 5

MCP6271/1R/2/3/4/5
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.7 “Supply Bypass”.

VDD
VIN 0.1 µF 1 µF

RN VOUT
MCP627X
CL RL
VDD/2 RG RF
VL

FIGURE 1-2: AC and DC Test Circuit for

Most Non-Inverting Gain Conditions.

VDD
VDD/2 0.1 µF 1 µF

RN VOUT
MCP627X
CL RL
VIN RG RF
VL

FIGURE 1-3: AC and DC Test Circuit for

Most Inverting Gain Conditions.

DS20001810G-page 6  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low.

18% 14%
832 Samples 832 Samples
Percentage of Occurrences

Percentage of Occurrences
16%
VCM = VSS 12% VCM = VSS
14%
TA = -40°C to +125°C
12% 10%
10% 8%
8%
6%
6%
4% 4%
2% 2%
0%
0%
-3.0

-2.4

-1.8

-1.2

-0.6

0.0

0.6

1.2

1.8

2.4

3.0

-10

-8

-6

-4

-2

10
Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C)

FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage Drift.

32% 22%
422 Samples 20% 422 Samples
Percentage of Occurrences

28% TA = 85°C TA = +125°C

Percentage of Occurrences

18%
24% 16%
20% 14%
12%
16% 10%
12% 8%
6%
8%
4%
4% 2%
0% 0%
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
0 10 20 30 40 50 60 70 80 90 100
Input Bias Current (pA) Input Bias Current (nA)

FIGURE 2-2: Input Bias Current at FIGURE 2-5: Input Bias Current at
TA = +85°C. TA = +125°C.

300 300
VDD = 2.0V VDD = 5.5V
250 250
Input Offset Voltage (µV)

Input Offset Voltage (µV)

200 200
150 150 TA = +125°C
100 100
TA = +125°C
50 50
TA = +85°C TA = +85°C
0 TA = +25°C 0 TA = +25°C
-50 TA = -40°C -50 TA = -40°C
-100 -100
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4

-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0

Common Mode Input Voltage (V) Common Mode Input Voltage (V)

FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs.
Common-mode Input Voltage, with VDD = 2.0V. Common-mode Input Voltage, with VDD = 5.5V.

 2019 Microchip Technology Inc. DS20001810G-page 7

MCP6271/1R/2/3/4/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low.

0.00 0.50
Common Mode Input Voltage

Common Mode Input Voltage

-0.05 Typical lower (VCM – VSS) limit 0.45
-0.10 0.40 VDD = 5.5V
Range Limit (V)

Range Limit (V)

-0.15 0.35
-0.20 VDD = 2.0V 0.30
-0.25 0.25
-0.30 0.20
VDD = 2.0V
-0.35 0.15
VDD = 5.5V
-0.40 0.10
-0.45 0.05 Typical upper (VCM – VDD) limit
-0.50 0.00
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Ambient Temperature (°C) Ambient Temperature (°C)

FIGURE 2-7: Common-mode Input FIGURE 2-10: Common-mode Input

Voltage Range Lower Limit vs. Temperature. Voltage Range Upper Limit vs. Temperature.

300
VCM = VSS 10,000
250 VCM = VDD
Input Offset Voltage (µV)

Input Bias, Offset Currents

Representative Part
200 VDD = 5.5V
1,000
150
100
(pA)

100 Input Bias Current

50
0 VDD = 2.0V VDD = 5.5V 10
Input Offset Current
-50
-100 1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 45 55 65 75 85 95 105 115 125
Output Voltage (V) Ambient Temperature (°C)

FIGURE 2-8: Input Offset Voltage vs. FIGURE 2-11: Input Bias, Input Offset
Output Voltage. Currents vs. Temperature.

110 120
100 CMRR
110
PSRR, CMRR (dB)

90
CMRR, PSRR (dB)

80 100 CMRR
70
90
60 PSRR–
PSRR+ PSRR
50 80
(VCM = VSS)
40 70
30
20 60
1
1.E+00 10 1.E+02
1.E+01 100 1.E+03
1k 10k 1.E+05
1.E+04 100k 1.E+06
1M -50 -25 0 25 50 75 100 125
Frequency (Hz) Ambient Temperature (°C)

FIGURE 2-9: CMRR, PSRR vs. FIGURE 2-12: CMRR, PSRR vs.
Frequency. Temperature.

DS20001810G-page 8  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low.

55 2.5
Input Bias, Offset Currents

Input Bias, Offset Currents

45 2.0
35 Input Bias Current 1.5
Input Bias Current
25
1.0
(pA)

(nA)
15
0.5
5
Input Offset Current 0.0 Input Offset Current
-5
TA = 85°C TA = 125°C
-15 -0.5
VDD = 5.5V VDD = 5.5V
-25 -1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V) Common Mode Input Voltage (V)

FIGURE 2-13: Input Bias, Offset Currents FIGURE 2-16: Input Bias, Offset Currents
vs. Common-mode Input Voltage, with vs. Common-mode Input Voltage, with
TA = +85°C. TA = +125°C.

250 1000

Ouput Voltage Headroom

200
Quiescent Current
(µA/amplifier)

100
150 (mV)
TA = +125°C
100
TA = +85°C 10
TA = +25°C VOL – VSS
50
TA = -40°C VDD – VOH

0 1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.01 0.1 1 10
Power Supply Voltage (V) Output Current Magnitude (mA)

FIGURE 2-14: Quiescent Current vs. FIGURE 2-17: Output Voltage Headroom
Supply Voltage. vs. Output Current Magnitude.

120 0 3.0 80
Gain Bandwidth Product

100 -30 2.5 75

Open-Loop Gain (dB)

Open-Loop Phase (°)

Gain

Phase Margin (°)

80 -60 GBWP, VDD = 5.5V
2.0 70
60 -90 VDD = 2.0V
(MHz)

Phase 1.5 65
40 -120
20 -150 1.0 60
PM, VDD = 5.5V
0 -180 0.5 VDD = 2.0V 55
-20 -210 0.0 50
1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

0.1 1 10 100 1k 10k 100k 1M 10M 100M -50 -25 0 25 50 75 100 125
Frequency (Hz) Ambient Temperature (°C)

FIGURE 2-15: Open-Loop Gain, Phase vs. FIGURE 2-18: Gain Bandwidth Product,
Frequency. Phase Margin vs. Temperature.

 2019 Microchip Technology Inc. DS20001810G-page 9

MCP6271/1R/2/3/4/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low.

10 1.8
Maximum Output Voltage

1.6 VDD = 5.5V

VDD = 5.5V 1.4 Falling Edge

Slew Rate (V/µs)

Swing (V P-P )

1.2
VDD = 2.0V
1.0
1
0.8 VDD = 2.0V
0.6
Rising Edge
0.4
0.2
0.1 0.0
1.E+03

1.E+04

1.E+05

1.E+06

1.E+07
1k 10k 100k 1M 10M -50 -25 0 25 50 75 100 125
Frequency (Hz) Ambient Temperature (°C)

FIGURE 2-19: Maximum Output Voltage FIGURE 2-22: Slew Rate vs. Temperature.
Swing vs. Frequency.

1,000 25

Input Noise Voltage Density

Input Noise Voltage Density

20

(nV/¥Hz) 15
(nV/—Hz)

100
10

5 f = 1 kHz
VDD = 5.0V
0
10
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.1 1 10 100 1k 10k 100k 1M
1.E- 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+ 1.E+
01 00 01 Frequency
02 03(Hz) 04 05 06 Common Mode Input Voltage (V)

FIGURE 2-20: Input Noise Voltage Density FIGURE 2-23: Input Noise Voltage Density
vs. Frequency. vs. Common-mode Input Voltage, with f = 1 kHz.

35 140
Ouptut Short-Circuit Current

30
Channel-to-Channel

130
Separation (dB)

25

20
120
(mA)

15 TA = +125°C
TA = +85°C
10 TA = +25°C 110
5 TA = -40°C

0 100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100
Power Supply Voltage (V) Frequency (kHz)

FIGURE 2-21: Output Short Circuit Current FIGURE 2-24: Channel-to-Channel

vs. Supply Voltage. Separation vs. Frequency (MCP6272 and
MCP6274).

DS20001810G-page 10  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low.

250 700
VDD = 2.0V VDD = 5.5V
Op Amp turns Off 600 Hysteresis
200

Quiescent Current
Quiescent Current

Op Amp turns On 500

(µA/amplifier)
(µA/amplifier)

CS swept
150 Low-to-High
400
Hysteresis

High-to-Low
300

CS swept
100 Op Amp
CS swept CS swept turns
200
High-to-Low Low-to-High On/Off
50
100
0 0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V) Chip Select Voltage (V)

FIGURE 2-25: Quiescent Current vs. Chip FIGURE 2-28: Quiescent Current vs. Chip
Select (CS) Voltage, with VDD = 2.0V (MCP6273 Select (CS) Voltage, with VDD = 5.5V (MCP6273
and MCP6275 only). and MCP6275 only).

5.0 5.0
G = +1 V/V G = -1 V/V
4.5 4.5
VDD = 5.0V VDD = 5.0V
4.0 4.0
Output Voltage (V)

3.5 Output Voltage (V) 3.5

3.0 3.0
2.5 2.5
2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
0.0 0.0
Time (5 µs/div) Time (5 µs/div)

FIGURE 2-26: Large Signal Non-inverting FIGURE 2-29: Large Signal Inverting Pulse
Pulse Response. Response.

G = +1 V/V G = -1 V/V
Output Voltage (10 mV/div)
Output Voltage (10 mV/div)

Time (2 µs/div) Time (2 µs/div)

FIGURE 2-27: Small Signal Non-inverting FIGURE 2-30: Small Signal Inverting Pulse
Pulse Response. Response.

 2019 Microchip Technology Inc. DS20001810G-page 11

MCP6271/1R/2/3/4/5
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.0V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2,
VL = VDD/2, RL = 10 k to VL, CL = 60 pF and CS is tied low.

2.5 6.0
VDD = 2.0V VDD = 5.5V
Chip Select, Output Voltages

5.5

Chip Select, Output Voltages

CS G = +1 V/V 5.0 CS G = +1 V/V
2.0 VIN = VSS VIN = VSS
4.5
4.0
1.5 3.5
VOUT
(V)

Output On

(V)
VOUT 3.0
1.0 2.5
2.0
1.5
0.5
Output High-Z 1.0
0.5 Output High-Z Output On
0.0 0.0
Time (5 µs/div) Time (5 µs/div)

FIGURE 2-31: Chip Select (CS) to FIGURE 2-33: Chip Select (CS) to
Amplifier Output Response Time, with Amplifier Output Response Time, with
VDD = 2.0V (MCP6273 and MCP6275 only). VDD = 5,5V (MCP6273 and MCP6275 only).

1.E-02
10m 6
Input Current Magnitude (A)

1.E-03
1m VDD = 5.0V
1.E-04
100µ Input, Output Voltage (V) 5 G = +2 V/V
1.E-05
10µ 4
1.E-06
1µ
100n
1.E-07 3
10n
1.E-08
+125°C 2
1n
1.E-09
+85°C VIN
100p
1.E-10 1
+25°C VOUT
10p
1.E-11 -40°C 0
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -1
Input Voltage (V) Time (1 ms/div)

FIGURE 2-32: Input Current vs. Input FIGURE 2-34: The MCP6271/1R/2/3/4/5
Voltage. Show no Phase Reversal.

DS20001810G-page 12  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).

TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS

MCP6271 MCP6271R MCP6273

PDIP, SOIC, PDIP, SOIC, Symbol Description

SOT-23-5 SOT-23-5 SOT-23-6
MSOP MSOP

2 4 4 2 4 VIN– Inverting Input

3 3 3 3 3 VIN+ Non-inverting Input
4 2 5 4 2 VSS Negative Power Supply
6 1 1 6 1 VOUT Analog Output
7 5 2 7 6 VDD Positive Power Supply
— — — 8 5 CS Chip Select
1,5,8 — — 1,5 — NC No Internal Connection

TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6272 MCP6274 MCP6275 Symbol Description

1 1 — VOUTA Analog Output (op amp A)

2 2 2 VINA– Inverting Input (op amp A)
3 3 3 VINA+ Non-inverting Input (op amp A)
8 4 8 VDD Positive Power Supply
5 5 — VINB+ Non-inverting Input (op amp B)
6 6 6 VINB– Inverting Input (op amp B)
7 7 7 VOUTB Analog Output (op amp B)
— 8 — VOUTC Analog Output (op amp C)
— 9 — VINC– Inverting Input (op amp C)
— 10 — VINC+ Non-inverting Input (op amp C)
4 11 4 VSS Negative Power Supply
— 12 — VIND+ Non-inverting Input (op amp D)
— 13 — VIND– Inverting Input (op amp D)
— 14 — VOUTD Analog Output (op amp D)
— — 1 VOUTA / VINB+ Analog Output (op amp A)/Non-inverting Input (op amp B)
— — 5 CS Chip Select

3.1 Analog Outputs 3.4 Chip Select Digital Input

The output pins are low impedance voltage sources. This is a CMOS, Schmitt triggered input that places the
part into a low power mode of operation.
3.2 Analog Inputs
3.5 Power Supply Pins
The non-inverting and inverting inputs are high
impedance CMOS inputs with low bias currents. The positive power supply (VDD) is 2.0V to 6.0V higher
than the negative power supply (VSS). For normal
3.3 MCP6275’s VOUTA/VINB+ Pin operation, the other pins are at voltages between VSS
and VDD.
For the MCP6275 only, the output of op amp A is
Typically, these parts are used in a single (positive)
connected directly to the non-inverting input of op amp
supply configuration. In this case, VSS is connected to
B; this is the VOUTA/VINB+ pin. This connection makes
ground and VDD is connected to the supply. VDD will
it possible to provide a CS pin for duals in 8-pin
need bypass capacitors.
packages.

 2019 Microchip Technology Inc. DS20001810G-page 13

MCP6271/1R/2/3/4/5
4.0 APPLICATION INFORMATION dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
The MCP6271/1R/2/3/4/5 family of op amps is through D1 and D2.
manufactured using Microchip’s state of the art CMOS
process, specifically designed for low cost, low power
and general purpose applications. The low supply VDD
voltage, low quiescent current and wide bandwidth
make the MCP6271/1R/2/3/4/5 ideal for battery
powered applications. D1
V1
4.1 Rail-to-Rail Inputs R1 D2 MCP627X VOUT

4.1.1 PHASE REVERSAL V2

R2
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-34 shows an input voltage R3
exceeding both supplies with no phase inversion.
VSS – (minimum expected V1)
R1 >
4.1.2 INPUT VOLTAGE AND CURRENT 2 mA
LIMITS VSS – (minimum expected V2)
R2 >
The ESD protection on the inputs can be depicted as 2 mA
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias FIGURE 4-2: Protecting the Analog
current (IB). The input ESD diodes clamp the inputs Inputs.
when they try to go more than one diode drop below It is also possible to connect the diodes to the left of the
VSS. They also clamp any voltages that go too far resistor R1 and R2. In this case, the currents through
above VDD; their breakdown voltage is high enough to the diodes D1 and D2 need to be limited by some other
allow normal operation, and low enough to bypass mechanism. The resistors then serve as in-rush current
quick ESD events within the specified limits. limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
VDD Bond inputs (through the ESD diodes) when the Common-
Pad
mode voltage (VCM) is below ground (VSS); see
Figure 2-32. Applications that are high impedance may
need to limit the usable voltage range.
VIN+ Bond Input Bond V –
IN
Pad Stage Pad 4.1.3 NORMAL OPERATIONS
The input stage of the MCP6271/1R/2/3/4/5 op amps
uses two differential CMOS input stages in parallel.
VSS Bond One operates at low Common-mode input voltage
Pad (VCM and the other at high VCM. With this topology, the
input operates with VCM up to 0.3V past either supply
FIGURE 4-1: Simplified Analog Input ESD rail (see Figure 2-7 and Figure 2-10). The input offset
Structures. voltage (VOS) is measured at VCM = VSS – 0.3V and
VDD + 0.3V to ensure proper operation.
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents The transition between the two input stage occurs
(and voltages) at the input pins (see Absolute Maxi- when VCM  VDD – 1.1V (see Figure 2-3 and Figure 2-
mum Ratings † at the beginning of Section 1.0 “Elec- 6). For the best distortion and gain linearity, with non-
trical Characteristics”). Figure 4-2 shows the inverting gains, avoid this region of operation.
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+ 4.2 Rail-to-Rail Output
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out The output voltage range of the MCP6271/1R/2/3/4/5
of the input pins. Diodes D1 and D2 prevent the input op amps is VDD – 15 mV (minimum) and VSS + 15 mV
pins (VIN+ and VIN–) from going too far above VDD, and (maximum) when RL = 10 k is connected to VDD/2
and VDD = 5.5V. Refer to Figure 2-17 for more informa-
tion.

DS20001810G-page 14  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
4.3 Capacitive Loads 4.4 MCP6273/5 Chip Select
Driving large capacitive loads can cause stability The MCP6273 and MCP6275 are single and dual op
problems for voltage feedback op amps. As the load amps with Chip Select (CS), respectively. When CS is
capacitance increases, the feedback loop’s phase pulled high, the supply current drops to 0.7 µA (typical)
margin decreases and the closed-loop bandwidth is and flows through the CS pin to VSS. When this
reduced. This produces gain peaking in the frequency happens, the amplifier output is put into a high
response, with overshoot and ringing in the step impedance state. By pulling CS low, the amplifier is
response. A unity gain buffer (G = +1) is the most enabled. The CS pin has an internal 5 M (typical) pull-
sensitive to capacitive loads, though all gains show the down resistor connected to VSS, so it will go low if the
same general behavior. CS pin is left floating. Figure 1-1 shows the output volt-
When driving large capacitive loads with these op age and supply current response to a CS pulse.
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the 4.5 Cascaded Dual Op Amps
feedback loop’s phase margin (stability) by making the (MCP6275)
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth The MCP6275 is a dual op amp with Chip Select (CS).
with no capacitive load. The Chip Select input is available on what would be the
non-inverting input of a standard dual op amp (pin 5).
This pin is available because the output of op amp A
connects to the non-inverting input of op amp B, as
_ RISO shown in Figure 4-5. The Chip Select input, which can
be connected to a microcontroller I/O line, puts the
MCP627X VOUT
device in low power mode. Refer to Section 4.4
VIN
+ CL “MCP6273/5 Chip Select (CS)”.

VOUTA/VINB+ VINB–
FIGURE 4-3: Output Resistor, RISO
1 6
stabilizes large capacitive loads.
_
Figure 4-4 gives recommended RISO values for VINA–
2 _ 7
different capacitive loads and gains. The x-axis is the B VOUTB
normalized load capacitance (CL/GN), where GN is the 3 A +
VINA+ +
circuit's noise gain. For non-inverting gains, GN and the MCP6275
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., –1 V/V gives GN = +2 V/V).
5
CS
1,000
FIGURE 4-5: Cascaded Gain Amplifier.
Recommended RISO (:)

The output of op amp A is loaded by the input

impedance of op amp B, which is typically
100 10136 pF, as specified in the DC specification table
(Refer to Section 4.3 “Capacitive Loads” for further
GN = 1 V/V
GN = 2 V/V details regarding capacitive loads).
GN t 4 V/V The Common-mode input range of these op amps is
10 specified in the data sheet as VSS – 300 mV and
10 100 1,000 10,000 VDD + 300 mV. However, since the output of op amp A
Normalized Load Capacitance; CL / GN (pF) is limited to VOL and VOH (20 mV from the rails with a
10 k load), the non-inverting input range of op amp B
FIGURE 4-4: Recommended RISO Values is limited to the Common-mode input range of
for Capacitive Loads. VSS + 20 mV and VDD – 20 mV.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6271/1R/2/3/4/5 SPICE
macro model are helpful.

 2019 Microchip Technology Inc. DS20001810G-page 15

MCP6271/1R/2/3/4/5
4.6 Unused Amplifiers
VIN– VIN+
An unused op amp in a quad package (MCP6274) VSS
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. In Circuit A, R1 and R2 produce a voltage
within its output voltage range (VOH, VOL). The op amp
buffers this voltage, which can be used elsewhere in
the circuit. Circuit B uses the minimum number of
components and operates as a comparator.
Guard Ring
¼ MCP6274 (A) ¼ MCP6274 (B) FIGURE 4-7: Example Guard Ring Layout
VDD VDD for Inverting Gain.
1. For Inverting Gain and Transimpedance
VDD Amplifiers (convert current to voltage, such as
R1
+ photo detectors):
+ a) Connect the guard ring to the non-inverting
VREF – input pin (VIN+). This biases the guard ring
R2 –
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input
R2 with a wire that does not touch the PCB
V REF = V DD  ------------------ surface.
R1 + R2
2. Non-inverting Gain and Unity Gain Buffer:
FIGURE 4-6: Unused Op Amps. a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
4.7 Supply Bypass
b) Connect the guard ring to the inverting input
With this family of operational amplifiers, the power pin (VIN–). This biases the guard ring to the
supply pin (VDD for single supply) should have a local Common-mode input voltage.
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.

4.8 PCB Surface Leakage

In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6271/1R/2/3/4/5 family’s bias current at 25°C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is illustrated in
Figure 4-7.

DS20001810G-page 16  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
4.9 Application Circuits 4.9.2 LOSSY NON-INVERTING
INTEGRATOR
4.9.1 ACTIVE FULL-WAVE RECTIFIER
The non-inverting integrator shown in Figure 4-9 is
The MCP6271/1R/2/3/4/5 family of amplifiers can be easy to build. It saves one op amp over the typical
used in applications such as an Active Full-Wave Miller integrator plus inverting amplifier configuration.
Rectifier or an Absolute Value circuit, as shown in The phase accuracy of this integrator depends on the
Figure 4-8. The amplifier and feedback loops in this matching of the input and feedback resistor-capacitor
active voltage rectifier circuit eliminate the diode drop time constants. RF makes this a lossy integrator (it has
problem that exists in a passive voltage rectifier. This finite gain at DC) and stable by itself.
circuit behaves as a follower (the output follows the
input) as long as the input signal is more positive than
R1
the reference voltage. If the input signal is more
VIN +
negative than the reference voltage, however, the
circuit behaves as an inverting amplifier. Therefore, the MCP6271 VOUT
C1
output voltage will always be above the reference _
voltage, regardless of the input signal. RF

R2 C2

VIN R1
– RF  R2 R2
Op Amp B
R 1 C 1 =  R 2 ||R F C 2
R3 R5 + VOUT
R4 1/2
V OUT 1 - 1
MCP6272 -------------  -------------------  f  ---------------------------------------------------
V IN s  R1 C1  2R 1 C 1  1 + R F  R 2 
VREF
D1 FIGURE 4-9: Non-Inverting Integrator.
D2

R1 = R2 = R3
– V D1
R 4 < R 3  1 – ----------------------------
Op Amp A  V REF – V SS
+ R2 R4
1/2 R 5 = ------------
VREF MCP6272 2R 3

Input Output

VREF VREF

time time

FIGURE 4-8: Active Full-wave Rectifier.

The design equations give a gain of ±1 from VIN to
VOUT, and produce rail-to-rail outputs.

 2019 Microchip Technology Inc. DS20001810G-page 17

MCP6271/1R/2/3/4/5
4.9.3 CASCADED OP AMP
APPLICATIONS R4 R3 R2 R1
The MCP6275 provides the flexibility of Low power
mode for dual op amps in an 8-pin package. The –
MCP6275 eliminates the added cost and space in a – B VOUT
battery powered application by using two single op A +
amps with Chip Select (CS) lines or a 10-pin device VIN + MCP6275
with one CS line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements CS
between the two op amps. However, there are several
applications where this op amp configuration with a CS FIGURE 4-11: Cascaded Gain Circuit
line becomes suitable. The circuits below show Configuration.
possible applications for this device.
4.9.3.3 Difference Amplifier
4.9.3.1 Load Isolation
Figure 4-12 shows op amp A configured as a difference
With the cascaded op amp configuration, op amp B can amplifier with Chip Select. In this configuration, it is
be used to isolate the load from op amp A. In recommended that well matched resistors (e.g., 0.1%)
applications where op amp A is driving capacitive or be used to increase the Common-mode Rejection
low resistive loads in the feedback loop (such as an Ratio (CMRR). Op amp B can be used to provide addi-
integrator or filter circuit) the op amp may not have tional gain and isolate the load from the difference
sufficient source current to drive the load. In this case, amplifier.
op amp B can be used as a buffer.

R2 R1 R4 R3
– VIN2
– B VOUTB
A + –
+ – B VOUT
MCP6275 Load +
R2 A
VIN1 + MCP6275

CS R1

CS
FIGURE 4-10: Isolating the Load with a
Buffer. FIGURE 4-12: Difference Amplifier Circuit.
4.9.3.2 Cascaded Gain 4.9.3.4 Inverting Integrator with Active
Figure 4-11 shows a cascaded gain circuit configura- Compensation and Chip Select
tion with Chip Select. Op amps A and B are configured
Figure 4-13 uses an active compensator (op amp B) to
in a non-inverting amplifier configuration. In this
compensate for the non-ideal op amp characteristics
configuration, it is important to note that the input offset
introduced at higher frequencies. This circuit uses
voltage of op amp A is amplified by the gain of op amp
op amp B as a unity gain buffer to isolate the
A and B, as shown below:
integration capacitor C1 from op amp A and drives the
V OUT = V IN G A G B + V OSA G A G B + V OSB G B capacitor with a low impedance source. Since both op
amps are matched very well, they provide a high quality
Where: integrator.
GA = op amp A gain
GB = op amp B gain R1 C1
–
VOSA = op amp A input offset voltage VIN B
+
VOSB = op amp B input offset voltage –
A VOUT
+ MCP6275
Therefore, it is recommended that you set most of the
gain with op amp A and use op amp B with relatively
small gain (e.g., a unity gain buffer).
CS

DS20001810G-page 18  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
FIGURE 4-13: Integrator Circuit with Active 4.9.3.7 Capacitorless Second Order
Compensation. Low-Pass filter with Chip Select
The low-pass filter shown in Figure 4-16 does not
4.9.3.5 Second Order MFB with an Extra
require external capacitors and uses only three
Pole-Zero Pair external resistors; the op amp’s GBWP sets the corner
Figure 4-14 is a second order multiple feedback low- frequency. R1 and R2 are used to set the circuit gain. R3
pass filter with Chip Select. Use the FilterLab® software is used to set the Q. To avoid gain peaking in the
from Microchip Technology Inc. to determine the R and frequency response, Q needs to be low (lower values
C values for op amp A’s second order filter. Op amp B need to be selected for R3). Note that the amplifier
can be used to add a pole-zero pair using C3, R6 and bandwidth varies greatly over temperature and
R7. process. This configuration, however, provides a low
cost solution for applications with high bandwidth
C3 requirements.
R6

R7 R2 R1
R1 VIN
– R3
R3 R2 C1 B VOUT –
VIN + A +
+ B VOUT
– VREF –
R5 A
+ MCP6275
VDD MCP6275
R4
CS
CS
FIGURE 4-16: Capacitorless Second Order
FIGURE 4-14: Second Order Multiple
Low-Pass Filter with Chip Select.
Feedback Low-Pass Filter with an Extra Pole-
Zero Pair.

4.9.3.6 Second Order Sallen-Key with an

Extra Pole-Zero Pair
Figure 4-15 is a second order Sallen-Key low-pass
filter with Chip Select. Use the Filterlab® software from
Microchip to determine the R and C values for
op amp A’s second order filter. Op amp B can be used
to add a pole-zero pair using C3, R5 and R6.

R5 C3

R6
R2 R1
– VOUT
– B
VIN R4 R3 A +
+ MCP6275
C2 C1
CS

FIGURE 4-15: Second Order Sallen-Key

Low-Pass Filter with an Extra Pole-Zero Pair and
Chip Select.

 2019 Microchip Technology Inc. DS20001810G-page 19

MCP6271/1R/2/3/4/5
NOTES:

DS20001810G-page 20  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
5.0 DESIGN TOOLS 5.5 Analog Demonstration and
Evaluation Boards
Microchip provides the basic design tools needed for
the MCP6271/1R/2/3/4/5 family of op amps. Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
5.1 SPICE Macro Model designed to help you achieve faster time to market. For
a complete listing of these boards and their
The latest SPICE macro model for the MCP6271/1R/2/ corresponding user’s guides and technical information,
3/4/5 op amps is available on the Microchip web site at visit the Microchip web site at www.microchip.com/
www.microchip.com. This model is intended to be an analogtools.
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See Two of our boards that are especially useful are:
the model file for information on its capabilities. • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Bench testing is a very important part of any design and Evaluation Board
cannot be replaced with simulations. Also, simulation • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evalu-
results using this macro model need to be validated by ation Board
comparing them to the data sheet specifications and
characteristic curves. 5.6 Application Notes
The following Microchip Application Notes are avail-
5.2 FilterLab® Software able on the Microchip web site at www.microchip. com/
Microchip’s FilterLab® software is an innovative appnotes and are recommended as supplemental ref-
software tool that simplifies analog active filter (using erence resources.
op amps) design. Available at no cost from the ADN003: “Select the Right Operational Amplifier for
Microchip web site at www.microchip.com/filterlab, the your Filtering Circuits,” DS21821
FilterLab design tool provides full schematic diagrams
AN722: “Operational Amplifier Topologies and DC
of the filter circuit with component values. It also
Specifications,” DS00722
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter AN723: “Operational Amplifier AC Specifications and
performance. Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps,”
5.3 Mindi™ Circuit Designer & DS00884
Simulator AN990: “Analog Sensor Conditioning Circuits – An
Microchip’s Mindi™ Circuit Designer & Simulator aids Overview,” DS00990
in the design of various circuits useful for active filter, These application notes and others are listed in the
amplifier and power-management applications. It is a design guide:
free online circuit designer & simulator available from “Signal Chain Design Guide,” DS21825
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.

5.4 MAPS (Microchip Advanced Part

Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data sheets,
Purchase, and Sampling of Microchip parts.

 2019 Microchip Technology Inc. DS20001810G-page 21

MCP6271/1R/2/3/4/5
NOTES:

DS20001810G-page 22  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Example:
5-Lead SOT-23 (MCP6271 and MCP6271R)

Device Code

XXNN MCP6271 CGNN CG25

MCP6271R ETNN
Note: Applies to 5-Lead SOT-23

6-Lead SOT-23 (MCP6273) Example:

XXNN CK25

8-Lead MSOP Example:

6271E
644256

8-Lead PDIP (300 mil) Example:

XXXXXXXX MCP6271 MCP6271

XXXXXNNN E/P256 OR E/P^^256
e3
YYWW 0437 0644

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2019 Microchip Technology Inc. DS20001810G-page 23

MCP6271/1R/2/3/4/5
Package Marking Information (Continued)

8-Lead SOIC (150 mil) Example:

XXXXXXXX MCP6271 MCP6271E

XXXXYYWW E/SN0437 SN^^0644
e3
OR
NNN 256 256

14-Lead PDIP (300 mil) (MCP6274) Example:

XXXXXXXXXXXXXX MCP6274-E/P
XXXXXXXXXXXXXX
YYWWNNN 0437256

OR

MCP6274
E/P^^
e3
0644256

14-Lead SOIC (150 mil) (MCP6274) Example:

XXXXXXXXXX MCP6274ESL
XXXXXXXXXX
YYWWNNN 0437256

OR

MCP6274
E/SL^^
e3
0644256

14-Lead TSSOP (MCP6274) Example:

XXXXXX 6274EST
YYWW 0437
NNN 256

DS20001810G-page 24  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

0.20 C 2X
D

e1
A D

E/2
E1/2

E1 E
(DATUM D)
(DATUM A-B)

0.15 C D
2X
NOTE 1 1 2

B NX b
0.20 C A-B D

TOP VIEW

A A2
0.20 C

SEATING PLANE
A
SEE SHEET 2 A1 C

SIDE VIEW

Microchip Technology Drawing C04-091-OT Rev E Sheet 1 of 2

 2019 Microchip Technology Inc. DS20001810G-page 25

MCP6271/1R/2/3/4/5

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

T
L
L1

VIEW A-A
SHEET 1

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 5
Pitch e 0.95 BSC
Outside lead pitch e1 1.90 BSC
Overall Height A 0.90 - 1.45
Molded Package Thickness A2 0.89 - 1.30
Standoff A1 - - 0.15
Overall Width E 2.80 BSC
Molded Package Width E1 1.60 BSC
Overall Length D 2.90 BSC
Foot Length L 0.30 - 0.60
Footprint L1 0.60 REF
Foot Angle I 0° - 10°
Lead Thickness c 0.08 - 0.26
Lead Width b 0.20 - 0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-091-OT Rev E Sheet 2 of 2

DS20001810G-page 26  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5

5-Lead Plastic Small Outline Transistor (OT) [SOT23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

5 SILK SCREEN

Z C G

1 2

E
GX

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.95 BSC
Contact Pad Spacing C 2.80
Contact Pad Width (X5) X 0.60
Contact Pad Length (X5) Y 1.10
Distance Between Pads G 1.70
Distance Between Pads GX 0.35
Overall Width Z 3.90

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091B [OT]

 2019 Microchip Technology Inc. DS20001810G-page 27

MCP6271/1R/2/3/4/5

6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

2X
0.15 C A-B
D
e1
A D

E
2

E1 E
E1
2

2X
0.15 C D
2X
0.20 C A-B
e
B 6X b
0.20 C A-B D

TOP VIEW

A A2
C
SEATING PLANE
6X
A1 0.10 C
SIDE VIEW

R1
R L2
c
GAUGE PLANE

L Ĭ
(L1)
END VIEW
Microchip Technology Drawing C04-028C (CH) Sheet 1 of 2

DS20001810G-page 28  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5

6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 6
Pitch e 0.95 BSC
Outside lead pitch e1 1.90 BSC
Overall Height A 0.90 - 1.45
Molded Package Thickness A2 0.89 1.15 1.30
Standoff A1 0.00 - 0.15
Overall Width E 2.80 BSC
Molded Package Width E1 1.60 BSC
Overall Length D 2.90 BSC
Foot Length L 0.30 0.45 0.60
Footprint L1 0.60 REF
Seating Plane to Gauge Plane L1 0.25 BSC
Foot Angle φ 0° - 10°
Lead Thickness c 0.08 - 0.26
Lead Width b 0.20 - 0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-028C (CH) Sheet 2 of 2

 2019 Microchip Technology Inc. DS20001810G-page 29

MCP6271/1R/2/3/4/5

6-Lead Plastic Small Outline Transistor (CH, CHY) [SOT-23]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

GX

Z C G G

SILK SCREEN

X
E

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.95 BSC
Contact Pad Spacing C 2.80
Contact Pad Width (X3) X 0.60
Contact Pad Length (X3) Y 1.10
Distance Between Pads G 1.70
Distance Between Pads GX 0.35
Overall Width Z 3.90

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2028B (CH)

DS20001810G-page 30  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2019 Microchip Technology Inc. DS20001810G-page 31

MCP6271/1R/2/3/4/5

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20001810G-page 32  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2019 Microchip Technology Inc. DS20001810G-page 33

MCP6271/1R/2/3/4/5

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D A
N B

E1

NOTE 1
1 2
TOP VIEW

C A A2

PLANE
L c
A1

e eB
8X b1
8X b
.010 C

SIDE VIEW END VIEW

Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2

DS20001810G-page 34  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5

8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

ALTERNATE LEAD DESIGN

(NOTE 5)

DATUM A DATUM A

b b
e e
2 2

e e

Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 - -
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB - - .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
5. Lead design above seating plane may vary, based on assembly vendor.

Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2

 2019 Microchip Technology Inc. DS20001810G-page 35

MCP6271/1R/2/3/4/5

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

2X
0.10 C A–B
D
A D
NOTE 5
N

E
2
E1
2

E1 E

NOTE 1 1 2

e NX b
B 0.25 C A–B D
NOTE 5
TOP VIEW
0.10 C

C A A2
SEATING
PLANE 8X
0.10 C
A1 SIDE VIEW

h
R0.13
h
R0.13
H 0.23

L
SEE VIEW C
(L1)
VIEW A–A

VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2

DS20001810G-page 36  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A - - 1.75
Molded Package Thickness A2 1.25 - -
Standoff § A1 0.10 - 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (Optional) h 0.25 - 0.50
Foot Length L 0.40 - 1.27
Footprint L1 1.04 REF
Foot Angle 0° - 8°
Lead Thickness c 0.17 - 0.25
Lead Width b 0.31 - 0.51
Mold Draft Angle Top 5° - 15°
Mold Draft Angle Bottom 5° - 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2

 2019 Microchip Technology Inc. DS20001810G-page 37

MCP6271/1R/2/3/4/5

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

SILK SCREEN

Y1

X1
E

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 5.40
Contact Pad Width (X8) X1 0.60
Contact Pad Length (X8) Y1 1.55

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2057-SN Rev E

DS20001810G-page 38  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5

             

  J & ' !&" & K# 3!* !!&    K %&  &#&
&& GQQ333'    'Q K

NOTE 1
E1

1 2 3

A A2

L c

A1
b1

b e eB

U&! Y9Z<
'! ['&! Y Y\ ]
Y"'+  %! Y 
&  @9
& &  ^ ^ 
 ##K K!!  ? ; ?
@!& &  ? ^ ^
 "# &  "# _#& <  ; ;?
 ##K_#& <  ? `
\ [&  ;? ? ?
 & & [ ? ; ?
[# K!!  `  ?
U  [#_#& + ? j 
[ 3 [#_#& +  ` 
\  3 7 @ ^ ^ ;
 
 !"#$%&" ' *+"&'"!&+ &#3& &  & # 
 7%&9  & !&
; '! !#<#  &"#' #%!   & "! ! #%!   & "! !!  &$#=  !#
 '! #&    <>?
@9G@!'!   &$&"! 33& "&&  !

        3 9?@

 2019 Microchip Technology Inc. DS20001810G-page 39

MCP6271/1R/2/3/4/5

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

2X
0.10 C A–B
D
A NOTE 5 D
N

E
2
E2
2

E1 E

2X
0.10 C D
2X N/2 TIPS
NOTE 1 1 2 3 0.20 C
e NX b
B NOTE 5 0.25 C A–B D

TOP VIEW

0.10 C

C A A2
SEATING
PLANE 14X
A1 SIDE VIEW 0.10 C

h h

H R0.13
R0.13

SEE VIEW C
L
VIEW A–A (L1)

VIEW C
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2

DS20001810G-page 40  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 1.27 BSC
Overall Height A - - 1.75
Molded Package Thickness A2 1.25 - -
Standoff § A1 0.10 - 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 8.65 BSC
Chamfer (Optional) h 0.25 - 0.50
Foot Length L 0.40 - 1.27
Footprint L1 1.04 REF
Lead Angle 0° - -
Foot Angle 0° - 8°
Lead Thickness c 0.10 - 0.25
Lead Width b 0.31 - 0.51
Mold Draft Angle Top 5° - 15°
Mold Draft Angle Bottom 5° - 15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.

Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2

 2019 Microchip Technology Inc. DS20001810G-page 41

MCP6271/1R/2/3/4/5

14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

14

SILK SCREEN

1 2
X
E

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 1.27 BSC
Contact Pad Spacing C 5.40
Contact Pad Width (X14) X 0.60
Contact Pad Length (X14) Y 1.55

Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-2065-SL Rev D

DS20001810G-page 42  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2019 Microchip Technology Inc. DS20001810G-page 43

MCP6271/1R/2/3/4/5

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20001810G-page 44  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2019 Microchip Technology Inc. DS20001810G-page 45

MCP6271/1R/2/3/4/5
NOTES:

DS20001810G-page 46  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
APPENDIX A: REVISION HISTORY Revision C (June 2004)
• Undocumented Changes
Revision G (December 2019)
The following is the list of modifications: Revision B (October 2003)
1. Updated Section 6.0 “Packaging Informa- • Undocumented Changes
tion”.
Revision A (June 2003)
Revision F (March 2008)
• Original data sheet release.
The following is the list of modifications:
1. Increased maximum operating VDD.
2. Updated Section 5.0 “Design Tools”
3. Various cleanups thoughout document.
4. Updated package outline drawings in
Section 6.0 “Packaging Information”

Revision E (December 2006)

The following is the list of modifications:
1. Updated specifications (Section 1.0 “Electrical
Characteristics”):
a) Clarified Absolute Maximum Analog Input
Voltage and Current specifications.
b) Clarified VCMR, VOL, VOH, and PM
specifications.
c) Corrected the typical Eni.
2. Added plots on Common Mode Input Range
behavior vs. temperature and supply voltage
(Section 2.0 “Typical Performance Curves”).
3. Added applications writeup on unused op amps
and corrected description of floating CS pin
behavior (Section 4.0 “Application Informa-
tion”).
4. Updated package information (Section 6.0
“Packaging Information”):
a) Corrected package markings.
b) Added disclaimer to package outline
drawings.

Revision D (December 2004)

The following is the list of modifications:
1. Added SOT-23-5 packages for the MCP6271
and MCP6271R single op amps.
2. Added SOT-23-6 packages for the MCP6273
single op amp.
3. Added Section 3.0 “Pin Descriptions”.
4. Corrected application circuits
(Section 4.9 “Application Circuits”).
5. Added SOT-23-5 and SOT-23-6 packages and
corrected package marking information
(Section 6.0 “Packaging Information”).
6. Added Appendix A: Revision History.

 2019 Microchip Technology Inc. DS20001810G-page 47

MCP6271/1R/2/3/4/5
NOTES:

DS20001810G-page 48  2019 Microchip Technology Inc.

 MCP6271/1R/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO. – X /XX
a) MCP6271-E/SN: Extended Temperature,
Device Temperature Package 8LD SOIC package.
Range b) MCP6271-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6271-E/P: Extended Temperature,
8LD PDIP package.
Device: MCP6271: Single Op Amp
d) MCP6271T-E/OT: Tape and Reel,
MCP6271T: Single Op Amp
Extended Temperature,
(Tape and Reel)
5LD SOT-23 package.
(SOIC, MSOP, SOT-23-5)
MCP6271RT: Single Op Amp
a) MCP6271RT-E/OT: Tape and Reel,
(Tape and Reel) (SOT-23-5)
Extended Temperature,
MCP6272: Dual Op Amp
5LD SOT-23 package.
MCP6272T: Dual Op Amp
(Tape and Reel) (SOIC, MSOP)
MCP6273: Single Op Amp with Chip Select a) MCP6272-E/SN: Extended Temperature,
MCP6273T: Single Op Amp with Chip Select 8LD SOIC package.
(Tape and Reel) b) MCP6272-E/MS: Extended Temperature,
(SOIC, MSOP, SOT-23-6) 8LD MSOP package.
MCP6274: Quad Op Amp c) MCP6272-E/P: Extended Temperature,
MCP6274T: Quad Op Amp 8LD PDIP package.
(Tape and Reel) (SOIC, TSSOP) d) MCP6272T-E/SN: Tape and Reel,
MCP6275: Dual Op Amp with Chip Select Extended Temperature,
MCP6275T: Dual Op Amp with Chip Select 8LD SOIC package.
(Tape and Reel) (SOIC, MSOP)
a) MCP6273-E/SN: Extended Temperature,
8LD SOIC package.
Temperature Range: E = -40°C to +125°C b) MCP6273-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6273-E/P: Extended Temperature,
Package: OT = Plastic Small Outline Transistor (SOT-23), 5-lead 8LD PDIP package.
(MCP6271, MCP6271R) d) MCP6273T-E/CH: Extended Temperature,
CH = Plastic Small Outline Transistor (SOT-23), 6-lead 6LD SOT-23 package.
(MCP6273)
MS = Plastic MSOP, 8-lead a) MCP6274-E/P: Extended Temperature,
P = Plastic DIP (300 mil Body), 8-lead, 14-lead 14LD PDIP package.
SN = Plastic SOIC, (150 mil Body), 8-lead b) MCP6274T-E/SL: Tape and Reel,
SL = Plastic SOIC (150 mil Body), 14-lead Extended Temperature,
ST = Plastic TSSOP (4.4 mm Body), 14-lead 14LD SOIC package.
c) MCP6274-E/SL: Extended Temperature,
14LD SOIC package.
d) MCP6274-E/ST: Extended Temperature,
14LD TSSOP package.

a) MCP6275-E/SN: Extended Temperature,

8LD SOIC package.
b) MCP6275-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6275-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6275T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.

 2019 Microchip Technology Inc. DS20001810G-page 49

MCP6271/1R/2/3/4/5
NOTES:

DS20001810G-page 50  2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec,
and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in
FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries.
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company,
the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.

© 2019, Microchip Technology Incorporated, All Rights Reserved.

For information regarding Microchip’s Quality Management Systems, ISBN: 978-1-5224-5343-7

please visit www.microchip.com/quality.

 2019 Microchip Technology Inc. DS20001810G-page 51

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Australia - Sydney India - Bangalore Austria - Wels
2355 West Chandler Blvd. Tel: 61-2-9868-6733 Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 China - Beijing India - New Delhi Fax: 43-7242-2244-393
Tel: 480-792-7200 Tel: 86-10-8569-7000 Tel: 91-11-4160-8631 Denmark - Copenhagen
Fax: 480-792-7277 Tel: 45-4450-2828
China - Chengdu India - Pune
Technical Support: Fax: 45-4485-2829
Tel: 86-28-8665-5511 Tel: 91-20-4121-0141
http://www.microchip.com/
China - Chongqing Japan - Osaka Finland - Espoo
support
Tel: 86-23-8980-9588 Tel: 81-6-6152-7160 Tel: 358-9-4520-820
Web Address:
www.microchip.com China - Dongguan Japan - Tokyo France - Paris
Tel: 86-769-8702-9880 Tel: 81-3-6880- 3770 Tel: 33-1-69-53-63-20
Atlanta Fax: 33-1-69-30-90-79
Duluth, GA China - Guangzhou Korea - Daegu
Tel: 678-957-9614 Tel: 86-20-8755-8029 Tel: 82-53-744-4301 Germany - Garching
Tel: 49-8931-9700
Fax: 678-957-1455 China - Hangzhou Korea - Seoul
Austin, TX Tel: 86-571-8792-8115 Tel: 82-2-554-7200 Germany - Haan
Tel: 512-257-3370 Tel: 49-2129-3766400
China - Hong Kong SAR Malaysia - Kuala Lumpur
Tel: 852-2943-5100 Tel: 60-3-7651-7906 Germany - Heilbronn
Boston
Tel: 49-7131-72400
Westborough, MA China - Nanjing Malaysia - Penang
Tel: 774-760-0087 Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Germany - Karlsruhe
Fax: 774-760-0088 Tel: 49-721-625370
China - Qingdao Philippines - Manila
Chicago Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Germany - Munich
Itasca, IL Tel: 49-89-627-144-0
China - Shanghai Singapore
Tel: 630-285-0071 Fax: 49-89-627-144-44
Tel: 86-21-3326-8000 Tel: 65-6334-8870
Fax: 630-285-0075 Germany - Rosenheim
China - Shenyang Taiwan - Hsin Chu
Dallas Tel: 49-8031-354-560
Tel: 86-24-2334-2829 Tel: 886-3-577-8366
Addison, TX Israel - Ra’anana
China - Shenzhen Taiwan - Kaohsiung
Tel: 972-818-7423 Tel: 86-755-8864-2200 Tel: 886-7-213-7830 Tel: 972-9-744-7705
Fax: 972-818-2924 Italy - Milan
China - Suzhou Taiwan - Taipei
Detroit Tel: 39-0331-742611
Tel: 86-186-6233-1526 Tel: 886-2-2508-8600
Novi, MI Fax: 39-0331-466781
Tel: 248-848-4000 China - Wuhan Thailand - Bangkok
Tel: 86-27-5980-5300 Tel: 66-2-694-1351 Italy - Padova
Houston, TX Tel: 39-049-7625286
Tel: 281-894-5983 China - Xian Vietnam - Ho Chi Minh
Tel: 86-29-8833-7252 Tel: 84-28-5448-2100 Netherlands - Drunen
Indianapolis Tel: 31-416-690399
Noblesville, IN China - Xiamen Fax: 31-416-690340
Tel: 86-592-2388138
Tel: 317-773-8323 Norway - Trondheim
Fax: 317-773-5453 China - Zhuhai Tel: 47-7288-4388
Tel: 317-536-2380 Tel: 86-756-3210040
Poland - Warsaw
Los Angeles Tel: 48-22-3325737
Mission Viejo, CA
Romania - Bucharest
Tel: 949-462-9523 Tel: 40-21-407-87-50
Fax: 949-462-9608
Tel: 951-273-7800 Spain - Madrid
Tel: 34-91-708-08-90
Raleigh, NC Fax: 34-91-708-08-91
Tel: 919-844-7510
Sweden - Gothenberg
New York, NY Tel: 46-31-704-60-40
Tel: 631-435-6000
Sweden - Stockholm
San Jose, CA Tel: 46-8-5090-4654
Tel: 408-735-9110
Tel: 408-436-4270 UK - Wokingham
Tel: 44-118-921-5800
Canada - Toronto Fax: 44-118-921-5820
Tel: 905-695-1980
Fax: 905-695-2078

DS20001810G-page 52  2019 Microchip Technology Inc.

05/14/19