Computer Trainer Kit

By:

Muiad Salem Elias Yacoub

Presented to the Department of Computer Engineering

At Al-Balqa’ Applied University
Amman – Jordan

In Partial Fulfillment
Of the Requirement
For the Degree of
Bachelor in Computer Engineering

Al-Balqa’ Applied University

June 2004

I
Computer trainer kit

Supervisor: Dr Ziad Al Qadi

Approved: _______________
_______________
_______________

II
 Dedication
I would like to dedicate my work to my family to whom without such guidance,
love and support I would not write these words, and to my mentors who have entrusted in
and shared with me their knowledge and needed time, and to my supervisor, I also make
dedication to for his faith in my ability in completing this project and for his wisdom
throughout the process,
Sure I will not forget my boss at work, Mr. Radi Abdul-Hadi and all the company
family for supporting in my studied years.

III
 Acknowledgment
I would like first and foremost thank God for the knowledge and capability he
gave me in order to complete this project.
And secondly, I wish to acknowledge my appreciation to Dr Ziad Al-Qadi for his
shared advice and thoughts which have helped greatly in accomplishing a successful
finish.
And of course to my friends who were there to give helpful advice and suggestion
when at all possible.
And last but not least to my family who is always there to give all they can, thank you.

IV
 Abstract

Computerize Trainer is a practical learning tool specially designed to help student

to understand 16-bit microprocessor operation, programming and application, it helps
them to design and work with the computer for controlling and interfacing different
electrical and electronic circuit.
Computerize Trainer biased on the power of the personal computer to give student
the knowledge they need to work in micro controlling and interfacing with external
equipment using high level computer software.

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 Table of contents

Title Page

Dedication III
Acknowledgement IV
Abstract V
Table of contents IV
List of figures VII

1 Introduction 1
1.1 Motivation 2
1.1 The Trainer 2
2 Computer system 4
2.1 introduction 5
2.2 Basic of PC hardware 6
2.3 Birth of the PC 6
2.3.1 Choosing a processor 6
2.4 The Bus 7
2.4.1 Operation the PC Bus 8
2.4.2 AT Bus 8
2.4.3 Wait state 9
2.4.4 Problem with 16 bit board on the AT Bus 9
2.5 The processor 10
2.5.1 The PC’s brain 10
2.5.1.1 Intel 80xx series 10
2.5.2 Processor registers 11
2.5.2.1 Registry grouping 12
2.5.2.2 Common registers 13
2.5.2.3 Flag registers 14
2.6 Memory addresses 14
2.6.1 Address registers 15
2.6.2 Segment registers 15
2.6.3 Segment and offset address 16
2.6.4 Segment address 17
2.6.5 Segment address for program execution 17
2.6.6 Overlapping segments 18
2.6.7 Near and far pointers 18
2.6.8 Data type and their storage 19

VI
3 ISA SLOT 21
3.1 ISA overview 22
3.2 ISA signal description 22
3.3 ISA Bus timing diagram 26
3.3.1 8 bit I/O Bus cycle 26
3.3.2 8 bit Memory Bus cycle 26
3.3.3 16 bit I/O Bus cycle 26
3.3.4 16-Bit Memory Bus Cycles (1 or more Wait States 27
3.3.5 16-Bit Memory Bus Cycles (0 Wait State) 27
3.3.6 DMA Read 28
3.3.7 DMA Write 28
3.3.8 Alternate Bus Master Cycles 29
3.3.9 Memory Refresh Cycles 29
3.4 ISA Signal Usage 30
3.5 ISA Connector Pin out 32

4 Trainer Kit and The PC 33

4.1 Specification 34
4.2 Trainer Component 35
4.3 8255 PPI Unit 36
4.4 Computer description 38
4.5 Working Address 38

5 Circuit and Examples 39

5.1 Data lines, bits, nibbles, bytes, words, binary and HEX 40
5.2 Boolean Logic 43
5.3 Address Lines and Port 47
5.4 Example and Circuit 48
5.4.1 Controlling Motors 48
5.4.2 Digital To Analog Conversion. 54

Appendixes
Appendix A Table of Acronyms 60
Appendix B Glossary 62

VII
Chapter One

Introduction

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1 Introduction

1.1 Motivation:

An important application of computer science is that of using microcomputers to

control hardware systems. These are ubiquitous in electronic devices found almost
everywhere in modern society, and, in particular, in control systems and robots used in
industry, science, and defense. Many modern devices -- as common as microwave ovens
or automobiles, to machines that automate and control the positioning of electronic
components on printed circuit boards, to pilot-less airplanes used to spy on and/or deliver
weapon systems to potential enemy targets, to something as exotic as the Mars Sojourner
Rover robot -- use microprocessors to control hardware. It is important that computer
science students have the opportunity to learn about these devices, how they work, and
how to design and program them.

1.2 The Trainer

Computerize Trainer is a practical learning tool specially designed to help student

to understand 16 bit microprocessor operation , programming and application , it help
them to design and work with the computer for controlling and interfacing different
electrical and electronic circuit .
Computerize Trainer biased on the power of the personal computer to give student
the knowledge they need to work in micro controlling and interfacing with external
equipment using high level computer software.

By using computer facilities which is:

1- 16 bit microprocessor facilities throw ISA slot.
2- Using high level computer software languages
3- High speed in processing instruction.

The training board gives student the features for:

1- large breadboard for building experiment circuit
2- binary logic switch
3- 16 display status light emitting diodes (LEDs)
4- connectors block for solder less connection between part and wires
5- power supply output allow access to +5 , +12 , -5 , - 12 , GND
6- three I/O port using 8255

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 The trainer board is connected to computer throw interfacing board on ISA slot on the
motherboard, thus the trainer can be operated throw any computer software have a
facilities to access hardware port and system buss.
In this document I will illustrate

• The work of the PC hardware and operation instruction.

• ISA slot interface structure hardware and software
• Trainer board
o Component
o Circuit diagram
o Connection
• Software application.
• Example’s and application’s

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 Chapter Two

Computer System

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2 Computer system

To go ahead with the computer trainer kit illustration first I will give short information
about computer and microprocessor structure and architecture.

2.1 Introduction
Computers basically perform three functions: inputting data, processing the data and
outputting data. Some devices that are commonly used to input Information to a computer
is keyboards, DIP switches and joysticks. Common computer output devices are light
emitting diodes (LEDs), liquid Crystal displays (LCDs), video monitors, and printers. Disk
drives and modems are common devices that have both input and output characteristics.
To process the information obtained by the input devices and to control what
information will be sent to the output devices we must introduce the next lower level of a
computer; the microprocessor.
A microprocessor, which is also referred to as the central processing unit (CPU),
processes the information that is input to the computer and determines what data will be
sent to the output devices. The microprocessor has within it an arithmetic logic unit (ALU)
which performs addition, subtraction, comparisons and logical functions, which will be
discussed later.

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 One thing you must know about computers is that they don't really think like
people do. They can only do what the computer manufacturer or the computer user tells
them to do. The microprocessor can do many different things, but in order for something
useful to be done it must follow a group of instructions called a program. Below is a
"program" or a group of instructions that you could write which a person may follow in
order to quench their thirst.
1) Get a glass.
2) Get some milk from the refrigerator.
3) Pour the milk in the glass.
4) Drink the milk.
5) If you are still thirsty continue from step three.
6) Put glass in sink
7) Put milk in refrigerator.

In the same way, by knowing the microprocessor's language, you can give it a
group of instructions that it can perform and it would perform them exactly as you
commanded it. The microprocessor can only obey one instruction of a program at a time
and these instructions tell the microprocessor whether to input data, output data or perform
one of the ALU functions.

2.2 Basics of PC Hardware

In this section I will examine some of the basic concepts of PC architecture, which
lead all the way to the system programming level. Knowing something about the hardware
will make it easier to understand some of the programming problems and interfacing of
new hardware with the computer system
.

2.3 Birth of the PC

When the PC appeared on the market, much of what PC users take for granted
today was inconceivable. The concept of having a flexible computer on a desktop wasn't
new; companies much smaller than IBM had already introduced similar computers.
IBM had just completed work on its System/23 Data Master. However, the Data
Master was equipped with an 8085 8-bit processor from Intel, which was outdated. In
1980, the 16-bit processor was introduced and IBM began planning a new, revolutionary
machine.

2.3.1 Choosing a processor

The 8086 processor and 8088 processors from Intel were the first representatives of
the new 16-bit processors. Both had 16-bit registers. This meant they could access 1
megabyte memory addresses instead of the old 64K memory addresses. A megabyte was
an unimaginable amount of memory in 1980, just as 1 Gigabyte of RAM is still
unimaginable to many today.

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 Another reason developers were anxious to use the 8086 and 8088 processors was
that many support chips already existed.
Obviously this saved a lot of development time. Also, both processors were
supported by an operating system and an implementation of the BASIC language, which
was developed by Microsoft Corporation.
CPU

The developers chose the 8088 over the 8086 because, while the 8088 worked on a
16-bit basis internally, it only communicated with the outside world using an 8-bit data
bus. Since the 8-bit Data Master Data bus already existed, the 8088 was the obvious
choice. This bus connects the motherboard of the PC, where the processor and its support
chips are resident, to the memory and the expansion boards, which are plugged into the
expansion slots.

2.4 The Bus

Although the bus is vital to the operation of the computer system, the development
of the PC bus represents one of the darkest moments in the history of the PC. Although
IBM tried to create an open system and publish all technical information, it neglected to
document the exact sequence of the bus signals, probably assuming that no one would need
or want this information.
However, the openness of the PC and the option of easily adding expansion boards
and more hardware added to the PC's success on the market. Many users quickly took
advantage of this, buying IBM expansion boards and third-party Compatible boards. The
PC has its entire data and address bus on the outside; the bus connects to RAM, the various
expansions boards, and some support chips.

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2.4.1 Operating the PC bus

The bus is basically a cable with 62 lines, from which data are loaded into memory
by the processor, and through which data can be transported to the processor. The bus
consists of the data bus and the address bus. When memory is accessed, the processor puts
the address of the desired memory location on the address bus, with the individual lines
indicating a binary character. Each line can be only a 0 or a 1. Together, the lines form a
number that specifies the address of the memory location.
Twenty lines were available on the original address bus because with 20 bits you
can address 1 megabyte of memory, which corresponds to the processor's performance.
The actual data are sent over the data bus. The first data bus was only 8 bits wide,
so it could transfer only one byte at a time.
If the processor wanted to discard the contents of a 16-bit register or a 16-bit value
in memory, it had to split the register or value into two bytes and transfer one byte at a
time.
Although theoretically this sounds simple, it's a complicated procedure. Along with
the data and address buses, almost two dozen other signal lines communicate between the
processor and memory. All the boards communicate with the bus. When a board takes
responsibility for the specified address, it must send an appropriate signal to the processor.
At this point, all the other boards separate from the rest of the communication and wait for
the beginning of the next data transfer cycle.
Using expansion boards always leads to problems. This usually occurs when two
boards claim the same address range or there are overlapping address ranges. The DIP
switches on these boards let you specify the address range. One board must be
reconfigured to avoid conflict with the other board.

As a system programmer, you'll never encounter bus signals. Bus performance

usually isn't important to system programming. The bus signal timing is very important to
expansion board manufacturers. Their products must follow this protocol to function in
the PC. However, this is the protocol that IBM never published. So, the manufacturers
must measure the signal sequences by using existing cards and then imitate those cards.

2.4.2 AT bus

In 1991, the IEEE (Institute of Electrical and Electronic Engineers) submitted an

international standard for the AT bus. The PC bus was limited by its 8-bit width. When
the AT appeared on the market, it included a 16-bit bus that was compatible with
the older bus. That's why the old PC 8-bit boards can be used with the new 16-bit
boards in one device.
Obviously, the 16-bit boards are much faster because they can transfer the same
data in half the time it would take an 8-bit board.
The address bus was expanded to 24 bits, so the AT can address 16 megabytes of
memory. Also, higher clock signal speed increased bus transfer time. From 4.77 MHz on
the PC, the AT speed increased to 8 MHz. However, that's as fast as the AT address bus
can handle information, although Intel processor speeds have reached the 100 MHz limit.

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 As a result, the bus is a bottleneck, through which the data will never be transferred
quickly enough between memory and the processor. Modern hard drives have a higher
data transfer rate than the bus.

2.4.3 Wait state

The wait state signals found in some expansion boards give slow boards more
time to deliver data to the processor. This is also one reason why the AT bus resulted in
more powerful successors like the Micro Channel bus and the EISA bus, which Haven’t
been very successful on the market for other reasons. At first there wasn't a generic name
for the AT bus.
However, when competition appeared on the market, the bus was assigned the
name Industry Standard Architecture bus, or ISA bus.

2.4.4 Problems with 16-bit boards on the AT bus

Since many 386es and 486es have an ISA bus, many problems in the PC can be
traced to this bus. For example, the coexistence of 8-bit and 16-bit expansion boards
within a PC causes problems if the address range for which these boards are responsible
is located within any area of 128K.
The problem starts at the beginning of a data transfer when a 16-bit board has to
signal from a control line that it can take a 16-bit word from the bus and, unlike an 8-bit
board, doesn't depend on the transfer being split into two bytes.
However, the board must send this signal when it cannot even be aware the
address on the data bus is intended for it and requires an answer. Of the 24 address lines
that carry the desired address, only lines A17 to A23 have been correctly initialized to
this point. This means the board only recognizes bits 17 to 23. These bits cover a
complete 128K region, regardless of what might follow in address bits 0 to 16. So for the
moment, the board only knows whether the memory address is located in the 0K-127K
region, the 128K-255K region, etc.
If the 16-bit board sends the signal for a 16-bit transfer at this moment, it's
speaking for all other boards within this region. They experience this in the next moment,
because after address bits 0 to 16 have arrived on the bus, the intended board will be
determined. If it really is the 16-bit board, no problems occur. However, if an 8-bit board
was intended, the 16-bit board will simply separate from the rest of the transfer, leaving
the 8-bit board by itself.
However, the 8-bit board won't be able to manage the transfer because it's only set
for 8-bit transfers. So, the expansion board cannot accept the data as sent.

2.5 The Processor

You don't have to become a professional assembly language programmer to

understand system programming. You can also use high level languages, such as BASIC,
Pascal, or C, for system programming.

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 However, you must understand some concepts of the processor that are important
in system programming. These concepts, which overlap into high level language
programs, include the processor register, memory addressing, interrupts, and hardware
access.
Although these principles haven't changed much since the 8088 was introduced,
this chip is in its fifth generation and has capabilities that were unheard of ten years ago.
However, these changes relate to the processor's speed instead of its fundamental
concept.

2.5.1 The PC's brain

Let's discuss the family of Intel PC processors. The microprocessor is the brain of
the PC. It understands a limited number of assembly language instructions and processes
or executes programs in this assembly language. These instructions are very simple and
can't be compared to commands in high level languages, such as BASIC, Pascal, or C.
Commands in these languages must be translated into numerous assembly language
instructions the PC's microprocessor can then execute.
For example, displaying text with the BASIC PRINT statement requires the
equivalent of several hundred assembly language instructions.
Assembly language instructions are different for each microprocessor used in
different computers. The terms Z/80, 6502, or 8088 assembly language (or machine
language) refer to the microprocessor being programmed.

2.5.1.1 Intel's 80xx series

The PC has its own family of microprocessor chips, which were designed by the
Intel Corporation. The following figure shows the Intel 80xx family tree. Your PC may
contain an 8086 processor, an 8088 processor (used in the PC/XT), and an 80186
processor, an 80286 processor (used in the AT), or even an 80386 processor
microprocessor. The first generation of this group (the 8086) was developed in 1978. The
successors of the 8086 were different from the original chip. The 8088 is actually a step
backward because it has the same internal structure and instructions of the 8086, but is
slower than the 8086. The reason for this is the 8086 transfers 16 bits (2 bytes) between
memory and the microprocessor simultaneously. The 8088 is slower since it transfers
only 8 bits (1 byte) at a time.
The other microprocessors of this family are improved versions of the 8086.
The 80186 provides auxiliary functions.
The 80286 has additional registers and extended addressing capabilities.
The 80386 followed the 80286, and marks a great leap forward in performance.
However, it's already outdated, and you will hardly find 386es on the market any
more. This processor has advanced protected mode and 32-bit registers.
The 80386 includes SX and DX versions, which differ in clock frequency and
data bus width. The SX works with a 16-bit data bus, while the DX can transfer an entire
32-bit word at one time.

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 The 80486 (often simply called "486”) is no longer the most advanced processor.
It remains, however, very popular and sells in high numbers. It differs from the
80386 because it includes the 80387 math coprocessor, a code cache, and faster
processing of many assembly language instructions. However, the 486 also maintains
downward compatibility with the 8086.
The Pentium is today's most advanced processor. The main improvement in the
Pentium compared to the 486 is the internal processing speed. In specific situations, this
processor is able to process two sequential commands simultaneously, provided the
second command doesn't depend on the result of the first command.
The name of the processor, Pentium, is also new. Users were expecting the 80586.
Intel preferred to break with tradition, because names such as 8088 or 80586 cannot be
protected by copyright. Other chip manufacturers took advantage of this to sell Intel
compatible processors under similar names. Intel decided to take the wind out of the
competition's sails and came up with "Pentium", which is protected by copyright.
No one knows yet whether the Pentium will by followed by the "Hexium", but we
can start looking forward to the next generation of Intel processors, which will be
introduced in 1995.

2.5.2 Processor registers

Registers are memory locations within the processor itself instead of in RAM.
These registers can be accessed much faster than RAM. Registers are also specialized
memory locations. The processor performs arithmetic and logical operations using its
registers. The processor registers are important for system programming because the flow
of information between a program and the DOS and BIOS functions that call this
program occurs through these registers. From a system programming viewpoint, nothing
has changed in registers since the 8086. This is because the BIOS and DOS were
developed in connection with this processor, so they only support this processor's 16-bit

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 registers. The 32-bit registers of an 80386 and i486 cannot be used in system
programming under DOS. We'll discuss only 8088 registers, which apply to all later
chips.

All registers are 16 bits (2 bytes) in size. If all 16 bits of a register contain a 1, the
result, which is the decimal number 65535, is the largest number that can be represented
within 16 bits. So, a register can contain any value from 0 to 65535 (FFFFH or
1111111111111111b).

2.5.2.1 Register groupings

As the illustration above shows, registers are divided into four groups: common
registers, segment registers, the program counter and the flag register. The different
register assignments are designed to duplicate the way in which a program processes
data, which is the basic task of a microprocessor.
The disk operating system and the routines stored in ROM use the common
registers extensively, especially the AX, BX, CX, and DX registers. The contents of these
registers tell DOS what tasks it should perform and which data to use for execution.
These registers are affected mainly by mathematical (addition, subtraction, etc.)
and input/output instructions.
They are assigned a special position within the registers of the 8088 because they
can be separated into two 8-bit (1 byte) registers. Each common register usually contains
three registers: a single 16-bit register and two smaller 8-bit registers.

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2.5.2.2 Common registers

The common registers are important for calling DOS and BIOS functions and are
used to pass parameters to a particular function that needs these parameters for execution.
These registers are also influenced by mathematical operations (addition, subtraction,
etc.), which are the central focus of all software activities at processor level. Registers
AX, BX, CX, and DX have a special position within this set of registers, because they
can be divided into two 8-bit registers. This means that each of these registers consists of
three registers, one big 16-bit register and two small 8-bit registers.

The small registers have H (high) and L (low) designators. So, the 16-bit AX
register may be divided into an 8-bit AH and an 8-bit AL register. The H and the L
register designators occur in such a way the L register contains the lower 8 bits (bit 0
through 7) of the X register, and the H register contains the higher 8 bits (bits 8 through
15) of the X register. The AH register consists of bits 8-15 and the AL register consists of
bits 0-7 of the AX register.
However, the three registers cannot be considered independent of each other. For
example, if bit 3 of the AH register is changed, then the value of bit 11 of the AX register
also changes automatically. The values change in both the AH and the AX registers. The
value of the AL register remains constant since it is made of bits 0-7 of the AX register
(bit 11 of the AX register doesn't belong to it). This connection between the AX, the AH,
and the AL register is also valid for all other common registers and can be expressed
mathematically.
You can determine the value of the X register from the values of the H and the L
registers, and vice versa. To calculate the value of the X register, multiply the value of
the H register by 256 and add the value of the L register.

Example:
The value of the CH register is 10 and the value of the CL register is 118. The
value of the CX register results from CH*256+CL, which is 10*256+118 = 2678.

By specifying register CH or CL, you can read or write an 8-bit data item from or to any
memory location. Read or write a 16-bit data item from or to a memory location by specifying
register CX.

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2.5.2.3 Flag register

Besides common registers, segment registers and the flag register are an important
part of system programming. The flag register communicates between consecutive
assembly language instructions by storing the status of mathematical and logical
operations. For example, after using the carry flag to add two 16-bit registers, a program
can determine whether the result is greater than 65,535 and thus present it as a 32-bit
number. The sign, zero, and overflow bits perform similar tasks and can be used after two
registers have been compared to establish whether the value of the first register is greater
than, less than or equal to the value of the second register.
Only the carry flag and zero flag are important for system programming from
high level languages. Most DOS and BIOS functions use these flags to indicate errors for
insufficient memory or unknown filenames (see Chapter 2 for information on accessing
these flags from high level languages).

2.6 Memory addresses

How the processor generates memory addresses is especially important for system
programming, because you must constantly pass buffer addresses to a DOS or BIOS
function. In these instances, you must understand what the processor is doing. The 8088
and its descendants use a complicated procedure. So that you'll understand this
procedure, we'll discuss the origins of the 8086.
One of the design goals of the 8088 was to provide an instruction set that was
superior to the earlier 8-bit microprocessors (6502, Z/80, etc.). Another goal was to
provide easy access to more than 64K of memory. This was important because increasing
processor capabilities allows programmers to write more complex applications, which
require more memory. The designers of the 8088 processor increased the memory
capacity or address space of the microprocessor (more than 16 times) to one megabyte.

Flags of the flag register

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2.6.1 Address register

The number of memory locations that a processor can access depends on the
width of the address register. Since every memory location is accessed by specifying a
unique number or address, the maximum value contained in the address register
determines the address space. Earlier microprocessors used a 16-bit address register,
which enables users to access addresses from 0 to 65535. This corresponds to the 64K
memory capacity of these processors. To address one megabyte of memory, the address
register must be at least 20 bits wide. At the time the 8088 was developed, it was
impossible to use a 20-bit address register, so the designers used an alternate way to
achieve the 20-bit width. The contents of two different 16-bit numbers are used to form
the 20-bit address.

2.6.2 Segment register

One of these 16-bit numbers is contained in a segment register. The 8088 has four
segment registers. The second number is contained in another register or in a memory
location. To form a 20-bit number, the contents of the segment register are shifted left by
4 bits (thereby multiplying the value by 16) and the second number is added to the first.

15
2.6.3 Segment and offset addresses
These addresses are the segment address and the offset address. The segment
address, which is formed by a segment register, indicates the start of a segment of
memory. When the address is created, the offset address is added to the segment address.
The offset address indicates the number of the memory location within the segment
whose beginning was defined by the segment register. Since the offset address cannot be
larger than 16 bits, a segment cannot be larger than 65,535 bytes (64K).
Let's assume the offset address is always 0 and the segment address is also 0 at
first. In this case, you receive the address of memory location 0. If the segment address is
increased to 1, you receive the address of memory location 1 instead of memory location
16. This happens because the segment address is multiplied by 16 when addresses are
formed.
If you continue incrementing the segment address, you'll receive memory
addresses of 32, 48, 64, etc., if the offset address continues to be 0. According to this
principle, the maximum memory address is 1 megabyte when the segment address
reaches 65535 (FFFFH), which is its maximum value. However, if you keep the segment
address constant and increment the offset address instead, the segment address will
quickly become the base address for a memory segment from which you can reach a total
of 65,536 different memory locations. Each memory segment contains 64K. The offset
address represents the distance of the desired memory locations from the beginning of the
segment.
Although the individual memory segments are only 16 bytes apart, they contain
64K. So they obviously overlap in memory. Because of this, a memory address, such as
130, can be represented in various ways by using segment and offset addresses.

For example, you could specify 0 as the segment address and 130 as the offset address.
It's also possible to specify 1 as the segment address and 114 as the offset address or 2 as
the segment address and 98 as the offset address, etc. These overlapping segments are
easy to use. When you specify an address you can choose the combination of segment

16
 address and offset address yourself. You must obtain the desired address by multiplying
the segment address by 16 and adding the offset address to it; everything else is
unimportant. A segment cannot start at every one of the million or so memory locations.
Multiplying the segment register by 16 always produces a segment address that is
divisible by 16 (i.e., it's not possible for a segment to begin at memory location 22).

2.6.4 Segmented address

The segmented address results from the combined segment and offset addresses.
This segmented address specifies the exact number of the memory location that should be
accessed. Unlike the segmented address, the segment and the offset addresses are relative
addresses or relative offsets.
Combining the segment and offset addresses requires special address notation to
indicate a memory location's address. This notation consists of the segment address, in
four-digit hexadecimal format, followed by a colon, and the offset address in four digit
hexadecimal format. For example, in this notation a memory location with a segment
address of 2000H and an offset address of AF3H would appear as "2000:0AF3". Because
of this notation, you can omit the H suffix from hexadecimal numbers.

2.6.5 The segment register for program execution

The 8088 contains four important segment registers for the execution of an
assembly language program. These registers contain the basic structure of any program,
which consists of a set of instructions (code). Variables and data items are also processed
by the program. A structured program keeps the code and data separate from each other
while they reside in memory. Assigning code and data their own segments conveniently
separates them. These segment registers are as follows:
CS The CS (Code Segment) register uses the IP (Instruction Pointer) register as the
offset address. Then it determines the address at which the next assembly
language instruction is located. The IP is also called the Program Counter. When
the processor executes the current instruction, the IP register is automatically
incremented to point to the next assembly language instruction. This ensures the
instructions are executed in the proper order.
DS Like the CS register; the DS (Data Segment) register contains the segment
address of the data the program accesses (writing or reading data to or from
memory). The offset address is added to the content of the DS register and may be
contained in another register or may be contained as part of the current
instruction.
SS The SS (Stack Segment) register specifies the starting address of the stack. The
stack acts as temporary storage space for some assembly language programs. It
allows fast storage and retrieval of data for various instructions. For example,
when the CALL instruction is executed, the processor places the return address on
the stack. The SS register and either the SP or BP registers form the address that

17
 is pushed onto the stack. When accessing the stack, address generation occurs
from the SS register in conjunction with the SP or BP register.
ES The last segment register is the ES (Extra Segment) register. It's used by some
assembly language instructions to address more than 64K of data or to transfer
data between two different segments of memory.

With the help of the ES register, however, it's possible to leave the DS
register on the memory segment of the source area while referencing the target
area using the ES memory segment. The 8088 and its descendants even have
assembly language instructions that can copy an entire buffer by assuming, before
their execution, the segment address of the start area has been loaded into the DS
register and the segment address of the target area has been loaded into the ES
register. To copy the instructions also need the start of both areas within their
memory segments. They expect the start of the source area in the SI register and
the start of the target area in the DI register. Expressed in the notation introduced
earlier, these instructions copy data from DS: SI to ES: DI.

2.6.6 Overlapping segments

As the illustration on the following page shows, two segment registers can specify
areas of memory that overlap or are completely different from each other. Usually, a
program doesn't require a full 64K segment for storing code or data. So, you can conserve
memory by overlapping the segments. For example, you can store data, which
immediately follows the program code, by setting the DS and CS registers accordingly.

2.6.7 NEAR and FAR pointers

The numbers we've been calling memory addresses are called pointers in high
level languages. A pointer in the Pascal or C language receives the addresses of the
objects referenced by the pointers. If these addresses change location in memory, the
pointers also change. The two types of pointers are NEAR pointers and FAR pointers.
NEAR pointers specify the offset address of an object and are only 16 bits wide. Memory
cannot be accessed without a segment address. So the compiler prepares the segment
address, which it automatically loads, to the appropriate segment register when accessing

18
 the object. Because of this, NEAR pointer access is only possible for variables within the
64K segment created by the compiler.
FAR pointers consist of a segment address and an offset address, so they are
saved as two words. The low word receives the offset address and the high word receives
the segment address. In Turbo Pascal, pointers are VAR, while in C their type depends on
the memory model (see Chapter 2 for more information about pointers).

2.6.8 Data types and their storage

Bytes and words aren't the only data types you'll encounter in system
programming. You'll frequently encounter DWORDs (double words), which are used
when the 16 bits of one word aren't enough to store a number. For example, this applies
to the internal BIOS clock, which exceeds the 16-bit level of 65535 after a little more
than ten hours.

The members of the Intel 80xxx family place DWORDs in memory so the low
word (bits 0 to 15) precedes the high word (bits 16 to 31). This procedure is referred to as
the little endian format. This is different than the big endian format, which reverses the
order and is used by processors of the Motorola 68000 family (e.g., the Apple
Macintosh). The little endian principle also applies to word storage, in which the low
word is placed in front of the high word. Even with QWORDs (4 words), which are used
by the numerical coprocessor, the low-order DWORD (bits 0 to 31) is stored in front of
the high-order DWORD (bits 32 to 63). Then, within these two DWORDs, the high word
is placed in front of the low word, etc. The following illustration demonstrates this
principle:

19
Chapter Three

ISA Slot

20
21
3 ISA slot
3.1 ISA Overview
The Industry Standard Architecture or ISA, bus originated in the early 1980s at an
IBM development lab in Boca Raton, Florida. The original IBM Personal Computer
introduced in 1981 included the 8-bit subset of the ISA bus. In 1984, IBM introduced the
PC-AT which was the first full 16-bit implementation of the ISA bus.
The "AT bus", as IBM originally called it, was first documented in an IBM
publication called the PC-AT Technical Reference. The Technical Reference included
schematics and BIOS listings that made it easy for other companies like Compaq to
produce IBM compatible clones. The companies producing IBM compatibles could not
use the "AT bus" name however since IBM had protected it with a trademark. In
response, the industry coined "ISA" as a new name for the bus that was eventually
adopted by everyone including IBM.
Although the PC-AT Technical Reference included detailed schematics and BIOS
listings, it did not include the rigorous timings, rules, and other requirements that would
make it a good bus specification. As a result, the various implementations of ISA were
not always compatible with each other. Over time various ISA bus specifications were
produced in an attempt to alleviate the compatibility problems. But unfortunately these
specifications did not always agree with each other, so no single specification for the
ISA bus was ever developed.

3.2 ISA Signal Descriptions

SA19 to SA0
System Address bits 19:0 are used to address memory and I/O devices within the
system. These signals may be used along with LA23 to LA17 to address up to 16
megabytes of memory. Only the lower 16 bits are used during I/O operations to
address up to 64K I/O locations. SA19 is the most significant bit. SA0 is the least
significant bit. These signals are gated on the system bus when BALE is high and
are latched on the falling edge of BALE. They remain valid throughout a read or
write command. These signals are normally driven by the system microprocessor
or DMA controller, but may also be driven by a bus master on an ISA board that
takes ownership of the bus.

LA23 to LA17
Unlatched Address bits 23:17 are used to address memory within the system.
They are used along with SA19 to SA0 to address up to 16 megabytes of memory.
These signals are valid when BALE is high. They are "unlatched" and do not stay

22
 valid for the entire bus cycle. Decodes of these signals should be latched on the
falling edge of BALE.

AEN
Address Enable is used to degate the system microprocessor and other devices
from the bus during DMA transfers. When this signal is active the system DMA
controller has control of the address, data, and read/write signals. This signal
should be included as part of ISA board select decodes to prevent incorrect board
selects during DMA cycles.

BALE
Buffered Address Latch Enable is used to latch the LA23 to LA17 signals or
decodes of these signals. Addresses are latched on the falling edge of BALE. It is
forced high during DMA cycles. When used with AEN, it indicates a valid
microprocessor or DMA address.

CLK
System Clock is a free running clock typically in the 8MHz to 10MHz range,
although its exact frequency is not guaranteed. It is used in some ISA board
applications to allow synchronization with the system microprocessor.

SD15 to SD0
System Data serves as the data bus bits for devices on the ISA bus. SD15 is the
most significant bit. SD0 is the least significant bits. SD7 to SD0 are used for
transfer of data with 8-bit devices. SD15 to SD0 are used for transfer of data with
16-bit devices. 16-bit devices transferring data with 8-bit devices shall convert the
transfer into two 8-bit cycles using SD7 to SD0.

-DACK0 to -DACK3 and -DACK5 to -DACK7

DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge DMA requests on
DRQ0 to DRQ3 and DRQ5 to DRQ7.

DRQ0 to DRQ3 and DRQ5 to DRQ7

DMA Requests are used by ISA boards to request service from the system DMA
controller or to request ownership of the bus as a bus master device. These signals
may be asserted asynchronously. The requesting device must hold the request
signal active until the system board asserts the corresponding DACK signal.

-I/O CH CK
I/O Channel Check signal may be activated by ISA boards to request than an non-
maskable interrupt (NMI) be generated to the system microprocessor. It is driven
active to indicate a uncorrectable error has been detected.

23
I/O CH RDY
I/O Channel Ready allow slower ISA boards to lengthen I/O or memory cycles by
inserting wait states. This signals normal state is active high (ready). ISA boards
drive the signal inactive low (not ready) to insert wait states. Devices using this
signal to insert wait states should drive it low immediately after detecting a valid
address decode and an active read or write command. The signal is release high
when the device is ready to complete the cycle.

-IOR
I/O Read is driven by the owner of the bus and instructs the selected I/O device to
drive read data onto the data bus.

-IOW
I/O Write is driven by the owner of the bus and instructs the selected I/O device to
capture the write data on the data bus.

IRQ3 to IRQ7 and IRQ9 to IRQ12 and IRQ14 to IRQ15

Interrupt Requests are used to signal the system microprocessor that an ISA board
requires attention. An interrupt request is generated when an IRQ line is raised
from low to high. The line must be held high until the microprocessor
acknowledges the request through its interrupt service routine. These signals are
prioritized with IRQ9 to IRQ12 and IRQ14 to IRQ15 having the highest priority
(IRQ9 is the highest) and IRQ3 to IRQ 7 have the lowest priority (IRQ7 is the
lowest).

-SMEMR
System Memory Read instructs a selected memory device to drive data onto the
data bus. It is active only when the memory decodes is within the low 1 megabyte
of memory space. SMEMR is derived from MEMR and a decode of the low 1
megabyte of memory.

-SMEMW
System Memory Write instructs a selected memory device to store the data
currently on the data bus. It is active only when the memory decodes is within the
low 1 megabyte of memory space. SMEMW is derived from MEMW and a
decode of the low 1 megabyte of memory.

-MEMR
Memory Read instructs a selected memory device to drive data onto the data bus.
It is active on all memory read cycles.

-MEMW

24
 Memory Write instructs a selected memory device to store the data currently on
the data bus. It is active on all memory write cycles.

-REFRESH
Memory Refresh is driven low to indicate a memory refresh operation is in
progress.

OSC
Oscillator is a clock with a 70ns period (14.31818 MHz). This signal is not
synchronous with the system clock (CLK).

RESET DRV
Reset Drive is driven high to reset or initialize system logic upon power up or
subsequent system reset.

TC
Terminal Count provides a pulse to signal a terminal count has been reached on a
DMA channel operation.

-MASTER
Master is used by an ISA board along with a DRQ line to gain ownership of the
ISA bus. Upon receiving a -DACK a device can pull -MASTER low which will
allow it to control the system address, data, and control lines. After -MASTER is
low, the device should wait one CLK period before driving the address and data
lines, and two clock periods before issuing a read or write command.

-MEM CS16
Memory Chip Select 16 is driven low by a memory slave device to indicate it is
capable of performing a 16-bit memory data transfer. This signal is driven from a
decode of the LA23 to LA17 address lines.

-I/O CS16
I/O Chip Select 16 is driven low by a I/O slave device to indicate it is capable of
performing a 16-bit I/O data transfer. This signal is driven from a decode of the
SA15 to SA0 address lines.

-0WS
Zero Wait State is driven low by a bus slave device to indicate it is capable of
performing a bus cycle without inserting any additional wait states. To perform a
16-bit memory cycle without wait states, -0WS is derived from an address
decode.

25
 -SBHE
System Byte High Enable is driven low to indicate a transfer of data on the high
half of the data bus (D15 to D8).

3.3 ISA Bus Timing Diagrams

3.3.1 8-Bit I/O Bus Cycles

________
BALE __| |_________________________________________
_ ______________________________________________ __
SA (15:0) _><______________________________________________><__
-SBHE
______________ _______
-IOR/W |______________________________|
_____________
SD (7:0) -------------------------------------<_____________>-
(READ)
__________________________________
SD (7:0) ----------------<__________________________________>-
(WRITE)
__________________ _ _ _ _ _ _ _ _ _ _ _ _ _________
I/OCHRDY |________________________|

3.3.2 8-Bit Memory Bus Cycles

_____
BALE ________| |______________________________________
_ ________________ ________________________________
LA (23:17)_><________________><________________________________
_______ ________________________________________ __
SA (19:0) _______><________________________________________><__
______________ _______
-MEMR/W |______________________________|
_____________
SD (7:0) -------------------------------------<_____________>-
(READ)
__________________________________
SD (7:0) ----------------<__________________________________>-
(WRITE)
__________________ _ _ _ _ _ _ _ _ _ _ _ _ _________
I/OCHRDY |________________________|

26
3.3.3 16-Bit I/O Bus Cycles

________
BALE ______________| |_____________________________
_____________ __________________________________ __
SA(15:0) _____________><__________________________________><__
_________________ ___
-IOCS16 |_______________________________|
_____________________ ______
-IOR/W |________________________|
__________________
SD(15:0) -----------------------------<__________________>----
(READ)
________________________
SD(15:0) -----------------------<________________________>----
(WRITE)
_______________________ _ _ _ _ _ _ _ _ _ _ ______
I/OCHRDY |___________________|

3.3.4 16-Bit Memory Bus Cycles (1 or more Wait States)

______
BALE _________________| |____________________________
___ ________________________ ______________________
LA(23:17) ___><________________________><______________________
________________ ________________________________ _
SA(19:0) ________________><________________________________><_
_______ ______________________
-MEMCS16 |______________________|
________________________ ______
-MEMR/W |_____________________|
_______________
SD(15:0) --------------------------------<_______________>----
(READ)
_____________________
SD(15:0) --------------------------<_____________________>----
(WRITE)
__________________________ _ _ _ _ _ _ _ _ __________
I/OCHRDY |_______________|

27
3.3.5 16-Bit Memory Bus Cycles (0 Wait State)
______
BALE _________________| |____________________________
___ ________________________ ______________________
LA(23:17) ___><________________________><______________________
________________ _________________________ ________
SA(19:0) ________________><_________________________><________
_______ ______________________
-MEMCS16 |______________________|
_________________________ ______________________
-0WS |____|
________________________ ________________
-MEMR/W |___________|
______
SD(15:0) --------------------------------<______>-------------
(READ)
____________
SD(15:0) --------------------------<____________>-------------
(WRITE)

3.3.6 DMA Read

______________
DRQ(n) __| |___________________________________
_______________ __________
-DACK(n) |__________________________|
____________________________________
AEN,BALE ________| |_______
_______________ ___________________________ _______
SA(15:0) _______________><___________________________><_______
-SBHE
________________ ________________________ _________
SA(19:16) ________________><________________________><_________
LA(23:17)
____________________ __________
-MEMR |_____________________|
____________
SD(15:0) -------------------------------<____________>--------
______________________ ___________
-IOW |__________________|
__________
TC _______________________________| |__________
________________________ _____________________
I/OCHRDY |______|

28
3.3.7 DMA Write
______________
DRQ(n) __| |___________________________________
_______________ __________
-DACK(n) |__________________________|
____________________________________
AEN,BALE ________| |_______
_______________ ___________________________ _______
SA(15:0) _______________><___________________________><_______
-SBHE
________________ ________________________ _________
SA(19:16) ________________><________________________><_________
LA(23:17)
____________________ __________
-IOR |_____________________|
____________
SD(15:0) -------------------------------<____________>--------
______________________ ___________
-MEMW |__________________|
__________
TC _______________________________| |__________
________________________ _____________________
I/OCHRDY |______|

3.3.8 Alternate Bus Master Cycles

___________________________________
DRQ(n) __| |______________
_______________ __________
-DACK(n) |__________________________|
__________________ _______
-MASTER |__________________________|
__________________ _______
AEN ________| |__________________________| |_
_____________________________________________________
BALE ________| |_
________________________ ___________ ______________
SA(19:0) ________________________><___________><_______________
-SBHE
________________________ ___________ ______________
LA(23:17) ________________________><___________><______________

_____________________________ _________________
-IOR,-IOW |_____|
-MEMR,-MEMW
_____
SD(15:0) -------------------------------<_____>---------------

29
3.3.9 Memory Refresh Cycles
_______________ _______________
-REFRESH |_____________________|
_________________ ____________ ____________________
SA(9:0) _________________><____________><____________________
______________________ ________________
-SMEMR |_____________|
_________________________ _ _ _ _ ___________________
I/OCHRDY |_______|

3.4 ISA Signal Usage

Legend:
I/O = Input and Output
I = Input
O = Output
- = Signal not needed
An I/O shown in parentheses () indicates that the signal is Optional for this device.

The following table indicates typical signal usage by an ISA system board:

Signal Name System Board Usage Signal Name System Board Usage
AEN O -MEM CS16 I/O
BALE O -MEMR I/O
CLK O -MEMW I/O
-DACK O OSC O
DRQ I -REFRESH I/O
-IO CS16 I RESET DRV O
-I/O CH CK I SA I/O
I/O CH RDY I/O SD I/O
-IOR I/O -SBHE I/O
-IOW I/O -SMEMR I/O
IRQ I -SMEMW I/O
LA I/O TC I/O
-MASTER I -0WS I

30
The following table indicates typical signal usage by the various types of ISA expansion
boards:

ISA 16-bit ISA 8-bit

ISA Bus ISA 16-bit ISA 8-bit ISA DMA
Signal Name Mem Mem
Master I/O Slave I/O Slave Device
Slave Slave
AEN - - I - I -
BALE - I - (I) - -
CLK (I) (I) (I) (I) (I) (I)
-DACK I - - - - I
DRQ O - - - - O
-IO CS16 I - O - - -
-I/O CH CK (O) (O) (O) (O) (O) (O)
I/O CH RDY I (O) (O) (O) (O) -
-IOR O - I - I I
-IOW O - I - I I
IRQ (O) (O) (O) (O) (O) (O)
LA(23:17) O I - (I) - -
-MASTER O - - - - -
-MEM CS16 I 0 - - - -
-MEMR O I - (I) - -
-MEMW O I - (I) - -
OSC (I) (I) (I) (I) (I) (I)
-REFRESH (O) I - I - -
RESET DRV I I I I I I
SA(16:0) O I I I I -
SA(19:17) - (I) - (I) - -
SD(7:0) I/O I/O I/O I/O I/O I/O
SD(15:8) I/O I/O I/O - - (I/O)
-SBHE O I I - - -
-SMEMR - - - I - -
-SMEMW - - - I - -
TC - - - - - (I)
-0WS - (O) - (O) (O) -

31
3.5 ISA Connector Pin out

Signal Name Pin Pin Signal Name Signal Name Pin Pin Signal Name
Ground B1 A1 -I/O CH CK Key
RESET DRV B2 A2 SD7 -MEM CS16 D1 C1 -SBHE
+5 V dc B3 A3 SD6 -IO CS16 D2 C2 LA23
IRQ 9 B4 A4 SD5 IRQ10 D3 C3 LA22
-5 V dc B5 A5 SD4 IRQ11 D4 C4 LA21
DRQ2 B6 A6 SD3 IRQ12 D5 C5 LA20
-12 V dc B7 A7 SD2 IRQ15 D6 C6 LA19
-0WS B8 A8 SD1 IRQ14 D7 C7 LA18
+12 V dc B9 A9 SD0 -DACK0 D8 C8 LA17
Ground B10 A10 I/O CH RDY DRQ0 D9 C9 -MEMR
-SMEMW B11 A11 AEN -DACK5 D10 C10 -MEMW
-SMEMR B12 A12 SA19 DRQ5 D11 C11 SD08
-IOW B13 A13 SA18 -DACK6 D12 C12 SD09
-IOR B14 A14 SA17 DRQ6 D13 C13 SD10
-DACK3 B15 A15 SA16 -DACK7 D14 C14 SD11
DRQ3 B16 A16 SA15 DRQ7 D15 C15 SD12
-DACK1 B17 A17 SA14 +5 V dc D16 C16 SD13
DRQ1 B18 A18 SA13 -MASTER D17 C17 SD14
-REFRESH B19 A19 SA12 Ground D18 C18 SD15
CLK B20 A20 SA11
IRQ7 B21 A21 SA10
IRQ6 B22 A22 SA9
IRQ5 B23 A23 SA8
IRQ4 B24 A24 SA7
IRQ3 B25 A25 SA6
-DACK2 B26 A26 SA5
TC B27 A27 SA4
BALE B28 A28 SA3
+5 V dc B29 A29 SA2
OSC B30 A30 SA1
Ground B31 A31 SA0

32
Chapter Four

Trainer kit
And The PC

33
4 Trainer kit and The PC
The Trainer board figure (4-1) is a compact, 8086 based microprocessor system, designed primarily
for educational purposes. it contains a simple unit it make easy for student to build there own application
and circuit ,and give student the ability to handle computer I/O bus throw ISA slot. And it will give them a
good chance to learn more about how the computer works in low level lire.

4.1 Specifications

Computer system:
•
CPU Module ………………………………P II 350 MHZ
•
Motherboard………………………………Dell original
•
Display……………………………………14 inc digital
•
Keyboard , mouse ………………………..102 Key , Microsoft mouse
•
Memory ………………………………...64 MB RAM
•
Hard drive ……………………………….4 GB
•
Power connector…………………………ATX
•
Removal drives……………………….....CDROM , Floppy
•
NIC……………………………………...3 com fast Ethernet 10/100Mb
•
IO read data port for ISA plug and play enumerator
•
Interface card with 8255 PPI on ISA slot
•
Interface card direct on ISA slot
Training board figure (4-1)
• large breadboard for building the circuit
• I/O port …………………………three 8 bit I/O port throw 8255 PPI
• Output power supply ……………………+5, +12,-5,-12, GND.
• Logic indicator …………………….........16 green lead with separated
input terminal
• Logic switch …………………………….16 miniature on/OFF binary
switch in a dual in line package with separate input terminal
General
Power requirement …………………………………. 240 VAC, 50/60 Hz

34
 Figure (4-1)

o Component
o Circuit diagram
o Connection

4.2 Trainer Component

The trainer consists of the following circuit:

• Interface card: The function of this card is to interface the data but from
computer ISA Slot to trainer board kit
• Working kit: which hold all the other component:
• Dipswitch output
• LED indicator
• Breadboard
• Output power connectors
• Output of 8255 PPI circuit
• Output of ISA I/O line
• 8255 PPI Unit
All the connectors output is design to be used with jumper wire 0.4 mm to 0.8 mm.

35
4.3 8255 PPI Unit
PPI (Parallel Programmable Interface) is one of Intel interface controller family,
witch allow you to prepare parallel communication with external device or with other
computer systems.
The 8255 provide 3-buffers 8-bit input/output ports, Port-A, Port-B, and Port-C, for
Port-C you can divide this port to 2-Groups with 4-bit input/output ports.
To initiate the 8255, you must send it the control word, witch tells the PPI how to
work and in witch mode, you can make it work in three modes:
1- Mode 0 the basic input/output mode.
2- Mode 1 with handshaking, in this mode Port-C handles the handshaking
signals.
3- Mode 2, the BI-directional input/output and just for Port-A.

The card designed to plug in the ISA slot, to use the 8-bit data bus and 20-line
address bus
The 8255 chip was connected in the simple I/O mode. - All three ports is for input
or output – .there for data line and read and write and reset line connected directly with
data bus , and address line to go circuit selection line to define a unique address for the
I/O port of the chip .
The circuit can be initialized by the command OUT 80hex to the word control
register of the 8255 chip .

36
 Base address selection is made by three DIP switch sections connected to a 74LS688 8-
bit magnitude comparator, chosen because it offers a simple, straight-forward way of decoding
the DIP switches:

74LS688 8-bit magnitude comparator

Figure 4-2

37
4.4 Computer description
The trainer kit is connected to Pentium II PC, with 350 MHZ microprocessor
The computer is provided with windows 98 operating system and with all software program
student need to work with trainer kit such:
1- Turbo C
2- Visual C++
3- Q basic
4- Assembly language

4.5 Working address

One of the important thing should student know when they build their circuit is to chose an
address to his circuit or application, to find available address we can check that from
Computer properties, for example: for next figure we can find an available address range at 0300
– 032f,
So we can build our circuit or application, at this address and sure we will not have any
conflict in the hard ware with any other resources in the computer

38
 Chapter Five

Circuit and examples

39
5 Circuit and examples

5.1 Data lines, bits, nibbles, bytes, words, binary and HEX

This chapter hands-on experiment to show the basics of how real things in the real world
are controlled with computers that means it's about most of the computers in the world. Most
computers don't sit on desks, but are used to control things that don't look anything like a
computer, such as factories, spacecraft, toys and appliances. This site provides the opportunity to
learn basic control and embedded system concepts while taking advantage of the low cost and
convenience of using a PC as a platform.

I will explain about monitoring and controlling such things as motors, lights and switches,
or recording and playing everything from sound to the arm position on a robot.

Data inside a computer, as well as on the board used in this tutorial, is exchanged among
the various components by means of metallic conductors called data lines. A group of data lines
is called a data bus.
Each data line carries a unit of data called a bit. A bit can be on or off. On is typically
considered to be 5 volts, and off is considered to be 0 volts, although modern systems often use
lower on voltages to decrease power consumption.
Data can be represented on paper as a series of ones and zeros. A one means a bit is on, and a
zero means it is off. A group of 8 bits is called a byte. A byte with a value of 0 would be
represented as 00000000. Non-zero bytes can be any combination of 1s and 0s. 01100010 will be
used as an example here. In the C language, a byte is called a character and is abbreviated char.
When data is represented as a series of ones and zeros, it is said to be a binary
representation, or to have a base of 2 because it uses 2 digits.
The left-end bit of a number represented in binary is called the most significant bit, abbreviated
msb, and the right-end bit is called the least significant bit, abbreviated lsb.
A little review might be helpful to those who are a little rusty on raising a number to a power. No
high maths here -- to raise a number to a power just writes it down the exponent number of times
and multiplies. The exponent is the power to which a number is raised. One way to recognize an
exponent is by the fact that it is often raised when written:

52 = 5 * 5 = 25
23 = 2 * 2 * 2 = 8
44 = 4 * 4 * 4 * 4 = 256

Each bit position has a weight. For all numbering systems I am aware of (the
mathematicians probably know of others), the right, least-significant position is known as the 1's
place. There, the weight is equal to the base raised to the power of 0. Any number raised to the
power of 0 is equal to 1.
The exponent is increased by 1 with each move to the left. Thus, the second place from
the right has a weight equal to the base raised to the power of 1. Any number raised to the power

40
of 1 is equal to itself. We were taught in grade school that the second place from the right is the
10's place. That's because we were using a base of 10 and we were raising it to the power of 1.
Since a base of 2 is used in binary, the second place from the right has a weight of 2 because it is
2 raised to the power of 1. The next weight is 22 = 4, then 23 = 8 and so on.
The exponents are often used to designate a bit in a binary number. Bit 0 is on the right
end of the byte and bit 7 is on the left end. Bit 0 is the lsb and bit 7 is the msb. Data bits are
often abbreviated using the letter D -- D0, D1, D2, etc.

Bit D7 D6 D5 D4 D3 D2 D1 D0
exponent 7 6 5 4 3 2 1
Base 2 2 2 2 2 2 2 20
Weights 128 64 32 16 8 4 2 1

The example binary number above was 01100010. To figure out what the decimal value
is, simply add the weights for the bits that are turned on. In this case, bits 6, 5 and 1 are on. The
total of their weights equals 64 + 32 + 2 = 98.
A more general description of the procedure is to multiply the position weights by the
values at the positions, then add them up. The example 01100010 would be:
(0 * 128) + (1 * 64) + (1 * 32) + (0 * 16) + (0 * 8) + (0 * 4) + (1 * 2) + (0 * 1) = 98.
A common way of representing numbers in a C program is to use hexadecimal notation,
or HEX. It uses a base of 16. Break a byte into two groups of 4 bits each: nnnn nnnn. Each
group is called a nibble. A nibble with all low bits, 0000, is equal to 0. With all of its bits turned
on, 1111, a nibble has a value of 15 (8 + 4 + 2 + 1). Thus, we are dealing with the 16 values from
0 through 15, and a base of 16.
Hexadecimal notation is simple. Just use digits for 0 through 9, and A through F for 10
through 15. The following table shows all of the combinations.

Binary Decimal Hexadecimal Binary Decimal Hexadecimal

0000 00 0 1000 08 8
0001 01 1 1001 09 9
0010 02 2 1010 10 A
0011 03 3 1011 11 B
0100 04 4 1100 12 C
0101 05 5 1101 13 D
0110 06 6 1110 14 E
0111 07 7 1111 15 F

The right nibble of a byte is the least significant nibble. It's the 1's place because it's 160.
Next is the 16's place because it's 161, then 162 = 256, and so on. To get the decimal value, take
the value of the nibbles, multiply by the position weight values and add them up. Thus, the HEX
value 9B = (9 * 16) + (11 * 1) = 155.

41
To show a number is hexadecimal in the C language, prefix it with 0x. The above would be
represented as 0x9B or 0x9b. This particular notation is not case-sensitive, although many things
in C are.

The following shows the byte table again, but this time with the weights also expressed in
hexadecimal notation, as often seen in C operations.

Bit D7 D6 D5 D4 D3 D2 D1 D0
Baseexponent 27 26 25 24 23 22 21 20
Weights 128 64 32 16 8 4 2 1
HEX Weights 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01

A word is usually 16 bits, D0 through D15. A table with the bit names and their
relationship to the binary base of 2 is below.

Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Baseexponent 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20

The following two tables show the bits with their HEX weights.

Bit D15 D14 D13 D12 D11 D10 D9 D8

HEX Weights 0x8000 0x4000 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100
Bit D7 D6 D5 D4 D3 D2 D1 D0
HEX Weights 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001

A word can be broken up into 4 nibbles. It can be represented by showing its 4 nibbles as
a 4-place hexadecimal number. For example, the decimal number 19070 can be represented as
the hexadecimal number 0x4A7E.

0x4A7E = (4 * 163) + (10 * 162) + (7 * 161) + (14 * 160)

= ( 4 * 4096) + (10 * 256) + (7 * 16) + (14 * 1)
= 19070.

In the C language, a word is most often called an integer, abbreviated int. An integer can
be used to represent numbers that range from negative to positive values, or numbers that have
only positive values. In other words, an integer can be signed or unsigned. A signed integer can
have either positive or negative values. An unsigned integer can only be positive. An unsigned
16-bit integer can have values from 0 through 65535. It is often abbreviated simply as unsigned.
Bit 15 is used as a sign bit for signed integers. If it is on, the number is negative. If it is
off, it is positive. Positive values can range from 0 to 32767. Negative values can range from -1
to -32768. Some examples are shown below. Notice that the signed version is equal to -1 *
(65536 - unsigned version). For example, to get the signed number from the unsigned value

42
49151,
signed = -1 * (65536 - 49151) = -16385.

HEX 8000 BFFF FFFE FFFF 0000 3FFF 7FFE 7FFF

Signed -32768 -16385 -0002 -0001 00000 16383 32766 32767
Unsigned 32768 49151 65534 65535 00000 16383 32766 32767

A long word is generally considered to be 4 bytes or 32 bits. A long is used for very large
numbers. Longs can also be signed or unsigned. Signed longs have a range from -2,147,483,648
to 2,147,483,647. The maximum unsigned value is 0xFFFFFFFF = 4,294,967,295. The
minimum unsigned value is 0.

5.2 Boolean Logic

Control and embedded systems frequently deal with individual bits in order to control
specific operations or to determine the condition of part of a system. For example, a bit might be
turned on to light a lamp or activate a relay, or a bit might be off to indicate a switch is on (off
meaning on is very common due to the nature of hardware -- order some and see what I mean).

Boolean logic, developed by George Boole (1815-1864), is often used to refine the
determination of system status or to set or clear specific bits. Boolean logic is simply a way of
comparing individual bits. It uses what are called operators to determine how the bits are
compared. They simulate the gates that you will see in the hardware section you will read
shortly.

Think of operators as boxes with multiple inputs and one output. Feed in various
combinations of bit values, and the output will be high or low depending on the type of
operation. The examples show 2 inputs, although gates can have more. Also, gates are often
combined to form more complex logic. A modern microprocessor contains huge numbers of
them with many inputs and many varying combinations. Please note that the terms on, high and
1 will be considered the same logical state, and off, low and 0 will be considered the same
logical state in the discussions that follow.

The operators used most often are AND and OR. The AND operation says if and only if
all inputs are on, the output will be on. The output will be off if any of the inputs are off. The
OR operation says if any input is on, the output will be on. It's easy to see all of the
combinations by using what are called truth tables, illustrated below. At the bottom of each
table is shown the schematic symbol found in circuit diagrams.

43
AND (all high = high, else low) OR (any high = high, else low)
Input 1 Input 2 Output Input 1 Input 2 Output
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1

There are two operations that have the same logic as above, but with an inverted output.
The NAND operation says if and only if all inputs are on, the output will be off. The output will
be on if any of the inputs are off. The NOR operation says if any input is on, the output will be
off. Notice the bubble on the output of the schematic symbol used to indicate an inversion.

NAND (all high = low, else high) NOR (any high = low, else high)
Input 1 Input 2 Output Input 1 Input 2 Output
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0

There is a variation on the OR logic called Exclusive OR or XOR. Exclusive OR says

the output will be on if the inputs are different.

Another one, the inverter or NOT operation, says that the output will be opposite in state
to the input. It obviously has only one input and one output. Note that it will change an AND to a
NAND, an OR to a NOR and an XOR to a NXOR if connected to their outputs. It simply
changes 1s to 0s and 0s to 1s.

44
XOR (different = high, same = low)
Input 1 Input 2 Output
NOT (inverter)
0 0 0
Input = 1 Output = 0
0 1 1
Input = 0 Output = 1
1 0 1
1 1 0

One other basic digital device is on the board. It actually performs no logic. It looks like
an inverter without the bubble, and is called a buffer. It's a triangle with a single input and
output. It is not used for logic, but to increase the output drive capability of a line, or to lighten
the load seen by circuits outside of ours. This is sometimes called repowering. Some buffers
have a third line entering the side of the triangle. When it is not activated, the output of the buffer
is removed from the circuit to keep it from interfering with other devices. The 74LS244 is an
example:

In C, symbols are substituted for the full description or abbreviation of a Boolean

operation. They are as follows for the operations covered:

Logical Operation Abbreviation Symbol

And AND &
Or OR |
Exclusive OR XOR ^
Inversion NOT ~

It is common in the C language to perform logical operations on bytes or words.

Combinations of on and off conditions are often important determinants of condition, and the use
of logical combinations as outputs can be used to cause complex actions. To determine the result
when logical operations are applied to larger variable types, simply work with one bit at a time.
Some examples follow. The numbers are presented in both hexadecimal and binary form. The
top line shows an equation illustrating the operation in hexadecimal notation and the symbol
used in C. It is not a C statement, but simply an illustration of the action taken the three lines

45
following it show the numbers used in the operation and the result in both HEX and binary. The
first example is expanded to show how the result is determined one bit at a time.

0xC1 & 0xEA = 0xC0 (this says 0xC1 AND 0xEA = 0xC0)

0xC1 11000001 (the two nibbles are 1100 = 12 = 0xC and 0001 = 1 = 0x1)

0xEA 11101010

0xC0 1 1 0 0 0 0 0 0
| | | | | | | |_ 1 AND 0 = 0
| | | | | | |__ 0 AND 1 = 0
| | | | | |___ 0 AND 0 = 0
| | | | |____ 0 AND 1 = 0
| | | |_____ 0 AND 0 = 0
| | |______ 0 AND 1 = 0
| |_______ 1 AND 1 = 1
|________ 1 AND 1 = 1

0x00 & 0x86 = 0x00 (this says 0x00 AND 0x86 = 0x00)
0x00 00000000
0x86 10000110
0x00 00000000 (Think, "This bit will be on
only if both of the ones above it are on.")
0x88 & 0xE0 = 0x80 (this says 0x88 AND 0xE0 = 0x80)
0x88 10001000
0xE0 11100000
0x80 10000000

0xC0 | 0xAD = 0xED (this says 0xC0 OR 0xAD = 0xED)

0xC0 11000000
0xAD 10101101
0xED 11101101 (Think, "If either one of the bits above is on,
this one will be on.")
0xAD | 0xEF = 0xEF (this says 0xAD OR 0xEF = 0xEF)
0xAD 10101101
0xEF 11101111
0xEF 11101111
0xC4 | 0x84 = 0xC4 (this says 0xC4 OR 0x84 = 0xC4)
0xC4 11000100
0x84 10000100
0xC4 11000100

0xD4 ^ 0x8D = 0x59 (this says 0xD4 XOR 0x8D = 0x59)

0xD4 11010100
0x8D 10001101

46
0x59 01011001 (Think, "This bit will be on only if the two above it are
not the same.")
0xDA ^ 0x87 = 0x5D (this says 0xDA XOR 0x87 = 0x5D)
0xDA 11011010
0x87 10000111
0x5D 01011101
0xAB ^ 0xFC = 0x57 (this says 0xAB XOR 0xFC = 0x57)
0xAB 10101011
0xFC 11111100
0x57 01010111

~0x86 = 0x79 (this says 0x86 inverted = 0x79)

0x86 10000110
0x79 01111001 (Think, "This is all of the bits above reversed.")
~0xC1 = 0x3E (this says 0xC1 inverted = 0x3E)
0xC1 11000001
0x3E 00111110
~0xEA = 0x15 (this says 0xEA inverted = 0x15)
0xEA 11101010
0x15 00010101

5.3 Address Lines and Ports

Data inside a computer is accessed by means of metallic conductors called address lines.
Each of them carries a bit of information, the same as a data line. A group of address lines is
called an address bus. Just as with data, a bit can be on or off, and addresses can be represented
on paper as a series of ones and zeros.
Addresses are seldom represented in binary, however. They are almost always shown in
HEX with the 0x prefix. An exception is in the schematic diagram. Individual lines are often
drawn and labeled with abbreviations using the capital A -- A0, A1, A2, etc.
Any time a variable or constant is accessed in the C language, the appropriate address lines
are activated. This is not readily apparent since variables and constants are almost always
referenced by name. It's a lot easier to work with words than with obscure memory addresses.
There is a way to more directly access address space in C. It's through the powerful concept of
pointers,

The PC actually has two memory systems. One deals with variables and constants as noted
above. The other addresses what are called ports. Ports provide access to outside-world devices.
The printer, serial communications, disk drives and sound cards, among others, all use ports for
monitoring and control. A typical PC uses A0 through A9 as the bases for addressing ports, with
A9 always high. That means that the range of port addresses is 0X200 through 0X3FF:

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 0 0 = 0X200 minimum port address

47
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 1 1 1 1 1 1 = 0X3FF maximum port address

The board used in the examples is capable of using all of these addresses in 64 byte
blocks. Subdivisions within each block allow access to several sub-systems on the board. All of
them will be covered in detail in the hardware and experiments sections.
Port read or write status depends on the state of the Input/Output Read and Write lines,
which are dedicated to port activities. The appropriate line must be low. If both are high, then
port I/O will not take place. The Input/Output Read line is abbreviated IOR, and the
Input/Output Write line is abbreviated IOW. In addition to IOR or IOW, a line called Address
Enable (AEN) must be low for port access.

5.4 Example and circuit

5.4.1 Controlling Motors

More current is needed for things such as motors, relays and solenoids. Even a
small motor draws more current than the PPI or a small transistor can provide. A power
device is called for.
One such device is the TIP120, a Darlington transistor:

A Darlington is actually two transistors. Notice that the emitter of the first
transistor is connected to the base of the second. That causes their current gains to be
multiplied, giving the TIP120 an hfe of about 1000. The base to emitter resistors is built
into the package.
The TO-220 package has a metal tab with a hole in it which can be used to bolt
the TIP120 to a piece of metal called a heat sink, used to pull heat away from the
package. The tab is connected to the collectors of the transistors though, so if the heat
sink is grounded the tab must be insulated from the heat sink but still conduct heat to it.
That's accomplished with special materials made for the job. A heat sink is not needed for
this experiment. Notice that the positions of the Base, Collector and Emitter are not the
same as they were on the PN2222. The diode connected from collector to emitter will be
discussed shortly.

48
 Let's say we want to power an electric motor that needs about 1 Amp, such as the
Radio Shack 273-223. With a current gain of 1000, we need only drive the base with 1ma
(1ma * 1000 = 1A). The full 2.5ma capability of the 82C55 will be used however, in
order to make certain plenty of current is delivered to the motor. The voltage between the
base and emitter is about two diode drops, or about 1.4V. If we say we can provide 3V,
our resistor has 3 - 1.4 = 1.6V across it. The value of the resistor would then be:

R = V/I = 1.6/2.5ma = 640

The closest standard value is 620 ohms, but 560 ohms is easier to find.
The power is: P = 1.62/560 = 4.57mw so any normal rating is OK.
Re-calculate the current:

I = V/R = 1.6/560 = 2.857ma plus a little

This circuit should deliver the full 2.5ma to the base of the TIP120 that times
1000 are 2.5 amps. The TIP120 is being asked to provide only half of its maximum 5
amps current. A 4.7K pull down resistor from the output of the PPI to ground is added to
make certain the PPI line goes low when it's supposed to

A short discussion of magnetism and motors will be helpful to explain the need
for the diodes in the circuit. Incidentally, diodes such as these handle high powers and are
usually called rectifiers. A 1N4001 for example, can handle 1 amp at 50V or 50W
(although I wouldn't advise pushing one that hard), compared to the 1N4148, which is
rated at only about 500mw maximum.

49
 Just about everybody played with magnets in grade school. From that experience
it was discovered that opposite poles of magnets attract and like poles repel. We were
told later that an electromagnet could be formed by running electrical current through a
wire wrapped around a piece of iron. By using a direct current, such as that from a battery
or the 5V power supply of a computer, the piece of iron will have fixed North and South
poles just like a permanent magnet. It will be attracted to and repelled from a permanent
magnet in the same manner as another permanent magnet. A motor can be constructed
using that knowledge.

I will cover only the basic ideas of motor operation here. Notice what will happen
when an electromagnet is placed inside a permanent magnet (wrap the fingers of your left
hand around the electromagnet in the direction of the current and your thumb will point
to North). The electromagnet is mounted on an imaginary shaft to allow it to rotate:

The opposite poles will attract, and the like poles will repel, so the electromagnet
will rotate:

50
 Now turn off the power long enough to let the electromagnet coast a little, then
turn it back on, but with the polarity reversed. The whole process starts over:

The rotating electromagnet is called the armature. The switch used to reverse
polarity is formed by brushes which connect to the coil by sliding over curved pieces of
metal. Together the curved pieces of metal are called the commutator. They are bonded to
an insulator on the shaft going through the armature.

In addition to producing mechanical movement, magnetism can also produce

voltage. If a wire moves at right angles through a magnetic field or a magnetic field
moves across a wire, a voltage will be produced in the wire. The magnitude of the voltage

51
 depends on the velocity of the wire or field, among other things. A magnet is formed
when voltage is applied to the motor. A magnetic field exists around the armature just as
it would around a permanent magnet. When the voltage is turned off, the magnetic field
rapidly collapses. Since the field collapses in the opposite direction from which it was
initiated, the voltage is reversed. It can be quite high compared to the powering voltage;
enough to damage components connected to it.

We are providing one side of the motor with 5 volts. The TIP120 will take the
other side near ground (actually about 1 volt above ground). Note that the 1N4001 will be
reverse biased when the motor is turned on since its cathode is more positive than its
anode.

A relatively large voltage spike of short duration will occur when the motor is
turned off that is opposite in polarity to the applied voltage. The TIP120 side will be
significantly more positive than the 5V side. This will forward bias the 1N4001 which
will short out the spike, protecting the TIP120 and other circuitry. I measured peaks as
high as 100 volts across the Radio Shack motor. Please do not leave out spike
protection rectifiers! The diode that is built into the TIP120 also helps by shorting
negative spikes to ground. Another term for voltage is Electromotive Force or EMF.
The large reverse voltage spike seen when power is removed from a coil is often called
Back EMF.

The program function:

52
void motor(long on, long off)
{
int x;
long y,z;

printf("ON ");
outp(ppi_porta, 0xff);
for(y=0L; y<on; y++);

printf("OFF ");
outp(ppi_porta, 0);
for(z=0L; z<off; z++);
}

// turn port a on
void portaon(void)
{
outp(ppi_porta, 0xff);
}

// turn port a off

void portaoff(void)
{
outp(ppi_porta, 0);
}

// set up the ppi according to the dictates of the mode argument

void set_up_ppi(int mode)
{
unsigned control = base + 0x23;
int command;

mode>>=6; // shift the mode value to the right 6 places

command = (mode & 0x0c) << 1; // shift bits 2 and 3 into positions 4 and 5
command += (mode & 3); // add in bits 0 and 2
command |= 0x80; // OR in bit 7 for PPI set up

outp(control, command); // set according to mode command

} // end set_up_ppi()

53
5.4.2 Digital To Analog Conversion

There is frequently a need to convert digital information into a voltage or current.

As noted in Data lines, bits, nibbles, bytes, words, binary and HEX, digital data
changes in steps. Turning on or off a bit increases or decreases a digital quantity.
The following circuit, derived from the DAC0832 digital to analog converter
(DAC) datasheet, is one approach to making the conversion from stepwise digital
information to a voltage. It's called an R 2R ladder and is part of the circuit used in the
two DAC0832s on the board. R and Rfb are about 15K ohms, which makes 2R about
30K ohms. The actual values are not as important as the fact that the resistors are very
closely matched to each other.
The "1" and "0" indicate the positions of MOSFET switches in the converter. A
switch will connect to the "1" side if the corresponding bit is on, and to the "0" side if the
bit is off. A switch connected to the "1" position will send a portion of Vref-derived
current to Iout1, whereas a switch connected to the "0" position will send a portion of the
current to Iout2.

To see how the R 2R ladder fits into the scheme of things, consider the following.
The left side is a copy of one of the DAC0832 sections taken from the board's schematic.
On the right is a simplified block diagram of the same thing, derived from the datasheet.
Rfb is drawn in the manner shown to indicate it is internal to the DAC but can be
accessed outside and be connected the Op-Amp:

Iout1 of the R 2R ladder is connected to the inverting input of the Op-Amp Iout2
of the R 2R ladder is connected to the non-inverting input and to ground. One end of the
internal Rfb feedback resistor is connected to the output of the external Op-Amp. The

54
other end is internally connected to the R 2R ladder's Iout1 as shown above. Thus, it is
connected from the output of the Op-Amp to the inverting input.
Recall that the Op-Amp will attempt to cancel any current through the inverting
input. To do so, it will cause the current in the feedback resistor to be equal to the current
in the inverting input resistor, but with an inverted polarity:

Since the currents are equal but opposite, they cancel each other out, resulting in 0
volts at the inverting input. Thus, the inverting input is at the same potential as ground.
This generated ground equivalent is termed a virtual ground.
Here is what we know and what can be derived from it:

Ifb = -Iin

The voltage on the left side of Rfb is 0 due to the virtual ground, so the voltage on
the right is the voltage drop across Rfb, which is Vout = Rfb * Ifb.

Since Ifb = -Iin, that also means that Vout = Rfb * -Iin

The current being canceled at the inverting input in the block diagram above is
Iout1. Thus, Vout = Rfb * -Iout1. The datasheet says Vout = -(Iout1 * Rfb), which is the
same thing.

The board uses -5V from the computer as the reference voltage. Consider the case
where the only the MSB is turned on (see Data lines, bits, nibbles, bytes, words, binary
and HEX for a definition of MSB). The only resistor connected to Iout1 is the 2R
resistor on the left end of the ladder. Since 2R = 30K and Rfb = 15K and Vref = -5V, we
now have this:

Now Vout = -(-5V) * (15K /30K) = 2.5V

55
 Remember that the MSB has a weight of 128. The data sheet also says that
Vout = -(Vref * (Digital Input)10)/256 (the 10 means "base 10 number").
In the case of the MSB input,

Vout = -(-5V * 128)/256 = 2.5V, which agrees with the previous voltage calculations.
Getting rid of the double negatives and generalizing the numbers gives this:

Vout = (5 * DAvalue)/256, where DAvalue is the base 10 number output to the converter.
A value of 1 will provide the voltage per step:

Vout = (5 * 1)/256 = .01953125 volts

That would be true in a perfect world. There is however, no such thing as perfect
in this world, despite the claims of some I have known regarding their own attributes. See
the datasheet for a discussion of linearity.

The MSB case is relatively easy. Others require a bit more thought. They are also
useful as exercises in a little circuit analysis. For example, consider the case where only
bit 6 is high. The bit 6 MOSFET is switched to "1". All of the other bits will be
connected to "0", which ends up at ground. The circuit will look like this, including the
external Op-Amp and using the nominal resistor values from the datasheet:

The current through R1 does not influence the current referenced at the inverting
input. Although one end is connected to the -5V reference, the other end simply goes to
ground, so the current through R1 never even makes it to the inverting input.

All of the other resistors do contribute to the current at the inverting input and to
the output of the amplifier. The current through R2 splits into two paths. One is through
R3 which goes directly to the inverting input, and the other is through the network of R4

56
and all of the other resistors to ground. The method to determine their composite value is
more easily seen if the R4 part of the drawing is reorganized. A careful study will show
that only the drawing has changed. The circuit is the same:

First consider the two 30K resistors on the bottom. Recalling the parallel resistor
equation:
Rparallel = 1/(1/30K + 1/30K) = 15K ohms

A tip: the parallel value of resistors of the same value is the value of one of the
resistors divided by the number of resistors.

The 15K parallel combination adds to the 15K above it since it is in series with it.
Again,
Rseries = 15K + 15K = 30K ohms

This 30K combination is in parallel with the 30K to the left of it, which produces
15K again which adds to the 15K above to produce 30K, and so on. The final value of the
network is 30K. It would be a very good idea to print the picture, calculate the values and

57
 write them down as an exercise to clarify the process. There are other, more sophisticated
ways to analyze the circuit, but this is straight forward and will do just fine for now.
The bit-6 circuit ends up looking like this after the resistor equivalents have been
identified:

Since the inverting input is a virtual ground, the two 30Ks look like they are
paralleled, which means they look like 15K ohms. It is as if R1 is in series with another
15K resistor. Recall from the equivalent resistance in a series circuit is the sum of the
resistors. Thus, the total resistance seen by the reference is 30K ohms. The current
through R1 is I = -5/30K.
Half of it goes to ground through R2 and half through R3, making
Iout1 = (-5/30K)/2 = -1/12K.
That makes Vout = -(15K * (-1/12K)) = 1.25 volts.
Also, since bit 6 has a weight of 64 and Vout = (5 * DAvalue)/256 from above,
Vout = (5 * 64)/256 = 1.25 volts.
The two agree.
Program
extern unsigned get_port(void);
main(void)
{
int x;
unsigned port,da1;
printf("This sends 0 to 255 then 254 to 1 to DAC1\n");
printf("as quickly as possible, then repeats.\n");
printf("Both DACs have their grounds on pin 1 of header 1.\n");
printf("DAC1's output is on pin 15 and DAC2's on pin 14.\n");
printf("Press any key to begin, then press any key to end the test.\n\n");
getch();
while(!kbhit())
{
for(x=0; x<256; x++) { outp(da1,x); }
for(x=254; x>0; x--) { outp(da1,x); }
}
}

58
 Appendixes

Appendix A

59
Table of Acronyms

AC alternating current
AGP Accelerated Graphics Port
ALU arithmetic logic unit
ANSI American National Standards Institute
ASCII American Standard Code for Information Interchange
ASPI Advanced SCSI Programming Interface
BIOS basic input/output system
BPS (bps) bits per second
CD-ROM compact disc read-only memory
CGA Color/Graphics Adapter
COM port serial communications port
CPU central processing unit
DC direct current
DIMM dual inline memory module
DIP dual inline package
DLL dynamic-link library
DMA direct memory access
DOS disk operating system
DRAM dynamic random access memory
DTE Data Terminal Equipment
DVD digital video disc
EGA Enhanced Graphics Adapter
EIDE Enhanced Integrated Drive Electronics
EISA Extended Industry Standard Architecture
FAT file allocation table
FTP File Transfer Protocol
GB gigabyte
HMA high memory area
I/O input/output
IDE Integrated Device Electronics
IEEE Institute of Electrical and Electronics Engineers
IOR input/output read wire
IOW input/output write wire
IRQ interrupt request
ISA Industry Standard Architecture

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LAN local area network
LBA Logical Block Addressing
LPT line printer, now refers to a parallel printer port
MB megabyte
MHz megahertz
NetBIOS/NetBEUI Networked Basic Input/Output System/NetBIOS Enhanced User Interface
NIC network interface card
PC personal computer
PCI Peripheral Component Interconnect
PIO Programmed Input/Output
RAM random access memory
ROM read-only memory
SCSI Small Computer System Interface
SDRAM synchronous dynamic random access memory
SGRAM synchronous graphics RAM
SIMM single inline memory module
SIPP single inline pinned package
SMM System Memory Management
SPA Software Publishers Association
SRAM static random access memory
TB terabyte
TCP/IP Transmission Control Protocol/Internet Protocol
TSR terminate-and-stay-resident program
UART universal asynchronous receiver-transmitter
UMB upper memory block
UPS uninterruptible power supply
USB universal serial bus
VESA Video Electronics Standards Association
VGA Video Graphics Adapter
VLB VESA local bus
VOM volt-ohm meter
VPN virtual private network
XMS extended memory specification

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Appendex B

Glossary

A
access speed
The time required to complete read or write instructions as required by the memory
controller chip. Usually measured in nanoseconds (ns) for memory chips and
milliseconds (ms) for disk drives. Most manufacturers rate average access time on a hard
disk as the time required for a seek across one third of the total number of cylinders plus
one half of the time for a single revolution of the disk platters.
address bus
A group of parallel conductors (circuit traces) found on the motherboard that are used
by the CPU (central processing unit) to "address" memory locations. Determines what
information or code is sent to or received from the data bus.
AGP (Accelerated Graphics Port)
An Intel- designed expansion port found on Pentium II and later computers that allows a
separate data path for display adapters.
Ampere
A measurement of electrical current strength.
ASCII file
Commonly used term to refer to a text file that contains only data as set forth by the
American Standard Code for Information Interchange to conform to their standard.
Asynchronous
Not synchronized—the computer is free to transmit any number of characters at any
time. The bits constituting a single character are transmitted at a fixed rate, but the
pauses between transmissions can be of any duration.

B
Bandwidth
Used in several ways to denote the amount of data or load capacity of a medium. (1)
The range of frequencies that an electronic system can transmit. High bandwidth allows
fast transmission or the ability to transmit many signals at once. (2) On a monitor screen,
a higher bandwidth provides a sharper image. (3) The rate at which data can be sent over
a modem or other telecommunication device.

Battery

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 A power source for use outside or as an alternate to electricity. Prevents unique
information about the setup of the computer from being lost when the power is turned
off. Also maintains the external clock time (not to be confused with the CPU's clock).
baud
Roughly speaking, a measurement of how fast data can be sent over telephone lines.
binary file
A file type in the form of pure data (1s and 0s) that needs to be converted to an image,
sound, or application to be used. See also ASCII file.
binary system
The language used by computers that is based on something being either on or off. There
are only two digits used in binary language: 1 equals on, and 0 equals off.
BIOS (basic input/output system)
Software that includes the initialization programs stored on ROM (read-only memory)
chips. Used during the startup routine to check out the system and prepare to run the
hardware.
bit
The smallest unit of information that is recognized by a microcomputer. Shorthand term
for binary digit. There are only two possible binary digits: 0 and 1.
bps (bits per second)
The speed at which a modem transmits data. Typical rates are 14,400, 28,800, 33,600,
and 56,600 bps. This represents the actual number of data bits that can be transmitted per
second.
bus
The main communication avenue in a computer. It consists of a set of parallel wires that
are connected to the CPU (central processing unit), memory, and all input/output
devices. The bus can transmit data in either direction between any two components. If a
computer did not have a bus, it would need separate wires to connect all the components.
bus mastering
The ability of a device to control its own data bus, only making use of the main system
bus when data must be sent to the CPU or another device. This reduces CPU and system
bus traffic, improving overall performance.
bus network
A network in which all computers are connected to a single linear cable. Both ends of
the cable must be terminated. Because there is no central point, it is harder to isolate
problems in a bus network than in a star network topology.

Byte
A group of 8 bits that represents 1 character of information (for instance, pressing one
key on the keyboard). A byte is the standard unit for measuring memory in a

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 microprocessor. Memory size is measured in terms of kilobytes (KB) or megabytes
(MB). 1 KB of RAM is 1024 bytes; 1 MB is approximately one million bytes.

C
cache
A place where data is stored so that it does not need to be read from a slower device.
Copies of frequently used disk sectors are stored in RAM (random access memory) so
they can be accessed without accessing the hard disk.
case sensitivity
The ability of the operating system to distinguish between uppercase and lowercase
letters. MS-DOS commands are not case-sensitive; UNIX commands are.
CD-ROM (compact disc read-only memory)
A disc similar to an audio compact disc containing computer data.
central processing unit
See CPU (central processing unit).
CGA (Color Graphics Adapter)
An early color graphics adapter standard with resolutions of 320 pixels by 200 pixels or
640 × 200. CGA supported no more than four colors.
chip
The ultimate integrated circuit; contains the complete arithmetic and logic unit of a
computer. See microprocessor.
chip set
A group of computer chips or integrated circuits (ICs) that, when working in harmony,
manage and control the computer system. This set includes the CPU (central processing
unit) and other chips that control the flow of data throughout the system. Typical chip
sets consist of a bus controller, a memory controller, data and address buffer, and a
peripheral controller.
CISC (complex instruction set computing)
A computer with many different machine-language instructions.
clock
Establishes the maximum speed at which the processor can execute commands. Not to
be confused with the clock that keeps time.
clock speed
Measured in megahertz (MHz)—millions of cycles per second—it is the speed at which
a clock can cycle, or how fast a CPU (central processing unit) can execute a command.
With faster CPUs, the term is now migrating to gigahertz (GHz).
COM1, COM2
The names assigned to the first two serial ports on a PC.
conventional memory

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 The memory area between 0 and 640 KB that is designated for running MS-DOS and
MS-DOS applications.
Coprocessor
A separate circuit inside a computer that adds additional functions to the CPU (central
processing unit) or handles extra work while the CPU is busy.
CPU (central processing unit)
The part of a computer that controls the arithmetic and logical operations and decoding
and executing instructions.

D
data bus
A group of parallel conductors (circuit traces) found on the motherboard that is used by
the CPU (central processing unit) to send and receive data from all the devices in the
computer. Also called the external data bus.
DOS (disk operating system)
A text-based operating system used by most early PCs to manage hardware, data, and
applications.
DRAM (dynamic random access memory)
Memory that requires a refresh signal to be sent to it periodically.

E
EMS (Expanded Memory Specification)
A technique, developed by Lotus/Intel/Microsoft (LIM), that adds addressable memory
to a computer system, overcoming the original MS-DOS upper memory limit. The LIM
EMS uses a 64-KB section of memory (usually in upper memory) to provide a
"window" into which data can be written. Once in this area, the data can be transferred
to the expanded memory. The memory chips are located on an expansion card installed
inside the computer.
Enhanced IDE (EIDE)
A standard developed to increase the size of available disk drives and the speed of data
transfer between the host and the disk drive. See also IDE (Integrated Device
Electronics).
EPP (Enhanced Parallel Port)
Features 2 MB per second data transfer rates, bidirectional 8-bit operation, and
addressing to support multiple (daisy-chained) peripherals on a single computer.
Ethernet
A type of local area network in which communication takes place by means of radio
frequency signals carried by a coaxial cable.

expansion buses

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 Provide the connection between expansion cards (drive controllers, video cards,
modems, and so forth) and the system bus.
expansion slots
Specialized sockets that allow additional devices (circuit boards/adapter cards) to be
attached to the motherboard (by means of the expansion bus). These are used to expand
or customize a computer. They are an extension of the computer's bus system.

H
HTML (Hypertext Markup Language)
An application of SGML (Standardized General Markup Language) used to create Web
pages.
HTTP (Hypertext Transfer Protocol)
The protocol used to transmit data in the HTML (Hypertext Markup Language) format.

I
icon
A small picture on a computer screen used in Windows (or other graphical operating
system) to represent a group of files, an object, or operations. A user accesses the item
he or she wants by clicking on the picture with the mouse.
IDE (Integrated Device Electronics)
The most common standard for interfacing hard disk and CD-ROM drives in the PC
environment. Much of the actual work of controlling the hard disk drive is handled by
the system BIOS. This reduces hardware cost but introduces an overall system
performance penalty during I/O (input/output) operations. See also Enhanced IDE
(EIDE).
integrated circuit (IC)
An electronic device consisting of many miniature transistors and other circuit elements
(resistors, capacitors, and so forth).
internal cache
High-speed memory built into the processor to store frequently used data. This bypasses
the need to access slower devices such as RAM (random access memory) or hard drives.
Internet
A system that links computer networks all over the world.

I/O address
A unique name assigned to each device that allows the CPU (central processing unit) to
recognize the device with which it is communicating.

IP (Internet Protocol)

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 The protocol used to define how data is transmitted over the Internet.
IP address (Internet Protocol address)
A unique address that identifies every network and host on the Internet. (A host is
defined as the TCP/IP network interface within the computer, not the computer itself—a
computer with two network cards will have two IP addresses.)
IRQ (interrupt request)
A wire used by the CPU (central processing unit) to control the flow of data. It prevents
devices from trying to communicate with the CPU at the same time by "interrupting"
and temporarily stopping the CPU to deal with a particular request.
ISA (Industry Standard Architecture)
One of several common expansion slot and card designs.
ISDN
A telecommunication standard that allows a channel to carry voice and data in digital
form over a single line.
ISO (International Organization for Standardization)
Groups of experts drawn from the industry that set standards for various technologies.
The work of these teams has led to development of SCSI (Small Computer System
Interface), SGML and Internet standards, as well as the ASCII character set.
ISP (Internet service provider)
A host computer that users can dial into over a modem to connect to the Internet.

L
local bus
A separate bus in the computer designed to provide extra-fast access to the CPU (central
processing unit) for certain devices, such as video cards.
LPT1, LPT2, LPT3
The names assigned to the parallel printer ports on a PC.

M
mainboard
See motherboard.
megabyte (MB)
An amount of computer memory equal to 220. 1,048,576 bytes = 1024 kilobytes. One
megabyte can store more than one million characters.
megahertz (MHz)
One million hertz (one million cycles per second). A measurement of CPU clock speed.

memory

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 The area within a computer where information is stored while being worked on. It stores
information (in the form of data bits) that the CPU (central processing unit) and software
need to keep running.
Micro Channel Architecture (MCA)
A short-lived, 32-bit expansion bus that was a proprietary design of IBM used on the
IBM PS/2 computer. By abandoning the open design of the existing PC market, IBM
limited the willingness of developers and buyers alike to use MCA.
Microprocessor
An integrated circuit containing the entire CPU (central processing unit) of a computer,
all on one chip, so that only the memory and I/O (input/output) devices need to be
added.
miniconnector
A type of power supply connector primarily used on 3.5-inch floppy disk drives.
Motherboard
Also known as a PWB or printed wiring board, it is the large circuit board found inside
the computer. For all practical purposes, it is the computer. It contains the following
items: chip set, data bus, address bus, expansion slots, clock, battery, and memory.

N
nanosecond (ns)
One-billionth of one second. The time increment used to measure access speed of the
memory chip.
network
A group of computers connected together to share data and resources.
network card
An expansion card that connects a computer to a group of computers so they can access
information and programs. Also known as a network interface card (NIC) and network
adapter card.

O
ohm
A unit of electrical resistance.

operating system
The program that controls a PC and makes it possible for users to run their own
applications. The operating system provides the built-in routines that allow the computer
to recognize commands, manage files, connect devices, and perform I/O (input/output)
operations.

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P
Parallel
The transmission of several bits at the same time over separate wires.
parity bit
A very basic type of error-correcting code that uses the value of an extra bit sent at the
end of a data string. The bit must have a set value based on an algorithm to verify that
the data at the receiving end is correct.
peripheral
An external device connected to a computer such as a printer, scanner, modem, or
joystick.
port
Specific channel used by a network service. For example, Gopher often uses port 70,
while some Web sites use port 80.
Power
The strength or force actually put forth by electricity. Electrical power is measured in
watts, which is measured by multiplying voltage by current.
power supply
Takes alternating current (AC) power from a local source (a wall outlet) and converts it
to direct current (DC) for on-board electronics use.

R
RAM (random access memory)
The main memory where a computer temporarily stores data.
read-only memory
See ROM (read-only memory).
register
Temporary memory storage areas located inside the CPU (central processing unit). Used
to hold the intermediate results of calculations or other operations.
ROM (read-only memory)
Computer memory that contains instructions that do not need to be changed, such as
operating system startup instructions. The computer can access data from ROM but
cannot put new data into it.

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S
SCSI (Small Computer System Interface)
A standard way of interfacing a computer to disk drives and other devices that require
high-speed data transfer. Up to 16 SCSI devices, including the host adapter, can be
connected in a daisy chain fashion. These devices can be hard disk drives, CD-ROMs,
scanners, or printers. SCSI is the only common computer interface that allows adding
both internal and external devices on the same chain. (Pronounced "scuzzy.")
Serial
Transmission of one bit at a time over a single wire.
system bus
Supports the CPU (central processing unit), RAM (random access memory), and other
motherboard components that provide the controlling element to the computer. It is
responsible for coordinating the operation of the individual system components and
central to the communications system of a computer. Also called the control bus.

U
UMA (upper memory area)
The area from 640 KB to 1024 KB that is designated for hardware needs such as video
RAM, BIOS, and memory-mapped hardware.
UMB (upper memory block)
Unused spaces in upper memory that can be divided into blocks. These empty locks have
no RAM associated with them and are simply reserved space. This unused space is
valuable because, unlike expanded and extended memory, MS-DOS can run programs in
UMB.
UPS (uninterruptible power supply)
Acts as both a surge suppressor and a power leveler to provide the computer with a
constant source of power. It also provides power during a power failure or interruption
so the user can safely save data before shutting down.
USB (universal serial bus)
A new external expansion bus that is popular for use with low-speed mass storage
devices such as Zip drives, modems, and printers.

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V
VGA (Video Graphics Array)
A graphics adapter that offers 16 colors at a resolution of 640 pixels × 480 pixels. To
gain more colors, VGA uses an analog video signal instead of a digital signal. With the
analog signal, the VGA standard is able to provide 64 distinct levels for each color,
giving users 643 or 262,144 possible colors. It uses a 15-pin, three-row, female DB-type
connector.

W
word
The largest amount of data that can be handled by the microprocessor in one operation
and also, as a rule, the width of the main data bus.

X
XMS (extended memory specification)
RAM (random access memory) above the 1-MB address. Extended memory is accessed
through an extended memory manager (HIMEM.SYS for DOS).

71