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DLD Mock Up Exam

The document is a mock exam for a digital logic design course containing 20 multiple choice questions testing concepts like binary, boolean algebra, flip flops, encoding schemes, adders, and counters. It provides the questions, possible answer choices for each, and spans 4 pages with the questions numbered 1 through 20.

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79 views4 pages

DLD Mock Up Exam

The document is a mock exam for a digital logic design course containing 20 multiple choice questions testing concepts like binary, boolean algebra, flip flops, encoding schemes, adders, and counters. It provides the questions, possible answer choices for each, and spans 4 pages with the questions numbered 1 through 20.

Uploaded by

teklethelatter
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Addis Ababa Institute of Technology

School of Electrical and Computer Engineering


NAME: ______________________________________ ID_____________________ SECTION ____________

DLD Mockup Examination Date: Nov 25, 2023 Time: 25 minutes

1. The Octal equivalent of the binary number 1011101011;


A. 7353. C. 5651.
B. 1353. D. 5657.

2. In Boolean algebra, (A.A’) + A = ?


A. A. C. A’.
B. 0. D. 1.

3.D flip flop can be made from a J-K flip flop by making;
A. J = K. C. J = 0.
B. J = K = 1. D. J = K’.

4.In 16-Bit 2’s complement representation, the decimal number -28 is;
A. 1111 1111 0001 1100 C. 1111 1111 1110 0100
B. 0000 0000 1110 0100 D. 1000 0000 1110 0100

5.Original ASCII coding scheme uses ____ bits for coding 128 different characters.
A. 6 C. 8
B. 7 D. 16

6.Which coding scheme is used in computer to represent data internally?


A. Decimal. C. Binary.
B. Integral. D. None.

7.A device which converts BCD to seven segments is called;


A. Encoder C. Multiplexer
B. Decoder D. None.

8.In 2's complement representation the number 11100101 represents the decimal
number;
A. +37. C. +27.
B. -31. D. -27.

9. If one input of an XNOR gate is 0 and the other is A, the output will be;
A. 0. C. A.
B. 1. D. A’.

10. The circuit of the given figure realizes the function;

A. Y = (A’+B’)C + (DE)’ C. Y = AB + C + DE
B. Y = A’+B’ + C’ + D’ + E’ D. Y = AB + C(D+E)

11. The basic storage element in a digital system is;


A. Flip flop C. Multiplexer
B. Counter D. Encoder

12. A full adder can be made out of;


A. Two half adders. C. Two half adders and a NOT
B. Two half adders and an OR gate.
gate. D. Three half adders.

13. Minimum number of 2-input NAND gates required to implement F = (X’+Y’).


(Z+W) is;
A. 3 C. 5
B. 4 D. 6

14. For the K map in the given figure the simplified Boolean expression is;

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A. A’C’ + A’D’ + ABC. C. A’C + A’D + ACD.
B. A’C + A’D’ + ABC. D. A’C’ + A’D’ + ABC’.

15. A 4:1 multiplexer requires __________ data select line;


A. 1. C. 3.
B. 2. D. 4.

16. An 8 bit data is to be entered into a parallel register. The number of clock pulses
required is;
A. 8. C. 2.
B. 4. D. 1.

17. A XOR gate has inputs A and B and output Y. Then the output equation is.
A. Y = AB C. Y = A’B + AB’
B. Y = AB + AB’ D. Y = AB + A’B’

18. How many J-K flip flops are required to design 4-Bit Gray bit counter;
A. 3 C. 4
B. 2 D. 1

19. Full adder circuit can be implemented by;


A. Multiplexers. C. AND or OR gates.
B. Half Adders. D. Decoders.

20. How many flip flops are required to design Modulus-6 counter;
A. 3. C. 6.
B. 2. D. 4.

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