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A 1.92 GHz Charge Pump PLL using 45nm

CMOS Technology
Muhammad Aldacher, Student Member, IEEE, and Chad Santos, Student Member, IEEE
Department of Electrical Engineering, San Jose State University
San Jose, CA – 95112
muhammad.aldacher@sjsu.edu, chad.santos@sjsu.edu

Abstract—This paper proposes the design of a low-

power frequency synthesizer PLL system that produces
a 1.92 GHz signal with a reference input of 30 MHz. A
standard PLL topology is used, with a comparison
between using an LC VCO and using a Ring VCO.
Index Terms — Phase Lock Loop, Voltage-Controlled
Oscillator, Frequency Synthesizer, Divider.

I. INTRODUCTION Fig. 2. Schematic of the PFD circuit

T HE work provided in this paper analyzes the

differences between the standard PLL topology with a
ring oscillator versus that with an LC oscillator. System
IV. CHARGE PUMP (CP) & LOOP FILTER (LF)
A. Circuit
The CP receives the “Up” or “Down” signal from the
level simulations and extreme corner simulations are PFD and charges or discharges the loop filter accordingly.
provided to verify the performance on the preferred version. An “Up” signal causes the upper switch to switch on,
causing the upper current source to charge the LF. If a
II.SYSTEM OVERVIEW “Down” signal is high, the bottom switch turns on allowing
The proposed PLL is a 2nd order Charge-Pump PLL the bottom current source to discharge the LF. The LF is a
system that produces a 1.92 GHz output signal. As shown low-pass filter that serves the purpose of averaging out the
in Fig. 1, the PLL is a closed-loop system with a divider of phase-error signal generated from the PFD and generating a
N=64 to ensure a desired output frequency of 1.92 GHz control voltage (Vctrl) for the VCO.
from the VCO while using a reference signal of 30 MHz. Fig. 3 shows the proposed bootstrapped CP with the LF,
Vin
Vout
where the lower switch and source are implemented using
Charge Icp Loop Vctrl
PFD VCO NMOS transistors, and the upper switch and source are
Vfb Up
Down
Pump Filter

implemented using PMOS. The CP opamp uses a typical

single stage differential amplifier topology.
Divider
Fig. 1. PLL system block diagram

III. PHASE FREQUENCY DETECTOR (PFD)

A. Circuit
The first block of the PLL system is the PFD, shown in
Fig. 2. Its main function is to compare the phase and the
frequency of the reference and the feedback signal coming
from the divider, producing an “Up” or a “Down” signal
depending on if the reference signal is leading or lagging.
Since the PFD deals with relatively low frequencies, all the
Fig. 3. Schematic of the Bootstrapped Charge Pump and the Loop Filter
gates used in it are built using static CMOS logic.
B. Simulations
The differential opamp is connected in unity gain to
provide equal voltage on either end of the current branches.
Because the PM of the opamp is > 60 degrees and the GM
is > 12dB, the opamp will avoid oscillation.
 inductor’s resistance.

Fig. 4. Stability of the Differential Amplifier in the CP Fig. 7. Schematic of the LC VCO

The PFD, the CP, and the LF are connected and C.Simulations
simulated together. Fig. 5 shows that when the reference Both VCOs are designed to give a 1.9 GHz output at V ctrl
signal leads the feedback signal, the “Up” switch turns on, = 0.5v. Fig. 8 shows the ring VCO’s output waveform and
increasing the control voltage, telling the oscillator to speed its frequency at Vctrl = 0.5v. Sweeping the V ctrl value from 0
up. The opposite is true when the reference signal is to VDD, it is shown in Fig. 9 that the wide tuning range of
lagging. the ring oscillator results in a K VCO of 9.65 GHz/V, and in
Fig. 10, the phase noise is seen to be -85dBc/Hz at a 0.5v
Vctrl.

(a) (b)
Fig. 5. Output Waveforms when the reference signal (a) leads (b) lags

V. VOLTAGE-CONTROLLED OSCILLATOR (VCO)

Fig. 8. Ring Oscillator - Output waveform and frequency at Vctrl = 0.5v
A. Ring VCO Circuit
There are two VCO topologies under investigation in this
study. The first topology is a current-starved ring VCO,
shown in Fig. 6. A 7-stage ring oscillator is used to improve
Vctrl’s tuning range and additional inter-stage capacitors are
added to slow the VCO down. The V ctrl is applied as a gate
voltage to the lower NMOS transistors in each stage to
control the charging or the discharging currents, controlling
the delays and thus controlling the output frequency.

Fig. 9. Ring Oscillator - Oscillation frequency vs Vctrl

Fig. 6. Schematic of the current-starved ring VCO

Fig. 10. Ring Oscillator – Phase Noise vs Vctrl
B. LC VCO Circuit
The second oscillator topology used is an LC VCO, as In the case of the LC VCO, the output waveform (seen in
shown in Fig. 7. Here, V ctrl tunes the varactor to resonate Fig. 11) takes a longer time to turn on and does not give a
with the inductors. NMOS transistors are used to build the rail-to-rail square output as in the ring VCO. Fig. 12 and
varactors to get an increasing output frequency as V ctrl Fig. 13 show the output frequency and the phase noise
increases. The cross-coupled transistors were designed to against Vctrl, respectively. The LC VCO has a much tighter
provide a negative resistance that cancels with the tuning range with a KVCO of 600MHz/V, but a better phase
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noise performance of -113dBc/Hz at a 0.5v Vctrl. VII. SYSTEM SIMULATIONS

A. Transient & Jitter Simulations
Table I shows the circuit parameters chosen based on the
system’s stability. From the open-loop and the closed-loop
transfer functions, given by equations (1) and (2), and their
bode plots in Fig. 16, a phase margin of 56.36 O and a
closed-loop bandwidth of 1.4 MHz are achieved.

I cp K VCO s R1 C1 +1
H OL ( s) = 2
Fig. 11. LC Oscillator - Output waveform and frequency of at Vctrl = 0.5v 2 πN s (s R 1 C 1 C 2+(C 1+C 2 ))
(1)
H CL ( s ) =
I cp K VCO s R1 C1 +1
2π 3 2 I cp K VCO I cp K VCO
s R1 C1 C 2+ s ( C 1+C 2 ) + s R1 C 1 +
2 πN 2 πN
(2)

Fig. 12. LC Oscillator - Oscillation frequency vs Vctrl

TABLE I. CIRCUIT PARAMETERS USED
Parameter Value
Supply Voltage VDD 1v
Reference frequency fref 30 MHz
Output frequency fout 1.92 GHz
Divider N 64
CP Current ICP 100 uA
VCO Gain KVCO 600 MHz/V
RP 6.5 KΩ
Fig. 13. LC Oscillator – Phase Noise vs Vctrl Loop Filter Components CP 100 pF
C2 10 pF
VI. DIVIDER
With a reference signal of 30MHz and the output of the
VCO being 1.9GHz, a divider of multiple 64 is needed. The
divider consists of 6 divide-by-2 stages. The first two are
true-single-phase-clock (TSPC) flipflops, since they operate
at relatively high frequencies, and the remaining four are
static CMOS flipflops.

(a) (b)
Fig. 16. (a) Open-loop response. (b) Closed-loop response.

Using the testbench in Fig. 17, the whole PLL system

was simulated using the 2 different VCOs. From the
transient simulations, both the lock time and the power
Fig. 14. Divide-by-64 Top Level Circuit
dissipation are obtained, while the RMS and the peak-to-
peak jitters are calculated from the pss and pnoise analyses.
Both jitters were integrated within 1KHz and 1GHz offset
range. Table II shows a comparison in performance
between the PLL using the ring VCO and the PLL with the
LC VCO.
(a) (b)
Fig. 15. Flipflops (a) TSPC (b) Static CMOS
 Fig. 17. Testbench for the whole PLL system
TABLE II. PERFORMANCE COMPARISON BETWEEN
PLL WITH LC VCO & PLL WITH RING VCO Fig. 20. Transient Simulation Results for PLL with Ring Oscillator
Current Starved
Parameter LCVCO
Ring VCO
VCO Gain (KVCO) 600 MHz/v 9.65 GHz/v
Tuning Range 1.68 GHz – 2.02 GHz 0.5 GHz – 3 GHz
Locking Time ~ 2 us ~ 1.5 us
P Dissipation 1.26175 mW 1.21701 mW
RMS Jitter 1.5421 ps 18.9632 ps
FOM -235.23 dB -213.43dB (a) (b)
Fig. 21. Jitter Simulation for PLL with Ring VCO
Using the figure-of-merit (FOM) defined by equation (3), (a) RMS Jitter (b) Pk-to-Pk Jitter at different BERs
it is clear that the LC VCO achieves a much better
performance than the ring VCO in terms of RMS jitter (at B. Corner Simulations
similar power dissipation) due to its small K VCO. Also, using Because of the preferred jitter results that the LC VCO
the LC VCO results in less ringing in V ctrl, as seen in Fig. PLL circuit provides, this topology is used for the extreme
18. Yet, the ring VCO offers a large tuning range and takes corner simulations. As shown by Fig. 22, corner
a shorter time to reach the lock state (Fig. 20). simulations show a VCO output frequency range from

( )
Power 1.916GHz – 1.946 GHz and a feedback frequency range
FOM=10 log Jitter 2 . from 29.95MHz – 30.16MHz
1 mW
(3)

Fig. 22. Corner Simulation Results for PLL with LC VCO

Fig. 18. Transient Simulation Results for PLL with LCVCO
VIII.CONCLUSION
The design of a 1.92 GHz 2 nd order Charge-Pump PLL
using CMOS 45nm technology at 1V is presented, along
with a comparison between using an LC VCO and using a
Ring VCO. The LC VCO showed a better jitter and power
performance, while with the ring VCO, a larger tuning
range and a shorter lock time were achieved. Using the LC
(a) (b)
Fig. 19. Jitter Simulation for PLL with LCVCO
VCO, measured RMS jitter integrated over a range of 1KHz
(a) RMS Jitter (b) Pk-to-Pk Jitter at different BERs to 1GHz offset is 1.5421 ps while consuming 1.26175mW,
resulting in an FOM of -235.23 dB.
Many improvements can still be applied to the design,
like reducing power consumption by investigating other LC
VCO and charge pump topologies. Also, using synchronous
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counters and CML flipflops in the divider can help reduce

the accumulated jitter in the divider path.

REFERENCES
[1] R. Ratan, “Design of a Phase Locked Loop based clocking circuit for
High Speed Serial Link applications”, Thesis, Urbana Illinois, 2014.
[2] B. Razavi, “Design of Analog CMOS Integrated Circuits”, Boston:
McGraw-Hill, 2001.
[3] J. Pattavina, “Charge-Pump Phase-Locked Loop--A Tutorial”,
www.eetimes.com/document.asp?doc_id=1278888, June 30, 2011.
[4] S. Suman, K. Sharma, P. Ghosh, “Analysis and Design of Current
Starved Ring VCO”, International Conference on Electrical,
Electronics, and Optimization Techniques (ICEEOT) – 2016, 3-5
March 2016