Features

• Single 2.7V - 3.6V Supply

• Dual-interface Architecture
– RapidS Serial Interface: 66 MHz Maximum Clock Frequency
SPI Compatible Modes 0 and 3
– Rapid8 8-bit Interface: 50 MHz Maximum Clock Frequency
• User Configurable Page Size
– 1024 Bytes per Page
– 1056 Bytes per Page
– Page Size Can Be Factory Pre-configured for 1024 Bytes 64-megabit
• Page Program Operation
– Intelligent Programming Operation 2.7-volt
•
– 8192 Pages (1024/1056 Bytes/Page) Main Memory
Flexible Erase Options
Dual-interface
– Page Erase (1 Kbyte)
– Block Erase (8 Kbytes)
DataFlash®
– Sector Erase (256 Kbytes)
– Chip Erase (64 Mbits)
• Two SRAM Data Buffers (1024/1056 Bytes) AT45DB642D
– Allows Receiving of Data while Reprogramming the Flash Array
• Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
• Low-power Dissipation
– 10 mA Active Read Current Typical – Serial Interface
– 10 mA Active Read Current Typical – 8-bit Interface
– 25 µA Standby Current Typical
– 15 µA Deep Power Down Typical
• Hardware and Software Data Protection Features
– Individual Sector
• Permanent Sector Lockdown for Secure Code and Data Storage
– Individual Sector
• Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
• JEDEC Standard Manufacturer and Device ID Read
• 100,000 Program/Erase Cycles Per Page Minimum
• Data Retention – 20 Years
• Green (Pb/Halide-free/RoHS Compliant) Packaging Options
• Temperature Range
– Industrial: -40°C to +85°C

3542K–DFLASH–04/09
1. Description
The AT45DB642D is a 2.7-volt, dual-interface sequential access Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications. The
AT45DB642D supports RapidS serial interface and Rapid8 8-bit interface. RapidS serial inter-
face is SPI compatible for frequencies up to 66 MHz. The dual-interface allows a dedicated
serial interface to be connected to a DSP and a dedicated 8-bit interface to be connected to a
microcontroller or vice versa. However, the use of either interface is purely optional. Its
69,206,016 bits of memory are organized as 8,192 pages of 1,024 bytes (binary page size) or
1,056 bytes (standard DataFlash page size) each. In addition to the main memory, the
AT45DB642D also contains two SRAM buffers of 1,024 (binary buffer size) bytes/1,056 bytes
(standard DataFlash buffer size) each. The buffers allow receiving of data while a page in the
main Memory is being reprogrammed, as well as writing a continuous data stream. EEPROM
emulation (bit or byte alterability) is easily handled with a self-contained three step read-modify-
write operation. Unlike conventional Flash memories that are accessed randomly with multiple
address lines and a parallel interface, the DataFlash uses either a RapidS serial interface or a
8-bit Rapid8 interface to sequentially access its data. The simple sequential access dramatically
reduces active pin count, facilitates hardware layout, increases system reliability, minimizes
switching noise, and reduces package size. The device is optimized for use in many commercial
and industrial applications where high-density, low-pin count, low-voltage and low-power are
essential.
To allow for simple in-system reprogrammability, the AT45DB642D does not require high input
voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for
both the program and read operations. The AT45DB642D is enabled through the chip select pin
(CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output
(SO), and the Serial Clock (SCK), or an 8-bit interface consisting of the input/output pins (I/O7 -
I/O0) and the clock pin (CLK).
All programming and erase cycles are self-timed.

2 AT45DB642D
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 AT45DB642D

2. Pin Configurations and Pinouts

Table 2-1. Pin Configurations
Asserted
Symbol Name and Function State Type
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device
will be deselected and normally be placed in the standby mode (not Deep Power-Down mode),
and the output pins (SO or I/O7 - I/O0) will be in a high-impedance state. When the device is
deselected, data will not be accepted on the input pins (SI or I/O7 - I/O0).
CS Low Input
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation such as
a program or erase cycle, the device will not enter the standby mode until the completion of the
operation.
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI or I/O7 - I/O0
SCK/CLK – Input
pins are always latched on the rising edge of SCK/CLK, while output data on the SO or I/O7 -
I/O0 pins are always clocked out on the falling edge of SCK/CLK.
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input
SI including command and address sequences. Data on the SI pin is always latched on the rising – Input
edge of SCK. If the SER/BYTE pin is always driven low, the SI pin should be a “no connect”.
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is always
SO clocked out on the falling edge of SCK. If the SER/BYTE pin is always driven low, the SO pin – Output
should be a “no connect”.
8-bit Input/Output: The I/O7-I/O0 pins are bidirectional and used to clock data into and out of the
device. The I/O7-I/O0 pins are used for all data input, including opcodes and address sequences. Input/
I/O7 - I/O0 –
The use of these pins is optional, and the pins should be treated as “no connect” if the SER/BYTE Output
pin is not connected or if the SER/BYTE pin is always driven high externally.
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector
Protection Register will be protected against program and erase operations regardless of
whether the Enable Sector Protection command has been issued or not. The WP pin functions
independently of the software controlled protection method.
If a program or erase command is issued to the device while the WP pin is asserted, the device
WP will simply ignore the command and perform no operation. The device will return to the idle state Low Input
once the CS pin has been deasserted. The Enable Sector Protection command and Sector
Lockdown command, however, will be recognized by the device when the WP pin is asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to VCC
whenever possible.
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset
the internal state machine to an idle state. The device will remain in the reset condition as long as
a low level is present on the RESET pin. Normal operation can resume once the RESET pin is
RESET brought back to a high level. Low Input
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended
that the RESET pin be driven high externally.
Ready/Busy: This open drain output pin will be driven low when the device is busy in an
internally self-timed operation. This pin, which is normally in a high state (through an external
pull-up resistor), will be pulled low during programming/erase operations, compare operations,
RDY/BUSY – Output
and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.

3
3542K–DFLASH–04/09
Table 2-1. Pin Configurations (Continued)
Asserted
Symbol Name and Function State Type
Serial/8-bit Interface Control: The DataFlash may be configured to utilize either its serial port or
8-bit port through the use of the serial/8-bit control pin (SER/BYTE). When the SER/BYTE pin is
held high, the serial port (SI and SO) of the DataFlash will be used for all data transfers, and the
8-bit port (I/O7 - I/O0) will be in a high impedance state. Any data presented on the 8-bit port
while SER/BYTE is held high will be ignored. When the SER/BYTE is held low, the 8-bit port will
be used for all data transfers, and the SO pin of the serial port will be in a high impedance state.
While SER/BYTE is low, any data presented on the SI pin will be ignored. Switching between the
SER/BYTE serial port and 8-bit port should only be done while the CS pin is high and the device is not busy Low Input
in an internally self-timed operation.
The SER/BYTE pin is internally pulled high; therefore, if the 8-bit port is never to be used, then
connection of the SER/BYTE pin is not necessary. In addition, if the SER/BYTE pin is not
connected or if the SER/BYTE pin is always driven high externally, then the 8-bit input/output pins
(I/O7-I/O0), the VCCP pin, and the GNDP pin should be treated as “no connect”.

Device Power Supply: The VCC pin is used to supply the source voltage to the device.
VCC – Power
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
Ground: The ground reference for the power supply. GND should be connected to the system
GND – Ground
ground.
8-bit Port Supply Voltage: The VCCP pin is used to supply power for the 8-bit input/output pins
(I/O7-I/O0). The VCCP pin needs to be used if the 8-bit port is to be utilized; however, this pin
VCCP – Power
should be treated as “no connect” if the SER/BYTE pin is not connected or if the SER/BYTE pin is
always driven high externally.
8-bit Port Ground: The GNDP pin is used to provide ground for the 8-bit input/output pins (I/O7-
I/O0). The GNDP pin needs to be used if the 8-bit port is to be utilized; however, this pin should
GNDP – Ground
be treated as “no connect” if the SER/BYTE pin is not connected or if the SER/BYTE pin is
always driven high externally.

Figure 2-1. TSOP Top View: Type 1 Figure 2-2. BGA Package Ball-Out (Top View)
1 2 3 4 5
RDY/BUSY 1 28 NC
RESET 2 27 NC
WP 3 26 I/O7
NC 4 25 I/O6 A
NC NC NC NC
NC 5 24 I/O5
VCC 6 23 I/O4 B
NC SCK GND VCC NC
GND 7 22 VCCP
C
NC 8 21 GNDP NC CS RDY/BSY WP NC

NC 9 20 I/O3 D
NC SO SI RESET NC
NC 10 19 I/O2
CS 11 18 I/O1 E
NC NC NC NC NC
SCK/CLK 12 17 I/O0
SI 13 16 SER/BYTE
SO 14 15 NC

Figure 2-3. CASON Top View through Package

SI 1 8 SO
SCK 2 7 GND
RESET 3 6 VCC
CS 4 5 WP

4 AT45DB642D
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 AT45DB642D

3. Block Diagram

WP FLASH MEMORY ARRAY

PAGE (1024/1056 BYTES)

BUFFER 1 (1024/1056 BYTES) BUFFER 2 (1024/1056 BYTES)

SCK/CLK
CS I/O INTERFACE
RESET
VCC
GND
RDY/BUSY SI SO I/O7 - I/O0
SER/BYTE

4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB642D is divided into three levels of
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page by page basis. The erase operations can
be performed at the chip, sector, block or page level.

Figure 4-1. Memory Architecture Diagram

SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE
SECTOR 0a = 8 Pages SECTOR 0 BLOCK 0 8 Pages PAGE 0
8192/8,448 bytes BLOCK 1 PAGE 1
BLOCK 0

BLOCK 2
SECTOR 1

SECTOR 0b = 248 Pages

253,952/261,888 bytes
PAGE 6
PAGE 7
BLOCK 30
SECTOR 1 = 256 Pages PAGE 8
BLOCK 31
262,144/270,336 bytes PAGE 9
BLOCK 32
BLOCK 1

BLOCK 33
SECTOR 2

SECTOR 2 = 256 Pages

262,144/270,336 bytes PAGE 14
PAGE 15
BLOCK 62 PAGE 16
BLOCK 63 PAGE 17
BLOCK 64 PAGE 18
SECTOR 30 = 256 Pages BLOCK 65
262,144/270,336 bytes

SECTOR 31 = 256 Pages

262,144/270,336 bytes BLOCK 1022 PAGE 8,190
BLOCK 1023 PAGE 8,190
Block = 8,192/8,448 bytes Page = 1,024/1,056 bytes

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5. Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Table 15-1 on page 28 through Table 15-6 on
page 31. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit
opcode and the desired buffer or main memory address location. While the CS pin is low, tog-
gling the SCK/CLK pin controls the loading of the opcode and the desired buffer or main memory
address location through either the SI (serial input) pin or the 8-bit input pins (I/O7 - I/O0). All
instructions, addresses, and data are transferred with the most significant bit (MSB) first.
Buffer addressing for standard DataFlash page size (1056 bytes) is referenced in the datasheet
using the terminology BFA10 - BFA0 to denote the 11 address bits required to designate a byte
address within a buffer. Main memory addressing is referenced using the terminology PA12 -
PA0 and BA10 - BA0, where PA12 - PA0 denotes the 13 address bits required to designate a
page address and BA10 - BA0 denotes the 11 address bits required to designate a byte address
within the page.
For “Power of 2” binary page size (1024 bytes) the Buffer addressing is referenced in the
datasheet using the conventional terminology BFA9 - BFA0 to denote the 10 address bits
required to designate a byte address within a buffer. Main memory addressing is referenced
using the terminology A22 - A0.

6. Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two SRAM data buffers. The DataFlash supports RapidS and Rapid8 protocols for
Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this
datasheet for details on the clock cycle sequences for each mode.

6.1 Continuous Array Read (Legacy Command: E8H): Up to 66 MHz

By supplying an initial starting address for the main memory array, the Continuous Array Read
command can be utilized to sequentially read a continuous stream of data from the device by
simply providing a clock signal; no additional addressing information or control signals need to
be provided. The DataFlash incorporates an internal address counter that will automatically
increment on every clock cycle, allowing one continuous read operation without the need of
additional address sequences. To perform a continuous read from the standard DataFlash page
size (1056 bytes), an opcode of E8H must be clocked into the device followed by three address
bytes (which comprise the 24-bit page and byte address sequence) and a series of don’t care
bytes (4 bytes if using the serial interface or 19 bytes if using the 8-bit interface). The first 13 bits
(PA12 - PA0) of the 24-bit address sequence specify which page of the main memory array to
read, and the last 11 bits (BA10 - BA0) of the 24-bit address sequence specify the starting byte
address within the page. To perform a continuous read from the binary page size (1024 bytes),
the opcode (E8H) must be clocked into the device followed by three address bytes and a series
of don’t care bytes (4 bytes if using the serial interface, or 19 bytes if using the 8-bit interface).
The first 13 bits (A22 - A10) of the 24-bits sequence specify which page of the main memory
array to read, and the last 10 bits (A9 - A0) of the 24-bits address sequence specify the starting
byte address within the page. The don’t care bytes that follow the address bytes are needed to
initialize the read operation. Following the don’t care bytes, additional clock pulses on the
SCK/CLK pin will result in data being output on either the SO (serial output) pin or the eight out-
put pins (I/O7- I/O0).

6 AT45DB642D
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 AT45DB642D

The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached during a
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one page
to the beginning of the next page). When the last bit (or byte if using the 8-bit interface mode) in
the main memory array has been read, the device will continue reading back at the beginning of
the first page of memory. As with crossing over page boundaries, no delays will be incurred
when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Continuous Array
Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both data buf-
fers and leaves the contents of the buffers unchanged.

6.2 Continuous Array Read (High Frequency Mode: 0BH): Up to 66 MHz

This command can be used with the serial interface to read the main memory array sequentially
in high speed mode for any clock frequency up to the maximum specified by fCAR1. To perform a
continuous read array with the page size set to 1056 bytes, the CS must first be asserted then
an opcode 0BH must be clocked into the device followed by three address bytes and a dummy
byte. The first 13 bits (PA12 - PA0) of the 24-bit address sequence specify which page of the
main memory array to read, and the last 11 bits (BA10 - BA0) of the 24-bit address sequence
specify the starting byte address within the page. To perform a continuous read with the page
size set to 1024 bytes, the opcode, 0BH, must be clocked into the device followed by three
address bytes (A22 - A0) and a dummy byte. Following the dummy byte, additional clock pulses
on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous
Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both
data buffers and leaves the contents of the buffers unchanged.

6.3 Continuous Array Read (Low Frequency Mode: 03H): Up to 33 MHz

This command can be used with the serial interface to read the main memory array sequentially
without a dummy byte up to maximum frequencies specified by fCAR2. To perform a continuous
read array with the page size set to 1056 bytes, the CS must first be asserted then an opcode,
03H, must be clocked into the device followed by three address bytes (which comprise the 24-bit
page and byte address sequence). The first 13 bits (PA12 - PA0) of the 24-bit address sequence
specify which page of the main memory array to read, and the last 11 bits (BA10 - BA0) of the
24-bit address sequence specify the starting byte address within the page. To perform a contin-
uous read with the page size set to 1024 bytes, the opcode, 03H, must be clocked into the
device followed by three address bytes (A22 - A0). Following the address bytes, additional clock
pulses on the SCK pin will result in data being output on the SO (serial output) pin.

7
3542K–DFLASH–04/09
 The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The Continuous Array Read bypasses both data buffers and
leaves the contents of the buffers unchanged.

6.4 Main Memory Page Read

A main memory page read allows the user to read data directly from any one of the 8,192 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read from the standard DataFlash page size (1056 bytes), an
opcode of D2H must be clocked into the device followed by three address bytes (which comprise
the 24-bit page and byte address sequence) and a series of don’t care bytes (4 bytes if using the
serial interface or 19 bytes if using the 8-bit interface). The first 13 bits (PA12 - PA0) of the 24-bit
address sequence specify the page in main memory to be read, and the last 11 bits (BA10 -
BA0) of the 24-bit address sequence specify the starting byte address within that page. To start
a page read from the binary page size (1024 bytes), the opcode D2H must be clocked into the
device followed by three address bytes and a series of don’t care bytes (4 bytes if using the
serial interface or 19 bytes if using the 8-bit interface). The first 13 bits (A22 - A10) of the 24-bits
sequence specify which page of the main memory array to read, and the last 10 bits (A9 - A0) of
the 24-bits address sequence specify the starting byte address within the page. The don’t care
bytes that follow the address bytes are sent to initialize the read operation. Following the don’t
care bytes, additional pulses on SCK/CLK result in data being output on either the SO (serial
output) pin or the eight output pins (I/O7 - I/O0). The CS pin must remain low during the loading
of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of
a page in main memory is reached, the device will continue reading back at the beginning of the
same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state
the output pins (SO or I/O7 - I/O0). The maximum SCK/CLK frequency allowable for the Main
Memory Page Read is defined by the fSCK specification. The Main Memory Page Read bypasses
both data buffers and leaves the contents of the buffers unchanged.

6.5 Buffer Read

The SRAM data buffers can be accessed independently from the main memory array, and utiliz-
ing the Buffer Read Command allows data to be sequentially read directly from the buffers. In
serial mode, four opcodes, D4H or D1H for buffer 1 and D6H or D3H for buffer 2 can be used for
the Buffer Read Command. The use of each opcode depends on the maximum SCK frequency
that will be used to read data from the buffer. The D4H and D6H opcode can be used at any
SCK frequency up to the maximum specified by fCAR1. The D1H and D3H opcode can be used
for lower frequency read operations up to the maximum specified by fCAR2.
In 8-bit mode, two opcodes, 54H for buffer 1 and 56H for buffer 2 can be used for the Buffer
Read Command. The two opcodes, 54H and 56H, can be used at any SCK frequency up to the
maximum specified by fCAR1. To perform a buffer read from the standard DataFlash buffer (1056
bytes), the opcode must be clocked into the device followed by three address bytes comprised
of 13 don’t care bits and 11 buffer address bits (BFA10 - BFA0). To perform a buffer read from
the binary buffer (1024 bytes), the opcode must be clocked into the device followed by three
address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0).

8 AT45DB642D
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 AT45DB642D
Following the address bytes, additional don’t care bytes (one byte if using the serial interface or
two bytes if using the 8-bit interface) must be clocked in to initialize the read operation. The CS
pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes,
and the reading of data. When the end of a buffer is reached, the device will continue reading
back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read
operation and tri-state the output pins (SO or I/O7 - I/O0).

7. Program and Erase Commands

7.1 Buffer Write

Data can be clocked in from the input pins (SI or I/O7 - I/O0) into either buffer 1 or buffer 2. To
load data into the standard DataFlash buffer (1056 bytes), a 1-byte opcode, 84H for buffer 1 or
87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of
13 don’t care bits and 11 buffer address bits (BFA10 - BFA0). The 11 buffer address bits specify
the first byte in the buffer to be written. To load data into the binary buffers (1024 bytes each), a
1-byte opcode 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by
three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0).
The 10 buffer address bits specify the first byte in the buffer to be written. After the last address
byte has been clocked into the device, data can then be clocked in on subsequent clock cycles.
If the end of the data buffer is reached, the device will wrap around back to the beginning of the
buffer. Data will continue to be loaded into the buffer until a low-to-high transition is detected on
the CS pin.

7.2 Buffer to Main Memory Page Program with Built-in Erase

Data written into either buffer 1 or buffer 2 can be programmed into the main memory. A 1-byte
opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the device. For the standard
DataFlash page size (1056 bytes), the opcode must be followed by three address bytes consist
of 13 page address bits (PA12 - PA0) that specify the page in the main memory to be written and
11 don’t care bits. To perform a buffer to main memory page program with built-in erase for the
binary page size (1024 bytes), the opcode 83H for buffer 1 or 86H for buffer 2, must be clocked
into the device followed by three address bytes consisting of 13 page address bits (A22 - A10)
that specify the page in the main memory to be written and 10 don’t care bits. When a low-to-
high transition occurs on the CS pin, the part will first erase the selected page in main memory
(the erased state is a logic 1) and then program the data stored in the buffer into the specified
page in main memory. Both the erase and the programming of the page are internally self-timed
and should take place in a maximum time of tEP. During this time, the status register and the
RDY/BUSY pin will indicate that the part is busy.

7.3 Buffer to Main Memory Page Program without Built-in Erase

A previously-erased page within main memory can be programmed with the contents of either
buffer 1 or buffer 2. A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2, must be clocked into
the device. For the standard DataFlash page size (1056 bytes), the opcode must be followed by
three address bytes consist of 13 page address bits (PA12 - PA0) that specify the page in the
main memory to be written and 11 don’t care bits. To perform a buffer to main memory page pro-
gram without built-in erase for the binary page size (1024 bytes), the opcode 88H for buffer 1 or
89H for buffer 2, must be clocked into the device followed by three address bytes consist of
13-page address bits (A22 - A10) that specify the page in the main memory to be written and
10 don’t care bits. When a low-to-high transition occurs on the CS pin, the part will program the
data stored in the buffer into the specified page in the main memory. It is necessary that the

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3542K–DFLASH–04/09
 page in main memory that is being programmed has been previously erased using one of the
erase commands (Page Erase or Block Erase). The programming of the page is internally self-
timed and should take place in a maximum time of tP. During this time, the status register and
the RDY/BUSY pin will indicate that the part is busy.

7.4 Page Erase

The Page Erase command can be used to individually erase any page in the main memory array
allowing the Buffer to Main Memory Page Program to be utilized at a later time. To perform a
page erase in the standard DataFlash page size (1056 bytes), an opcode of 81H must be loaded
into the device, followed by three address bytes comprised of 13 page address bits (PA12 -
PA0) that specify the page in the main memory to be erased and 11 don’t care bits. To perform
a page erase in the binary page size (1024 bytes), the opcode 81H must be loaded into the
device, followed by three address bytes consist of 13 page address bits (A22 - A10) that specify
the page in the main memory to be erased and 10 don’t care bits. When a low-to-high transition
occurs on the CS pin, the part will erase the selected page (the erased state is a logical 1). The
erase operation is internally self-timed and should take place in a maximum time of tPE. During
this time, the status register and the RDY/BUSY pin will indicate that the part is busy.

7.5 Block Erase

A block of eight pages can be erased at one time. This command is useful when large amounts
of data has to be written into the device. This will avoid using multiple Page Erase Commands.
To perform a block erase for the standard DataFlash page size (1056 bytes), an opcode of 50H
must be loaded into the device, followed by three address bytes comprised of 10 page address
bits (PA12 -PA3) and 14 don’t care bits. The 10 page address bits are used to specify which
block of eight pages is to be erased. To perform a block erase for the binary page size (1024
bytes), the opcode 50H must be loaded into the device, followed by three address bytes consist-
ing of 10 page address bits (A22 - A13) and 13 don’t care bits. The 10 page address bits are
used to specify which block of eight pages is to be erased. When a low-to-high transition occurs
on the CS pin, the part will erase the selected block of eight pages. The erase operation is inter-
nally self-timed and should take place in a maximum time of t BE. During this time, the status
register and the RDY/BUSY pin will indicate that the part is busy.

Table 7-1. Block Erase Addressing

PA12/ PA11/ PA10/ PA9/ PA8/ PA7/ PA6/ PA5/ PA4/ PA3/ PA2/ PA1/ PA0/
A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Block
0 0 0 0 0 0 0 0 0 0 X X X 0
0 0 0 0 0 0 0 0 0 1 X X X 1
0 0 0 0 0 0 0 0 1 0 X X X 2
0 0 0 0 0 0 0 0 1 1 X X X 3
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
1 1 1 1 1 1 1 1 0 0 X X X 1020
1 1 1 1 1 1 1 1 0 1 X X X 1021
1 1 1 1 1 1 1 1 1 0 X X X 1022
1 1 1 1 1 1 1 1 1 1 X X X 1023

10 AT45DB642D
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 AT45DB642D

7.6 Sector Erase

The Sector Erase command can be used to individually erase any sector in the main memory.
There are 32 sectors and only one sector can be erased at one time. To perform sector 0a or
sector 0b erase for the standard DataFlash page size (1056 bytes), an opcode of 7CH must be
loaded into the device, followed by three address bytes comprised of 10 page address bits
(PA12 - PA3) and 14 don’t care bits. To perform a sector 1-31 erase, the opcode 7CH must be
loaded into the device, followed by three address bytes comprised of 5 page address bits (PA12
- PA8) and 19 don’t care bits. To perform sector 0a or sector 0b erase for the binary page size
(1024 bytes), an opcode of 7CH must be loaded into the device, followed by three address bytes
comprised of 1 don’t care bit and 10 page address bits (A22 - A13) and 13 don’t care bits. To
perform a sector 1-31 erase, the opcode 7CH must be loaded into the device, followed by three
address bytes comprised of 1 don’t care bit and 5 page address bits (PA12 - PA8) and 18 don’t
care bits. The page address bits are used to specify any valid address location within the sector
which is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the
selected sector. The erase operation is internally self-timed and should take place in a maximum
time of tSE. During this time, the status register and the RDY/BUSY pin will indicate that the part
is busy.

Table 7-2. Sector Erase Addressing

PA12/ PA11/ PA10/ PA9/ PA8/ PA7/ PA6/ PA5/ PA4/ PA3/ PA2/ PA1/ PA0/
A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 Sector
0 0 0 0 0 0 0 0 0 0 X X X 0a
0 0 0 0 0 0 0 0 0 1 X X X 0b
0 0 0 0 1 X X X X X X X X 1
0 0 0 1 0 X X X X X X X X 2
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
• • • • • • • • • • • • • •
1 1 1 0 0 X X X X X X X X 28
1 1 1 0 1 X X X X X X X X 29
1 1 1 1 0 X X X X X X X X 30
1 1 1 1 1 X X X X X X X X 31

7.7 Chip Erase(1)

The entire main memory can be erased at one time by using the Chip Erase command.
To execute the Chip Erase command, a 4-byte command sequence C7H, 94H, 80H and 9AH
must be clocked into the device. Since the entire memory array is to be erased, no address
bytes need to be clocked into the device, and any data clocked in after the opcode will be
ignored. After the last bit of the opcode sequence has been clocked in, the CS pin can be deas-
serted to start the erase process. The erase operation is internally self-timed and should take
place in a time of tCE. During this time, the Status Register will indicate that the device is busy.
The Chip Erase command will not affect sectors that are protected or locked down; the contents
of those sectors will remain unchanged. Only those sectors that are not protected or locked
down will be erased.

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 The WP pin can be asserted while the device is erasing, but protection will not be activated until
the internal erase cycle completes.

Command Byte 1 Byte 2 Byte 3 Byte 4

Chip Erase C7H 94H 80H 9AH

Figure 7-1. Chip Erase

CS

Opcode Opcode Opcode Opcode

SI Byte 1 Byte 2 Byte 3 Byte 4

Each transition
represents 8 bits

Note: 1. Refer to the errata regarding Chip Erase on page 57.

7.8 Main Memory Page Program Through Buffer

This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program
with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pins (SI
or I/O7-I/O0) and then programmed into a specified page in the main memory. To perform the
main memory page program through buffer for the standard DataFlash page size (1056 bytes), a
1-byte opcode, 82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, fol-
lowed by three address bytes. The address bytes are comprised of 13 page address bits,
(PA12-PA0) that select the page in the main memory where data is to be written, and 11 buffer
address bits (BFA10-BFA0) that select the first byte in the buffer to be written. To perform a
main memory page program through buffer for the binary page size (1024 bytes), the opcode
82H for buffer 1 or 85H for buffer 2, must be clocked into the device followed by three address
bytes consisting of 13 page address bits (A22 - A10) that specify the page in the main memory
to be written, and 10 buffer address bits (BFA9 - BFA0) that selects the first byte in the buffer to
be written. After all address bytes are clocked in, the part will take data from the input pins and
store it in the specified data buffer. If the end of the buffer is reached, the device will wrap
around back to the beginning of the buffer. When there is a low-to-high transition on the CS pin,
the part will first erase the selected page in main memory to all 1s and then program the data
stored in the buffer into that memory page. Both the erase and the programming of the page are
internally self-timed and should take place in a maximum time of tEP. During this time, the status
register and the RDY/BUSY pin will indicate that the part is busy.

8. Sector Protection
Two protection methods, hardware and software controlled, are provided for protection against
inadvertent or erroneous program and erase cycles. The software controlled method relies on
the use of software commands to enable and disable sector protection while the hardware con-
trolled method employs the use of the Write Protect (WP) pin. The selection of which sectors
that are to be protected or unprotected against program and erase operations is specified in the
nonvolatile Sector Protection Register. The status of whether or not sector protection has been
enabled or disabled by either the software or the hardware controlled methods can be deter-
mined by checking the Status Register.

12 AT45DB642D
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 AT45DB642D

8.1 Software Sector Protection

8.1.1 Enable Sector Protection Command

Sectors specified for protection in the Sector Protection Register can be protected from program
and erase operations by issuing the Enable Sector Protection command. To enable the sector
protection using the software controlled method, the CS pin must first be asserted as it would be
with any other command. Once the CS pin has been asserted, the appropriate 4-byte command
sequence must be clocked in via the input pins (SI or I/O7-I/O0). After the last bit of the com-
mand sequence has been clocked in, the CS pin must be deasserted after which the sector
protection will be enabled.

Command Byte 1 Byte 2 Byte 3 Byte 4

Enable Sector Protection 3DH 2AH 7FH A9H

Figure 8-1. Enable Sector Protection

CS

Opcode Opcode Opcode Opcode

SI or IO7 - IO0 Byte 1 Byte 2 Byte 3 Byte 4

Each transition
represents 8 bits

8.1.2 Disable Sector Protection Command

To disable the sector protection using the software controlled method, the CS pin must first be
asserted as it would be with any other command. Once the CS pin has been asserted, the
appropriate 4-byte sequence for the Disable Sector Protection command must be clocked in via
the input pins (SI or I/O7-I/O0). After the last bit of the command sequence has been clocked in,
the CS pin must be deasserted after which the sector protection will be disabled. The WP pin
must be in the deasserted state; otherwise, the Disable Sector Protection command will be
ignored.

Command Byte 1 Byte 2 Byte 3 Byte 4

Disable Sector Protection 3DH 2AH 7FH 9AH

Figure 8-2. Disable Sector Protection

CS

Opcode Opcode Opcode Opcode

SI or IO7 - IO0 Byte 1 Byte 2 Byte 3 Byte 4

Each transition
represents 8 bits

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8.1.3 Various Aspects About Software Controlled Protection
Software controlled protection is useful in applications in which the WP pin is not or cannot be
controlled by a host processor. In such instances, the WP pin may be left floating (the WP pin is
internally pulled high) and sector protection can be controlled using the Enable Sector Protection
and Disable Sector Protection commands.
If the device is power cycled, then the software controlled protection will be disabled. Once the
device is powered up, the Enable Sector Protection command should be reissued if sector pro-
tection is desired and if the WP pin is not used.

9. Hardware Controlled Protection

Sectors specified for protection in the Sector Protection Register can be protected from program
and erase operations by asserting the WP pin and keeping the pin in its asserted state. Any sec-
tor specified for protection cannot be erased or reprogrammed as long as the WP pin is
asserted.
The WP pin will override the software controlled protection method but only for protecting the
sectors. For example, if the sectors were not previously protected by the Enable Sector Protec-
tion command, then simply asserting the WP pin would enable the sector protection within the
maximum specified tWPE time. When the WP pin is deasserted; however, the sector protection
would no longer be enabled (after the maximum specified tWPD time) as long as the Enable Sec-
tor Protection command was not issued while the WP pin was asserted. If the Enable Sector
Protection command was issued before or while the WP pin was asserted, then simply deassert-
ing the WP pin would not disable the sector protection. In this case, the Disable Sector
Protection command would need to be issued while the WP pin is deasserted to disable the sec-
tor protection. The Disable Sector Protection command is also ignored whenever the WP pin is
asserted.
A noise filter is incorporated to help protect against spurious noise that may inadvertently assert
or deassert the WP pin.
The table below details the sector protection status for various scenarios of the WP pin, the
Enable Sector Protection command, and the Disable Sector Protection command.

Figure 9-1. WP Pin and Protection Status

1 2 3
WP

Table 9-1. WP Pin and Protection Status

Time Disable Sector Protection Sector Protection
Period WP Pin Enable Sector Protection Command Command Status
Command Not Issued Previously X Disabled
1 High – Issue Command Disabled
Issue Command – Enabled
2 Low X X Enabled
Command Issued During Period 1 or 2 Not Issued Yet Enabled
3 High – Issue Command Disabled
Issue Command – Enabled

14 AT45DB642D
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 AT45DB642D

9.1 Sector Protection Register

The nonvolatile Sector Protection Register specifies which sectors are to be protected or unpro-
tected with either the software or hardware controlled protection methods. The Sector Protection
Register contains 32 bytes of data, of which byte locations 0 through 31 contain values that
specify whether sectors 0 through 31 will be protected or unprotected. The Sector Protection
Register is user modifiable and must first be erased before it can be reprogrammed. Table 9-3
illustrates the format of the Sector Protection Register.:

Table 9-2. Sector Protection Register

Sector Number 0 (0a, 0b) 1 to 31
Protected FFH
See Table 9-3
Unprotected 00H

Table 9-3. Sector 0 (0a, 0b)

0a 0b
(Page 0-7) (Page 8-255)
Data
Bit 7, 6 Bit 5, 4 Bit 3, 2 Bit 1, 0 Value
Sectors 0a, 0b Unprotected 00 00 xx xx 0xH
Protect Sector 0a 11 00 xx xx CxH
Protect Sector 0b (Page 8-255) 00 11 xx xx 3xH
Protect Sectors 0a (Page 0-7), 0b
11 11 xx xx FxH
(Page 8-255)(1)
Note: 1. The default value for bytes 0 through 31 when shipped from Atmel is 00H.
x = don’t care

9.1.1 Erase Sector Protection Register Command

In order to modify and change the values of the Sector Protection Register, it must first be
erased using the Erase Sector Protection Register command.
To erase the Sector Protection Register, the CS pin must first be asserted as it would be with
any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode
sequence must be clocked into the device via the SI or I/O7 - I/O0 pin. The 4-byte opcode
sequence must start with 3DH and be followed by 2AH, 7FH, and CFH. After the last bit of the
opcode sequence has been clocked in, the CS pin must be deasserted to initiate the internally
self-timed erase cycle. The erasing of the Sector Protection Register should take place in a time
of tPE, during which time the Status Register will indicate that the device is busy. If the device is
powered-down before the completion of the erase cycle, then the contents of the Sector Protec-
tion Register cannot be guaranteed.
The Sector Protection Register can be erased with the sector protection enabled or disabled.
Since the erased state (FFH) of each byte in the Sector Protection Register is used to indicate
that a sector is specified for protection, leaving the sector protection enabled during the erasing
of the register allows the protection scheme to be more effective in the prevention of accidental
programming or erasing of the device. If for some reason an erroneous program or erase com-
mand is sent to the device immediately after erasing the Sector Protection Register and before

15
3542K–DFLASH–04/09
 the register can be reprogrammed, then the erroneous program or erase command will not be
processed because all sectors would be protected.

Command Byte 1 Byte 2 Byte 3 Byte 4

Erase Sector Protection Register 3DH 2AH 7FH CFH

Figure 9-2. Erase Sector Protection Register

CS

SI or IO7 - IO0 Opcode Opcode Opcode Opcode

Byte 1 Byte 2 Byte 3 Byte 4

Each transition
represents 8 bits

9.1.2 Program Sector Protection Register Command

Once the Sector Protection Register has been erased, it can be reprogrammed using the Pro-
gram Sector Protection Register command.
To program the Sector Protection Register, the CS pin must first be asserted and the appropri-
ate 4-byte opcode sequence must be clocked into the device via the SI or I/O7 - I/O0 pin. The 4-
byte opcode sequence must start with 3DH and be followed by 2AH, 7FH, and FCH. After the
last bit of the opcode sequence has been clocked into the device, the data for the contents of the
Sector Protection Register must be clocked in. As described in Section 9.1, the Sector Protec-
tion Register contains 32 bytes of data, so 32 bytes must be clocked into the device. The first
byte of data corresponds to sector 0, the second byte corresponds to sector 1, and so on with
the last byte of data corresponding to sector 31.
After the last data byte has been clocked in, the CS pin must be deasserted to initiate the inter-
nally self-timed program cycle. The programming of the Sector Protection Register should take
place in a time of tP, during which time the Status Register will indicate that the device is busy. If
the device is powered-down during the program cycle, then the contents of the Sector Protection
Register cannot be guaranteed.
If the proper number of data bytes is not clocked in before the CS pin is deasserted, then the
protection status of the sectors corresponding to the bytes not clocked in can not be guaranteed.
For example, if only the first two bytes are clocked in instead of the complete 32 bytes, then the
protection status of the last 30 sectors cannot be guaranteed. Furthermore, if more than 32
bytes of data is clocked into the device, then the data will wrap back around to the beginning of
the register. For instance, if 33 bytes of data are clocked in, then the 33rd byte will be stored at
byte location 0 of the Sector Protection Register.
If a value other than 00H or FFH is clocked into a byte location of the Sector Protection Register,
then the protection status of the sector corresponding to that byte location cannot be guaran-
teed. For example, if a value of 17H is clocked into byte location 2 of the Sector Protection
Register, then the protection status of sector 2 cannot be guaranteed.
The Sector Protection Register can be reprogrammed while the sector protection enabled or dis-
abled. Being able to reprogram the Sector Protection Register with the sector protection enabled
allows the user to temporarily disable the sector protection to an individual sector rather than dis-
abling sector protection completely.

16 AT45DB642D
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 AT45DB642D

The Program Sector Protection Register command utilizes the internal SRAM buffer for process-
ing. Therefore, the contents of the buffer will be altered from its previous state when this
command is issued.

Command Byte 1 Byte 2 Byte 3 Byte 4

Program Sector Protection Register 3DH 2AH 7FH FCH

Figure 9-3. Program Sector Protection Register

CS

Opcode Opcode Opcode Opcode Data Byte Data Byte Data Byte
SI or IO7 - IO0 Byte 1 Byte 2 Byte 3 Byte 4 n n+1 n + 31

Each transition
represents 8 bits

9.1.3 Read Sector Protection Register Command

To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has
been asserted, an opcode of 32H and a series of dummy bytes (3 dummy bytes if using the
serial interface or 7 dummy bytes if using the 8-bit interface) must be clocked in via the SI or I/O7
or I/O0 pins. After the last bit of the opcode and dummy bytes have been clocked in, any addi-
tional clock pulses on the SCK/CLK pins will result in data for the content of the Sector
Protection Register being output on the SO or I/O7-I/O0 pins. The first byte corresponds to sec-
tor 0 (0a, 0b), the second byte corresponds to sector 1 and the last byte (byte 32) corresponds to
sector 31. Once the last byte of the Sector Protection Register has been clocked out, any addi-
tional clock pulses will result in undefined data being output on the SO or I/O pins. The CS must
be deasserted to terminate the Read Sector Protection Register operation and put the output
into a high-impedance state.

Command Byte 1 Byte 2 Byte 3 Byte 4

Read Sector Protection Register 32H xxH xxH xxH

Note: xx = Dummy Byte Serial Interface = 3 Dummy Bytes 8-bit Interface = 7 Dummy Bytes

Figure 9-4. Read Sector Protection Register

CS

SI or IO7 - IO0 Opcode X X X

Data Byte Data Byte Data Byte

SO or IO7 - IO0 n n+1 n + 31

Each transition
represents 8 bits

17
3542K–DFLASH–04/09
9.1.4 Various Aspects About the Sector Protection Register
The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Users are
encouraged to carefully evaluate the number of times the Sector Protection Register will be
modified during the course of the applications’ life cycle. If the application requires that the Sec-
tor Protection Register be modified more than the specified limit of 10,000 cycles because the
application needs to temporarily unprotect individual sectors (sector protection remains enabled
while the Sector Protection Register is reprogrammed), then the application will need to limit this
practice. Instead, a combination of temporarily unprotecting individual sectors along with dis-
abling sector protection completely will need to be implemented by the application to ensure that
the limit of 10,000 cycles is not exceeded.

10. Security Features

10.1 Sector Lockdown

The device incorporates a Sector Lockdown mechanism that allows each individual sector to be
permanently locked so that it becomes read only. This is useful for applications that require the
ability to permanently protect a number of sectors against malicious attempts at altering program
code or security information. Once a sector is locked down, it can never be erased or pro-
grammed, and it can never be unlocked.
To issue the Sector Lockdown command, the CS pin must first be asserted as it would be for
any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode
sequence must be clocked into the device in the correct order. The 4-byte opcode sequence
must start with 3DH and be followed by 2AH, 7FH, and 30H. After the last byte of the command
sequence has been clocked in, then three address bytes specifying any address within the sec-
tor to be locked down must be clocked into the device. After the last address bit has been
clocked in, the CS pin must then be deasserted to initiate the internally self-timed lockdown
sequence.
The lockdown sequence should take place in a maximum time of tP, during which time the Status
Register will indicate that the device is busy. If the device is powered-down before the comple-
tion of the lockdown sequence, then the lockdown status of the sector cannot be guaranteed. In
this case, it is recommended that the user read the Sector Lockdown Register to determine the
status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com-
mand if necessary.

Command Byte 1 Byte 2 Byte 3 Byte 4

Sector Lockdown 3DH 2AH 7FH 30H

Figure 10-1. Sector Lockdown

CS

SI or IO7 - IO0 Opcode Opcode Opcode Opcode Address Address Address

Byte 1 Byte 2 Byte 3 Byte 4 Bytes Bytes Bytes

Each transition
represents 8 bits

18 AT45DB642D
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 AT45DB642D
10.1.1 Sector Lockdown Register
Sector Lockdown Register is a nonvolatile register that contains 32 bytes of data, as shown
below:

Sector Number 0 (0a, 0b) 1 to 31

Locked FFH
See Below
Unlocked 00H

Table 10-1. Sector 0 (0a, 0b)

0a 0b
(Page 0-7) (Page 8-255)
Data
Bit 7, 6 Bit 5, 4 Bit 3, 2 Bit 1, 0 Value
Sectors 0a, 0b Unlocked 00 00 00 00 00H
Sector 0a Locked 11 00 00 00 C0H
Sector 0b Locked (Page 8-255) 00 11 00 00 30H
Sectors 0a, 0b Locked (Page 0-255) 11 11 00 00 F0H

10.1.2 Reading the Sector Lockdown Register

The Sector Lockdown Register can be read to determine which sectors in the memory array are
permanently locked down. To read the Sector Lockdown Register, the CS pin must first be
asserted. Once the CS pin has been asserted, an opcode of 35H and a series of dummy bytes
(3 dummy bytes if using the serial interface or 7 dummy bytes if using the 8-bit interface) must
be clocked into the device via the SI or I/O7-O0 pins. After the last bit of the opcode and dummy
bytes have been clocked in, the data for the contents of the Sector Lockdown Register will be
clocked out on the SO pin or the I/O7-O0 pins. The first byte corresponds to sector 0 (0a, 0b) the
second byte corresponds to sector 1 and the las byte (byte 32) corresponds to sector 31. After
the last byte of the Sector Lockdown Register has been read, additional pulses on the SCK pin
will simply result in undefined data being output on the SO pin.
Deasserting the CS pin will terminate the Read Sector Lockdown Register operation and put the
SO pin or I/O7-O0 pins into a high-impedance state.
Table 10-2 details the values read from the Sector Lockdown Register.
Table 10-2. Sector Lockdown Register
Command Byte 1 Byte 2 Byte 3 Byte 4
Read Sector Lockdown Register 35H xxH xxH xxH
Note: xx = Dummy Byte Serial Interface = 3 Dummy Bytes 8-bit Interface = 7 Dummy Bytes

Figure 10-2. Read Sector Lockdown Register

CS

SI or IO7 - IO0 Opcode X X X

Data Byte Data Byte Data Byte

SO or IO7 - IO0 n n+1 n + 31

Each transition
represents 8 bits

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3542K–DFLASH–04/09
10.2 Security Register
The device contains a specialized Security Register that can be used for purposes such as
unique device serialization or locked key storage. The register is comprised of a total of 128
bytes that is divided into two portions. The first 64 bytes (byte locations 0 through 63) of the
Security Register are allocated as a one-time user programmable space. Once these 64 bytes
have been programmed, they cannot be reprogrammed. The remaining 64 bytes of the register
(byte locations 64 through 127) are factory programmed by Atmel and will contain a unique
value for each device. The factory programmed data is fixed and cannot be changed.

Table 10-3. Security Register

Security Register Byte Number
0 1 ••• 62 63 64 65 ••• 126 127
Data Type One-time User Programmable Factory Programmed By Atmel

10.2.1 Programming the Security Register

The user programmable portion of the Security Register does not need to be erased before it is
programmed.
To program the Security Register, the CS pin must first be asserted and the appropriate 4-byte
opcode sequence must be clocked into the device in the correct order. The 4-byte opcode
sequence must start with 9BH and be followed by 00H, 00H, and 00H. After the last bit of the
opcode sequence has been clocked into the device, the data for the contents of the 64-byte user
programmable portion of the Security Register must be clocked in.
After the last data byte has been clocked in, the CS pin must be deasserted to initiate the inter-
nally self-timed program cycle. The programming of the Security Register should take place in a
time of tP, during which time the Status Register will indicate that the device is busy. If the device
is powered-down during the program cycle, then the contents of the 64-byte user programmable
portion of the Security Register cannot be guaranteed.
If the full 64 bytes of data is not clocked in before the CS pin is deasserted, then the values of
the byte locations not clocked in cannot be guaranteed. For example, if only the first two bytes
are clocked in instead of the complete 64 bytes, then the remaining 62 bytes of the user pro-
grammable portion of the Security Register cannot be guaranteed. Furthermore, if more than 64
bytes of data is clocked into the device, then the data will wrap back around to the beginning of
the register. For instance, if 65 bytes of data are clocked in, then the 65th byte will be stored at
byte location 0 of the Security Register.
The user programmable portion of the Security Register can only be programmed one
time. Therefore, it is not possible to only program the first two bytes of the register and then pro-
gram the remaining 62 bytes at a later time.
The Program Security Register command utilizes the internal SRAM buffer for processing.
Therefore, the contents of the buffer will be altered from its previous state when this command is
issued.

20 AT45DB642D
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 AT45DB642D

Figure 10-3. Program Security Register

CS

SI or IO7 - IO0 Opcode Opcode Opcode Opcode Data Byte Data Byte Data Byte
Byte 1 Byte 2 Byte 3 Byte 4 n n+1 n+x

Each transition
represents 8 bits

10.2.2 Reading the Security Register

The Security Register can be read by first asserting the CS pin and then clocking in an opcode
of 77H followed by three dummy bytes if using the serial interface and seven dummy bytes if
using the 8-bit interface. After the last don't care bit has been clocked in, the content of the
Security Register can be clocked out on the SO or I/O7 - I/O0 pins. After the last byte of the
Security Register has been read, additional pulses on the SCK/CLK pin will simply result in
undefined data being output on the SO or I/O7 - I/O0 pins.
Deasserting the CS pin will terminate the Read Security Register operation and put the SO or
I/O7 - I/O0 pins into a high-impedance state.

Figure 10-4. Read Security Register

CS

SI or IO7 - IO0 Opcode X X X

Data Byte Data Byte Data Byte

SO or IO7 - IO0 n n+1 n+x

Each transition
represents 8 bits

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3542K–DFLASH–04/09
11. Additional Commands

11.1 Main Memory Page to Buffer Transfer

A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start
the operation for the standard DataFlash page size (1056 bytes), a 1-byte opcode, 53H for buf-
fer 1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes
comprised of 13 page address bits (PA12 - PA0), which specify the page in main memory that is
to be transferred, and 11 don’t care bits. To perform a main memory page to buffer transfer for
the binary page size (1024 bytes), the opcode 53H for buffer 1 or 55H for buffer 2, must be
clocked into the device followed by three address bytes consisting of 13 page address bits (A22
- A10) which specify the page in the main memory that is to be transferred, and 10 don’t care
bits. The CS pin must be low while toggling the SCK/CLK pin to load the opcode and the
address bytes from the input pins (SI or I/O7 - I/O0). The transfer of the page of data from the
main memory to the buffer will begin when the CS pin transitions from a low to a high state. Dur-
ing the transfer of a page of data (tXFR), the status register can be read or the RDY/BUSY can be
monitored to determine whether the transfer has been completed.

11.2 Main Memory Page to Buffer Compare

A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate
the operation for standard DataFlash page size, a 1-byte opcode, 60H for buffer 1 and 61H for
buffer 2, must be clocked into the device, followed by three address bytes consisting of 13 page
address bits (PA12 - PA0) that specify the page in the main memory that is to be compared to
the buffer, and 11 don’t care bits. To start a main memory page to buffer compare for a binary
page size, the opcode 60H for buffer 1 or 61H for buffer 2, must be clocked into the device fol-
lowed by three address bytes consisting of 13 page address bits (A22 - A10) that specify the
page in the main memory that is to be compared to the buffer, and 10 don’t care bits. The CS pin
must be low while toggling the SCK/CLK pin to load the opcode and the address bytes from the
input pins (SI or I/O7 - I/O0). On the low-to-high transition of the CS pin, the data bytes in the
selected main memory page will be compared with the data bytes in buffer 1 or buffer 2. During
this time (tCOMP), the status register and the RDY/BUSY pin will indicate that the part is busy. On
completion of the compare operation, bit 6 of the status register is updated with the result of the
compare.

11.3 Auto Page Rewrite

This mode is only needed if multiple bytes within a page or multiple pages of data are modified in
a random fashion within a sector. This mode is a combination of two operations: Main Memory
Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of
data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data
(from buffer 1 or buffer 2) is programmed back into its original page of main memory. To start the
rewrite operation for standard DataFlash page size (1056 bytes), a 1-byte opcode, 58H for buffer
1 or 59H for buffer 2, must be clocked into the device, followed by three address bytes com-
prised of 13 page address bits (PA12-PA0) that specify the page in main memory to be rewritten
and 11 don’t care bits. To initiate an auto page rewrite for a binary page size (1024 bytes), the
opcode 58H for buffer 1 or 59H for buffer 2, must be clocked into the device followed by three
address bytes consisting of 13 page address bits (A22 - A10) that specify the page in the main
memory that is to be written and 10 don’t care bits. When a low-to-high transition occurs on the
CS pin, the part will first transfer data from the page in main memory to a buffer and then pro-
gram the data from the buffer back into same page of main memory. The operation is internally
self-timed and should take place in a maximum time of tEP. During this time, the status register
and the RDY/BUSY pin will indicate that the part is busy.

22 AT45DB642D
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 AT45DB642D

If a sector is programmed or reprogrammed sequentially page by page, then the programming

algorithm shown in Figure 26-1 (page 49) is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sector, then the programming algorithm
shown in Figure 26-2 (page 50) is recommended. Each page within a sector must be
updated/rewritten at least once within every 10,000 cumulative page erase/program operations
in that sector.

11.4 Status Register Read

The status register can be used to determine the device’s ready/busy status, page size, a Main
Memory Page to Buffer Compare operation result, the Sector Protection status or the device
density. To read the status register, an opcode of D7H must be loaded into the device. After the
opcode is clocked in, the 1-byte status register will be clocked out on the output pins (SO or
I/O7 - I/O0), starting with the next clock cycle. In case of applications with 8-bit interface, opcode
D7H and two dummy clock cycles should be used. When using the serial interface, the data in
the status register, starting with the MSB (bit 7), will be clocked out on the SO pin during the next
eight clock cycles. After the one byte of the status register has been clocked out, the sequence
will repeat itself (as long as CS remains low and SCK/CLK is being toggled). The data in the sta-
tus register is constantly updated, so each repeating sequence will output new data.
Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is
not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy
state. Since the data in the status register is constantly updated, the user must toggle SCK/CLK
pin to check the ready/busy status. There are several operations that can cause the device to be
in a busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare,
Buffer to Main Memory Page Program, Main Memory Page Program through Buffer, Page
Erase, Block Erase, Sector Erase, Chip Erase and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer Compare operation is indicated using
bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the
data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does
not match the data in the buffer.
Bit 1 in the Status Register is used to provide information to the user whether or not the sector
protection has been enabled or disabled, either by software-controlled method or hardware-con-
trolled method. A logic 1 indicates that sector protection has been enabled and logic 0 indicates
that sector protection has been disabled.
Bit 0 in the Status Register indicates whether the page size of the main memory array is config-
ured for “power of 2” binary page size (1024 bytes) or standard DataFlash page size
(1056 bytes). If bit 0 is a 1, then the page size is set to 1024 bytes. If bit 0 is a 0, then the page
size is set to 1056 bytes.
The device density is indicated using bits 5, 4, 3, and 2 of the status register. For the
AT45DB642D, the four bits are 1111 The decimal value of these four binary bits does not equate
to the device density; the four bits represent a combinational code relating to differing densities
of DataFlash devices. The device density is not the same as the density code indicated in the
JEDEC device ID information. The device density is provided only for backward compatibility.

Table 11-1. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY COMP 1 1 1 1 PROTECT PAGE SIZE

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12. Deep Power-down
After initial power-up, the device will default in standby mode. The Deep Power-down command
allows the device to enter into the lowest power consumption mode. To enter the Deep Power-
down mode, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode
of B9H command must be clocked in via input pins (SI or IO7-IO0). After the last bit of the com-
mand has been clocked in, the CS pin must be de-asserted to initiate the Deep Power-down
operation. After the CS pin is de-asserted, the will device enter the Deep Power-down mode
within the maximum tEDPD time. Once the device has entered the Deep Power-down mode, all
instructions are ignored except for the Resume from Deep Power-down command.

Command Serial/8-bit Opcode

Deep Power-down Both B9H

Figure 12-1. Deep Power-down

CS

SI or IO7 - IO0 Opcode

Each transition
represents 8 bits

12.1 Resume from Deep Power-down

The Resume from Deep Power-down command takes the device out of the Deep Power-down
mode and returns it to the normal standby mode. To Resume from Deep Power-down mode, the
CS pin must first be asserted and an opcode of ABH command must be clocked in via input pins
(SI or IO7-IO0). After the last bit of the command has been clocked in, the CS pin must be de-
asserted to terminate the Deep Power-down mode. After the CS pin is de-asserted, the device
will return to the normal standby mode within the maximum tRDPD time. The CS pin must remain
high during the tRDPD time before the device can receive any commands. After resuming form
Deep Power-down, the device will return to the normal standby mode.

Command Serial/8-bit Opcode

Resume from Deep Power-down Both ABH

Figure 12-2. Resume from Deep Power-Down

CS

SI or IO7 - IO0 Opcode

Each transition
represents 8 bits

24 AT45DB642D
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 AT45DB642D

13. “Power of 2” Binary Page Size Option

“Power of 2” binary page size Configuration Register is a user-programmable nonvolatile regis-
ter that allows the page size of the main memory to be configured for binary page size
(1024 bytes) or standard DataFlash page size (1056 bytes). The “power of 2” page size is a
one-time programmable configuration register and once the device is configured for
“power of 2” page size, it cannot be reconfigured again. The devices are initially shipped
with the page size set to 1056 bytes. The user has the option of ordering binary page size (1024
bytes) devices from the factory. For details, please refer to Section 27. ”Ordering Information” on
page 51.
For the binary “power of 2” page size to become effective, the following steps must be followed:
1. Program the one-time programmable configuration resister using opcode sequence
3DH, 2AH, 80H and A6H (please see Section 13.1).
2. Power cycle the device (i.e. power down and power up again).
3. User can now program the page for the binary page size.
If the above steps are not followed in setting the the page size prior to page programming, user
may expect incorrect data during a read operation.

13.1 Programming the Configuration Register

To program the Configuration Register for “power of 2” binary page size, the CS pin must first be
asserted as it would be with any other command. Once the CS pin has been asserted, the
appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The 4-
byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H. After the
last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate
the internally self-timed program cycle. The programming of the Configuration Register should
take place in a time of tP, during which time the Status Register will indicate that the device is
busy. The device must be power-cycled after the completion of the program cycle to set the
“power of 2” page size. If the device is powered-down before the completion of the program
cycle, then setting the Configuration Register cannot be guaranteed. However, the user should
check bit 0 of the status register to see whether the page size was configured for binary page
size. If not, the command can be re-issued again.

Command Byte 1 Byte 2 Byte 3 Byte 4

Power of Two Page Size 3DH 2AH 80H A6H

Figure 13-1. Erase Sector Protection Register

CS

SI or IO7 - IO0 Opcode Opcode Opcode Opcode

Byte 1 Byte 2 Byte 3 Byte 4

Each transition
represents 8 bits

14. Manufacturer and Device ID Read

Identification information can be read from the device to enable systems to electronically query
and identify the device while it is in system. The identification method and the command opcode
comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI
Compatible Serial Interface Memory Devices”. The type of information that can be read from the

25
3542K–DFLASH–04/09
 device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the ven-
dor specific Extended Device Information.
To read the identification information, the CS pin must first be asserted and the opcode of 9FH
must be clocked into the device. After the opcode has been clocked in, the device will begin out-
putting the identification data on the SO pin during the subsequent clock cycles. The first byte
that will be output will be the Manufacturer ID followed by two bytes of Device ID information.
The fourth byte output will be the Extended Device Information String Length, which will be 00H
indicating that no Extended Device Information follows. As indicated in the JEDEC standard,
reading the Extended Device Information String Length and any subsequent data is optional.
Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put
the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not
require that a full byte of data be read.

14.1 Manufacturer and Device ID Information

14.1.1 Byte 1 – Manufacturer ID
JEDEC Assigned Code
Hex
Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1FH 0 0 0 1 1 1 1 1 Manufacturer ID 1FH = Atmel

14.1.2 Byte 2 – Device ID (Part 1)

Family Code Density Code
Hex
Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Family Code 001 = DataFlash

28H 0 0 1 0 1 0 0 0 Density Code 01000 = 64-Mbit

14.1.3 Byte 3 – Device ID (Part 2)

MLC Code Product Version Code
Hex
Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLC Code 000 = 1-bit/Cell Technology

00H 0 0 0 0 0 0 0 0 Product Version 00000 = Initial Version

14.1.4 Byte 4 – Extended Device Information String Length

Byte Count
Hex
Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00H 0 0 0 0 0 0 0 0 Byte Count 00H = 0 Bytes of Information

CS

SI 9FH
Opcode
SO 1FH 28H 00H 00H Data Data
Manufacturer ID Device ID Device ID Extended Extended Extended
Byte n Byte 1 Byte 2 Device Device Device
Information Information Information
String Length Byte x Byte x + 1

Each transition
represents 8 bits
This information would only be output
if the Extended Device Information String Length
value was something other than 00H.

Note: Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be comprised of any number of bytes. Some manufacturers may have
Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code
7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID
data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte.

26 AT45DB642D
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 AT45DB642D

14.2 Operation Mode Summary

The commands described previously can be grouped into four different categories to better
describe which commands can be executed at what times.
Group A commands consist of:
1. Main Memory Page Read
2. Continuous Array Read
3. Read Sector Protection Register
4. Read Sector Lockdown Register
5. Read Security Register

Group B commands consist of:

1. Page Erase
2. Block Erase
3. Sector Erase
4. Chip Erase
5. Main Memory Page to Buffer 1 (or 2) Transfer
6. Main Memory Page to Buffer 1 (or 2) Compare
7. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase
8. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase
9. Main Memory Page Program through Buffer 1 (or 2)
10. Auto Page Rewrite

Group C commands consist of:

1. Buffer 1 (or 2) Read
2. Buffer 1 (or 2) Write
3. Status Register Read
4. Manufacturer and Device ID Read

Group D commands consist of:

1. Erase Sector Protection Register
2. Program Sector Protection Register
3. Sector Lockdown
4. Program Security Register

If a Group A command is in progress (not fully completed), then another command in Group A,
B, C, or D should not be started. However, during the internally self-timed portion of Group B
commands, any command in Group C can be executed. The Group B commands using buffer 1
should use Group C commands using buffer 2 and vice versa. Finally, during the internally self-
timed portion of a Group D command, only the Status Register Read command should be
executed.

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15. Command Tables
Table 15-1. Read Commands
Command Serial/8-bit Opcode
Main Memory Page Read Both D2H
Continuous Array Read (Legacy Command) Both E8H
Continuous Array Read (Low Frequency) Serial 03H
Continuous Array Read Serial 0BH
Buffer 1 Read (Low Frequency) Serial D1H
Buffer 2 Read (Low Frequency) Serial D3H
Buffer 1 Read Serial D4H
Buffer 2 Read Serial D6H
Buffer 1 Read 8-bit 54H
Buffer 2 Read 8-bit 56H

Table 15-2. Program and Erase Commands

Command Serial/8-bit Opcode
Buffer 1 Write Both 84H
Buffer 2 Write Both 87H
Buffer 1 to Main Memory Page Program with Built-in Erase Both 83H
Buffer 2 to Main Memory Page Program with Built-in Erase Both 86H
Buffer 1 to Main Memory Page Program without Built-in Erase Both 88H
Buffer 2 to Main Memory Page Program without Built-in Erase Both 89H
Page Erase Both 81H
Block Erase Both 50H
Sector Erase Both 7CH
Chip Erase Both C7H, 94H, 80H, 9AH
Main Memory Page Program Through Buffer 1 Both 82H
Main Memory Page Program Through Buffer 2 Both 85H

28 AT45DB642D
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 AT45DB642D

Table 15-3. Protection and Security Commands

Command Serial/8-Bit Opcode
Enable Sector Protection Both 3DH + 2AH + 7FH + A9H
Disable Sector Protection Both 3DH + 2AH + 7FH + 9AH
Erase Sector Protection Register Both 3DH + 2AH + 7FH + CFH
Program Sector Protection Register 3DH + 2AH + 7FH + FCH
Read Sector Protection Register Both 32H
Sector Lockdown Both 3DH + 2AH + 7FH + 30H
Read Sector Lockdown Register Both 35H
Program Security Register Both 9BH + 00H + 00H + 00H
Read Security Register Both 77H

Table 15-4. Additional Commands

Command Serial/8-bit Opcode
Main Memory Page to Buffer 1 Transfer Both 53H
Main Memory Page to Buffer 2 Transfer Both 55H
Main Memory Page to Buffer 1 Compare Both 60H
Main Memory Page to Buffer 2 Compare Both 61H
Auto Page Rewrite through Buffer 1 Both 58H
Auto Page Rewrite through Buffer 2 Both 59H
Deep Power-down Both B9H
Resume from Deep Power-down Both ABH
Status Register Read Both D7H
Manufacturer and Device ID Read Serial 9FH

29
3542K–DFLASH–04/09
Table 15-5. Detailed Bit-level Addressing Sequence for Binary Page Size (1024 Bytes)
Page Size = 1024 bytes Address Byte Address Byte Address Byte

Additional
Don’t Care

A20
A19
A18
A23

A17

A16

A15
A14

A12
A22
A21

A10
A11
A13

A2
A3
A6

A1
A4

A0
A9

A8

A7

A5
Opcode Opcode Bytes*
03h 0 0 0 0 0 0 1 1 x A A A A A A A A A A A A A A A A A A A A A A A N/A

0Bh 0 0 0 0 1 0 1 1 x A A A A A A A A A A A A A A A A A A A A A A A 1

50h 0 1 0 1 0 0 0 0 x A A A A A A A A A A x x x x x x x x x x x x x N/A

53h 0 1 0 1 0 0 1 1 x A A A A A A A A A A A A A x x x x x x x x x x N/A

54h 0 1 0 1 0 1 0 0 x x x x x x x x x x x x x x A A A A A A A A A A 2*

55h 0 1 0 1 0 1 0 1 x A A A A A A A A A A A A A x x x x x x x x x x N/A

56h 0 1 0 1 0 1 1 0 x x x x x x x x x x x x x x A A A A A A A A A A 2*

58h 0 1 0 1 1 0 0 0 x A A A A A A A A A A A A A x x x x x x x x x x N/A

59h 0 1 0 1 1 0 0 1 x A A A A A A A A A A A A A x x x x x x x x x x N/A

60h 0 1 1 0 0 0 0 0 x A A A A A A A A A A A A A x x x x x x x x x x N/A

61h 0 1 1 0 0 0 0 1 x A A A A A A A A A A A A A x x x x x x x x x x N/A

77h 0 1 1 1 0 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x 0 or 4*

7Ch 0 1 1 1 1 1 0 0 x A A A A A x x x x x x x x x x x x x x x x x x N/A

81h 1 0 0 0 0 0 0 1 x A A A A A A A A A A A A A x X x x x x x x x x N/A

82h 1 0 0 0 0 0 1 0 x A A A A A A A A A A A A A A A A A A A A A A A N/A

83h 1 0 0 0 0 0 1 1 x A A A A A A A A A A A A A x X x x x x x x x x N/A

84h 1 0 0 0 0 1 0 0 x x x x x x x x x x x x x x A A A A A A A A A A N/A

85h 1 0 0 0 0 1 0 1 x A A A A A A A A A A A A A A A A A A A A A A A N/A

86h 1 0 0 0 0 1 1 0 x A A A A A A A A A A A A A x x x x x x x x x x N/A

87h 1 0 0 0 0 1 1 1 x x x x x x x x x x x x x x A A A A A A A A A A N/A

88h 1 0 0 0 1 0 0 0 x A A A A A A A A A A A A A x x x x x x x x x x N/A

89h 1 0 0 0 1 0 0 1 x A A A A A A A A A A A A A x x x x x x x x x x N/A

9Fh 1 0 0 1 1 1 1 1 N/A N/A N/A N/A

B9h 1 0 1 1 1 0 0 1 N/A N/A N/A N/A

ABh 1 0 1 0 1 0 1 1 N/A N/A N/A N/A

D1h 1 1 0 1 0 0 0 1 x x x x x x x x x x x x x x A A A A A A A A A A N/A

D2h 1 1 0 1 0 0 1 0 x A A A A A A A A A A A A A A A A A A A A A A A 4 or 19*

D3h 1 1 0 1 0 0 1 1 x x x x x x x x x x x x x x A A A A A A A A A A N/A

D4h 1 1 0 1 0 1 0 0 x x x x x x x x x x x x x x A A A A A A A A A A 1

D6h 1 1 0 1 0 1 1 0 x x x x x x x x x x x x x x A A A A A A A A A A 1

D7h 1 1 0 1 0 1 1 1 N/A N/A N/A 2*

E8h 1 1 1 0 1 0 0 0 x A A A A A A A A A A A A A A A A A A A A A A A 4 or 19*

Notes: x = Don’t Care A = Address Bit

*The number with (*) is for 8-bit interface.

30 AT45DB642D
3542K–DFLASH–04/09
 AT45DB642D

Table 15-6. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (1056 Bytes)
Page Size = 1056 bytes Address Byte Address Byte Address Byte

Additional

PA10

BA10
PA12
PA11

BA2

BA0
BA3
BA6

BA1
PA9
PA8
PA7
Don’t Care

BA9

BA8

BA7

BA5
PA6

PA5

PA4
PA3

PA1
PA0

BA4
PA2
Opcode Opcode Bytes*
03h 0 0 0 0 0 0 1 1 P P P P P P P P P P P P P B B B B B B B B B B B N/A

0Bh 0 0 0 0 1 0 1 1 P P P P P P P P P P P P P B B B B B B B B B B B 1

50h 0 1 0 1 0 0 0 0 P P P P P P P P P P x x x x x x x x x x x x x x N/A

53h 0 1 0 1 0 0 1 1 P P P P P P P P P P P P P x x x x x x x x x x x N/A

54h 0 1 0 1 0 1 0 0 x x x x x x x x x x x x x B B B B B B B B B B B 2*

55h 0 1 0 1 0 1 0 1 P P P P P P P P P P P P P x x x x x x x x x x x N/A

56h 0 1 0 1 0 1 1 0 x x x x x x x x x x x x x B B B B B B B B B B B 2*

58h 0 1 0 1 1 0 0 0 P P P P P P P P P P P P P x x x x x x x x x x x N/A

59h 0 1 0 1 1 0 0 1 P P P P P P P P P P P P P x x x x x x x x x x x N/A

60h 0 1 1 0 0 0 0 0 P P P P P P P P P P P P P x x x x x x x x x x x N/A

61h 0 1 1 0 0 0 0 1 P P P P P P P P P P P P P x x x x x x x x x x x N/A

77h 0 1 1 1 0 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x 0 or 4*

7Ch 0 1 1 1 1 1 0 0 P P P P P x x x x x x x x x x x x x x x x x x x N/A

81h 1 0 0 0 0 0 0 1 P P P P P P P P P P P P P x x x x x x x x x x x N/A

82h 1 0 0 0 0 0 1 0 P P P P P P P P P P P P P B B B B B B B B B B B N/A

83h 1 0 0 0 0 0 1 1 P P P P P P P P P P P P P x x x x x x x x x x x N/A

84h 1 0 0 0 0 1 0 0 x x x x x x x x x x x x x B B B B B B B B B B B N/A

85h 1 0 0 0 0 1 0 1 P P P P P P P P P P P P P B B B B B B B B B B B N/A

86h 1 0 0 0 0 1 1 0 P P P P P P P P P P P P P x x x x x x x x x x x N/A

87h 1 0 0 0 0 1 1 1 x x x x x x x x x x x x x B B B B B B B B B B B N/A

88h 1 0 0 0 1 0 0 0 P P P P P P P P P P P P P x x x x x x x x x x x N/A

89h 1 0 0 0 1 0 0 1 P P P P P P P P P P P P P x x x x x x x x x x x N/A

9Fh 1 0 0 1 1 1 1 1 N/A N/A N/A N/A

B9h 1 0 1 1 1 0 0 1 N/A N/A N/A N/A

ABh 1 0 1 0 1 0 1 1 N/A N/A N/A N/A

D1h 1 1 0 1 0 0 0 1 x x x x x x x x x x x x x B B B B B B B B B B B N/A

D2h 1 1 0 1 0 0 1 0 P P P P P P P P P P P P P B B B B B B B B B B B 4 or 19*

D3h 1 1 0 1 0 0 0 1 x x x x x x x x x x x x x B B B B B B B B B B B N/A

D4h 1 1 0 1 0 1 0 0 x x x x x x x x x x x x x B B B B B B B B B B B 1

D6h 1 1 0 1 0 1 1 0 x x x x x x x x x x x x x B B B B B B B B B B B 1

D7h 1 1 0 1 0 1 1 1 N/A N/A N/A 2*

E8h 1 1 1 0 1 0 0 0 P P P P P P P P P P P P P B B B B B B B B B B B 4 or 19*

P = Page Address Bit B = Byte/Buffer Address Bitx = Don’t Care

*The number with (*) is for 8-bit interface.

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3542K–DFLASH–04/09
16. Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device
will default to Mode 3. In addition, the output pins (SO or I/O7 - I/O0) will be in a high impedance
state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The
mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling
the inactive clock state.

16.1 Initial Power-up/Reset Timing Restrictions

At power up, the device must not be selected until the supply voltage reaches the VCC (min.) and
further delay of tVCSL. During power-up, the internal Power-on Reset circuitry keeps the device in
reset mode until the VCC rises above the Power-on Reset threshold value (VPOR). At this time, all
operations are disabled and the device does not respond to any commands. After power up is
applied and the VCC is at the minimum operating voltage VCC (min.), the tVCSL delay is required
before the device can be selected in order to perform a read operation.
Similarly, the tPUW delay is required after the VCC rises above the Power-on Reset threshold
value (VPOR) before the device can perform a write (Program or Erase) operation. After initial
power-up, the device will default in Standby mode.

Symbol Parameter Min Typ Max Units

tVCSL VCC (min.) to Chip Select low 50 µs
Power-Up Device Delay before Write
tPUW 20 ms
allowed
VPOR Power-ON Reset Voltage 1.5 2.5 V

17. System Considerations

The RapidS serial interface is controlled by the clock SCK, serial input SI and chip select CS
pins. The sequential 8-bit Rapid8 is controlled by the clock CLK, 8 I/Os and chip select CS pins.
These signals must rise and fall monotonically and be free from noise. Excessive noise or ring-
ing on these pins can be misinterpreted as multiple edges and cause improper operation of the
device. The PC board traces must be kept to a minimum distance or appropriately terminated to
ensure proper operation. If necessary, decoupling capacitors can be added on these pins to pro-
vide filtering against noise glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A
key element of any voltage regulation scheme is its current sourcing capability. Like all Flash
memories, the peak current for DataFlash occur during the programming and erase operation.
The regulator needs to supply this peak current requirement. An under specified regulator can
cause current starvation. Besides increasing system noise, current starvation during program-
ming or erase can lead to improper operation and possible data corruption.
The device uses an adaptive algorithm during program and erase operations. In order to opti-
mize the erase and program time, use the RDY/BUSY bit of the status register or the
RDY/BUSY pin to determine whether the program or erase operation was completed. Fixed tim-
ing is not recommended.

32 AT45DB642D
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 AT45DB642D

18. Electrical Specifications

Table 18-1. Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. The "Absolute Maximum Rat-
ings" are stress ratings only and functional
All Input Voltages (except VCC but including NC pins) operation of the device at these or any other con-
with Respect to Ground ...................................-0.6V to +6.25V ditions beyond those indicated in the operational
sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for
extended periods may affect device reliability.
Voltage Extremes referenced in the "Absolute
All Output Voltages
Maximum Ratings" are intended to accommo-
with Respect to Ground .............................-0.6V to VCC + 0.6V
date short duration undershoot/overshoot condi-
tions and does not imply or guarantee functional
device operation at these levels for any extended
period of time

Table 18-2. DC and AC Operating Range

AT45DB642D
Operating Temperature (Case) Ind. -40°C to 85°C
VCC Power Supply 2.7V to 3.6V

33
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Table 18-3. DC Characteristics
Symbol Parameter Condition Min Typ Max Units
CS, RESET, WP = VIH, all inputs at
IDP Deep Power-down Current 15 25 µA
CMOS levels
CS, RESET, WP = VIH, all inputs at
ISB Standby Current 25 50 µA
CMOS levels
Active Current, Read Operation, f = 33 MHz; IOUT = 0 mA;
ICC1(1) 10 15 mA
Serial Interface VCC = 3.6V
Active Current, Read Operation, f = 33 MHz; IOUT = 0 mA;
ICC2(1) 10 15 mA
Rapid8 Interface VCC = 3.6V
Active Current, Program
ICC3 VCC = 3.6V 25 mA
Operation, Page Program
Active Current, Page Erase, Block
ICC4 VCC = 3.6V 25 mA
Erase, Sector Erase Operation
ILI Input Load Current VIN = CMOS levels 1 µA
ILO Output Leakage Current VI/O = CMOS levels 1 µA
VIL Input Low Voltage VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 V
VOL Output Low Voltage IOL = 1.6 mA; VCC = 2.7V 0.4 V
VOH Output High Voltage IOH = -100 µA VCC - 0.2V V
Notes: 1. AICC1 and ICC2 during a buffer read is 25 mA maximum.
2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed by design to be 5-Volt tolerant.

34 AT45DB642D
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 AT45DB642D
Table 18-4. AC Characteristics – RapidS/Serial Interface
Symbol Parameter Min Typ Max Units
fSCK SCK Frequency 66 MHz
fCAR1 SCK Frequency for Continuous Array Read 66 MHz
SCK Frequency for Continuous Array Read
fCAR2 33 MHz
(Low Frequency)
tWH SCK High Time 6.8 ns
tWL SCK Low Time 6.8 ns
tSCKR(1) SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns
tSCKF(1) SCK Fall Time, Peak-to-Peak (Slew Rate) 0.1 V/ns
tCS Minimum CS High Time 50 ns
tCSS CS Setup Time 5 ns
tCSH CS Hold Time 5 ns
tCSB CS High to RDY/BUSY Low 100 ns
tSU Data In Setup Time 2 ns
tH Data In Hold Time 3 ns
tHO Output Hold Time 0 ns
tDIS Output Disable Time 27 35 ns
tV Output Valid 6 ns
tWPE WP Low to Protection Enabled 1 µs
tWPD WP High to Protection Disabled 1 µs
tEDPD CS High to Deep Power-down Mode 3 µs
tRDPD CS High to Standby Mode 35 µs
tXFR Page to Buffer Transfer Time 400 µs
tcomp Page to Buffer Compare Time 400 µs
tEP Page Erase and Programming Time (1,024/1,056 bytes) 17 40 ms
tP Page Programming Time (1,024/1,056 bytes) 3 6 ms
tPE Page Erase Time (1,024/1,056 bytes) 15 35 ms
tBE Block Erase Time (8,192/8,448 bytes) 45 100 ms
tSE Sector Erase Time (262,144/270,336 bytes) 1.6 5 s
tCE Chip Erase Time TBD TBD s
tRST RESET Pulse Width 10 µs
tREC RESET Recovery Time 1 µs
Note: 1. Values are based on device characterization, not 100% tested in production.

35
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Table 18-5. AC Characteristics – Rapid8 8-bit Interface
Symbol Parameter Min Typ Max Units
fSCK1 CLK Frequency 50 MHz
fCAR1 CLK Frequency for Continuous Array Read 50 MHz
tWH CLK High Time 9 ns
tWL CLK Low Time 9 ns
tCLKR(1) CLK Rise Time, Peak-to-Peak (Slew Rate) 0.1 V/ns
tCLKF(1) CLK Fall Time, Peak-to-Peak (Slew Rate) 0.1 V/ns
tCS Minimum CS High Time 50 ns
tCSS CS Setup Time 5 ns
tCSH CS Hold Time 5 ns
tCSB CS High to RDY/BUSY Low 100 ns
tSU Data In Setup Time 2 ns
tH Data In Hold Time 5 ns
tHO Output Hold Time 0 ns
tDIS Output Disable Time 12 ns
tV Output Valid 12 ns
tWPE WP Low to Protection Enabled 1 µs
tWPD WP High to Protection Disabled 1 µs
tEDPD CS High to Deep Power-down Mode 3 µs
tRDPD CS High to Standby Mode 35 µs
tXFR Page to Buffer Transfer Time 400 µs
tcomp Page to Buffer Compare Time 400 µs
tEP Page Erase and Programming Time (1,024/1,056 bytes) 17 40 ms

tP Page Programming Time (1,024/1,056 bytes) 3 6 ms

tPE Page Erase Time (1,024/1,056 bytes) 15 35 ms

tBE Block Erase Time (8,192/8,448 bytes) 45 100 ms

tSE Sector Erase Time (262,144/270,336 bytes) 1.6 5 s

tRST RESET Pulse Width 10 µs
tREC RESET Recovery Time 1 µs
Note: Values are based on device characterization, not 100% tested in production.

19. Input Test Waveforms and Measurement Levels

AC 2.4V AC
DRIVING 1.5V MEASUREMENT
LEVELS 0.45V LEVEL

tR, tF < 2 ns (10% to 90%)

36 AT45DB642D
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 AT45DB642D

20. Output Test Load

DEVICE
UNDER
TEST
30 pF

21. AC Waveforms
Six different timing waveforms are shown below. Waveform 1 shows the SCK/CLK signal being
low when CS makes a high-to-low transition, and waveform 2 shows the SCK/CLK signal being
high when CS makes a high-to-low transition. In both cases, output SO becomes valid while the
SCK/CLK signal is still low (SCK/CLK low time is specified as tWL). Timing waveforms 1 and 2
conform to RapidS serial interface but for frequencies up to 66 MHz. Waveforms 1 and 2 are
compatible with SPI Mode 0 and SPI Mode 3, respectively.
Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These
are similar to waveform 1 and waveform 2, except that output SO is not restricted to become
valid during the tWL period. These timing waveforms are valid over the full frequency range (max-
imum frequency = 66 MHz) of the RapidS serial case. Waveform 5 and waveform 6 are for 8-bit
Rapid8 interface over the full frequency range of operation (maximum frequency = 50 MHz).

21.1 Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66 MHz)

tCS
CS

tCSS tWH tWL tCSH

SCK/CLK

tV tHO tDIS
HIGH IMPEDANCE HIGH IMPEDANCE
SO VALID OUT

tSU tH

SI VALID IN

21.2 Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66 MHz)

tCS
CS

tCSS tWL tWH tCSH

SCK/CLK

tV tHO tDIS
HIGH Z HIGH IMPEDANCE
SO VALID OUT

tSU tH

SI VALID IN

Note: To operate the device at 50 MHz in SPI mode, the combined CPU setup time and rise/fall time should be less than 2 ns.

37
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21.3 Waveform 3 – RapidS Mode 0 (FMAX = 66 MHz)
tCS
CS

tCSS tWH tWL tCSH

SCK/CLK

tV tHO tDIS
HIGH IMPEDANCE HIGH IMPEDANCE
SO VALID OUT

tSU tH

SI VALID IN

21.4 Waveform 4 – RapidS Mode 3 (FMAX = 66 MHz)

tCS
CS

tCSS tWL tWH tCSH

SCK/CLK

tV tHO tDIS
HIGH Z HIGH IMPEDANCE
SO VALID OUT

tSU tH

SI VALID IN

21.5 Waveform 5 – Rapid8 Mode 0 (FMAX = 50 MHz)

tCS
CS

tCSS tWH tWL tCSH

SCK/CLK

tV tHO tDIS
HIGH IMPEDANCE HIGH IMPEDANCE
I/O7 - I/O0 VALID OUT
(OUTPUT)
tSU tH

I/O7 - I/O0 VALID IN

(INPUT)

21.6 Waveform 6 – Rapid8 Mode 3 (FMAX = 50 MHz)

tCS
CS

tCSS tWL tWH tCSH

SCK/CLK

tV tHO tDIS
HIGH Z HIGH IMPEDANCE
I/O7 - I/O0 VALID OUT
(OUTPUT)
tSU tH

I/O7 - I/O0 VALID IN

(INPUT)

38 AT45DB642D
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 AT45DB642D

21.7 Utilizing the RapidS™ Function

To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full
clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is
designed to always clock its data out on the falling edge of the SCK signal and clock data in on
the rising edge of SCK.
For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the fall-
ing edge of SCK, the host controller should wait until the next falling edge of SCK to latch the
data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order
to give the DataFlash a full clock cycle to latch the incoming data in on the next rising edge of
SCK.

Figure 21-1. RapidS Mode

Slave CS

1 8 1 8 1
2 3 4 5 6 7 2 3 4 5 6 7
SCK
B E
A C D

MOSI MSB LSB

BYTE-MOSI H
G I
F

MISO MSB LSB

BYTE-SO

MOSI = Master Out, Slave In

MISO = Master In, Slave Out
The Master is the host controller and the Slave is the DataFlash

The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
A. Master clocks out first bit of BYTE-MOSI on the rising edge of SCK.
B. Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK.
C. Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK.
D. Last bit of BYTE-MOSI is clocked out from the Master.
E. Last bit of BYTE-MOSI is clocked into the slave.
F. Slave clocks out first bit of BYTE-SO.
G. Master clocks in first bit of BYTE-SO.
H. Slave clocks out second bit of BYTE-SO.
I. Master clocks in last bit of BYTE-SO.

39
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21.8 Utilizing the Rapid8™ Function
The Rapid8 functions like RapidS but with 8 bits of data instead of 1 bit. A full clock cycle must
be used to transmit data back and forth across the 8 bit bus. The DataFlash is designed to
always clock its data out on the falling edge of the SCK signal and clock data in on the rising
edge of SCK.
For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the fall-
ing edge of SCK, the host controller should wait until the next falling edge of SCK to latch the
data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order
to give the DataFlash a full clock cycle to latch the incoming data in on the next rising edge of
SCK.

Figure 21-2. Rapid8 Mode

Slave CS

1
2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
B tV D
E
F
A C G

I/O7-0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE a BYTE b BYTE c BYTE d BYTE e BYTE f BYTE g BYTE h

MOSI = Master Out, Slave In

MISO = Master In, Slave Out
The Master would be the ASIC/MCU and the Slave would be the memory device.

The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
A. Master clocks out BYTE 1 on the rising edge of SCK.
B. Slave clocks in BYTE 1 on the next rising edge of SCK.
C. Master clocks out BYTE 2 on the same rising edge of SCK.
D. Slave clocks in BYTE 6 (last input byte).
E. Slave clocks out BYTE a (first output byte).
F. Master clocks in BYTE a.
G. Master clocks in BYTE h (last output byte).

21.9 Reset Timing

CS
tREC tCSS

SCK/CLK
tRST

RESET

HIGH IMPEDANCE HIGH IMPEDANCE

SO or I/O7 - I/O0
(OUTPUT)

SI or I/O7 - I/O0
(INPUT)

Note: The CS signal should be in the high state before the RESET signal is deasserted.

40 AT45DB642D
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 AT45DB642D

21.10 Command Sequence for Read/Write Operations for Page Size 1024 Bytes (Except Status
Register Read, Manufacturer and Device ID Read)

SI or I/O7 - I/O0 CMD 8 bits 8 bits 8 bits

(INPUT)?

MSB XXX XXXX XXXX XXXX XXXX XXXX LSB

Page Address Byte/Buffer Address

(A22 - A10) (A9 - A0/BFA9 - BFA0)

21.11 Command Sequence for Read/Write Operations for Page Size 1056 Bytes (Except Status
Register Read, Manufacturer and Device ID Read)
SI or I/O7 - I/O0 CMD 8 bits 8 bits 8 bits
(INPUT)?

MSB XXXX XXXX XXXX XXXX XXXX XXXX LSB

Page Address Byte/Buffer Address

(PA12 - PA0) (BA10 - BA0/BFA10 - BFA0)

22. Write Operations

The following block diagram and waveforms illustrate the various write sequences available.

FLASH MEMORY ARRAY

PAGE (1024/1056 BYTES)

BUFFER 1 TO BUFFER 2 TO
MAIN MEMORY MAIN MEMORY
PAGE PROGRAM PAGE PROGRAM

BUFFER 1 (1024/1056 BYTES) BUFFER 2 (1024/1056 BYTES)

BUFFER 1 BUFFER 2
WRITE WRITE

I/O INTERFACE

SI I/O7 - I/O0

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22.1 Buffer Write
Completes writing into selected buffer
CS

BINARY PAGE SIZE

14 DON'T CARE + BFA9-BFA0
SI or I/O7 - I/O0
CMD X X···X, BFA10-8 BFA7-0 n n+1 Last Byte
(INPUT)

22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation

CS
BINARY PAGE SIZE
A22-A10 + 10 DON'T CARE BITS

SI or I/O7 - I/O0 CMD PA12-5 PA4-0, XXX XXXX XX

(INPUT)

Each transition n = 1st byte read

represents 8 bits n+1 = 2nd byte read

23. Read Operations

The following block diagram and waveforms illustrate the various read sequences available.

FLASH MEMORY ARRAY

PAGE (1024/1056 BYTES)

MAIN MEMORY MAIN MEMORY

PAGE TO PAGE TO
BUFFER 1 BUFFER 2

BUFFER 1 (1024/1056 BYTES) BUFFER 2 (1024/1056 BYTES)

BUFFER 1 MAIN MEMORY BUFFER 2

READ PAGE READ READ

I/O INTERFACE

SO I/O7 - I/O0

42 AT45DB642D
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 AT45DB642D

23.1 Main Memory Page Read

CS

ADDRESS FOR BINARY PAGE SIZE

A22-A16 A15-A8 A7-A0
SI or I/O7 - I/O0
CMD PA12-5, PA4-0 BA10-8 BA7-0 X X
(INPUT)

4 Dummy Bytes for Serial

19 Dummy Bytes for Parallel
SO or I/O7 - I/O0
n n+1
(OUTPUT)

23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer

CS

BINARY PAGE SIZE

A22-A10 + 10 DON'T CARE BITS

SI or I/O7 - I/O0
CMD PA12-5 PA4-0, XXX XXXX XXXX
(INPUT)

SO or I/O7 - I/O0
(OUTPUT)

23.3 Buffer Read

CS

BINARY PAGE SIZE

14 DON'T CARE + BFA9-BFA0

SI or IO7 - IO0 CMD X X..X, BFA10-8 BFA7- 0 X

No Dummy Byte (Serial, opcodes D1H and D3H)
1 Dummy Byte (Serial, opcodes D4H and D6H)
2 Dummy Bytes (Parallel)

SO or IO7 - IO0 n n+1

Each transition
represents 8 bits

43
3542K–DFLASH–04/09
24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 3

24.1 Continuous Array Read (Legacy Opcode E8H)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 62 63 64 65 66 67 68 69 70 71 72
SCK

OPCODE ADDRESS BITS 32 DON'T CARE BITS

SI 1 1 1 0 1 0 0 0 A A A A A A A A A X X X X X X
MSB MSB MSB

DATA BYTE 1

HIGH-IMPEDANCE
SO D D D D D D D D D D
MSB MSB
BIT 8191/8447 BIT 0 OF
OF PAGE n PAGE n+1

24.2 Continuous Array Read (Opcode 0BH)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK

OPCODE ADDRESS BITS A23 - A0 DON'T CARE

SI 0 0 0 0 1 0 1 1 A A A A A A A A A X X X X X X X X
MSB MSB MSB

DATA BYTE 1

HIGH-IMPEDANCE
SO D D D D D D D D D D
MSB MSB

24.3 Continuous Array Read (Low Frequency: Opcode 03H)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE ADDRESS BITS A23-A0

SI 0 0 0 0 0 0 1 1 A A A A A A A A A
MSB MSB

DATA BYTE 1

HIGH-IMPEDANCE
SO D D D D D D D D D D
MSB MSB

44 AT45DB642D
3542K–DFLASH–04/09
 AT45DB642D

24.4 Main Memory Page Read (Opcode: D2H)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 62 63 64 65 66 67 68 69 70 71 72
SCK

OPCODE ADDRESS BITS 32 DON'T CARE BITS

SI 1 1 0 1 0 0 1 0 A A A A A A A A A X X X X X X
MSB MSB MSB

DATA BYTE 1

HIGH-IMPEDANCE
SO D D D D D D D D D D
MSB MSB

24.5 Buffer Read (Opcode D4H or D6H)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
ADDRESS BITS
BINARY PAGE SIZE = 14 DON'T CARE + BFA9-BFA0
STANDARD DATAFLASH PAGE SIZE = DON'T CARE
OPCODE 13 DON'T CARE + BFA10-BFA0

SI 1 1 0 1 0 1 0 0 X X X X X X A A A X X X X X X X X
MSB MSB MSB

DATA BYTE 1

HIGH-IMPEDANCE
SO D D D D D D D D D D
MSB MSB

24.6 Buffer Read (Low Frequency: Opcode D1H or D3H)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40
SCK
ADDRESS BITS
BINARY PAGE SIZE = 14 DON'T CARE + BFA9-BFA0
STANDARD DATAFLASH PAGE SIZE =
OPCODE 13 DON'T CARE + BFA10-BFA0

SI 1 1 0 1 0 0 0 1 X X X X X X A A A
MSB MSB

DATA BYTE 1

HIGH-IMPEDANCE
SO D D D D D D D D D D
MSB MSB

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3542K–DFLASH–04/09
24.7 Read Sector Protection Register (Opcode 32H)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE DON'T CARE

SI 0 0 1 1 0 0 1 0 X X X X X X X X X
MSB MSB

DATA BYTE 1

HIGH-IMPEDANCE
SO D D D D D D D D D
MSB MSB

24.8 Read Sector Lockdown Register (Opcode 35H)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE DON'T CARE

SI 0 0 1 1 0 1 0 1 X X X X X X X X X
MSB MSB

DATA BYTE 1

HIGH-IMPEDANCE
SO D D D D D D D D D
MSB MSB

24.9 Read Security Register (Opcode 77H)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 29 30 31 32 33 34 35 36 37 38 39 40
SCK
OPCODE DON'T CARE

SI 0 1 1 1 0 1 1 1 X X X X X X X X X
MSB MSB

DATA BYTE 1

HIGH-IMPEDANCE
SO D D D D D D D D D
MSB MSB

46 AT45DB642D
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 AT45DB642D

24.10 Status Register Read (Opcode D7H)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCK
OPCODE

SI 1 1 0 1 0 1 1 1
MSB

STATUS REGISTER DATA STATUS REGISTER DATA

HIGH-IMPEDANCE
SO D D D D D D D D D D D D D D D D D D
MSB MSB MSB

24.11 Manufacturer and Device Read (Opcode 9FH)

CS

0 6 7 8 14 15 16 22 23 24 30 31 32 38
SCK
OPCODE

SI 9FH

HIGH-IMPEDANCE
SO 1FH DEVICE ID BYTE 1 DEVICE ID BYTE 2 00H

Note: Each transition shown for SI and SO represents one byte (8 bits)

47
3542K–DFLASH–04/09
25. Detailed 8-bit Read Waveforms – Rapid8 Mode 0/Mode 3

25.1 Continuous Array Read (Opcode: E8H)

CS

CLK 0 1 2 3 21 22 23 24 25 26

tSU BINARY & STANDARD

DATAFLASH PAGE SIZE 19 DUMMY BYTES
I/O7-I/O0
CMD ADDR ADDR ADDR X X X
(INPUT)
tV
DATA OUT
I/O7-I/O0 HIGH IMPEDANCE
DATA DATA DATA DATA DATA DATA DATA DATA DATA
(OUTPUT)

BYTE 1023/1055 BYTE 0

OF OF
PAGE n PAGE n+1

25.2 Main Memory Page Read (Opcode: D2H)

CS

CLK 0 1 2 3 19 20 21 22 23 24 25 26

tSU BINARY & STANDARD

DATAFLASH PAGE SIZE 19 DUMMY BYTES
I/07-I/O0
CMD ADDR ADDR ADDR X X X X X
(INPUT)
tV
DATA OUT
I/07-I/O0 HIGH IMPEDANCE
DATA DATA DATA DATA
(OUTPUT)

25.3 Buffer Read (Opcode: 54H or 56H)

CS

CLK 0 1 2 3 4 5 6 7

ADDRESS BYTES
tSU BINARY & STANDARD
DATAFLASH PAGE SIZE DUMMY BYTES
I/O7-I/O0
CMD X ADDR ADDR X X
(INPUT)
tV
DATA OUT
I/O7-I/O0 HIGH IMPEDANCE
DATA DATA DATA
(OUTPUT)

48 AT45DB642D
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 AT45DB642D

25.4 Status Register Read (Opcode: D7H)

CS

CLK 0 1 2 3

tSU

I/O7-I/O0 CMD
(INPUT)
tV
I/O7-I/O0 HIGH
X X DATA DATA
(OUTPUT) IMPEDANCE
STATUS REGISTER
OUTPUT

26. Auto Page Rewrite Flowchart

Figure 26-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially
START
provide address
and data

BUFFER WRITE
(84H, 87H)

MAIN MEMORY PAGE PROGRAM

THROUGH BUFFER
(82H, 85H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)

END

Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-
page.
2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.

49
3542K–DFLASH–04/09
Figure 26-2. Algorithm for Randomly Modifying Data
START

provide address of
page to modify

MAIN MEMORY PAGE If planning to modify multiple

TO BUFFER TRANSFER bytes currently stored within
(53H, 55H) a page of the Flash array

BUFFER WRITE
(84H, 87H)

MAIN MEMORY PAGE PROGRAM

THROUGH BUFFER
(82H, 85H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)

(2)
AUTO PAGE REWRITE
(58H, 59H)

INCREMENT PAGE
(2)
ADDRESS POINTER

END

Notes: 1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000
cumulative page erase and program operations.
2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command
must use the address specified by the Page Address Pointer.
3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000
cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application
note AN-4 (“Using Atmel’s Serial DataFlash”) for more details.

50 AT45DB642D
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 AT45DB642D

27. Ordering Information

27.1 Ordering Code Detail

AT 4 5DB 6 4 2D– S SU

Atmel Designator

Product Family Device Grade

U = Matte Sn lead finish, industrial
temperature range (-40°C to +85°C)

Device Density Package Option

CN = 8-lead, 6 x 8 mm CASON
64 = 64-megabit
T = 28-lead, 8 x 13.4 mm TSOP
C = 24 Ball BGA

Interface
2 = Dual

Device Revision

51
3542K–DFLASH–04/09
27.2 Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code(1)(2) Package Lead Finish Operating Voltage fSCK (MHz) Operation Range
AT45DB642D-CNU
AT45DB642D-CNU-SL954(3) 8CN3 Industrial
AT45DB642D-CNU-SL955(4) Matte Sn 2.7V to 3.6V 66
(-40°C to 85°C)
AT45DB642D-TU 28T 2.7V to 3.6V
AT45DB642D-CU 24C1 Matte Sn 2.7V to 3.6V 66
Notes: 1. The shipping carrier option is not marked on the devices.
2. Standard parts are shipped with the page size set to 1056 bytes. The user is able to configure these parts to a 1024-byte
page size if desired.
3. Parts ordered with suffix SL954 are shipped in bulk with the page size set to 1024 bytes. Parts will have a 954 or SL954
marked on them.
4. Parts ordered with suffix SL955 are shipped in tape and reel with the page size set to 1024 bytes. Parts will have a 954 or
SL954 marked on them.

Package Type
28T 28-lead, (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP)
8CN3 8-pad (6 mm x 8 mm) Chip Array Small Outline No Lead Package (CASON)
24C1 24-Ball, 6mm x 8mm x 1,4mm Ball Grid Array with a 1mm pitch 5 x 5 Ball Matrix

52 AT45DB642D
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 AT45DB642D

28. Packaging Information

28.1 28T – TSOP, Type 1

PIN 1
0º ~ 5º
c

Pin 1 Identifier Area

D1 D

e b L1

E A2 A SEATING PLANE GAGE PLANE

COMMON DIMENSIONS
A1 (Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 1.20
A1 0.05 – 0.15
A2 0.90 1.00 1.05
Notes: 1. This package conforms to JEDEC reference MO-183. D 13.20 13.40 13.60
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. D1 11.70 11.80 11.90 Note 2
3. Lead coplanarity is 0.10 mm maximum. E 7.90 8.00 8.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.55 BASIC

12/06/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline 28T C
R San Jose, CA 95131 Package, Type I (TSOP)

53
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28.2 8CN3 – CASON

Marked Pin1 Indentifier

A
D A1

Top View Side View

Pin1 Pad Corner

0.10 mm
L1
TYP

8 1

e
7 2
COMMON DIMENSIONS
(Unit of Measure = mm)
6 3
SYMBOL MIN NOM MAX NOTE
b
A 1.0
5 4
A1 0.17 0.21 0.25
b 0.41 TYP 4
e1 L
D 7.90 8.00 8.10
Bottom View E 5.90 6.00 6.10
e 1.27 BSC
e1 1.095 REF
L 0.67 TYP 4
L1 0.92 0.97 1.02 4
Notes: 1. All dimensions and tolerance conform to ASME Y 14.5M, 1994.
2. The surface finish of the package shall be EDM Charmille #24-27.
3. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2o.
4. Metal Pad Dimensions.

7/10/03
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8CN3, 8-pad (6 x 8 x 1.0 mm Body), Lead Pitch 1.27 mm, 8CN3 B
R San Jose, CA 95131 Chip Array Small Outline No Lead Package (CASON)

54 AT45DB642D
3542K–DFLASH–04/09
 AT45DB642D

28.3 24C1 - Ball Grid Array

Dimensions in Millimeters and (Inches).

Controlling dimension: Millimeters.

6.10(0.240)
5.90(0.232)

A1 ID

8.10(0.319)
7.90(0.311)
SIDE VIEW

0.30 (0.012)MIN
TOP VIEW
1.40 (0.055) MAX

1.00 (0.039) REF

4.0 (0.157) 2.00 (0.079) REF
5 4 3 2 1

B
1.00 (0.0394) BSC
C 4.0 (0.157)
NON-ACCUMULATIVE
D

1.00 (0.0394) BSC 0.46 (0.018)

NON-ACCUMULATIVE DIA BALL TYP

BOTTOM VIEW

04/11/01
TITLE DRAWING NO. REV.
2325 Orchard Parkway
24C1, 24-ball (5 x 5 Array), 6 x 8 x 1.4 mm Body, 1.0 mm Ball 24C1 A
R San Jose, CA 95131 Pitch Chip-scale Ball Grid Array Package (CBGA)

55
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29. Revision History

Revision Level – Release Date History

A – September 2005 Initial release
Changed tVCSL from 30 µs to 50 µs min.
Changed tPUW from 10 ms to 20 ms max.
B – November 2005
Changed tDIS from 8 ns to 6 ns max.
Changed tV from 8 ns to 6 ns max.
Added text, in “Programming the Configuration Register”, to indicate
C – March 2006 that power cycling is required to switch to “power of 2” page size
after the opcode has been executed.
D – July 2006 Corrected typographical errors.
E – August 2006 Added errata regarding Chip Erase.
F – August 2006 Added tSCKR and tSCKF parameters to Table 18-4.
Added additional text for “power of 2” binary page size option.
G – August 2007 Changed tRDPD from 30 µs to 35 µs.
Added tCLKR and tCLKF parameters to Table 18-5.
Added part number ordering code details for suffixes SL954/955.
H – April 2008
Added ordering code details.
Changed tDIS (Typ and Max) to 27 ns and 35 ns, respectively, for
I – February 2009
RapidS interface.

Changed Deep Power-Down Current values

J – March 2009 - Increased typical value from 9 µA to 15 µA.
- Increased maximum value from 18 µA to 25 µA.

Updated Absolute Maximum Ratings

K - April 2009 Added 24C1 24 Ball BGA package Option
Deleted DataFlash Card Package Option

56 AT45DB642D
3542K–DFLASH–04/09
 AT45DB642D

30. Errata

30.1 Chip Erase

30.1.1 Issue
In a certain percentage of units, the Chip Erase feature may not function correctly and may
adversely affect device operation. Therefore, it is recommended that the Chip Erase commands
(opcodes C7H, 94H, 80H, and 9AH) not be used.

30.1.2 Workaround
Use Block Erase (opcode 50H) as an alternative. The Block Erase function is not affected by the
Chip Erase issue.

30.1.3 Resolution
The Chip Erase feature may be fixed with a new revision of the device. Please contact Atmel for
the estimated availability of devices with the fix.

57
3542K–DFLASH–04/09
Headquarters International

Atmel Corporation Atmel Asia Atmel Europe Atmel Japan

2325 Orchard Parkway Unit 1-5 & 16, 19/F Le Krebs 9F, Tonetsu Shinkawa Bldg.
San Jose, CA 95131 BEA Tower, Millennium City 5 8, Rue Jean-Pierre Timbaud 1-24-8 Shinkawa
USA 418 Kwun Tong Road BP 309 Chuo-ku, Tokyo 104-0033
Tel: 1(408) 441-0311 Kwun Tong, Kowloon 78054 Saint-Quentin-en- Japan
Fax: 1(408) 487-2600 Hong Kong Yvelines Cedex Tel: (81) 3-3523-3551
Tel: (852) 2245-6100 France Fax: (81) 3-3523-7581
Fax: (852) 2722-1369 Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11

Product Contact

Web Site Technical Support Sales Contact

www.atmel.com dataflash@atmel.com www.atmel.com/contacts

Literature Requests
www.atmel.com/literature

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intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
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logo, Rapid8 ® logo and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names
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3542K–DFLASH–04/09