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This document provides an overview of the different types of database objects in the Stylus Common UI database. It describes objects like cells, pins, nets, blocks, layers, and more. The document is a table of contents that lists each type of database object and provides a brief 1-2 sentence description. It serves as an index for understanding the different kinds of objects that make up a design in the database.

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0% found this document useful (0 votes)

646 views866 pages

DBcom

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Stylus Common UI Database Object

Information
Product Version 21.11
July 2021
© 2021 Cadence Design Systems, Inc. All rights reserved.
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Stylus Common UI Database Object Information
Table of Contents

Contents
1 7
Types and Definitions 7
2 12
Database Objects 12
analysis_view 12
antenna_data 15
antenna_model 16
arc 18
attribute 30
base_cell 33
base_pin 48
boundary 61
bump 62
bus 65
bus_guide 66
clock 67
clock_spine 78
clock_tree 79
clock_tree_source_group 93
constraint_mode 94
delay_corner 96
density_shape 100
design 101
flexible_htree 121
flow 128
flow_step 130
foreign_cell 133
gcell_grid 134
group 135
gui_line 137
gui_polygon 138
gui_rect 139

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Table of Contents

gui_text 140
hinst 141
hnet 149
hpin 152
hport 156
inst 158
io_constraint 185
layer 188
layer_rule 195
layer_shape 196
lib_arc 197
lib_cell 201
lib_pin 213
library 226
library_set 231
marker 232
module 235
net 238
net_group 257
obj_type 259
opcond 260
package_component 261
package_object 263
partition 264
patch_wire 270
path_group 272
pg_base_pin 272
pg_pin 277
physical_pin 279
pin 280
pin_blockage 323
pin_group 324
pin_guide 326
place_blockage 328
port 330
port_shape 373
power_domain 375

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Table of Contents

preferred_cell_stripe 381
rc_corner 382
resize_blockage 386
root 387
route_blockage 775
route_rule 778
route_type 779
row 783
sdp 785
shape 788
shape_via 790
site 791
skew_group 793
special_via 796
special_wire 799
stack_via_rule 803
text 803
timing_condition 806
timing_path 807
timing_point 828
track_pattern 833
via 835
via_def 838
via_def_rule 842
virtual_wire 844
wire 846
resistor 848
message 852
what_if_wire 854
what_if_via 855
inst_obs 856
trim_grid 857
gcell 859
inst_obs_shape 861
bus_sink_group 863
bump_pin 864
lef_set 866

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Table of Contents

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Stylus Common UI Database Object Information
Types and Definitions

Types and Definitions

The following is the list of allowed data types and their descriptions:

Type Description Accepted Input (from TCL) Output Format (to

TCL)

bool A boolean value. true: true/1/on/yes true or false

false: false/0/off/no

int Signed 32-bit integer Any integer value. 26

corresponding to Tcl
integer.

double Double-precision Any numeric value. 26.4

(64-bit) signed float. A .0 is added to the
output of integer
values to force it to
be a double (e.g.
1.0 rather than 1).

string A string. Unlike other Any Tcl string value, like "abc" or abc
types, the empty {abc}.
string is a valid
value.

enum One of a fixed set of If "true" or "false" are enum auto

string values values, these are interpreted as
(provided in the type booleans.
qualification).
For example: enum (true false
auto) accepts
- "0", "no" and "off" as synonyms
for "false"
- "1", "yes" and "on" as
synonyms for "true"
- "auto" for "auto"

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Types and Definitions

obj A database object A dual-ported Tcl object or object layer:metal1

pointer. It is followed list. The string form for netlist
inst:my_design/i1/i2
by the list of object objects is <obj_type>:
types allowed for this <design_name>/<object_name>, wire:0x123300012
attribute. It is for example:
optionally followed
inst:my_design/i1/i2
by
For technology or library objects it
* object list of 0 or
is just <obj_type>:<name>, for
more
example:
+ object list of 1 or
layer:metal1
more
For objects with no useful name
? object link may be
(like a wire), it is just the hex
empty
memory pointer, for example:
For example, obj(inst
wire:0x123300012
hinst)+ is a list of 1 or
more inst or hinst Type "man get_db" for more
objects. A mixture of details on dual-ported Tcl objects.
both inst and hinst
objects is possible.

in_file A file name that will A Unix path name (relative or my_dir/myfile.tcl
be read in. absolute). The file must exist and
be readable.

out_file A file that will be A Unix path name (relative or my_dir/my_file.tcl

written to. absolute). The file must be
writable.

in_dir A directory to read A Unix path name (relative or my_dir

from. absolute). The directory must
exist and be readable.

out_dir A directory to write A Unix path name (relative or my_dir

into. absolute). The directory must be
writable.

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Types and Definitions

coord A single, linear Any numerical value in units of 26.4

distance in microns microns. A .0 is added to the
that type double.. output of integer
values to force it to
be a double (e.g.
1.0 rather than 1).

point A point in 2D space, Any list format that can be {1.0 2.2}
expressed as a two- translated into two coordinates.
element Tcl list of For example, the following
coord types: {<x> are allowed:
<y>}. {1.0 2.2}
Has sub types: {{1} {2.2}}
.x - the first
coordinate
.y - the second
coordinate

line A line in 2D space, Any list format that can be {{1.0 2.2} {3.0 4.0}}
expressed as a two- translated into two points. For
element Tcl list of example, the following
points: {{<x1> <y1>} are allowed as input.
{<x2> <y2>}}. {{1.0 2} {3 4.0}}
Has sub types: {1 2 3 4}
.begin - first point {{1} {2} {3} {4.0}}
.end - second point
.length - length of
the line
.dx - difference in x
coordinates
.dy - difference in y
coordinates

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Types and Definitions

rect A rectangle in 2D Any list format that can be A list of four coords:
space, expressed as translated into two points. For {1.0 2.0 3.0 4.0}
an ordered list of example, the following are
coordinates {<left_x> equivalent:
<lower_y> <right_x> {{1 2} {3 4}}
<upper_y>}. {1 2 3 4}
Has sub types: The two X coordinates and two Y
.ll - lower left point coordinates can be input in
.ur - upper right either order. They will be ordered
point as lower-left for the first point, and
.dx - difference in x upper-right as the second point for
coordinates output.
.dy - difference in y
coordinates
.area - area of the
rectangle
.width - shorter of
dx & dy
.length - longer of
dx and dy
.perimeter -
perimeter of the rect

polygon A polygon in 2D Any list format that can be A list of points: {{1.0
space, expressed as translated into multiple points. For 2.0} {3.0 4.0} {5.0
a list of points {{<x1> example, the following are 6.0}}.
y1>} {<x2> <y2>} equivalent:
{<x3> <y3>}...}. {{1 2} {3 4} {5 6}}
Has sub types: {1 2 3 4 5 6}
.bbox - bounding
box (rect type)
.area - area of the
rectangle
.perimeter -
perimeter of the
rectangle

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Types and Definitions

area An area in units of Any numerical value in units of Value in micron

micron squared that microns squared. squared without
is type double. 26.4 units. Example:
26.4
A .0 is added to the
output of integer
values to force it to
be a double (e.g.
1.0 rather than 1).

delay A time duration that Any numerical value in user units. 26.4
is type double. The units can be queried with A .0 is added to the
"get_db timing_time_unit". output of integer
values to force it to
be a double (e.g.
1.0 rather than 1).

resistance A resistance that is Any numerical value in user units. 26.4

type double. The units can be queried with A .0 is added to the
"get_resistance_unit". output of integer
values to force it to
be a double (e.g.
1.0 rather than 1).

capacitance A capacitance that is Any numerical value in user units. 26.4

type double. The units can be queried with A .0 is added to the
"get_db timing_cap_unit". output of integer
values to force it to
be a double (e.g.
1.0 rather than 1).

voltage A voltage that is type Any numerical value in units of 1.4

double. volts.
A .0 is added to the
output of integer
values to force it to
be a double (e.g.
1.0 rather than 1).

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Database Objects

Database Objects

analysis_view

Parent Objects
design, root

Definition
An analysis view binds together a constraint mode with a delay corner, providing all the information needed to
control a single MMMC analysis. Use the create_analysis_view and update_analysis_view commands to
create and modify analysis_views.

Attribute Description

constraint_mode

The constraint_mode object associated with the analysis_view.

Type: obj(constraint_mode)
Default: ""
Edit: No

delay_corner

The delay_corner object associated with the analysis_view.

Type: obj(delay_corner)
Default: ""
Edit: No

is_active

Indicates that the analysis_view is part of any leakage/dynamic/setup/hold designation

Type: bool
Default: ""
Edit: No

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Database Objects--analysis_view

is_dormant

Indicates that the analysis_view is not being timing analyzed, but a minimum set of data is
loaded to keep the view in synch with potential design changes.
Type: bool
Default: ""
Edit: No

is_drv

Indicates that the analysis_view is used as drv view.

Type: bool
Default: ""
Edit: No

is_dynamic

Indicates that the analysis_view is dynamic power view.

Type: bool
Default: ""
Edit: No

is_em

Indicates that the analysis_view is used for electromigration analysis.

Type: bool
Default: ""
Edit: No

is_hold

Indicates that the analysis_view is active for hold analysis

Type: bool
Default: ""
Edit: No

is_hold_default

Indicates that the analysis_view is the default view for hold analysis
Type: bool
Default: ""
Edit: No

is_leakage

Indicates that the analysis_view is leakage power view.

Type: bool
Default: ""
Edit: No

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Database Objects--analysis_view

is_setup

Indicates that the analysis_view is active for setup analysis

Type: bool
Default: ""
Edit: No

is_setup_default

Indicates that the analysis_view is the default view for setup analysis
Type: bool
Default: ""
Edit: No

latency_file

Specifies an optional file containing view-specific set_clock_latency constraints used for

balancing post_CTS IO timing. This file is normally generated automatically as part of the
clock tree implementation flow.
Type: string
Default: ""
Edit: No

name

Provides the name of this analysis_view object as specified by the create_analysis_view

command.
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (analysis_view)
Default: ""
Edit: No

power_modes

Specifies an optional list of power_mode objects defined by the power intent specification.
Type: string
Default: ""
Edit: No

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Database Objects--antenna_data

antenna_data

Parent Objects
base_pin, port

Definition
Antenna information for terminals

Attribute Description

area

Area value for non *Car type cases, 0 value used for *Car type cases as area is not applicable
in those cases.
Type: area
Default: ""
Edit: No

layer

The layer of antenna data. If layer is null(0x0), data applies to all layers.
Type: obj(layer)
Default: ""
Edit: No

model

Oxide model, none is used for cases where oxide model does not apply.
Type: enum
Enum Values: none oxide1 oxide2 oxide3 oxide4
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (antenna_data)
Default: ""
Edit: No

ratio

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Database Objects--antenna_model

Ratio value for *Car type cases. 0 value used for non *Car enums as ratio is not applicable in
those cases.
Type: double
Default: ""
Edit: No

type

Type of antenna data. Equivalent to LEF MACRO PIN ANTENNA* constructs.

Type: enum
Enum Values: lib_gate_area lib_diff_area lib_partial_metal_area
lib_partial_metal_side_area lib_max_area_car lib_max_side_area_car lib_partial_cut_area
lib_max_cut_car top_partial_metal_area top_partial_metal_side_area top_gate_area
top_diff_area top_max_area_car top_max_side_area_car top_partial_cut_area
top_max_cut_car
Default: ""
Edit: No

antenna_model

Parent Objects
layer

Definition
Antenna model information for one layer & oxide

Attribute Description

area_factor

Specifies the multiply factor for the antenna metal area calculation (default value 1.0),
LEF(ANTENNAAREAFACTOR)
Type: double
Default: ""
Edit: No

area_factor_diff_use_only

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Database Objects--antenna_model

Specifies that the current antenna area factor should only be used when the corresponding
layer is connected to the diffusion, LEF(DIFFUSEONLY)
Type: bool
Default: ""
Edit: No

area_ratio

Specifies the maximum legal antenna ratio, using the area of the metal wire that is not
connected to the diffusion diode (0 indicates that the attribute does not apply),
LEF(ANTENNAAREARATIO)
Type: double
Default: ""
Edit: No

cum_area_ratio

Specifies the cumulative antenna ratio, using the area of the wire that is not connected to the
diffusion diode (0 indicates that the attribute does not apply),
LEF(ANTENNACUMAREARATIO)
Type: double
Default: ""
Edit: No

cum_routing_plus_cut

Indicates that the cumulative ratio rules (ANTENNACUMAREARATIO and

ANTENNACUMDIFFAREARATIO) accumulate with the previous cut layer instead of the
previous metal layer, LEF(ANTENNACUMROUTINGPLUSCUT)
Type: bool
Default: ""
Edit: No

cum_side_area_ratio

Specifies the cumulative antenna ratio, using the side wall area of the metal wire that is not
connected to the diffusion diode (0 indicates that the attribute does not apply),
LEF(ANTENNACUMSIDEAREARATIO)
Type: double
Default: ""
Edit: No

gate_minus_diff

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Database Objects--arc

Indicates that the antenna ratio metal area should subtract the diffusion area connected to it (0
indicates that the attribute does not apply), LEF(ANTENNAAREAMINUSDIFF)
Type: double
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (antenna_model)
Default: ""
Edit: No

side_area_factor

Specifies the multiply factor for the antenna metal side wall area calculation (default value
1.0), LEF(ANTENNASIDEAREAFACTOR)
Type: double
Default: ""
Edit: No

side_area_factor_diff_use_only

Specifies that the current antenna side area factor should only be used when the
corresponding layer is connected to the diffusion, LEF(DIFFUSEONLY)
Type: bool
Default: ""
Edit: No

side_area_ratio

Specifies the antenna ratio, using the side wall area of the metal wire that is not connected to
the diffusion diode (0 indicates that the attribute does not apply),
LEF(ANTENNASIDEAREARATIO)
Type: double
Default: ""
Edit: No

arc

Parent Objects
inst, pin, net

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Database Objects--arc

Definition
cte timing arc

Attribute Description

aocv_derate_capture_clock_early_fall

Returns graph based AOCV derate factors in AOCV mode for a given timing arc that is a part
of early capture clock paths with fall sink pin transitions. You can use -index to return the value
for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_derate_capture_clock_early_rise

Returns graph based AOCV derate factors in AOCV mode for a given timing arc that is a part
of early capture clock paths with rise sink pin transitions. You can use -index to return the
value for a specific view
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_derate_capture_clock_late_fall

Returns graph based AOCV derate factors in AOCV mode for a given timing arc that is a part
of late capture clock paths with fall sink pin transitions. You can use -index to return the value
for a specific view
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_derate_capture_clock_late_rise

Returns graph based AOCV derate factors in AOCV mode for a given timing arc that is a part
of late capture clock paths with rise sink pin transitions. You can use -index to return the value
for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_derate_data_early_fall

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Database Objects--arc

Returns AOCV derate values for a timing arc on an early data path with fall sink pin
transitions. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_derate_data_early_rise

Returns AOCV derate values for a timing arc on an early data path with rise sink pin
transitions. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_derate_data_late_fall

Returns AOCV derate values for a timing arc on a late data path with fall sink pin transitions.
You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_derate_data_late_rise

Returns AOCV derate values for a timing arc on a late data path with rise sink pin transitions.
You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_derate_launch_clock_early_fall

Returns graph based AOCV derate factors in AOCV mode for a given timing arc that is a part
of early launch clock paths with fall sink pin transitions. You can use -index to return the value
for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_derate_launch_clock_early_rise

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Database Objects--arc

Returns graph based AOCV derate factors in AOCV mode for a given timing arc that is a part
of early launch clock paths with rise sink pin transitions. You can use -index to return the value
for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_derate_launch_clock_late_fall

Returns graph based AOCV derate factors in AOCV mode for a given timing arc that is a part
of late launch clock paths with fall sink pin transitions. You can use -index to return the value
for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_derate_launch_clock_late_rise

Returns graph based AOCV derate factors in AOCV mode for a given timing arc that is a part
of late launch clock paths with rise sink pin transitions. You can use -index to return the value
for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_stage_count_capture_clock_early

Returns graph based AOCV stage count values in AOCV mode for a given timing arc that is a
part of early capture clock paths. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_stage_count_capture_clock_late

Returns graph based AOCV stage count values in AOCV mode for a given timing arc that is a
part of late capture clock paths. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_stage_count_data_early

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Database Objects--arc

Returns AOCV stage count values for a timing arc on an early data path. You can use -index
to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_stage_count_data_late

Returns AOCV stage count values for a timing arc on a late data path. You can use -index to
return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_stage_count_launch_clock_early

Returns AOCV stage count values in AOCV mode for a given timing arc that is a part of early
launch clock paths. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_stage_count_launch_clock_late

Returns AOCV stage count values in AOCV mode for a given timing arc that is a part of late
launch clock paths. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

aocv_weight

Returns the AOCV stage weight for this arc. By default, all cells and arcs have default stage
weight of 1.0. The aocv_weight property is specified as a user-defined library attribute in the
Liberty timing library explicitly - or, by asserting it via command. This attribute is inherited from
the associated library arc. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_max_fall

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Database Objects--arc

Returns the largest falling delay through the arc across all concurrent MMMC views. You can
use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_max_rise

Returns the largest rising delay through the arc across all concurrent MMMC views. You can
use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_mean_max_fall

In SOCV analysis mode, this returns the mean component of the largest falling delay through
the arc across all concurrent MMMC views. You can use -index to return the value for a
specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_mean_max_rise

In SOCV analysis mode, this returns the mean component of the largest rising delay through
the arc across all concurrent MMMC views. You can use -index to return the value for a
specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_mean_min_fall

In SOCV analysis mode, this returns the mean component of the smallest falling delay through
the arc across all concurrent MMMC views. You can use -index to return the value for a
specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_mean_min_rise

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Database Objects--arc

In SOCV analysis mode, this returns the mean component of the smallest rising delay through
the arc across all concurrent MMMC views. You can use -index to return the value for a
specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_min_fall

Returns the smallest falling delay through the arc across all concurrent MMMC views. You can
use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_min_rise

Returns the smallest rising delay through the arc across all concurrent MMMC views can use -
index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_sigma_max_fall

In SOCV analysis mode, this returns the variation component of the largest falling delay
through the arc across all concurrent MMMC views. You can use -index to return the value for
a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_sigma_max_rise

In SOCV analysis mode, this returns the variation component of the largest rising delay
through the arc across all concurrent MMMC views. You can use -index to return the value for
a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_sigma_min_fall

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In SOCV analysis mode, this returns the variation component of the smallest falling delay
through the arc across all concurrent MMMC views. You can use -index to return the value for
a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delay_sigma_min_rise

In SOCV analysis mode, this returns the variation component of the smallest rising delay
through the arc across all concurrent MMMC views. You can use -index to return the value for
a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delta_delay_max_fall

Returns the delta/SI delay component of the largest falling delay through this arc across all
concurrent MMMC views. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delta_delay_max_rise

Returns the delta/SI delay component of the largest rising delay through this arc across all
concurrent MMMC views. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delta_delay_min_fall

Returns the delta/SI delay component of the smallest falling delay through this arc across all
concurrent MMMC views. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

delta_delay_min_rise

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Returns the delta/SI delay component of the smallest rising delay through this arc across all
concurrent MMMC views. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

dynamic_delta_delay_max_fall

Returns the dynamic delay component of the largest falling delay through this arc across all
concurrent MMMC views. This is computed if dynamic voltages have been specified. You can
use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

dynamic_delta_delay_max_rise

Returns the dynamic delay component of the largest rising delay through this arc across all
concurrent MMMC views. This is computed if dynamic voltages have been specified. You can
use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

dynamic_delta_delay_min_fall

Returns the dynamic delay component of the smallest falling delay through this arc across all
concurrent MMMC views. This is computed if dynamic voltages have been specified. You can
use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

dynamic_delta_delay_min_rise

Returns the dynamic delay component of the smallest rising delay through this arc across all
concurrent MMMC views. This is computed if dynamic voltages have been specified.You can
use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

from_pin

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Returns a pin object for the beginning pin of this timing arc
Type: obj(pin)* obj(hpin)* obj(hport)*
Allowed -index values: analysis_view
Default: ""
Edit: No

is_cell_arc

Returns true if the arc is a cell arc.

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_disabled

Returns a value of true if this library timing arc has been explicitly disabled by the user via a
set_disable_timing constraint
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

lib_arcs

Returns a list of the associated lib_arc objects. You can use -index to return the value for a
specific view.
Type: obj(lib_arc)*
Allowed -index values: analysis_view
Default: ""
Edit: No

mode

If the associated lib_arc is defined as part of a Liberty mode group, this attribute will return the
name of the library group
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (arc)
Default: ""
Edit: No

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sdf_cond

Returns the value of the Liberty sdf_cond attribute if specified for the associated lib_arc
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

sdf_cond_end

Returns the value of the Liberty sdf_cond_end attribute if specified for the associated lib_arc
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

sdf_cond_start

Returns the value of the Liberty sdf_cond_start attribute if specified for the associated lib_arc
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

sense

Returns the Liberty timing_sense value associated with this arc. This value is one
of:positive_unate, negative_unate, or non_unate. This is inherited from the lib_arc.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

ssi_derate_fall

Returns the fall ssi_derate for the arc.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

ssi_derate_rise

Returns the rise ssi_derate for the arc.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

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timing_type

Returns the Liberty timing_type associated with this arc. You can consult the Liberty
documentation for the list of possible values for this attribute. This is inherited from the lib_arc.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

to_pin

Returns a pin object for the terminating pin of this timing arc
Type: obj(pin)* obj(hpin)* obj(hport)*
Allowed -index values: analysis_view
Default: ""
Edit: No

when

Returns the value of the Liberty 'when' attribute if specified for the related lib_arc
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

when_end

Returns the value of the Liberty 'when_end' attribute if specified for the related lib_arc
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

when_library_string

Returns the exact value of the Liberty 'when' attribute if specified for the related lib_arc
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

when_start

Returns the value of the Liberty 'when_start' attribute if specified for the related lib_arc
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

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attribute

Parent Objects
root, obj_type

Definition

Attribute Description

additional_help

Range info or other additional help.

Type: string
Default: ""
Edit: No

base_name

The name without the obj_type (e.g. place_status rather than inst/place_status).
Type: string
Default: ""
Edit: No

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Specifies a previously defined Tcl procedure's name in order to get the newly defined
attribute's value later command. Procedure argument list: object
Type: string
Default: ""
Edit: No

data_type

data type attribute

Type: string
Default: ""
Edit: No

default_value

Specifies a default value for the attribute, most attributes do not have default values and will
use "".
Type: string
Default: ""
Edit: No

help

Specifies the help text for the attribute

Type: string
Default: ""
Edit: No

indices

List of object type names that represent indices for an attribute value.
Type: enum
Enum Values: analysis_view clock delay_corner clock_tree skew_group power_domain
layer
Default: ""
Edit: No

is_computed

Specifies whether the defined attribute will be computed. For .? use, the value will not be
displayed if it needs to be recomputed. For direct access of the attribute the value will be
returned or computed as needed (0 = static, 1 = computed)
Type: bool
Default: ""
Edit: No

is_settable

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whether the defined attribute is a read-only or settable attribute (0 = read-only, 1 = settable)

Type: bool
Default: ""
Edit: No

is_user_defined

Specifies whether the defined attribute was defined by the user via Tcl (define_attribute) or is
a system defined attribute (0 = system defined, 1 = user defined)
Type: bool
Default: ""
Edit: No

name

name of attribute
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (attribute)
Default: ""
Edit: No

parent

The attribute's parent object

Type: obj(obj_type)
Default: ""
Edit: No

possible_values

enum possible values attribute

Type: string
Default: ""
Edit: No

set_function

Specifies a previously defined Tcl procedure's name. This option allows you to override user-
defined values provided it conforms to the parameters in the Tcl procedure you created.
Procedure argument list: object new_value current_value
Type: string
Default: ""
Edit: No

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skip_in_db

Prevents write_db command to write out the defined

Type: bool
Default: ""
Edit: No

base_cell

Parent Objects
lib_cell, inst, pin_group, pg_base_pin, bump, pin_guide, root, base_pin

Definition
base cell

Attribute Description

aocv_weight

Returns the AOCV stage weight specified for the cell either explicitly in the library or as a user-
defined library attribute
Type: double
Default: ""
Edit: No

area

The area of the cell

Type: area
Default: ""
Edit: No

base_class

The base class is the prefix of the .class enum value. It is useful to separate the major cell
categories. See the .class description for the definition of each enum value
Type: enum
Enum Values: none cover block pad core corner
Default: ""
Edit: No

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base_name

Base name of the cell.

Type: string
Default: ""
Edit: No

base_pins

The base_pins for this cell

Type: obj(base_pin)*
Default: ""
Edit: No

bbox

The bounding box of the overlap rects that define the placement area used by this cell.
Type: rect*
Default: ""
Edit: No

bottom_edge_type

Name of cell edge type for the bottom edge of the cell (R0/N orientation), used to indicate
which cells need extra spacing to other cells.
Type: string
Default: ""
Edit: No

bottom_padding

The placer will leave this much extra space to the bottom side of the cell (in r0 orientation). It is
only valid for standard cells. It is in units of site width.
Type: int
Default: 0
Edit: Yes

class

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All the LEF CLASS and PROPERTY LEF58_CLASS values (and equivalent OpenAccess
values). Refer to the LEF documentation for the complete list and descriptions. They are
separated into 5 classes with a unique prefix based on their usage as described here:
CLASS COVER types all start with cover.
CLASS RING or BLOCK start with block.
CLASS PAD start with pad.
CLASS CORE start with core.
CLASS ENDCAP that are corner cells (TOPLEFT, TOPRIGHT, BOTTOMLEFT,
BOTTOMRIGHT) start with corner.
CLASS ENDCAP that are not corner cells all start with core because they are all placed in
the core rows like CLASS CORE cells.
No CLASS means the value is none.
Modifications are valid only for the current session.
Type: enum
Enum Values: none cover cover_bump cover_fill block_ring block block_blackbox block_soft
pad pad_input pad_output pad_inout pad_power pad_spacer pad_area_io core core_feedthru
core_tie_high core_tie_low core_spacer core_antenna core_welltap core_endcap_pre
core_endcap_post corner_top_left corner_top_right corner_bottom_left corner_bottom_right
core_endcap_top_edge core_endcap_bottom_edge core_endcap_left_edge
core_endcap_right_edge core_endcap_left_top_edge core_endcap_right_top_edge
core_endcap_left_bottom_edge core_endcap_right_bottom_edge
core_endcap_left_top_corner core_endcap_right_top_corner
core_endcap_left_bottom_corner core_endcap_right_bottom_corner
core_endcap_left_even_site_edge core_endcap_left_odd_site_edge
core_endcap_right_even_site_edge core_endcap_right_odd_site_edge
core_endcap_left_top_even_site_edge core_endcap_left_top_odd_site_edge
core_endcap_right_top_even_site_edge core_endcap_right_top_odd_site_edge
core_endcap_left_bottom_even_site_edge core_endcap_left_bottom_odd_site_edge
core_endcap_right_bottom_even_site_edge core_endcap_right_bottom_odd_site_edge
core_endcap_left_top_even_site_corner core_endcap_left_top_odd_site_corner
core_endcap_right_top_even_site_corner core_endcap_right_top_odd_site_corner
core_endcap_left_bottom_even_site_corner core_endcap_left_bottom_odd_site_corner
core_endcap_right_bottom_even_site_corner core_endcap_right_bottom_odd_site_corner
core_endcap_left_edge_bottom_border core_endcap_left_edge_top_border
core_endcap_right_edge_bottom_border core_endcap_right_edge_top_border
core_endcap_left_bottom_edge_neighbor core_endcap_left_top_edge_neighbor
core_endcap_right_bottom_edge_neighbor core_endcap_right_top_edge_neighbor
core_endcap_left_bottom_corner_neighbor core_endcap_left_top_corner_neighbor
core_endcap_right_bottom_corner_neighbor core_endcap_right_top_corner_neighbor
Default: ""
Edit: Yes

cts_cell_halo_x

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Specifies the clock halo distance in the x direction. The default value of this attribute is auto.
The following attributes can be used to assign x direction clock halos within CCOpt:
cts_cell_halo_x
cts_cell_density
cts_cell_halo_sites
Only one of these attributes is used to determine the clock halo in the x direction. The
following rules determine which:
. If cts_cell_halo_x is set to a non-auto value, then this defines the x direction clock halo. The
attributes cts_cell_density and cts_cell_halo_sites have no effect.
. If cts_cell_halo_x is set to auto and cts_cell_density is set to a non-auto value then
cts_cell_density defines the clock halo in the x direction. The attribute cts_cell_halo_sites has
no effect.
. If both cts_cell_halo_x and cts_cell_density are set to auto then cts_cell_halo_sites defines
the clock halo in the x direction.
See also:
. cts_cell_density
. cts_cell_halo_sites
Type: string
Allowed -index values: clock_tree power_domain
Default: auto
Edit: Yes

cts_cell_halo_y

Specifies the clock halo distance in the y direction. The default value of this attribute is auto.
The following attributes can be used to assign y direction clock halos within CCOpt:
cts_cell_halo_y
cts_adjacent_rows_legal
cts_cell_halo_rows
Only one of these attributes is used to determine the clock halo in the y direction. The
following rules determine which:
. If cts_cell_halo_y is set to a non-auto value, then this defines the y direction clock halo. The
attributes cts_adjacent_rows_legal and cts_cell_halo_rows have no effect.
. If cts_cell_halo_y is set to auto and cts_adjacent_rows_legal is set to a non-auto value then
cts_adjacent_rows_legal defines the clock halo in the y direction. The attribute
cts_cell_halo_rows has no effect.
. If both cts_cell_halo_y and cts_adjacent_rows_legal are set to auto then
cts_cell_halo_rows defines the clock halo in the y direction.
See also:
. cts_adjacent_rows_legal
. cts_cell_halo_rows
Type: string
Allowed -index values: clock_tree power_domain
Default: auto
Edit: Yes

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dont_touch

This attribute says any inst of this base_cell cannot be modified during optimization. This is
the effective dont_touch value for all lib_cells. It is set to the worst case of the lib_cells during
init_design and can only be updated by set_db / set_dont_touch after that (subsequent library
reads will not affect). This attribute will get restored back to the state during write_db
regardless if the library files have been altered.
Type: bool
Default: false
Edit: Yes

dont_use

This attribute says do not use this base_cell during optimization. This is the effective dont_use
value for all lib_cells. It is set to the worst case of the lib_cells during init_design and can only
be updated by set_db / set_dont_use after that (subsequent library reads will not affect). This
attribute is saved by write_db, and restored by read_db regardless if the library files have been
altered.
Type: bool
Default: false
Edit: Yes

drive_strength

This attribute allows the user to assign a drive strength to each cell (X1, X2, etc.) to be used for
metric capture.
Type: string
Default: ""
Edit: Yes

eeq_cells

Electrically equivalent base_cells. Same as LEF MACRO EEQ statement.

Type: obj(base_cell)*
Default: ""
Edit: No

eeq_variant

The LEF EEQ cell variant number from the LEF58_EEQ property 'EEQ macroName VARIANT
num'
Type: int
Default: no_value
Edit: Yes

escaped_name

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Escaped name of the cell.

Type: string
Default: ""
Edit: No

foreign_cells

List of foreign references. Equivalent to LEF MACRO FOREIGN.

Type: obj(foreign_cell)*
Default: ""
Edit: No

is_always_on

Specifies the cell is an always-on cell. An always-on cell normally has two power pins. One is
primary which aligns with the normal cell power-rail, and the other is the secondary which
actually powers the cell, even when the primary power is off. This attribute can be set by
liberty files, or by CPF commands.
Type: bool
Default: false
Edit: No

is_black_box

Returns a value of true if the cell is a black box cell.

Type: bool
Default: ""
Edit: No

is_buffer

This cell is a buffer.

Type: bool
Default: ""
Edit: No

is_combinational

Returns a value of true if the cell is a combinational cell (not a sequential cell).
Type: bool
Default: ""
Edit: No

is_fall_edge_triggered

Returns a value of true if the cell is triggered by the falling edge of the clock.
Type: bool
Default: ""
Edit: No

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is_fixed_mask

Indicates the cell has FIXEDMASK keyword in LEF.

Type: bool
Default: ""
Edit: No

is_flop

Returns true if the cell is recognized as flip-flop/register type cell

Type: bool
Default: ""
Edit: No

is_integrated_clock_gating

Returns true if the cell has the Liberty clock_gating_integrated_cell set to true
Type: bool
Default: ""
Edit: No

is_interface_timing

Returns a value of true if a cell has the Liberty interface_timing attribute set to true
Type: bool
Default: ""
Edit: No

is_inverter

This cell is an inverter.

Type: bool
Default: ""
Edit: No

is_iso_nor

Specifies the cell is an ISONOR cell. An ISONOR cell is a kind of isolation cell, which has
only one primary power pin and one primary ground pin. An ISONOR cell is defined by library
files. In cell library, it has permit_power_down true for primary power pin,
alive_during_power_up true for input signal pin, and alive_during_partial_power_down true
for enable pin and output signal pin. The attribute should be queried after read and commit
power intent.
Type: bool
Default: ""
Edit: No

is_isolation_cell

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Specifies the cell is an isolation cell. An isolation cell is used to clamp the signal to high or low
when its input is shutoff(unknown). This attribute can be set by liberty files, or by CPF
commands.
Type: bool
Default: false
Edit: No

is_latch

Returns true if the cell is recognized as latch type cell

Type: bool
Default: ""
Edit: No

is_level_shifter

Specifies the cell is a level shifter cell. A level-shifter cell is used to shift the signal voltage
from low(high) to high(low). This attribute can be set by liberty files, or by CPF commands.
Type: bool
Default: false
Edit: No

is_macro

Returns a value of true if the Liberty attribute is_macro_cell is set true

Type: bool
Default: ""
Edit: No

is_master_slave_flop

Returns true if the cell is recognized as a master/slave flip-flop type cell

Type: bool
Default: ""
Edit: No

is_master_slave_lssd_flop

Returns true if this cell has been recognized as a master/slave LSSD type cell
Type: bool
Default: ""
Edit: No

is_memory

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Returns true or false depending on whether the associated library cell is recognized as a
Liberty memory cell. Cells which include a Liberty memory group definition are recognized as
memory cells.
Type: bool
Default: ""
Edit: No

is_negative_level_sensitive

Returns a value of true if the cell is identified as a negative level-sensitive latch

Type: bool
Default: ""
Edit: No

is_pad

Returns a value of true if Liberty attribute is_pad is set to true

Type: bool
Default: ""
Edit: No

is_physical_defined

This cell has a physical abstract loaded from LEF or OA so the various physical attributes
have been set
Type: bool
Default: ""
Edit: No

is_pll

Returns a value of true if the Liberty library is_pll_cell attribute is set to true for this cell
Type: bool
Default: ""
Edit: No

is_positive_level_sensitive

Returns a value of true if the cell is identified as a positive level-sensitive latch

Type: bool
Default: ""
Edit: No

is_power_on_bottom

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Indicates this standard cell has a power pin along the bottom of the cell. This is derived from
the power and ground pin information in the cell. It is used by the placer to align multi-height
cells properly to the rows. It is not meaningful for non standard cells. Modifications are not
saved and are only valid for the current session.
Type: bool
Default: false
Edit: Yes

is_power_switch

Specifies the cell is a power switch cell. The power switch cell is used to switch off the
power/ground during shutoff. This attribute can be set by liberty files, or by CPF commands.
Type: bool
Default: false
Edit: No

is_quick_abstract

Indicates that the base_cell was created from reading an OpenAccess layout view and
inferred abstract (LEF MACRO equivalent) information from that view. The oa_abstract_lib
and oa_abstract_view attributes indicate which layout view was read. For most uses, the
inferred abstracts are intended for floorplanning only and are not recommended for final
implementation.
Type: bool
Default: ""
Edit: No

is_retention_cell

Specifies the cell is a state-retention cell. A state-retention cell is used to retain its state during
shutoff. It has a secondary power pin which powers the cell and retains its state, even when
the primary power is off. This attribute can be set by liberty files, or by CPF commands.
Type: bool
Default: false
Edit: No

is_rise_edge_triggered

Returns a value of true if the cell is triggered by the rising edge of the clock
Type: bool
Default: ""
Edit: No

is_scan_cell

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Indicates the base_cell is a scan cell. A scan cell has test_cell defined in liberty files.
Type: bool
Default: ""
Edit: No

is_sequential

This cell is sequential. Derived from .lib information

Type: bool
Default: ""
Edit: No

is_timing_defined

This cell has a .lib file definition loaded, so the various timing attributes have been set
Type: bool
Default: ""
Edit: No

is_tristate

Returns a value of true if the cell definition includes the Liberty attribute three_state set to true .
Type: bool
Default: ""
Edit: No

is_vdd_on_bottom

Indicates this standard cell has a power pin along the bottom of the cell. This is derived from
the power and ground pin information in the cell. It is used by the placer to align multi-height
cells properly to the rows. It it not meaningful for non standard cells. Modifications are not
saved and are only valid for the current session.
Type: bool
Default: false
Edit: Yes

lef_file_name

Specifies the LEF file name of the base_cell

Type: string
Default: ""
Edit: No

left_edge_type

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Name of cell edge type for the left edge of the cell (R0/N orientation), used to indicate which
cells need extra spacing to other cells.
Type: string
Default: ""
Edit: No

left_padding

The placer will leave this much extra space to the left side of the cell (in r0 orientation). It is
only valid for standard cells. It is in units of site width.
Type: int
Default: 0
Edit: Yes

lib_cells

Returns a list of lib_cell objects which are associated with this base_cell
Type: obj(lib_cell)*
Default: ""
Edit: No

logic_function

This attribute allows the user to assign a function to each cell (AND, OR, etc.) to be used for
metric capture.
Type: string
Default: ""
Edit: Yes

must_join_base_pins

Must join pins are physical-only pins that do not exist in the logical netlist. They do not appear
in Verilog or DEF files. The router will connect the must-join base_pin to its corresponding
logical pin. See the base_pin .must_join_pins attribute, and the LEF MACRO PIN MUSTJOIN
statement for more details
Type: obj(base_pin)*
Default: ""
Edit: No

name

Name of the cell.

Type: string
Default: ""
Edit: No

num_base_pins

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Number of signal base_pins for this cell. It does not include pg_base_pins or
must_join_base_pins.
Type: int
Default: ""
Edit: No

num_drivers

The number of driver base_pins for this base_cell. Signal base_pins that have direction = out
or inout are considered drivers.
Type: int
Default: ""
Edit: No

num_loads

The number of load base_pins for this base_cell. Signal base_pins that have direction = in or
inout are considered loads.
Type: int
Default: ""
Edit: No

oa_abstract_lib

OpenAccess library name of the physical abstract for the cell if read from OA.
Type: string
Default: ""
Edit: No

oa_abstract_view

OpenAccess view name for the physical abstract for this cell if read from OA (equivalent of
LEF MACRO data). The OA cell name is the same as this cell's 'name' attribute
Type: string
Default: ""
Edit: No

oa_layout_lib

OpenAccess library name of physical layout for the cell if read from OA.
Type: string
Default: ""
Edit: No

oa_layout_view

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OpenAccess view name for the physical layout for this cell if read from OA (equivalent of
GDSII data). The layout view data can optionally be displayed instead of the abstract view
data, but otherwise this layout data is not used in Innovus. The OA cell name is the same as
this cell's 'name' attribute
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (base_cell)
Default: ""
Edit: No

obs_layer_shapes

A list of cell obstruction layer_shapes (LEF OBS or OA abstract blockages that are not vias).
Note, use obs_shape_vias for obstructions that are from vias (LEF OBS VIA).
Type: obj(layer_shape)*
Default: ""
Edit: No

obs_shape_vias

A list of cell obstruction shape_vias (LEF OBS VIA or OA abstract via blockages). Use
obs_layer_shapes for obstructions on a single layer.
Type: obj(shape_via)*
Default: ""
Edit: No

pg_base_pins

The power/ground base_pins for this cell.

Type: obj(pg_base_pin)*
Default: ""
Edit: No

right_edge_type

Name of cell edge type for the right edge of the cell (R0/N orientation), used to indicate which
cells need extra spacing to other cells.
Type: string
Default: ""
Edit: No

right_padding

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The placer will leave this much extra space to the right side of the cell (in r0 orientation). It is
only valid for standard cells. It is in units of site width.
Type: int
Default: 0
Edit: Yes

site

The site for this cell.Modifications are valid only for the current session.
Type: obj(site)
Default: ""
Edit: Yes

symmetry

The allowed orientations for the placer to try. none means r0 only, x means ok to flip about X
axis (r0, mx), y means ok to flip about Y axis (r0, my), xy means ok to flip about X or Y axis (r0,
mx, my, r180), any means all orientations are allowed. Equivalent to LEF MACRO
SYMMETRY or OA oaSymmetry. LEF values of R90, X R90, Y R90, and X Y R90 are all
equivalent to the value = any. Modifications are not saved and are only valid for the current
session.
Type: enum
Enum Values: none x y xy any
Default: ""
Edit: Yes

tap_type

Specifies the name of a well tap type for this cell. Various rules for well taps are grouped
together for each tap_type. See the LEF documentation on the TAPTYPE keyword for more
details.
Type: string
Default: ""
Edit: Yes

tap_wall

Specifies a special well tap cell (LEF CLASS CORE WELLTAP) or a special end_cap (LEF
CLASS ENDCAP ...) cell that can be used for a tap wall purpose, which is used to break OD
diffusion and aligned vertically to form a tap wall. See the LEF docs about the keyword
TAPWALL for more details.
Type: bool
Default: false
Edit: Yes

timing_model_type

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Returns the Liberty model type for a given cell or instance. The supported values are
abstracted , extracted , and qtm .
Type: string
Default: ""
Edit: No

top_edge_type

Name of cell edge type for the top edge of the cell (R0/N orientation), used to indicate which
cells need extra spacing to other cells.
Type: string
Default: ""
Edit: No

top_padding

The placer will leave this much extra space to the top side of the cell (in r0 orientation). It is
only valid for standard cells. It is in units of site width.
Type: int
Default: 0
Edit: Yes

voltage_threshold_group

This attribute allows the user to assign a base_cell to a voltage threshold group for metric
capture. The threshold group name can be any valid string.
Type: string
Default: ""
Edit: Yes

base_pin

Parent Objects
partition, bump_pin, base_cell, pin_group, pin, root, lib_pin,

Definition
base pin

Attribute Description

antenna_data

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The various process antenna_data values for this pin, including area of gate, diffusion, metal,
cut, and cumulative area ratios for metal, cut attached to this pin.
Type: obj(antenna_data)*
Default: ""
Edit: No

base_cell

The base_cell of base pin.

Type: obj(base_cell)
Default: ""
Edit: No

base_name

The name without the base_cell name (e.g. out rather than and2/out).
Type: string
Default: ""
Edit: No

cts_max_fanout

The maximum fanout at any point in the clock tree.

Valid values: integer ranged between 2 and 1000 inclusive
Type: int
Default: 100
Edit: Yes

cts_max_source_to_sink_net_length

The maximum routing length in microns between driving source pin and driven
sink pin on each net that clock tree synthesis should observe.
This constraint can be applied to either a pin, a clock tree, or a net type.
By default (if this attribute is not set) no explicit clock tree net length
constraint is enforced. However, other clock tree constraints such as maximum
slew (transition) and maximum capacitance will indirectly limit the maximum
net length.
Valid values: double
Type: string
Allowed -index values: clock_tree
Default: top auto trunk auto leaf auto
Edit: Yes

cts_max_source_to_sink_net_length_leaf

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cts_max_source_to_sink_net_length_top

cts_max_source_to_sink_net_length_trunk

cts_spec_config_base_pin_trace_through_to

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Clock tree definition will, by default, not continue through certain types of
cell arc (for instance, the clock to Q arc in a DFF). This attribute allows
you to override this default behavior, permitting the clock tree to trace through
all instances of such a cell.
This attribute serves the same function as trace_through_to,
except that here the clock path is specified at the level of the library
cell.
The attribute should be configured on the input library pin at
which the clock will arrive. The value of the attribute specifies
the output library pin to which the clock should propagate. The specified
output pin must be another pin on the same library cell. The output pin may be
specified either by its fully qualified name (i.e. inclusive of the cell name),
or else simply by its local (cell-relative) name.
There must be a pre-existing (library-defined) chain of one or more delay arcs
that connect the input and output pins together. It is not possible to use
library_trace_through_to to synthesize delay arcs.
If multiple input pins are annotated on a given library cell, the value of
library_trace_through_to at each of those pins must select the same output pin:
i.e. the configuration must identify a single clock output for the cell. If
multiple clock outputs are necessary then library_trace_through_to should not
be used: instead for each instance of the library cell, define a generated
clock tree at each of the clock-carrying outputs.
If the configuration of library_trace_through_to settings for a given library
cell does not meet these requirements, a warning will be issued and the
settings for that cell will be ignored.
All instances of the library cell will be affected by this setting. If both
trace_through_to and library_trace_through_to are applicable at a given
instance pin, the trace_through_to value will take precedence.
Valid values: base_pin
Type: string
Default: ""
Edit: Yes

cts_stack_via_rule

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The preferred stack via rule for terminal connections.

This attribute helps guide the choice of stack via rule (via pillar) used for connecting
routes to netlist terminals. If the specified value names a valid candidate for terminal in
question (it is a member of list the candidate rules associated with the terminal's cell pin),
then it will used as the preferred stack via rule for connecting to that terminal.
Valid values: 'auto' or stack via rule name
Type: string
Allowed -index values: clock_tree
Default: ""
Edit: Yes

cts_stack_via_rule_leaf

The preferred stack via rule for terminal connections.

cts_stack_via_rule_required

The pin-specific required field for stack via rule connections.

Type: bool
Allowed -index values: clock_tree
Default: false
Edit: Yes

cts_stack_via_rule_required_leaf

The pin-specific required field for stack via rule connections.

Type: bool
Allowed -index values: clock_tree
Default: false
Edit: Yes

cts_stack_via_rule_required_top

The pin-specific required field for stack via rule connections.

Type: bool
Allowed -index values: clock_tree
Default: false
Edit: Yes

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cts_stack_via_rule_required_trunk

The pin-specific required field for stack via rule connections.

Type: bool
Allowed -index values: clock_tree
Default: false
Edit: Yes

cts_stack_via_rule_top

The preferred stack via rule for terminal connections.

cts_stack_via_rule_trunk

The preferred stack via rule for terminal connections.

cts_target_max_capacitance

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The target maximum capacitive load to allow during clock tree synthesis. This
attribute specifies a maximum (combined pin and wire) capacitance that the clock
tree synthesis algorithm will allow any given base_pin to drive in a given
clock tree when driving a given net_type. It is specified in library units. It
currently only constrains the primary delay corner capacitance values - other
delay corners can be specified but will not be constrained. This attribute is
applied in addition to the max_capacitance constraints read from the liberty
library data - the tightest (lowest) of the constraint specified by this
attribute and the constraint present in the liberty data will be used. It also
does not apply at the root pins of clock trees - to constrain those nets the
cts_clock_tree_source_max_capacitance CCOpt attribute should be used instead.
Valid values: auto | double
Type: string
Allowed -index values: delay_corner clock_tree
Default: top auto trunk auto leaf auto
Edit: Yes

cts_target_max_capacitance_leaf

cts_target_max_capacitance_top

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cts_target_max_capacitance_trunk

direction

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Base_pins's direction from .lib if available, otherwise from LEF/OA. It can be in, out, inout or
internal. Internal means it is an internal pin from a .lib file for the timing model, and is not part
of the netlist. If there is no .lib for this cell, then the direction comes from the LEF PIN
DIRECTION or equivalent OA oaTermType. The LEF DIRECTION values (and equivalent
oaTermType values) are mapped this way: INPUT = in, OUTPUT = out, OUTPUT TRISTATE
= out, INOUT = inout, FEEDTHRU = inout, and the oaTermType unknown = inout.
Type: enum
Enum Values: in out inout internal
Default: ""
Edit: No

effective_stack_via_rule

The stack_via_rule that is expected, but not required, to be used by the router for connecting to
the instance pins instantiated from this base_pin. The actual stack via rule used (if any) may
be effected by other pin and base_pin attributes, or by choices made by the software
(optimization, clock tree synthesis, the router etc.)
Type: obj(stack_via_rule)
Default: ""
Edit: No

is_always_on

The always on pin of an always on cell.

Type: bool
Default: false
Edit: No

is_analog

Specifies the pin is an analog signal. This attribute can be set by liberty files.
Type: bool
Default: false
Edit: No

is_isolated

Specifies the pin is isolated internally in the cell. It is used for cells where some pins are
internally isolated and some are not. This attribute can be set by liberty files.
Type: bool
Default: false
Edit: No

is_isolation_cell_enable

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Identifies the pin is an isolation enable pin. This pin is used to control when to clamp the
output and isolate it from the input. This attribute can be set by liberty files, or by CPF
commands.
Type: bool
Default: false
Edit: No

is_level_shifter_enable

Identifies the pin is a level shifter enable pin. This pin is used to control when to clamp the
output and isolate it from the input. This attribute can be set by liberty files, or by CPF
commands.
Type: bool
Default: false
Edit: No

is_power_switch_enable

Identifies the pin is a power switch enable pin. This pin is used to control when to turn on/off
the power switch. This attribute can be set by liberty files, or by CPF commands.
Type: bool
Default: false
Edit: No

is_retention_cell_enable

Identifies the pin as a retention cell enable pin. This pin is used to control when to retain the
state and ignore other inputs. This attribute can be set by liberty files, or by CPF commands.
Type: bool
Default: false
Edit: No

is_unconnected

Specifies the pin is floating internally. This is used for cells where some of the inputs or
outputs are unused by the cell. This attribute can be set by liberty files.
Type: bool
Default: false
Edit: No

is_via_in_pin_only

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Indicates that the pin has a LEF VIAINPINONLY property. It means that vias must be dropped
inside the original pin shapes to connect to the pin. In some advanced nodes, the pin shapes
can be extended for metal alignment purposes. However, via insertion is not allowed in that
extended portion if this attribute is true.
Type: bool
Default: ""
Edit: No

layer

Layer of the base_pin. For base_pins with more than one shape, it is the layer of the first
shape (which is the same shape used for the .location value).
Type: obj(layer)
Default: ""
Edit: No

must_join_pins

The must join base_pin

Type: obj(base_pin)
Default: ""
Edit: No

name

Terminal name
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (base_pin)
Default: ""
Edit: No

pg_type

Specifies the type of the power or ground pin from liberty data. Signal pins and PG pins with
no liberty entry will have "invalid".
Type: enum
Enum Values: primary_power primary_ground backup_power backup_ground
internal_power internal_ground pwell nwell deeppwell deepnwell invalid
Default: invalid
Edit: No

physical_direction

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Direction of this pin.

Type: enum
Enum Values: input output inout unknown feedthrough tristate
Default: ""
Edit: No

physical_pins

Physical pins for the base_pin. One logical base_pin can have multiple physical_pins. Each
physical_pin had a list of strongly connected shapes (equivalent to LEF or DEF PORT or OA
pin). The internal connection between physical_pins is weak (e.g. through poly or other high
resistance paths)
Type: obj(physical_pin)*
Default: ""
Edit: No

pin_edge

If this base_pin is for a partition, or inst that is a black-box, and the base_pin is assigned, the
edge value indicates along which edge of the boundary polygon the base_pin is assigned.
The edge number starts from the lowest Y, then left-most X vertex, staring with 0, and then
counting clock-wise. See the set_pin_constraint command document for a figure showing the
edge numbering. If the base_pin is not assigned, or not for a partition, or black-box inst, the
value of -1 is returned.
Type: int
Default: ""
Edit: No

related_ground_pin

Specifies which ground pin drives this signal pin. It must be one of the ground pins defined for
this cell. It can be set by CPF, Liberty, or LEF/OA, with CPF having highest precedence, then
Liberty, then LEF/OA. It is often only set when there is more than one ground pin for the cell.
Type: obj(base_pin)
Default: ""
Edit: No

related_power_pin

Specifies which power pin drives this signal pin. It must be one of the power pins defined for
this cell. It can be set by CPF, Liberty, or LEF/OA, with CPF having highest precedence, then
Liberty, then LEF/OA. It is often only set when there is more than one power pin for the cell.
Type: obj(base_pin)
Default: ""
Edit: No

stack_via_required

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Specifies whether a stack via is required when connecting to the instance pins instantiated
from this base_pin. If true, one of the stack_via_rule from stack_via_rule_list must be used to
generate a stack via even if a design rule violation occurs. If false, a stack via is optional. Note
that the pin stack_via_rule_required value may override this base_pin setting in some cases.
See the documentation of stack_via_rule(pin) and stack_via_rule_required(pin) for more
details.
Type: bool
Default: false
Edit: Yes

stack_via_rule_list

List of stack_via_rule that are valid choices for connecting to the instance pins instantiated
from this base_pin. If the list is empty, no stack via is allowed.
Type: obj(stack_via_rule)*
Default: ""
Edit: Yes

taper_rule

The taper route_rule for the pin. By default, if tapered routing is needed to access the pin, the
default route_rule will be used unless this attribute is set (see LEF MACRO PIN
TAPERRULE).
Type: obj(route_rule)
Default: ""
Edit: No

tied_to

Specifies the PG pin name or 'empty' which the PG pin tied to.
Type: string
Default: ""
Edit: No

use

Indicates how this pin is used from the LEF USE value or OA equivalent. The legal values are:
signal analog power ground clock. Note that timing analysis does not use these values, it uses
the .lib data instead (e.g. is_clock, is_analog, etc.). So the signal, clock or analog values are
not normally used by applications. The power/ground values are used by many applications.
Type: enum
Enum Values: signal analog power ground clock
Default: ""
Edit: No

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Database Objects--boundary

boundary

Parent Objects
hinst, design, root

Definition
A boundary object can only be attached to an hinst, normally when the hinst is a partition. It is used to
constrain the placement of all the insts of the hinst. See the group object for placement constraint information
attached to the group object (e.g. a list of insts, hinsts, or groups).

Attribute Description

area

Sum of the area of the .rects that define the boundary

Type: area
Default: ""
Edit: No

bbox

Bounding box of the boundary rects.

Type: rect
Default: ""
Edit: No

hinst

The parent hinst. This boundary affects all the insts inside the parent hinst.
Type: obj(hinst)
Default: ""
Edit: Yes

is_floating

Only affects boundary with .type = fence or region. If true, the global placer can move the fence
or region. The .bbox and .rects value must also be set. The global placer will not change the
size of the rect, but may move it.
Type: bool
Default: false
Edit: Yes

obj_type

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The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (boundary)
Default: ""
Edit: No

rects

List of non-overlapping rectangles that defines the shape of the boundary

Type: rect*
Default: ""
Edit: No

type

fence: all the insts are inside the boundary, and only these insts can be inside.
region: all the insts are inside, but other insts can also be inside.
guide: lower cost for insts to be inside boundary, but not required.
cluster: keep insts near each other (the .rects field is empty).
none: no affect on placement.
Type: enum
Enum Values: guide region fence cluster none
Default: ""
Edit: Yes

bump

Parent Objects
marker, bump_pin, design, io_constraint, root

Definition
Bump instance

Attribute Description

base_cell

The base_cell master of the bump.

Type: obj(base_cell)
Default: ""
Edit: No

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base_name

The base_name of the bump

Type: string
Default: ""
Edit: No

bbox

Bounding box of the bump shape for a package connection, which is the widest shape found
on the top routing layer in the base_cell. If there is more than one wide shape of the same
size, the bbox of all the wide shapes is returned.
Type: rect
Default: ""
Edit: No

bump_pins

The pins of the bump. A bump with ALLPINSCONNECTED LEF syntax can have multiple
bump_pins which are internally connected.
Type: obj(bump_pin)*
Default: ""
Edit: No

center

The center of the bump shape for a package connection, which is the center of the .bbox
attribute. This is not the same as the .location of the bump which is normally at the lower-left
corner of the cell.
Type: point
Default: ""
Edit: No

escaped_name

The escaped name of the bump

Type: string
Default: ""
Edit: No

is_fixed_assignment

Indicates that the bump is connected to one port

Type: bool
Default: ""
Edit: No

location

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Location of the bump.

Type: point
Default: ""
Edit: Yes

name

Name of the bump

Type: string
Default: ""
Edit: No

net

The net connected to the bump.

Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (bump)
Default: ""
Edit: No

orient

Bump orientation.
Type: enum
Enum Values: r0 r90 r180 r270 mx mx90 my my90
Default: ""
Edit: Yes

place_status

Placement status of bump.

Type: enum
Enum Values: unplaced placed fixed cover soft_fixed
Default: ""
Edit: Yes

port

The ports the bump is assigned to.

Type: obj(port)*
Default: ""
Edit: No

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ports

The ports the bump is assigned to.

Type: obj(port)*
Default: ""
Edit: No

bus

Parent Objects
design, net, root, port

Definition
The Verilog bus definitions in the top Verilog module.

Attribute Description

bits

The nets or ports of the bus. All the bits of one bus will have the same obj_type.
Type: obj(port)* obj(net)*
Default: ""
Edit: No

lsb

Bottom bit index of bus.

Type: int
Default: ""
Edit: No

msb

Top bit index of bus.

Type: int
Default: ""
Edit: No

name

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Non-vector portion of the bus name (eg. A for bus A[7:0])

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (bus)
Default: ""
Edit: No

bus_guide

Parent Objects
design

Definition
Bus guide

Attribute Description

area

Area of the bus_guide as defined by the LEF MACRO SIZE or OVERLAP information
Type: area
Default: ""
Edit: No

bottom_layer

The bottom layer of allowed layer range

Type: obj(layer)
Default: ""
Edit: Yes

net_group

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The net group with list of nets to be routed within the bus_guide
Type: obj(net_group)*
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (bus_guide)
Default: ""
Edit: No

rect

Rectangel that defines the bus_guide shape.

Type: rect
Default: ""
Edit: No

top_layer

The top layer of allowed layer range

Type: obj(layer)
Default: ""
Edit: Yes

type

The type of bus_guide.

hard: Specifies the bus_guide as a hard constraint for routing. eGR, NR and NRHF should
obey the path of bus guide.
soft: Specifies the bus_guide as a soft constraint for routing. eGR, NR and NRHF should be
guided by the route path. But tool can route the net out of the bus guide.
Type: enum
Enum Values: soft hard
Default: ""
Edit: Yes

clock

Parent Objects
pin, timing_path, root, port

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Definition
cte clock

Attribute Description

base_name

The base_name of the clock.

Type: string
Default: ""
Edit: No

clock_hold_uncertainty

clock_hold_uncertainty
Type: double
Default: ""
Edit: No

clock_network_pins

Returns a list of pin and hpin objects in the extended fanout of the clock source. The extended
fanout includes the fanout of generated clocks which the current clock is the master for.
Type: obj(port)* obj(pin)*
Default: ""
Edit: No

clock_setup_uncertainty

clock_setup_uncertainty
Type: double
Default: ""
Edit: No

comment

Returns the -comment option of a clock.

Type: string
Default: ""
Edit: No

delay_max_fall

Returns the maximum falling delay value for the clock.

Type: double
Default: ""
Edit: No

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delay_max_rise

Returns the maximum rising delay value for the clock.

Type: double
Default: ""
Edit: No

delay_min_fall

Returns the minimum falling delay value for the clock.

Type: double
Default: ""
Edit: No

delay_min_rise

Returns the minimum rising delay value for the clock.

Type: double
Default: ""
Edit: No

divide_by

Returns the create_generated_clock -divide_by option of a generated clock.

Type: int
Default: ""
Edit: No

duty_cycle

Returns the create_generated_clock -duty_cycle option of a generated clock.

Type: double
Default: ""
Edit: No

edge_shift

Returns the create_generated_clock -edge_shift option of a generated clock.

Type: string
Default: ""
Edit: No

edges

Returns the create_generated_clock -edges option of a generated clock.

Type: string
Default: ""
Edit: No

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generated_clocks

Returns a list of clock object which are the generated clocks derived from this master clock.
Type: obj(clock)*
Default: ""
Edit: No

hierarchical_name

hierarchical_name
Type: string
Default: ""
Edit: No

ideal_transition_max_fall

Returns the set_clock_transition -max -fall asserted on the clock and used during ideal mode
analysis.
Type: double
Default: ""
Edit: No

ideal_transition_max_rise

Returns the set_clock_transition -max -rise asserted on the clock and used during ideal mode
analysis.
Type: double
Default: ""
Edit: No

ideal_transition_min_fall

Returns the set_clock_transition -min -fall asserted on the clock and used during ideal mode
analysis.
Type: double
Default: ""
Edit: No

ideal_transition_min_rise

Returns the set_clock_transition -min -rise asserted on the clock and used during ideal mode
analysis.
Type: double
Default: ""
Edit: No

is_active

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Returns true if the clock has been set active by the set_active_clocks constraint.
Type: bool
Default: ""
Edit: No

is_combinational_source_path

Returns true if the create_generated_clock -combinational option was specified for the
creation of this generated clock.
Type: bool
Default: ""
Edit: No

is_context_mapped

Returns true if the clock is mapped in the block level SDC in the timing context reading
session
Type: bool
Default: ""
Edit: No

is_generated

Returns true if this clock object represents a generated clock

Type: bool
Default: ""
Edit: No

is_inverted

Returns true if the create_generated_clock -invert option was specified for the creation of this
generated clock.
Type: bool
Default: ""
Edit: No

is_library_created

Returns true if this generated_clock was specified in a Liberty generated_clock group and not
created by a create_generated_clock constraint
Type: bool
Default: ""
Edit: No

is_propagated

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Returns true if set_propagated_clock was asserted explicitly on this clock object.

Type: bool
Default: ""
Edit: No

is_source_inverted

Returns true if the create_generated_clock -source_invert option was specified for the creation
of this generated clock.
Type: bool
Default: ""
Edit: No

is_virtual

Returns true if this clock is virtual

Type: bool
Default: ""
Edit: No

master_clock

Returns the master clock of this generated clock as specified by the create_generated_clock -
master_clock option when this generated clock was created.
Type: obj(clock)*
Default: ""
Edit: No

master_source

Returns the master clock source pin of this generated clock as specified by the
create_generated_clock -source option when this generated clock was created.
Type: obj(pin)* obj(hpin)* obj(hport)*
Default: ""
Edit: No

max_capacitance_clock_path_fall

Returns the value asserted by set_max_capacitance -clock_path -fall on this clock.

Type: double
Default: ""
Edit: No

max_capacitance_clock_path_rise

Returns the value asserted by set_max_capacitance -clock_path -rise on this clock.

Type: double
Default: ""
Edit: No

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max_capacitance_data_path_fall

Returns the value asserted by set_max_capacitance -data_path -fall on this clock.

Type: double
Default: ""
Edit: No

max_capacitance_data_path_rise

Returns the value asserted by set_max_capacitance -data_path -rise on this clock.

Type: double
Default: ""
Edit: No

max_transition_clock_path_fall

Returns the value asserted by set_max_transition -clock_path -fall on this clock.

Type: double
Default: ""
Edit: No

max_transition_clock_path_rise

Returns the value asserted by set_max_transition -clock_path -rise on this clock.

Type: double
Default: ""
Edit: No

max_transition_data_path_fall

Returns the value asserted by set_max_transition -data_path -fall on this clock.

Type: double
Default: ""
Edit: No

max_transition_data_path_rise

Returns the value asserted by set_max_transition -data_path -rise on this clock.

Type: double
Default: ""
Edit: No

min_pulse_width_high

Returns the minimum pulse width high requirement set by set_min_pulse_width .

Type: double
Default: ""
Edit: No

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min_pulse_width_low

Returns the minimum pulse width low requirement set by set_min_pulse_width.

Type: double
Default: ""
Edit: No

multiply_by

Returns the create_generated_clock -multiply_by option of a generated clock.

Type: int
Default: ""
Edit: No

name

The name of the clock.

Type: string
Default: ""
Edit: No

network_latency_fall_max

Returns the maximum fall insertion delay specified by an explicit set_clock_latency on the
clock.
Type: double
Default: ""
Edit: No

network_latency_fall_min

Returns the minimum fall insertion delay specified by an explicit set_clock_latency on the
clock.
Type: double
Default: ""
Edit: No

network_latency_rise_max

Returns the maximum rise insertion delay specified by an explicit set_clock_latency on the
clock.
Type: double
Default: ""
Edit: No

network_latency_rise_min

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Returns the minimum rise insertion delay specified by an explicit set_clock_latency on the
clock.
Type: double
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (clock)
Default: ""
Edit: No

period

Returns the period of the clock. The period is either specified directly with create_clock or
derived from a generated clock.
Type: double
Default: ""
Edit: No

source_jitter_early_fall_max

Returns the amount of the maximum early fall source insertion delay that is due to cycle-to-
cycle variation. This is specified by using the set_clock_latency -jitter option.
Type: double
Default: ""
Edit: No

source_jitter_early_fall_min

Returns the amount of the minimum early fall source insertion delay that is due to cycle-to-
cycle variation. This is specified by using the set_clock_latency -jitter option.
Type: double
Default: ""
Edit: No

source_jitter_early_rise_max

Returns the amount of the maximum early rise source insertion delay that is due to cycle-to-
cycle variation. This is specified by using the set_clock_latency -jitter option.
Type: double
Default: ""
Edit: No

source_jitter_early_rise_min

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Returns the amount of the minimum early rise source insertion delay that is due to cycle-to-
cycle variation. This is specified by using the set_clock_latency -jitter option.
Type: double
Default: ""
Edit: No

source_jitter_late_fall_max

Returns the amount of the maximum late fall source insertion delay that is due to cycle-to-
cycle variation. This is specified by using the set_clock_latency -jitter option.
Type: double
Default: ""
Edit: No

source_jitter_late_fall_min

Returns the amount of the minimum late fall source insertion delay that is due to cycle-to-cycle
variation. This is specified by using the set_clock_latency -jitter option.
Type: double
Default: ""
Edit: No

source_jitter_late_rise_max

Returns the amount of the maximum late rise source insertion delay that is due to cycle-to-
cycle variation. This is specified by using the set_clock_latency -jitter option.
Type: double
Default: ""
Edit: No

source_jitter_late_rise_min

Returns the amount of the minimum late rise source insertion delay that is due to cycle-to-
cycle variation. This is specified by using the set_clock_latency -jitter option.
Type: double
Default: ""
Edit: No

source_latency_early_fall_max

Returns the maximum early fall source insertion delay specified by an explicit
set_clock_latency on the clock.
Type: double
Default: ""
Edit: No

source_latency_early_fall_min

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Returns the minimum early fall source insertion delay specified by an explicit
set_clock_latency on the clock.
Type: double
Default: ""
Edit: No

source_latency_early_rise_max

Returns the maximum early rise source insertion delay specified by an explicit
set_clock_latency on the clock.
Type: double
Default: ""
Edit: No

source_latency_early_rise_min

Returns the minimum early rise source insertion delay specified by an explicit
set_clock_latency on the clock.
Type: double
Default: ""
Edit: No

source_latency_late_fall_max

Returns the maximum late fall source insertion delay specified by an explicit
set_clock_latency on the clock.
Type: double
Default: ""
Edit: No

source_latency_late_fall_min

Returns the minimum late fall source insertion delay specified by an explicit set_clock_latency
on the clock.
Type: double
Default: ""
Edit: No

source_latency_late_rise_max

Returns the maximum late rise source insertion delay specified by an explicit
set_clock_latency on the clock.
Type: double
Default: ""
Edit: No

source_latency_late_rise_min

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Returns the minimum late rise source insertion delay specified by an explicit
set_clock_latency on the clock.
Type: double
Default: ""
Edit: No

sources

Returns the pin or port objects where the clock is attached to the design - as specified by
create_clock or create_generated_clock
Type: obj(port)* obj(pin)*
Default: ""
Edit: No

view_name

The name of the analysis view for the clock.

Type: string
Default: ""
Edit: No

waveform

Returns a list of the sequence of rising and falling edge times of a single period of the clock.
The first list entry is always the first rising edge time, and the second entry is always the
subsequent falling edge time.
Type: string
Default: ""
Edit: No

clock_spine

Parent Objects

Definition
clock tree spine

Attribute Description

name

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name of clock_spine
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (clock_spine)
Default: ""
Edit: No

clock_tree

Parent Objects
clock_tree_source_group, pin, root, port

Definition
clock tree in ccopt

Attribute Description

clock_tree_source_group

the clock_tree_source_group this clock_trees is a member of

Type: obj(clock_tree_source_group)*
Default: ""
Edit: No

cts_buffer_cells

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Specifies the buffer cells for CTS. If none are specified CCOpt will choose buffers from the
libraries.
Cell names may be specified as a Tcl list of names, or as a Tcl list of patterns to be expanded
to match names.
If set explicitly, CCOpt will ignore any dont_use settings for the cells specified.
Different buffer cells may be specified for any combination of clock tree and power domain.
To use different buffers for each net type set the cts_buffer_cells_top and
cts_buffer_cells_leaf attributes .
Some examples follow:
To specify buffer cells for all clock trees and all power domains:
set_db cts_buffer_cells {bufAX* bufBX*}
To specify buffer cells for a particular clock tree and all power domains:
set_db clock_tree:<clk> .cts_buffer_cells {bufX20 bufX18}
To specify buffer cells for a particular clock tree and power domain:
set_db clock_tree:<clk> .cts_buffer_cells -index {power_domain <pd>} {bufX12 bufX8}
Valid values: a list of library cell names, or a list of patterns to expand to library cell names
Type: string
Allowed -index values: power_domain
Default: ""
Edit: Yes

cts_buffer_cells_leaf

Specifies the buffer cells available for CTS to use on leaf nets. If none are specified CCOpt
will use the same buffers as on trunk nets
(as specified in the cts_buffer_cells attribute).
Cell names may be specified as a Tcl list of names, or as a Tcl list of patterns to be expanded
to match names.
If set explicitly, CCOpt will ignore any dont_use settings for the cells specified.
Different leaf buffer cells may be specified for any combination of clock tree and power
domain.
Valid values: a list of library cell names, or a list of patterns to expand to library cell names
Type: string
Allowed -index values: power_domain
Default: ""
Edit: Yes

cts_buffer_cells_top

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Specifies the buffers cells available for CTS to use on top nets. If none are specified CCOpt
will use the same buffers as on trunk nets
(as specified in the cts_buffer_cells attribute).
Cell names may be specified as a Tcl list of names, or as a Tcl list of patterns to be expanded
to match names.
If set explicitly, CCOpt will ignore any dont_use settings for the cells specified.
Different top buffer cells may be specified for any combination of clock tree and power
domain.
Valid values: a list of library cell names, or a list of patterns to expand to library cell names
Type: string
Allowed -index values: power_domain
Default: ""
Edit: Yes

cts_cell_density

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Specifies the clock halo in the x direction.

Any x direction clock halo defined by this attribute is proportional to the cell width.
The constant of proportionality is defined by the attribute value. For example:
. If cts_cell_density = 0.25 then the x direction clock halo equals 3 * cell width.
. If cts_cell_density = 0.5 then the x direction clock halo equals cell width.
. If cts_cell_density = 0.75 then the x direction clock halo equals cell width / 3.
. If cts_cell_density = 1 then the x direction clock halo equals zero.
This attribute can specify the x direction clock halo for all clock trees via:
set_db cts_cell_density 0.8
This attribute can specify the x direction clock halo per-clock tree via:
set_db clock_tree:<clk> .cts_cell_density 0.9
The following attributes can be used to assign x direction clock halos within CCOpt:
cts_cell_halo_x
cts_cell_density
cts_cell_halo_sites
Only one of these attributes is used to determine the clock halo in the x direction. The
following rules determine which:
. If cts_cell_halo_x is set to a non-auto value, then this defines the x direction clock halo. The
attributes cts_cell_density and cts_cell_halo_sites have no effect.
. If cts_cell_halo_x is set to auto and cts_cell_density is set to a non-auto value then
cts_cell_density defines the clock halo in the x direction. The attribute cts_cell_halo_sites has
no effect.
. If both cts_cell_halo_x and cts_cell_density are set to auto then cts_cell_halo_sites defines
the clock halo in the x direction.
Valid values: 0.01 to 1
See also:
. cts_cell_halo_x
. cts_cell_halo_sites
Type: string
Default: 0.75
Edit: Yes

cts_cell_halo_x

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cts_cell_halo_y

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cts_clock_gating_cells

Specifies the clock gates for CTS. If none are specified CCOpt will choose clock gates from
the libraries.
Cell names may be specified as a Tcl list of names, or as a Tcl list of patterns to be expanded
to match names.
If set explicitly, CCOpt will ignore any dont_use settings for the cells specified.
Different clock gates may be specified for any combination of clock tree and power domain.
Some examples follow:
To specify clock gates for all clock trees and all power domains:
set_db cts_clock_gating_cells {cgAX* cgBX*}
To specify clock gates for a particular clock tree and all power domains:
set_db clock_tree:<clk> .cts_clock_gating_cells {cgX20 cgX18}
To specify clock gates for a particular clock tree and power domain:
set_db clock_tree:<clk> .cts_clock_gating_cells -index {power_domain <pd>} {cgX12 cgX8}
Valid values: a list of library cell names, or a list of patterns to expand to library cell names
Type: string
Allowed -index values: power_domain
Default: ""
Edit: Yes

cts_clock_source_cells

Specifies the cells available for CTS to size clock sources if the cts_size_clock_sources
attribute is set to true. If none are specified the tool will choose cells from the libraries.
Cell names may be specified as a Tcl list of names, or as a Tcl list of patterns to be expanded
to match names.
If set explicitly, the tool will ignore any dont_use settings for the cells specified.
Different cells may be specified for clock trees or power domains. Only clock sources that are
buffers, inverters, logic and clock gating cells with a single output can be resized.
Valid values: a list of library cell names, or a list of patterns to expand to library cell names
Type: string
Allowed -index values: power_domain
Default: ""
Edit: Yes

cts_clock_tree_parents

The list of parent clock trees from which this clock tree is generated, if
any.
Valid values: list cts_clock_tree
Type: string
Default: ""
Edit: No

cts_clock_tree_source_driver

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Specifies the base_pin which is assumed to drive this clock tree. It is

either a single base_pin (in which case all arcs to that base_pin shall be used
when timing the clock tree root) or a pair of base_pins (in which case only
arcs from the first specified pin to the second will be considered).
By default this is generated from clock tree extraction
Valid values: base_pin | {base_pin base_pin}
Type: string
Default: ""
Edit: Yes

cts_clock_tree_source_group

Specifies the clock tree source group to which this clock tree belongs.
Valid values: list cts_clock_tree_source_group
Type: string
Default: ""
Edit: No

cts_clock_tree_source_group_clock_trees

A list of the clock trees relevant to this source group.

Valid values: list cts_clock_trees
Type: string
Default: ""
Edit: Yes

cts_clock_tree_source_input_max_transition_time

The slew which will be assumed at the input of the root driver.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

cts_clock_tree_source_max_capacitance

The maximum capacitive load which this clock tree is permitted to drive.
Valid values: double | auto
Auto: from clock tree extraction
Type: string
Default: auto
Edit: Yes

cts_clock_tree_source_output_max_transition_time

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If non-zero, the slew which will be assumed at the output of the root driver.
This overrides the value from SDC.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

cts_delay_cells

Specifies the delay cells available for CTS. If none are specified CCOpt will not use delay
cells.
Setting this attribute to the string 'auto' means that CCOpt will choose delay cells from the
libraries to use.
Cell names may be specified as a Tcl list of names, or as a Tcl list of patterns to be expanded
to match names.
If set explicitly, CCOpt will ignore any dont_use settings for the cells specified.
Different delay cells may be specified for any combination of clock tree and power domain, or
by omitting those
arguments a global setting can be applied.
Some examples follow:
To specify delay cells for all clock trees and power domains:
set_db cts_delay_cells {delayAX* delayBX*}
To specify delay cells for a particular clock tree and all power domains:
set_db clock_tree:<clk> .cts_delay_cells {delayX1 delayX2}
To specify delay cells for a particular clock tree and power domain:
set_db clock_tree:<clk> .cts_delay_cells -index {power_domain <pd>} {delayX2 delayX3}
Valid values: a list of library cell names, or a list of patterns to expand to library cell names, or
the string 'auto'
Type: string
Allowed -index values: power_domain
Default: ""
Edit: Yes

cts_inverter_cells

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Specifies the inverter cells available for CTS. If none are specified CCOpt will choose
inverters from the libraries.
Cell names may be specified as a Tcl list of names, or as a Tcl list of patterns to be expanded
to match names.
If set explicitly, CCOpt will ignore any dont_use settings for the cells specified.
Different inverter cells may be specified for any combination of clock tree and power domain.
To use different inverters for each net type set the cts_inverter_cells_top and
cts_inverter_cells_leaf attributes .
Some examples follow:
To specify inverter cells for all clock trees and all power domains:
set_db cts_inverter_cells {invAX* invBX*}
To specify inverter cells for a particular clock tree and all power domains:
set_db clock_tree:<clk> .cts_inverter_cells {invX20 invX18}
To specify inverter cells for a particular clock tree and power domain:
set_db clock_tree:<clk> .cts_inverter_cells -index {power_domain <pd>} {invX12 invX8}
Valid values: a list of library cell names, or a list of patterns to expand to library cell names
Type: string
Allowed -index values: power_domain
Default: ""
Edit: Yes

cts_inverter_cells_leaf

Specifies the inverter cells available for CTS to use on leaf nets. If none are specified CCOpt
will use the same inverters as on trunk nets
(as specified in the cts_inverter_cells attribute).
Cell names may be specified as a Tcl list of names, or as a Tcl list of patterns to be expanded
to match names.
If set explicitly, CCOpt will ignore any dont_use settings for the cells specified.
Different leaf inverter cells may be specified for any combination of clock tree and power
domain.
Valid values: a list of library cell names, or a list of patterns to expand to library cell names
Type: string
Allowed -index values: power_domain
Default: ""
Edit: Yes

cts_inverter_cells_top

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Specifies the inverter cells available for CTS to use on top nets. If none are specified CCOpt
will use the same inverters as on trunk nets
(as specified in the cts_inverter_cells attribute).
Cell names may be specified as a Tcl list of names, or as a Tcl list of patterns to be expanded
to match names.
If set explicitly, CCOpt will ignore any dont_use settings for the cells specified.
Different top inverter cells may be specified for any combination of clock tree and power
domain.
Valid values: a list of library cell names, or a list of patterns to expand to library cell names
Type: string
Allowed -index values: power_domain
Default: ""
Edit: Yes

cts_load_capacitance_cells

Specifies the load capacitance cells available for CTS. CTS will use cells from this collection
for load capacitance optimizations.
Cell names may be specified as a Tcl list of names, or as a Tcl list of patterns to be expanded
to match names.
Type: string
Allowed -index values: power_domain
Default: ""
Edit: Yes

cts_logic_cells

Specifies the clock logics for CTS. If none are specified CCOpt will choose clock logics from
the libraries.
Cell names may be specified as a Tcl list of names, or as a Tcl list of patterns to be expanded
to match names.
If set explicitly, CCOpt will ignore any dont_use settings for the cells specified.
Different logic cells may be specified for any combination of clock tree and power domain.
Some examples follow:
To specify logic cells for all clock trees and all power domains:
set_db cts_logic_cells {and* mux*}
To specify logic cells for a particular clock tree and all power domains:
set_db clock_tree:<clk> .cts_logic_cells {andX20 andX18}
To specify logic cells for a particular clock tree and power domain:
set_db clock_tree:<clk> .cts_logic_cells -index {power_domain <pd>} {andX12 andX8}
Valid values: a list of library cell names, or a list of patterns to expand to library cell names
Type: string
Allowed -index values: power_domain
Default: ""
Edit: Yes

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cts_route_type_leaf

Specifies the route type. Setting this attribute binds an existing user-defined route_type to one
or more types of clock tree nets. Binding a route_type to a type of clock tree nets means that all
nets of that type (including the nets created by CTS) will be routed according to the
specification of that route_type.
In the most common usage, the route_type is bound to one of the three types of clock tree
nets (top, trunk, or leaf) with the optional -net_type argument. Omitting the -net_type argument
causes the route_type to be bound to all three types of clock tree nets. The optional -
clock_tree <pattern> argument limits the binding to the clock trees whose name matches
<pattern>. Omitting the -clock_tree argument causes the binding to apply to all clock trees.
For a route_type to be used in CTS, it must be bound to at least one net type. If net type is not
bound to any route_type, a default route_type will be created for that net type at the start of
CTS.
Valid values: names of route_types created with create_route_type
Type: string
Default: default
Edit: Yes

cts_route_type_top

cts_route_type_trunk

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cts_source_latency

Specifies a delay value between the global clock source and this clock tree.
This additional delay will be included in all timing analysis involving skew
groups for which this clock tree is a source. The default is 0.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

cts_target_max_transition_time

The target slew used for clock tree synthesis. This attribute specifies a
maximum slew time that the clock tree synthesis algorithm will allow in this
clock tree, in library units. 'default' means 'auto' in primary half corner and
'ignore' in other half corners. If set to 'auto', CTS picks an appropriate value
based on the collection of allowed buffer sizes and library parameters,
although this may not give optimal quality of results. If set to 'ignore',
CTS does not constrain the corner.
Valid values: default | auto | ignore | double
Type: string
Allowed -index values: delay_corner power_domain
Default: top default trunk default leaf default
Edit: Yes

cts_target_max_transition_time_leaf

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cts_target_max_transition_time_sdc

If non-zero, the target slew used for clock tree synthesis, overriding the SDC. This attribute
specifies a
maximum slew time that the clock tree synthesis algorithm will allow, in library
units obtained from SDC.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

cts_target_max_transition_time_top

cts_target_max_transition_time_trunk

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cts_top_fanout_threshold

Minimum number of transitive fanout in the clock tree for a net to be routed
as a top net. Nets with at least this many sinks in their transitive fanout in
the clock tree will have the special routing rules applied to them.
Valid values: integer
Type: string
Default: unset
Edit: Yes

insts

instances in the clock tree

Type: obj(inst)*
Default: ""
Edit: No

name

name of clock_tree
Type: string
Default: ""
Edit: No

nets

nets in the clock tree

Type: obj(net)*
Default: ""
Edit: No

obj_type

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The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (clock_tree)
Default: ""
Edit: No

sinks

sinks (pins or ports) of the clock tree

Type: obj(pin)* obj(port)*
Default: ""
Edit: No

source

The source pin for this cts_clock_tree.

Valid values: pin
Type: obj(pin)* obj(port)*
Default: ""
Edit: No

clock_tree_source_group

Parent Objects
clock_tree, root

Definition
clock tree source group

Attribute Description

clock_trees

clock_tree_source_group member clock_trees

Type: obj(clock_tree)*
Default: ""
Edit: Yes

name

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name of clock_tree_source_group
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (clock_tree_source_group)
Default: ""
Edit: No

constraint_mode

Parent Objects
analysis_view, design, root

Definition
Associates a list of SDC constraint files with a specified constraint mode name, for multi-mode multi-corner
analysis. This constraint mode name can be referred to later when creating analysis views. Use the
create_constraint_mode and update_constraint_mode commands to create and modify constraint_modes.

Attribute Description

ilm_sdc_files

Specifies an optional list of constraint files to use when using ILM mode
Type: string
Default: ""
Edit: No

is_active

Indicates that the constraint_mode is associated with an analysis_view that is used in the
active analysis_view.
Type: bool
Default: ""
Edit: No

is_dynamic

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Indicates that the constraint_mode is associated with an analysis_view that is used in the
active dynamic analysis_view.
Type: bool
Default: ""
Edit: No

is_hold

Indicates that the constraint_mode is associated with an analysis_view that is active for hold
analysis.
Type: bool
Default: ""
Edit: No

is_leakage

Indicates that the constraint_mode is associated with an analysis_view that is used in the
active leakage analysis_view.
Type: bool
Default: ""
Edit: No

is_setup

Indicates that the constraint_mode is associated with an analysis_view that is active for setup
analysis.
Type: bool
Default: ""
Edit: No

name

Provides the name of this constraint_mode object as specified by create_constraint_mode.

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (constraint_mode)
Default: ""
Edit: No

sdc_files

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Specifies an optional list of constraint files to associate with the mode

Type: string
Default: ""
Edit: No

tcl_vars

Specifies an optional list of user-specified Tcl variable name and value pairs - e.g: {{my_var1
true} {my_var2 0.1}} - which are set before the constraint files are read, and can be used inside
the constraint files.
Type: string
Default: ""
Edit: No

delay_corner

Parent Objects
analysis_view, design, root

Definition
The delay_corner object provides references to rc_corner objects which define the interconnect corner and
timing_condition-to-domain bindings which define device operating corners - providing the majority of the
configuration information needed to drive delay calculation. An analysis_view object will reference the
delay_corner and combine it with a constraint_mode to complete the configuration. Use the
create_delay_corner and update_delay_corner commands to create and modify delay_corner objects.

Attribute Description

default_early_timing_condition

Specifies the timing condition to be used for early path analysis if one has not be explicitly
specified for a given power domain.
Type: obj(timing_condition)
Default: ""
Edit: No

default_late_timing_condition

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Specifies the timing condition to be used for late path analysis if one has not be explicitly
specified for a given power domain.
Type: obj(timing_condition)
Default: ""
Edit: No

early_irdrop_files

Specifies a file with instance-specific voltage data for early path analysis. Instance voltage
data can be either exported from power rail analysis tools such as Voltus, or specified with
set_instance_voltage constraints
Type: string
Default: ""
Edit: No

early_pg_net_voltages

Specifies the power/ground net voltages to use for early analysis

Type: string
Default: ""
Edit: No

early_rc_corner

Specifies the associated rc_corner object for early path analysis

Type: obj(rc_corner)
Default: ""
Edit: No

early_temperature_files

Specifies a file with instance-specific temperature data for early path analysis
Type: string
Default: ""
Edit: No

early_timing_condition

Provides the early timing_condition object associated with the specified power_domain index.
If no power_domain index is given, the default early timing_condition will be returned.
Type: obj(timing_condition)
Allowed -index values: power_domain
Default: ""
Edit: No

early_timing_condition_string

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Specifies the list of power_domain to timing_condition bindings for early path analysis - using
<power_domain>@<timing_condition> list syntax, for example 'defaultTC PD1@TC1
PD2@TC2'.
Type: string
Default: ""
Edit: No

is_active

Indicates that the delay_corner is associated with an analysis_view that is used in the active
analysis_view
Type: bool
Default: ""
Edit: No

is_dynamic

Indicates that the delay_corner is associated with an analysis_view that is used in the active
dynamic analysis_view
Type: bool
Default: ""
Edit: No

is_hold

Indicates that the delay_corner is associated with an analysis_view that is active for hold
analysis
Type: bool
Default: ""
Edit: No

is_leakage

Indicates that the delay_corner is associated with an analysis_view that is used in the active
leakage analysis_view
Type: bool
Default: ""
Edit: No

is_setup

Indicates that the delay_corner is associated with an analysis_view that is active for setup
analysis
Type: bool
Default: ""
Edit: No

is_si_enabled

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Indicates that analysis_views associated with this delay_corner should have SI analysis
performed on them
Type: bool
Default: ""
Edit: No

late_irdrop_files

Specifies a file with instance-specific voltage data for late path analysis. Instance voltage data
can be either exported from power rail analysis tools such as Voltus, or specified with
set_instance_voltage constraints
Type: string
Default: ""
Edit: No

late_pg_net_voltages

Specifies the power/ground net voltages to use for late analysis

Type: string
Default: ""
Edit: No

late_rc_corner

Specifies the associated rc_corner object for late path analysis

Type: obj(rc_corner)
Default: ""
Edit: No

late_temperature_files

Specifies a file with instance-specific temperature data for late path analysis
Type: string
Default: ""
Edit: No

late_timing_condition

Provides the late timing_condition object associated with the specified power_domain index. If
no power_domain index is given, the default late timing_condition will be returned.
Type: obj(timing_condition)
Allowed -index values: power_domain
Default: ""
Edit: No

late_timing_condition_string

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Specifies the list of power_domain to timing_condition bindings for late path analysis - using
<power_domain>@<timing_condition> list syntax, for example 'defaultTC PD1@TC1
PD2@TC2'.
Type: string
Default: ""
Edit: No

name

Provides the name of this delay_corner object as specified by create_delay_corner. This

name can referenced by other commands to refer to this object
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (delay_corner)
Default: ""
Edit: No

pg_net_voltages

Specifies the power/ground net voltages to use for both early/late analysis
Type: string
Default: ""
Edit: No

density_shape

Parent Objects
place_blockage

Definition
Rectangle with metal/cut or placement density information

Attribute Description

density

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Density value (range: 0.0-1.0

Type: double
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (density_shape)
Default: ""
Edit: No

rect

Rectangle. For cellDensity, the coordinates are local to cell, not relative to the design.
Type: rect
Default: ""
Edit: No

design

Parent Objects
hinst, inst, module, pin_group, pin_guide, root, port

Definition
top cell

Attribute Description

analysis_views

Returns the information about the analysis views in the design.

Type: obj(analysis_view)*
Default: ""
Edit: No

area

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The area of all the insts contained inside this design and below it. This does not include
phys_insts. Use 'get_db $design .boundary.area' if you want the area of the physical design
boundary.
Type: area
Default: ""
Edit: No

bbox

Bounding box of the design boundary,

Type: rect
Default: ""
Edit: No

boundaries

All the boundary objects (fence, region, etc.) in the design.

Type: obj(boundary)*
Default: ""
Edit: No

boundary

Polygon that define the shape of the floorplan boundary

Type: polygon*
Default: ""
Edit: No

bumps

List of bumps in the cell

Type: obj(bump)*
Default: ""
Edit: No

bus_guides

List of bus guide objects.

Type: obj(bus_guide)*
Default: ""
Edit: No

bus_sink_groups

A group of sinks (loads) that some floorplan and routing commands use to control adding
buffers and routing for a bus. See 'help *bus_sink*' for a list of commands related to this object.
Type: obj(bus_sink_group)*
Default: {}
Edit: No

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busses

The Verilog bus definitions for ports or nets in the top Verilog module.
Type: obj(bus)*
Default: ""
Edit: No

constraint_modes

Returns the information about the constraint modes in the design.

Type: obj(constraint_mode)*
Default: ""
Edit: No

core_bbox

Rectangle that defines the core row area

Type: rect
Default: ""
Edit: No

core_site

The site object to use during floorplan creation

Type: obj(site)
Default: ""
Edit: No

core_to_bottom

Distance between core edge and its die/io box

Type: coord
Default: ""
Edit: No

core_to_left

Distance between core edge and its die/io box

Type: coord
Default: ""
Edit: No

core_to_right

Distance between core edge and its die/io box

Type: coord
Default: ""
Edit: No

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core_to_top

Distance between core edge and its die/io box

Type: coord
Default: ""
Edit: No

delay_corners

Returns the information about the delay corners in the design.

Type: obj(delay_corner)*
Default: ""
Edit: No

dont_touch

This attributes defines the user preservation status of the design during optimization. This
setting will apply to all insts within the design unless overridden at a lower level hinst or on the
inst object itself. The dont_touch_effective attribute on each child inst and hinst will return the
resolved value.
Use 'help inst dont_touch' to see the enum value definitions.
Type: enum
Enum Values: none false true delete_ok const_prop_size_delete_ok const_prop_delete_ok
size_delete_ok size_ok size_same_height_ok size_same_footprint_ok
Default: none
Edit: Yes

dont_touch_effective

This attribute defines the effective preservation status of the design during optimization from
the dont_touch_sources values. If the read_only source is 'true' then the effective value for the
hinst is 'true'. Otherwise, the user value has precedence.
See help on inst dont_touch attribute for details on possible values.
Type: enum
Enum Values: none false true delete_ok const_prop_size_delete_ok const_prop_delete_ok
size_delete_ok size_ok size_same_height_ok size_same_footprint_ok
Default: false
Edit: No

dont_touch_sources

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Dictionary of {source <value>} pairs contributing to the dont_touch_effective attribute for this
object :
{user <value>} {read_only <value>}
user # This hinst dont_touch value
read_only # The design is read_only (set_module_view -top_read_only true)
Type: string
Default: ""
Edit: No

dont_use_cells

List of cell names (wildcards supported) to disallow for this design during optimization. This
can be overridden at a lower hinst level. Overrides any library dont_use values.
Type: string
Default: ""
Edit: Yes

dont_use_cells_effective

The resolved list of all cell names to disallow during optimization for the design based on the
library dont_use and the dont_use_cells and use_cells attributes of this design. The
precedence is: use_cells of this hinst), then dont_use_cells of this design.
Type: string
Default: ""
Edit: No

early_clk_cell_derate_factor

Returns the derating factor for early clock paths specified through the set_timing_derate
command with the -early parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_data_cell_derate_factor

Returns the derating factorfor early paths specified through the set_timing_derate command
with the -early parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_fall_cell_check_derate_factor

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Returns the early cell check derating factor specified through the set_timing_derate command
with the -fall parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_fall_clk_cell_derate_factor

Returns the early clock path derating factor specified through the set_timing_derate command
with the -fall parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_fall_data_cell_derate_factor

Returns the early data cell check derating factor specified through the set_timing_derate
command with the -fall parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_rise_cell_check_derate_factor

Returns the early cell check derating factor specified through the set_timing_derate command
with the -rise and -cell_check parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_rise_clk_cell_derate_factor

Returns the early clock cell check derating factor specified through the set_timing_derate
command with the -rise parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_rise_data_cell_derate_factor

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Returns the early data cell check derating factor specified through the set_timing_derate
command with the -rise parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

gcell_grids

All the gcell_grid objects in the design.

Type: obj(gcell_grid)*
Default: ""
Edit: No

gcells

The gcells for the current_design. The gcells are only created after global route has occurred.
Type: obj(gcell)*
Default: ""
Edit: No

groups

List of groups
Type: obj(group)
Default: ""
Edit: No

gui_lines

All the gui_line objects in the design.

Type: obj(gui_line)*
Default: ""
Edit: No

gui_polygons

All the gui_polygon objects in the design.

Type: obj(gui_polygon)*
Default: ""
Edit: No

gui_rects

All the gui_rect objects in the design.

Type: obj(gui_rect)*
Default: ""
Edit: No

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gui_shapes

All the gui_shape objects in the design.

Type: obj(gui_rect)* obj(gui_line)*
Default: ""
Edit: No

gui_texts

All the gui_text objects in the design.

Type: obj(gui_text)*
Default: ""
Edit: No

hinsts

all hinsts inside this design

Type: obj(hinst)*
Default: ""
Edit: No

hnets

all hnets inside this design

Type: obj(hnet)*
Default: ""
Edit: No

hpins

all hpins inside this design

Type: obj(hpin)*
Default: ""
Edit: No

insts

all the logical insts inside this design. Does not include physical-insts.
Type: obj(inst)*
Default: ""
Edit: No

io_bbox

Rectangle that defines the IO area

Type: rect
Default: ""
Edit: No

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io_constraints

List of io_constrains.
Type: obj(io_constraint)*
Default: ""
Edit: No

is_clock_synthesized

Design status: Clock synthesized

Type: bool
Default: false
Edit: Yes

is_core_to_io

Indicates whether core2* attributes are measured between core edge (core_bbox) and design
boundary (box) or between core edge and io box edge (io_bbox)
Type: bool
Default: ""
Edit: No

is_detail_routed

Design status: detail routed, true if route_design was run.

Type: bool
Default: false
Edit: Yes

is_io_placed

Design status: Is IO placed

Type: bool
Default: ""
Edit: No

is_placed

Design status: Placed

Type: bool
Default: false
Edit: Yes

is_proto_model_committed

Indicates that the design has committed FlexModels

Type: bool
Default: ""
Edit: No

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is_proto_model_specified

Indicates that the design has specified FlexModels

Type: bool
Default: ""
Edit: No

is_rc_extracted

Design status: Parasitic extracted

Type: bool
Default: false
Edit: Yes

is_routed

Design status: routed. true if design has global routes from place_design/route_early_global
or detail routes from route_design.
Type: bool
Default: false
Edit: Yes

is_scan_optimized

Design status: Scan optimized

Type: bool
Default: false
Edit: Yes

late_cell_check_derate_factor

Returns the derating factor for late paths specified through the set_timing_derate command
with the -late parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_clk_cell_derate_factor

Returns the derating factor for late clock paths specified through the set_timing_derate
command with the -late parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_data_cell_derate_factor

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Returns the derating factor for late data paths specified through the set_timing_derate
command with the -late parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_cell_check_derate_factor

Returns the late cell check derating factor specified through the set_timing_derate command
with the -fall parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_clk_cell_derate_factor

Returns the late clock cell check derating factor specified through the set_timing_derate
command with the -fall parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_data_cell_derate_factor

Returns the late data cell check derating factor specified through the set_timing_derate
command with the -fall parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_cell_check_derate_factor

Returns the late cell check derating factor specified through the set_timing_derate command
with the -rise parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_clk_cell_derate_factor

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Returns the late clock cell check derating factor specified through the set_timing_derate
command with the -rise parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_data_cell_derate_factor

Returns the late data cell check derating factor specified through the set_timing_derate
command with the -rise parameter.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

local_hinsts

List of hinsts in the current level of this design (e.g. from inside the design looking down at the
hinsts at this level)
Type: obj(hinst)*
Default: ""
Edit: No

local_hnets

List of hnets in the current level of this design (e.g. from inside the design looking down at the
hnets at this level)
Type: obj(hnet)*
Default: ""
Edit: No

local_hpins

List of hpins in the current level of this design (e.g. from inside the design looking down at the
hpins of hinsts at this level)
Type: obj(hpin)*
Default: ""
Edit: No

local_insts

List of insts in the current level of this design (e.g. from inside the design looking down at the
insts at this level)
Type: obj(inst)*
Default: ""
Edit: No

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local_pins

List of pins in the current level of this design (e.g. from inside the design looking down at the
pins of the insts at this level)
Type: obj(pin)*
Default: ""
Edit: No

markers

All the marker objects in the design.

Type: obj(marker)*
Default: ""
Edit: No

modules

all modules inside this design

Type: obj(module)*
Default: ""
Edit: No

name

Name of cell
Type: string
Default: ""
Edit: No

net_groups

List of net groups

Type: obj(net_group)*
Default: ""
Edit: No

nets

All the nets inside this design, including logical Verilog nets, physical-only nets, Verilog
supply0/supply1, and Verilog 1'b0/1'b1 nets.
Type: obj(net)*
Default: ""
Edit: No

num_core_rows

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Number of rows within the core area

Type: int
Default: ""
Edit: No

num_insts

Number of instances in the cell

Type: int
Default: ""
Edit: No

num_nets

Number of canonical (flat) nets in the cell

Type: int
Default: ""
Edit: No

num_pg_nets

Number of physical nets in the cell

Type: int
Default: ""
Edit: No

num_phys_insts

Number of physical instances in the cell

Type: int
Default: ""
Edit: No

oa_design_lib

Library name for the design in OpenAccess cellview

Type: string
Default: ""
Edit: No

oa_design_view

View name for the design in OpenAccess cellview

Type: string
Default: ""
Edit: No

obj_type

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The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (design)
Default: ""
Edit: No

package_components

List of other chips in the package

Type: obj(package_component)*
Default: ""
Edit: No

package_objects

List of objects in the package

Type: obj(package_object)*
Default: ""
Edit: No

partitions

all partitions inside this design

Type: obj(partition)*
Default: ""
Edit: No

pg_nets

List of power ground nets in the design. This include physical-only PG nets, and Verilog
supply0/supply1 nets. Note that Verilog nets assigned to 1'b0/1'b1 are returned by the nets
attribute, not the pg_nets attribute.
Type: obj(net)*
Default: ""
Edit: No

pg_pins

All PG pins inside this design.

Type: obj(pg_pin)*
Default: ""
Edit: No

pg_ports

List of power/ground terminals in the cell

Type: obj(port)*
Default: ""
Edit: No

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phys_insts

List of physical instances in the cell

Type: obj(inst)*
Default: ""
Edit: No

phys_ports

List of physical (unused) signal terminals in the cell

Type: obj(port)*
Default: ""
Edit: No

pin_blockages

List of partition pin blockage objects

Type: obj(pin_blockage)*
Default: ""
Edit: No

pin_groups

List of all the pin groups

Type: obj(pin_group)*
Default: ""
Edit: No

pin_guides

List of all the pin guide object

Type: obj(pin_guide)*
Default: ""
Edit: No

pin_to_corner_tracks

List of distance constraints (in tracks) of pins from design/partition corners where the lower left
corner is listed first and the remaining corners are listed in clockwise order.
Type: string*
Default: ""
Edit: No

pins

Short-cut for [get_db current_design .pins]

Type: obj(pin)*
Default: ""
Edit: No

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place_blockages

List of placement blockages.

Type: obj(place_blockage)*
Default: ""
Edit: No

port_shapes

These are all the individual physical_pin shapes of the top-level ports including signal and PG
ports.
Type: obj(port_shape)*
Default: ""
Edit: No

ports

ports of design. Does not include pg_ports, unless PG port is explicitly in the Verilog netlist.
Type: obj(port)*
Default: ""
Edit: No

power_domains

List of power domains (pd) in the design

Type: obj(power_domain)*
Default: ""
Edit: No

power_modes

List of the power mode names in the design.

Type: string
Default: ""
Edit: No

read_db_design_name

The design name of the restored design.

Type: string
Default: ""
Edit: No

read_db_tool_name

The tool name save the restored design in current session.

Type: string
Default: ""
Edit: No

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read_db_tool_version

The tool version number save the restored design in current session.
Type: string
Default: ""
Edit: No

read_only

This attribute is set by set_module_view to identify if the top_level is read only or not. It means
the partition cannot be optimized, and cells inside will not be moved. Setting this attribute will
set the dont_touch_effective attribute on all insts and hinsts within the top level partition unless
overridden at a lower level partition. It cannot be overridden by other hinst or inst values.
Supported values:
false: The top level is allowed to be optimized.
true: The top level is read_only.
none: No constraint.
Type: enum
Enum Values: none false true
Default: none
Edit: No

resize_blockages

List of resize_blockage objects

Type: obj(resize_blockage)*
Default: ""
Edit: No

route_blockages

List of routing blockages

Type: obj(route_blockage)*
Default: ""
Edit: No

route_halo_bottom_layer

The bottom layer for which routing halo will be created

Type: obj(layer)
Default: ""
Edit: No

route_halo_to_boundary

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Database Objects--design

Specifies routing halo inside the design boundary (honored by the signal router). Only positive
values are used and indicate the halo is inside of the design boundary.
Type: coord
Default: no_value
Edit: Yes

route_halo_top_layer

The top layer for which routing halo will be created

Type: obj(layer)
Default: ""
Edit: No

row_flip

Specification of floorplan row creation, none = no flipping; first = first row is flipped, other rows
alternate; second = first row is not flipped, other rows alternate
Type: enum
Enum Values: none second first
Default: ""
Edit: No

row_spacing

Specification of the floorplan row spacing

Type: coord
Default: no_value
Edit: Yes

row_spacing_type

Indicates whether the rowSpacing is applied between each row (1) or between each pair of
rows (2)
Type: enum
Enum Values: 0 1 2
Default: ""
Edit: Yes

rows

List of rows
Type: obj(row)*
Default: ""
Edit: No

setup_views

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Database Objects--design

Returns the information about the setup analysis views in the design.
Type: obj(analysis_view)*
Default: ""
Edit: No

symmetry

The allowed orientations for this design. This value only affects the SYMMETRY value written
out by write_lef_abstract. none means r0 only (no SYMMETRY statement), x means ok to flip
about X axis (SYMMETRY X), y means ok to flip about Y axis (SYMMETRY Y), xy means ok
to flip about X or Y axis (SYMMETRY X Y), any means all orientations are allowed
(SYMMETRY X Y R90). Modifications are not saved and are only valid for the current session.
Type: enum
Enum Values: none x y xy any
Default: any
Edit: Yes

texts

All the text objects in the design.

Type: obj(text)*
Default: ""
Edit: No

top_sdps

List of all top level structured data path (sdp) objects.

Type: obj(sdp)*
Default: ""
Edit: No

track_patterns

All the track_pattern objects in the design.

Type: obj(track_pattern)*
Default: ""
Edit: No

trim_grids

All the trim_grid objects in the design from the LEF TRIMMETALTRACK statement.
Type: obj(trim_grid)*
Default: ""
Edit: No

use_cells

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Database Objects--flexible_htree

List of cell names to allow for this design during optimization. This can be overridden at a
lower hinst level. All lib_cells of each base_cell will be allowed. Overrides cells in the
dont_use_cells list and any library dont_use values.
Type: string
Default: ""
Edit: Yes

write_lec_dft_constraints

This attribute is a TCL dict and holds the LEC dft pin constraints from the last LEC run by
Genus. It is passed forward through write_design. The write_do_lec command will
automatically include this constraints in the do file.
Type: string
Default: ""
Edit: Yes

write_lec_directory_naming_style

The directory name where 'write_do_lec' will write verification files when the 'write_lec_files'
attribute is 'true'. The directory will be created if it does not already exist, and will overwrite an
existing directory of the same name. A %s in the string is replaced with the design name (e.g.
it will overwrite the directory for the same design but not for a different design). A %d in the
string is replaced with a unique integer to avoid overwriting any existing directory.
Type: string
Default: fv/invs/%s
Edit: Yes

flexible_htree

Parent Objects
pin, root

Definition
flexible htree

Attribute Description

cts_flexible_htree_adjust_sink_grid_for_aspect_ratio

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Database Objects--flexible_htree

If true adjust the sink grid for the aspect ratio of the sink grid box.
Valid values: boolean
Type: bool
Default: true
Edit: Yes

cts_flexible_htree_final_cell

The library cell to use for the H-tree sinks.

Valid values: string
Type: string
Default: ""
Edit: Yes

cts_flexible_htree_hv_balance

Specifies whether horizontal and vertical wires can only be balanced against other wires of
the same orientation (true), or whether any wire can be balanced against any other wire
(false).
Valid values: true false
Type: bool
Default: true
Edit: Yes

cts_flexible_htree_image_directory

Name of the directory to which images generated by the H-tree synthesis algorithm are written.
Valid values: string
Color coding of images:
White Unobstructed edges of the synthesis grid
Red Grid points that are blocked for trunk cell placement in all modules
Orange Grid points that are blocked for final cell placement in all modules
Red orange Grid points that are blocked for trunk and final cell placement in all modules
Yellow circle The grid point of the source
Yellow points Candidate grid points of H-tree sinks
Yellow rectangle The sink area containing target grid point candidates of H-sinks, adjusted to
the synthesis grid
Brown If specified, the sink grid box adjusted to the synthesis grid
Green/blue The edges of the synthesized H-tree
Purple H-tree repeaters
Type: string
Default: ""
Edit: Yes

cts_flexible_htree_inverting

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Database Objects--flexible_htree

Specifies whether the flexible H-tree will invert its input.

Valid values: boolean
Type: bool
Default: false
Edit: Yes

cts_flexible_htree_layer_density

The assumed layer density used to compute the parasitics for timing estimates of H-tree nets
during H-tree synthesis based on the non default rule for top nets.
Valid values: Any float in the range 0 to 1.
Type: double
Default: 1
Edit: Yes

cts_flexible_htree_max_driver_distance

If specified, ignore DRVs and use the given value as the maximum length of the nets
connecting H-tree drivers.
Valid values: float
Type: string
Default: auto
Edit: Yes

cts_flexible_htree_max_root_distance

If specified, ignore DRVs and use the given value as the maximum length of the net
connecting the root and the first driver of the H-tree. This value overrides the attribute
cts_max_driver_distance of this net and can only be specified if -max_driver_distance is also
specified.
Valid values: float
Type: string
Default: auto
Edit: Yes

cts_flexible_htree_mode

The driver insertion mode for the H-tree.

If set to 'drv', the algorithm inserts drivers to avoid DRVs. It also minimizes the insertion delay
of the H-tree if the power weight is less than 1.0.
If set to 'distance', the attributes 'cts_max_driver_distance' and 'cts_max_root_distance'
determine the maximum net lengths allowed. Transitions and delays are not computed in this
case.
Valid values: drv distance
Type: string
Default: drv
Edit: Yes

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Database Objects--flexible_htree

cts_flexible_htree_omit_symmetry

Controls the omission of symmetry features to balance a flexible H-tree.

Symmetry drivers are drivers that are added to balance pin capacitances at branch points.
For example, if buffer pairs are inserted at branch points, one of these buffers may not drive
any fanout and is inserted to match other buffer pairs at the same level of the flexible H-tree.
Omitting symmetry drivers can reduce the power of the H-tree but increase its skew.
Similarly, symmetry branches are branches that are needed to balance the wire load at
branch points. They are added to match other branchpoints at the same level of the flexible H-
tree.
By default, symmetry branches and drivers are added.
Possible values for this attribute:
false Add symmetry branches and drivers
true Omit both symmetry drivers and branches
drivers Omit symmetry drivers
branches Omit symmetry branches
{drivers branches} Omit both symmetry drivers and branches
{} Add symmetry branches and drivers
Type: string
Default: auto
Edit: Yes

cts_flexible_htree_partition_boundary_inverting

Specifies whether the clock phase is inverting with regard to the root pin when entering
partitions.
Valid values: boolean
Type: bool
Default: false
Edit: Yes

cts_flexible_htree_partition_groups

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Database Objects--flexible_htree

The groups in which partition are clustered in channelless designs. Nested lists imply allowed
crossings between groups. Each group has zero or one input port and each partition must only
be specified once.
Optionally, a maximum pre-route net length from the boundary of a partition group can be
specified. This argument must be specified as the second parameter of a nested partition
group.
Optionally, the next argument specifies the clock phase when entering the partition group in
relation to the root pin of the H-tree. Allowed values are 'inverting' and 'non-inverting'. If no
value is specified, the clock phase is unconstrained. The clock phase is unconstrained when
crossing the boundaries of partitions within the same group. All specified clock phases must
be either inverting or non-inverting.
Example:
{{A} {{C D} 50 non_inverting {{E F}} {{G}}}}
- The H-tree starts in partition A and descends into group C/D.
- From partition group C/D, the tree descends into groups E/F and G.
- Any clustering of sinks inside the C/D and E/F groups are allowed, potentially crossing
internal partition boundaries several times.
- Partition A has no clock input port and one clock output port
- Partition group C/D has one clock input port and two clock output ports
- Partition group E/F and G have one clock input port and no clock output port
- The maximum net length from the entry point into partition group C/D is 50um (pre-route)
- The clock phase is non-inverting when entering partition group C/D. The clock phase is
unconstrained when entering other partition groups.
Valid values: string
Type: string
Default: ""
Edit: Yes

cts_flexible_htree_power_weight

The power versus insertion delay trade-off. The value specifies the weight that is put on the
optimization of power related attributes , in particular the number of repeaters in the H-tree,
during the synthesis of a flexible H-tree.
Valid values: Any float in the range 0 to 1.
Type: double
Default: 1
Edit: Yes

cts_flexible_htree_root

The pin under which the H-tree is created. This pin must be part of a clock tree at the time of
synthesis.
Valid values: pin
Type: string
Default: ""
Edit: Yes

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cts_flexible_htree_sink_grid

Specifies the columns and rows of a grid of H-tree sinks, where the columns and rows may be
swapped if the cts_flexible_htree_adjust_sink_grid_for_aspect_ratio attribute is true.
Valid values: {columns rows}
Type: string
Default: ""
Edit: Yes

cts_flexible_htree_sink_grid_box

The box describing the area that the grid of H-tree sinks should cover. This attribute only has
an effect if the cts_flexible_htree_sink_grid attribute of the flexible H-tree is set.
Valid values: {xmin ymin xmax ymax}
Type: string
Default: ""
Edit: Yes

cts_flexible_htree_sink_grid_exclusion_areas

Boxes describing zones that should not be covered by the grid of H-tree sinks. This attribute
only has an effect if the cts_flexible_htree_sink_grid attribute of the flexible H-tree is set.
Valid values: list {xmin ymin xmax ymax}
Type: string
Default: ""
Edit: Yes

cts_flexible_htree_sink_grid_sink_area

The approximate size of the rectangle describing valid locations for final cells (given by -
final_cell) per H-tree sink in the grid. This attribute only has an effect if the
cts_flexible_htree_sink_grid attribute of the flexible H-tree is set.
Valid values: {width height}
Type: string
Default: ""
Edit: Yes

cts_flexible_htree_sink_instance_prefix

Prefix used for instance names of final cells (given by -final_cell). The name of the cell will be
<prefix>_<htree_name>_<id>, where id is a running index.
Valid values: string
Type: string
Default: ""
Edit: Yes

cts_flexible_htree_sinks

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Database Objects--flexible_htree

Specifies H-tree sinks as approximate rectangular areas for locations of final cells (given by -
final_cell) or pins to wire to.
Valid values: list {pin | {xmin ymin xmax ymax}}
Type: string
Default: ""
Edit: Yes

cts_flexible_htree_stop_at_sdc_clock_roots

If specified, stop searching for parts of the clock tree through SDC clock roots when defining
generated clock trees for H-tree sinks.
Type: bool
Default: false
Edit: Yes

cts_flexible_htree_trunk_cell

The library cell to use inside the H-tree.

Valid values: string
Type: string
Default: ""
Edit: Yes

insts

instances in the clock tree

Type: obj(inst)*
Default: ""
Edit: No

name

name of flexible_htree
Type: string
Default: ""
Edit: No

nets

nets in the clock tree

Type: obj(net)*
Default: ""
Edit: No

obj_type

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Database Objects--flow

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (flexible_htree)
Default: ""
Edit: No

flow

Parent Objects
root

Definition
flow

Attribute Description

end_steps

List of steps for the flow

Type: string
Default: ""
Edit: Yes

feature_values

Feature values for instances of this flow.

Type: string
Default: ""
Edit: Yes

features

Features defined for this flow.

Type: string
Default: ""
Edit: Yes

name

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Database Objects--flow

The name of the flow

Type: string
Default: ""
Edit: Yes

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (flow)
Default: ""
Edit: No

owner

Owner of this flow

Type: string
Default: ""
Edit: Yes

run_count

Number of times this flow has been run.

Type: string
Default: 0
Edit: Yes

skip_metric

Do not create a metric snapshot for the flow

Type: bool
Default: false
Edit: Yes

start_steps

List of steps for the flow

Type: string
Default: ""
Edit: Yes

steps

List of steps for the flow

Type: string
Default: ""
Edit: Yes

tool

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Database Objects--flow_step

The tool to run this flow

Type: string
Default: ""
Edit: Yes

tool_options

The tool options for the tool for this flow

Type: string
Default: ""
Edit: Yes

flow_step

Parent Objects
root

Definition
flow step

Attribute Description

begin_tcl

The Tcl body to run at the start of the step

Type: string
Default: ""
Edit: Yes

body_tcl

The Tcl body of the step. The initial value for this attribute is provided by the create_flow_step
command.
Type: string
Default: ""
Edit: Yes

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Metric categories to calculate for this flow step.

Type: string
Default: ""
Edit: Yes

check_tcl

A block of Tcl to run to perform step-specific static checks.

Type: string
Default: ""
Edit: Yes

end_steps

A list of flows or flow_steps that will be run at the end of this step.
Type: string
Default: ""
Edit: Yes

end_tcl

The Tcl body to run at the end of the step.

Type: string
Default: ""
Edit: Yes

exclude_time_metric

Do not include cpu and wall time of this step in any parent steps
Type: bool
Default: false
Edit: Yes

feature_values

Feature values for instances of this flow step.

Type: string
Default: ""
Edit: Yes

features

Features defined for this flow step.

Type: string
Default: ""
Edit: Yes

name

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Database Objects--flow_step

The name of the step

Type: string
Default: ""
Edit: Yes

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (flow_step)
Default: ""
Edit: No

owner

Owner of this step.

Type: string
Default: ""
Edit: Yes

run_count

An integer indicating how many times the step has been run. The value is initially zero, so it
may be used as a Boolean indicating that the step has been run at all.
Type: int
Default: no_value
Edit: Yes

skip_db

Do not auto-save a db at the end of this step

Type: bool
Default: true
Edit: Yes

skip_metric

Do not auto-save a db at the end of this step

Type: bool
Default: false
Edit: Yes

start_steps

A list of flows or flow_steps that will be run at the start of this step.
Type: string
Default: ""
Edit: Yes

status

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Database Objects--foreign_cell

Flow step status

Type: string
Default: ""
Edit: Yes

foreign_cell

Parent Objects
base_cell, root

Definition
LEF MACRO FOREIGN information

Attribute Description

name

Name of the foreign cell (can be the same as the master if only a shift/offset is required)
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (foreign_cell)
Default: ""
Edit: No

orient

Orientation of the foreign cell (non-R0 values are only allowed if the cell name is different from
the master cell)
Type: enum
Enum Values: r0 r90 r180 r270 mx mx90 my my90
Default: ""
Edit: No

point

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Database Objects--gcell_grid

Location (offset) of the foreign cell

Type: point
Default: ""
Edit: No

gcell_grid

Parent Objects
design, root

Definition
Equivalent to DEF GCELLGRID statements

Attribute Description

direction

Specifies the location and direction of the first grid defined. x indicates vertical lines; y
indicates horizontal lines.
Type: enum
Enum Values: y x
Default: ""
Edit: No

num_grids

Specifies the number of grid lines to create (number of rows or columns is numGrids-1)
Type: int
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (gcell_grid)
Default: ""
Edit: No

start

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Database Objects--group

Specifies the coordinate of the first line

Type: coord
Default: ""
Edit: No

step

Specifies the spacing between the grids

Type: coord
Default: ""
Edit: No

group

Parent Objects
hinst, inst, design, power_domain, root,

Definition
group of hinsts, insts, or groups

Attribute Description

area

Area of the group as defined by the LEF MACRO SIZE or OVERLAP information
Type: area
Default: ""
Edit: No

constraint_type

Constraint type for the group

Type: enum
Enum Values: guide region fence cluster none
Default: ""
Edit: Yes

density

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Database Objects--group

Group density (legal range: 0.0-1.0)

Type: double
Default: no_value
Edit: Yes

exclusive_group_gap

This is the gap should be maintained between exclusive_groups (per safety island groups).
The value is measured in microns. It can be set by command create_exclusive_groups -gap. It
is only valid when the group's constraint_type is region or fence.
Type: coord
Default: 5
Edit: Yes

exclusive_groups

This attribute specifies a list of groups that are exclusive of this group. It can be used to
implement safety islands in automotive application designs.
Type: string
Default: ""
Edit: Yes

is_floating

Only affects groups with .constraint_type = fence or region. If true, the global placer can move
the fence or region. The .rects value must also be set, and is currently restricted to a single
rect. The global placer will not change the size of the rect, but may move it.
Type: bool
Default: false
Edit: Yes

members

List of group's members

Type: obj(hinst)* obj(inst)* obj(group)*
Default: ""
Edit: No

name

Name of group
Type: string
Default: ""
Edit: No

obj_type

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Database Objects--gui_line

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (group)
Default: ""
Edit: No

parent

The parent group if is a sub-group

Type: obj(group)
Default: ""
Edit: No

power_domain

The Power Domain (if group is a power domain)

Type: obj(power_domain)
Default: ""
Edit: No

rects

List of non-overlapping rectangles that defines the shape of the group

Type: rect*
Default: ""
Edit: Yes

gui_line

Parent Objects
design, root

Definition
A line that can be displayed on the GUI, and is not output to DEF.

Attribute Description

arrow

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Database Objects--gui_polygon

Draw arrow in the middle of the line with direction from start point to end point.
Type: bool
Default: ""
Edit: No

gui_layer_name

Normally a GUI-only layer name that is not a tech-file layer. If the name is the same as a tech-
file layer, it will be drawn on the GUI with other shapes on that layer, but it will not be output to
DEF.
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (gui_line)
Default: ""
Edit: No

pixel_width

Number of pixels in the border of the object.

Type: int
Default: ""
Edit: No

points

2 points for line

Type: point*
Default: ""
Edit: No

gui_polygon

Parent Objects
design, root

Definition
The polygon shape that can be displayed on the GUI, and is not output to DEF.

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Database Objects--gui_rect

Attribute Description

gui_layer_name

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (gui_polygon)
Default: ""
Edit: No

pixel_width

Number of pixels in the border of the object.

Type: int
Default: ""
Edit: No

points

point list for poly

Type: point*
Default: ""
Edit: No

gui_rect

Parent Objects
design, root

Definition
A rect that can be displayed on the GUI, and is not output to DEF.

Attribute Description

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Database Objects--gui_text

gui_layer_name

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (gui_rect)
Default: ""
Edit: No

pixel_width

Number of pixels in the border of the object.

Type: int
Default: ""
Edit: No

rect

Rectangle that defines the gui_rect shape.

Type: rect
Default: ""
Edit: No

gui_text

Parent Objects
design, root

Definition
A text that can be displayed on the GUI, and is not output to DEF.

Attribute Description

gui_layer_name

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Database Objects--hinst

GUI layer name

Type: string
Default: ""
Edit: No

height

Text height
Type: coord
Default: ""
Edit: No

label

Text string
Type: string
Default: ""
Edit: No

location

Text location (lower left)

Type: point
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (gui_text)
Default: ""
Edit: No

hinst

Parent Objects
partition, inst, module, design, hpin, boundary, root, group, hport

Definition
Hierarchical instance

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Database Objects--hinst

Attribute Description

area

The area of all the insts contained inside this hinst and below it.
Type: area
Default: ""
Edit: No

base_name

The name at the base of a hierarchical name. So the base_name of i1/i2/i3 is i3.
Type: string
Default: ""
Edit: No

bbox

Bounding box of all the insts inside this hinst.

Type: rect
Default: ""
Edit: No

boundary

The placement boundary (e.g. fence, region, group, cluster) for this hinst if it exists.
Type: obj(boundary)
Default: ""
Edit: No

dont_touch

This attributes defines the user preservation status of the hinst during optimization. Setting this
attribute will set the dont_touch attribute on the parent module of this hinst and all hinsts of the
same module. This setting will apply to all insts within the hinst unless overridden at a lower
level hinst or on the inst object itself. The dont_touch_effective attribute on each child inst and
hinst will return the resolved value.
Use 'help inst dont_touch' to see the enum value definitions but note that map_size_ok is
only allowed at the instance level.
Type: enum
Enum Values: none false true delete_ok const_prop_size_delete_ok const_prop_delete_ok
size_delete_ok size_ok size_same_height_ok size_same_footprint_ok
Default: none
Edit: Yes

dont_touch_effective

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Database Objects--hinst

This attribute defines the effective preservation status of this hinst during optimization from the
dont_touch_sources values. If the partition source is 'true' or the ilm source is 'true', then the
effective value for the hinst is 'true'. Otherwise, the user value has precedence. If the user
value is false, then the parent value is returned.
See help on inst dont_touch attribute for details on possible values.
Type: enum
Enum Values: none false true delete_ok const_prop_size_delete_ok const_prop_delete_ok
size_delete_ok size_ok size_same_height_ok size_same_footprint_ok
Default: false
Edit: No

dont_touch_hports

This attribute defines the user preservation status for the hports of this hinst during
optimization.
Supported values:
none: Unconstrained
false: Can add/remove ports
true: Cannot add/remove ports
delete_ok: Can delete ports (if they have no fanout)
add_ok: We cannot delete, or change the polarity or any hport but can add or duplicate
hports
invert_ok: We cannot delete, duplicate, or add but can change the polarity of any hport
add_invert_ok: We cannot delete any hport but can add, duplicate, and change the polarity
Type: enum
Enum Values: none false true delete_ok add_ok invert_ok add_invert_ok
Default: none
Edit: Yes

dont_touch_sources

Dictionary of {source <value>} pairs contributing to the dont_touch_effective attribute for this
object :
{user <value>} {parent <value>} {read_only_effecte <value>}
user # This hinst dont_touch value
parent # The efective dont_touch value from an hinst above (the closest hinst above that is
not false)
read_only_effective # True when this hinst is read_only because it is an ilm or
set_module_view set it or a parent partition to read_only. Local read_only value overrides
parent read_only value
Type: string
Default: ""
Edit: No

dont_use_cells

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Database Objects--hinst

List of cell names (wildcards supported) to disallow for this hinst during optimization. Setting
on an hinst sets the attribute on the module of the hinst (setting on the hinst is just for
convenience). If a cell is added to this list that is already in the .use_cells list, it will be
removed from the .use_cells list so that the lists are non-overlapping.
Type: string
Default: ""
Edit: Yes

dont_use_cells_effective

The resolved list of all cell names to disallow during optimization for this hinst, based on the
library dont_use and the dont_use_cells and use_cells attributes of this hinst or the closest
parent hinst with a non-empty list. The precedence is: union of the use_cells of this hinst (or
closest parent if empty), then dont_use_cells of this hinst (or closets parent if empty), then the
library dont_use setting. When there are multiple hinsts that share the same module, the
dont_touch_effective is calculated for the master hinst and the other (clone) hinsts inherit.
A cell C is in the don't use cell effective list for a hinst H if and only if.
(1) Walk from the hinst H up in the parent hierarchy (including H) to find the closest parent
hinst where C is referred to in use cell list or don't use cell list.
(2) If such a hinst is found and if it occurs as use cell in hinst then it is not in the effective don't
use list. If it occurs in the don't_use cell list of hinst then it is in the effective don't use list.
(3) If such a hinst is not found the library don't use determines if the cell is in the effective
don't use list or not.
Type: string
Default: ""
Edit: No

escaped_name

The full hierarchical name including escaped chars (if any). It follows DEF escaping syntax, so
bus-bit chars [], or a hierarchy char \ that is not a bus-bit or hierarchy char has a \ in front of it.
So i1/i2 is a two-level hierarchical name while i1\/i2 is single level name, and a[0] is a bus-bit,
while a\[0\] is a scalar.
Type: string
Default: ""
Edit: No

group

The parent group

Type: obj(group)
Default: ""
Edit: No

hinsts

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List of all the hinsts at the current level and below this hinst
Type: obj(hinst)*
Default: ""
Edit: No

hnets

List of all the hnets at the current level and below this hinst
Type: obj(hnet)*
Default: ""
Edit: No

hpins

List of all the hpins at the current level and below this hinst
Type: obj(hpin)*
Default: ""
Edit: No

hports

List of all the hports of this hinst (e.g. from inside the hinst looking up at the hinst boundary).
Type: obj(hport)*
Default: ""
Edit: No

ilm_inst

Specifies the inst object of this ilm when it is under unflatten view. This attribute is only valid
when the ilm is under flatten view.
Type: obj(inst)
Default: ""
Edit: No

insts

List of all the insts at the current level and below this hinst
Type: obj(inst)*
Default: ""
Edit: No

is_ilm

This attribute is true if the hinst is an ILM. It will affect the read_only_effective and
dont_touch_effective of this hinst and all hinsts within it, as well as the dont_touch_effective of
all insts within it. It cannot be overridden by other hinst or inst values.
Type: bool
Default: false
Edit: No

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local_hinsts

List of hinsts in the current level of this hinst (e.g. from inside the hinst looking down at the
hinsts at this level)
Type: obj(hinst)*
Default: ""
Edit: No

local_hnets

List of hnets in the current level of this hinst (e.g. from inside the hinst looking down at the
hnets at this level)
Type: obj(hnet)*
Default: ""
Edit: No

local_hpins

List of hpins in the current level of this hinst (e.g. from inside the hinst looking down at the
hpins of hinsts at this level)
Type: obj(hpin)*
Default: ""
Edit: No

local_insts

List of insts in the current level of this hinst (e.g. from inside the hinst looking down at the insts
at this level)
Type: obj(inst)*
Default: ""
Edit: No

local_pins

List of pins in the current level of this hinst (e.g. from inside the hinst looking down at the pins
of the insts at this level)
Type: obj(pin)*
Default: ""
Edit: No

module

The module cell that corresponds to the hInst

Type: obj(module)
Default: ""
Edit: No

name

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The same as .escaped_name without any \ escape chars. This name is commonly used to
avoid problems with \ escape chars in Tcl scripts unless you carefully use list operators. Like
SDC commands, 'get_db insts i1/i2' will first try to match i1/i2, and if not found then match i1\/i2
so that flattening hierarchical names (e.g. with ungroup) does not require changing the names
in Tcl scripts.
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (hinst)
Default: ""
Edit: No

parent

The parent of the hinst, which is either another hinst, or the design object.
Type: obj(hinst)* obj(design)*
Default: ""
Edit: No

partition

The partition of hInst

Type: obj(partition)
Default: ""
Edit: No

power_domain

Power domain of the hierarchical inst if in a group

Type: obj(power_domain)
Default: ""
Edit: No

power_dynamic

The sum of the power_dynamic value for all the insts inside this hinst. A value of no_value is
treated as 0.
Type: double
Default: ""
Edit: No

power_internal

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The sum of the power_internal value for all the insts inside this hinst. A value of no_value is
treated as 0.
Type: double
Default: ""
Edit: No

power_leakage

The sum of the power_leakage value for all the insts inside this hinst. A value of no_value is
treated as 0.
Type: double
Default: ""
Edit: No

power_switching

The sum of the power_switching value for all the insts inside this hinst. A value of no_value is
treated as 0.
Type: double
Default: ""
Edit: No

power_toggle_rate

The average of the power_toggle_rate value for all the insts inside this <hinst/design>. A
value of no_value is treated as 0
Type: double
Default: ""
Edit: No

power_total

The sum of the power_total value for all the insts inside this hinst. A value of no_value is
treated as 0.
Type: double
Default: ""
Edit: No

read_only

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This attribute is true if the hinst is a read_only. This is set by the set_module_view command.
When true, this hinst cannot be optimized and cells inside will not be moved. This attribute will
affect the dont_touch_effective and place_status_effective attributes on all insts and hinsts
within this hinst. It cannot be overridden by other hinst or inst values.
Supported values:
false: This hinst is allowed to be optimized
true: The hinst read_only due to partition or ILM status
none: No constraint.
Type: enum
Enum Values: none false true
Default: none
Edit: No

read_only_effective

This attribute defines the read_only status of this hinst. This can be true when the local
.read_only attribute is true or if a parent .read_only attribute is true. The hinst cannot be
optimized and cells inside will not be moved.
Supported values:
false: This hinst is allowed to be optimized
true: The hinst read_only due to local or parent read_only partition
Type: bool
Default: false
Edit: No

use_cells

List of base_cell names to allow for this hinst during optimization. Setting on an hinst sets the
attribute on the module of the hinst (setting on the hinst is just for convenience). All lib_cells of
each base_cell will be allowed. If a cell is added to this list that is already in the
.dont_use_cells list, it will be removed from the .dont_use_cells list so that the lists are non-
overlapping.
Type: string
Default: ""
Edit: Yes

hnet

Parent Objects
hinst, design, hpin, pin, net, root, hport, pg_pin, port

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Definition
Hierarchical net

Attribute Description

base_name

The name at the base of a hierarchical name. So the base_name of i1/i2/i3 is i3.
Type: string
Default: ""
Edit: No

constant

Returns if this hnet has a constant logic value in the Verilog (supply0/supply1 or assigned
1'b0/1'b1). If it is no_constant, and it is connected to a net, you must check the net .constant
value to see if the net is constant for other reasons. A supply0/1 hnet will cause its net to have
.use = power or ground.
Type: enum
Enum Values: 0 1 no_constant
Default: ""
Edit: No

dont_touch

This attribute defines the preservation status of an hnet during optimization. Setting this will
preserve all connections on the hnet at the level of hierarchy where the hnet exists (i.e. will
stop at the hpins and hports connected to this hnet).
Supported values:
false: Unconstrained
true: Cannot touch
delete_ok: Can delete (if net has no sinks)
Type: enum
Enum Values: false true delete_ok
Default: false
Edit: Yes

drivers

local to this hinst: pins, hpins that are output or bider, and hports. Ports that are input or bidir
Type: obj(pin)* obj(hpin)* obj(port)* obj(hport)*
Default: ""
Edit: No

escaped_name

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loads

local to this hinst: pins, hpins that are input or bider, and hports. Ports that are output or bidir
Type: obj(pin)* obj(hpin)* obj(port)* obj(hport)*
Default: ""
Edit: No

name

net

canonical (flat) net associated with the hierarchical net

Type: obj(net)
Default: ""
Edit: No

num_drivers

number of local drivers

Type: int
Default: ""
Edit: No

num_loads

number of local loads

Type: int
Default: ""
Edit: No

obj_type

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The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (hnet)
Default: ""
Edit: No

hpin

Parent Objects
arc, partition, hinst, design, hnet, clock, root, hport

Definition
Hierarchical instance pin

Attribute Description

base_name

The name at the base of a hierarchical name. So the base_name of i1/i2/i3 is i3.
Type: string
Default: ""
Edit: No

constant

Returns if this hpin has a constant logic value due to a 1'b0 or 1'b1 asserted directly on the
hpin in the Verilog. If it is no_constant, and it is connected to a net, you must check the net
.constant value to see if the net is constant for other reasons.
Type: enum
Enum Values: 0 1 no_constant
Default: ""
Edit: No

depth

Depth constraint of the hpin in microns. The edit_pin command can be used to set it. It is only
valid for partition .hpins affected by pin assignment commands.
Type: coord
Default: ""
Edit: No

direction

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Direction of pin.
Type: enum
Enum Values: internal in out inout
Default: ""
Edit: No

dont_touch

The preservation status of an hpin during optimization. A preserved hpin means the logical
function of the hpin must be preserved to maintain a simulation or test-point hpin in the netlist.
However, the name does not need to be preserved.
Supported values:
false: Unconstrained
true: Cannot add/remove ports
delete_ok: Can delete ports (if they have no fanout)
add_ok: We cannot delete, or change the polarity or any hport but can add or duplicate
hports
invert_ok: We cannot delete, duplicate, or add but can change the polarity of any hport
add_invert_ok: We cannot delete any hport but can add, duplicate, and change the polarity
none: No user setting; will inherit from the module/hinst
Type: enum
Enum Values: none false true delete_ok add_ok invert_ok add_invert_ok
Default: none
Edit: Yes

dont_touch_effective

This attribute defines the effective preservation status of an hpin during optimization based on
the .dont_touch_sources. If the local hpin .dont_touch is not "none", it will be used. Otherwise,
the hinst .dont_touch_effective is used if not "none" or "false". If not, then the hinst
.dont_touch_hports is used.
Type: enum
Enum Values: none false true delete_ok add_ok invert_ok add_invert_ok
Default: false
Edit: No

dont_touch_sources

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Dictionary of {source value>} pairs contributing to the dont_touch_effective attribute for this
object : {user <value>} {power_intent <value>}
{hinst_dont_touch_hports <value>}
{hinst_dont_touch_effective}.
user # This pins dont_touch value
power_intent # Value set by committing UPF/CPF
hinst_dont_touch_effective # The hinst .dont_touch_effective value
hinst_dont_touch_hports # The hinst .dont_touch_hports value
Type: string
Default: {user none} {power_intent false}
Edit: No

escaped_name

hinst

The hinst for this hpin.

Type: obj(hinst)
Default: ""
Edit: No

hnet

The hnet connected to this hpin (above the hinst for this hpin).
Type: obj(hnet)
Default: ""
Edit: No

hport

The hport is the internal view of this hpin from inside the hinst.
Type: obj(hport)
Default: ""
Edit: No

is_boundary_duplicate

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Captures duplicated ports after boundary optimizations and attributes is used during mapping
file generation.
Type: string
Default: ""
Edit: Yes

is_boundary_feedthru

Captures feedthrough created during boundary optimization and used during mapping file
generation.
Type: bool
Default: false
Edit: Yes

is_boundary_phase_inverted

Captures phase inversion during boundary optimization and attribute is used during mapping
file generation.
Type: bool
Default: false
Edit: Yes

is_phase_inverted

Identifies the Instance for which phase is inverted during optimizations.

Type: bool
Default: false
Edit: Yes

location

Location of the hpin. The edit_pin command can be used to change a partition .hpin location.
Type: point
Default: ""
Edit: No

name

net

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The canonical (flat) net attached to this hpin.

Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (hpin)
Default: ""
Edit: No

place_status

The place_status of the hpin. This is only valid for partition .hpins affected by pin assignment
commands.
Type: enum
Enum Values: unplaced placed fixed cover
Default: ""
Edit: Yes

side

Side constraint of the hpin. The edit_pin command can be used to set this value. It is only valid
for partition .hpins affected by pin assignment commands.
Type: enum
Enum Values: north west south east up none
Default: ""
Edit: No

width

Width constraint of the hpin in microns. The edit_pin command can be used to set it. This is
only valid for partition .hpins affected by pin assignment commands.
Type: coord
Default: ""
Edit: No

hport

Parent Objects
arc, hinst, hnet, hpin, clock, root

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Definition
hierarchical terminal

Attribute Description

base_name

The name without the leading hinst hierarchy (e.g. p3 for h1/h2/p3).
Type: string
Default: ""
Edit: No

direction

Direction of pin.
Type: enum
Enum Values: internal in out inout
Default: ""
Edit: No

escaped_name

The escaped name of the hport.

Type: string
Default: ""
Edit: No

hinst

The hinst for this hport.

Type: obj(hinst)
Default: ""
Edit: No

hnet

The hnet connected to this hport (inside the hinst of this hport).
Type: obj(hnet)
Default: ""
Edit: No

hpin

The hpin is the external view from outside the hinst for this hport.
Type: obj(hpin)
Default: ""
Edit: No

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name

The fully qualified path name of the hport (e.g. h1/h2/p3).

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (hport)
Default: ""
Edit: No

inst

Parent Objects
flexible_htree, marker, io_constraint, place_blockage, group, hinst, sdp, design, partition, clock_tree, root,
pg_pin, route_blockage, pin, inst_obs_shape

Definition
instance

Attribute Description

arcs

Returns a list of arc objects that are associated with this inst
Type: obj(arc)*
Allowed -index values: analysis_view
Default: ""
Edit: No

area

area of inst
Type: area
Default: ""
Edit: No

base_cell

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cell of inst
Type: obj(base_cell)
Default: ""
Edit: No

base_name

The name at the base of a hierarchical name. So the base_name of i1/i2/i3 is i3.
Type: string
Default: ""
Edit: No

bbox

Bounding box of the overlap rects that define the placement area used by this inst.
Type: rect
Default: ""
Edit: No

clock_gating_integrated_cell

clock_gating_integrated_cell
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

cts_cannot_clone_reasons

A list of reasons to explain why the inst could not be cloned.

This attribute will not be set if attributes cts_clone_clock_gates/cts_clone_clock_logic are
false.
The attribute returns a list of reasons why the inst cannot be cloned.
The reasons why a inst cannot be cloned can be divided into three categories:
1. The inst is marked as dont_touch
2. Reasons specific to the clock node
3. General reasons
The possible dont_touch reasons are:
dont_touch.add_port_driver Set if inst was added above an output port or below an input port
via attribute cts_add_port_driver
dont_touch.add_driver_cell Set if inst was added below the root via attribute
cts_add_driver_cell
dont_touch.clock_root Set during clock tree extraction if identified as having the root pin
dont_touch.clock_sink Set on inst if any pin is a clock sink in a clock tree
dont_touch.clock_tree_generator_path Set if nodes and wires are in clock tree generator
paths
dont_touch.clock_wire Set on inst if clock input wire is user dont_touch
dont_touch.clockgate_no_power_domain Set if clock gate / clock logic is a clocknode in a no

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clock gate / clock logic power domain

dont_touch.drives_multi_driver_net Set if inst drives wires with other drivers
dont_touch.external_skew_group_pin Set if a pin on the inst is a skew group sink, source or
ignore pin for a skew group created by the user
dont_touch.flexible_htree Set if inst was added to a flexible H-tree
dont_touch.internal_skew_group_pin Set if a pin on the inst is a skew group sink, source or
ignore pin for a skew group created by CCOpt
dont_touch.neg_edge_clock_gate Set if a clock gate gates the falling edge
dont_touch.non_flop_clock_gating Set by SetDontTouchBlackBoxGating
dont_touch.non_standard_inputs_clock_gate Set if inst is a clock gate with 'non-standard'
inputs, to avoid disconnecting them
dont_touch.observability_clock_gate Set if inst is a clock gate with an observability output pin
dont_touch.output_wire Set if inst drives a net that is dont_touch
dont_touch.placer.lock Set if inst is user locked or locked by DEF
dont_touch.power_management Set if inst is a power management inst
dont_touch.prevent_assign Set if inst is necessary to prevent an assign
dont_touch.sdc Set if constrained by SDC timing
dont_touch.sdc_path_group Set if there is an SDC path group start / endpoint on one of the
pins of this inst
dont_touch.sub_block Set if inst is in dont_touch module
dont_touch.unmergeable_composite_clock_gate Set if some of the clock gate is dont_touch
dont_touch.user Set by user
Contact Cadence Support if any of the following reasons are listed:
dont_touch.cannot_understand_clock_gate Set if clock gate not recognized
dont_touch.composite_clock_gate_enable_test_or_gate
The possible reasons specific to the clock node are:
PowerManagement Set if inst is a power management inst
PowerManagementInconsistency Set if a disconnection of the inst from the netlist would
cause a power management inconsistency
PreservedUMPB Set if clock node is a User Module Port Bit which is preserved
Contact Cadence Support if any of the following reasons are listed:
ClockGatesAlways Set if inst is clock gate, considered always dont_touch
ClockLogicAlways Set if inst is clock logic, considered always dont_touch
NodeIsRoot Set if the clock node is the clock root
NoRoot Set if the clock node has no root
RootIgnored Set if the clock root is ignored
SpineCell Set if cell is a clock spine inst and is marked as dont_touch
The possible general reasons are:
DrivesAcrossPowerDomains The inst drives across power domain boundaries
NodeHasSGConstraints The inst has user mode skew group constraints in default mode
ClockDriverCannotCloneInverter
ClockDriverCreatedByBuffLongNets Set if the inst was created by 'Buffering long nets'.
ClockDriverInverterCloningDisabled The inst is an inverter and cloning inverters is disabled.
UnclonableClockSource Set if the inst carries the -source of an SDC clock
UnclonableIODelayReference Set if the inst is associated with an I/O timing constraint
UnclonablePLLReference Set if the inst is associated with a PLL constraint
UnclonablePLLFeedback Set if the inst is analyzed as a PLL feedback

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UnclonablePLLOutput Set if the inst is analyzed as a PLL output

UnsupportedNodeType Set if the inst is not a supported type. Supported types are: clock
gate, clock logic and clock driver.
SingleOrZeroFanoutNode Set if the inst has fewer than two fanout.
Contact Cadence Support if any of the following reasons are listed:
NoCellInst
ClockLogicMultiOutputCell
InIgnoredTree
IsUnclonable
NonIntegratedClockGate
NotTreeViewNode
OutputPinCellPinNull
ClockDriverNeedToKeep
Valid values: list string
Type: string
Default: ""
Edit: Yes

cts_cannot_merge_reasons

A list of reasons to explain why the inst could not be merged.

The attribute returns a list of reasons why the inst cannot be merged. These
attributes are set on clock gates and clock logic instances.
For clock gates, the merge is driven by the enable function. If two clock gates
share the same enable function, potentially they may be merged together. The
reasons explains why potentially mergeable clock gates could not in fact be merged.
For clock logic, the merge is driven by the logical expression, or logic
function, at the clock output pin. If two clock logic express the same logic
function, at least potentially they may be merged. The reasons lists why the
potential merge could not be realized.
User configuration disabled merging:
ClockGateMergingDisabledOnTree Merging disabled: attribute
ccopt/cts_merge_clock_gates is false
ClockLogicMergingDisabledOnTree Merging disabled: attribute
ccopt/cts_merge_clock_logic is false
IsDontTouch The instance cannot be merged as it is marked dont_touch
Attributes of a clock node rendered it unmergeable:
GloballyUnique The clock node has no potential candidate with which it might merge
UniqueUnderParent There are potential merge candidates, but not on the same clock net
HasSkewGroupConstraints The instance carries a skew group source, sink or ignore pin
UndrivenEnablePins The clock gate has a floating enable input
UndrivenRetentionPins The clock gate has a floating retention input
UndrivenTestPins The clock gate has a floating test enable input
DifferentSplitOnInputs The multi-input clock logic has different skew groups at its clock inputs
SiblingsNotMergeable Could not merge because all other candidates were unmergeable
Otherwise mergeable clock nodes may have incompatibilities that prevent merging:

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DifferentSkewGroupForInputs Two clock nodes have different skew groups at their clock
inputs
DifferentSkewGroupForOutputs Two clock nodes have different skew groups at their clock
output
DifferentCellFamilies Two clock nodes belong to incompatible cell families
DifferentNumberOfInputPins Two clock nodes have different numbers of input pins
DifferentNonStandardInputs Two clock gates have non-standard* inputs which are non-
equivalent
MismatchingNonClockInputs Two clock nodes have non-clock inputs which receive non-
equivalent signals
MismatchingClockInputs Two clock nodes have clock inputs which receive non-equivalent
signals
MismatchingPowerDomains Two clock nodes are in incompatible power domains
NotLogicalClones Two clock nodes have outputs which are not logically equivalent
DifferentNumberOfParents Two clock nodes have different numbers of clock-carrying inputs
DifferentOutputPowerContext Two clock nodes have outputs with different power
domain/voltage
DifferentInputPowerContext Two clock nodes have inputs with different power
domain/voltage
IncompatibleRestrictedRegions Two clock nodes have incompatible restricted regions
DifferentAnnotations Two clock nodes have different annotations on its pins
(*) Non-standard inputs on a clock gate are inputs besides the clock, enable, test enable and
retention inputs.
Valid values: list string
Type: string
Default: ""
Edit: Yes

cts_effective_clock_halo_x

This read only attribute shows the x component of the clock halo The units are um.
The following attributes can be used to assign x direction clock halos within CCOpt:
cts_cell_halo_x
cts_cell_density
cts_cell_halo_sites
See also:
. cts_effective_clock_halo_x_source
. cts_effective_clock_halo_y_source
. cts_effective_clock_halo_y
Type: string
Default: ""
Edit: No

cts_effective_clock_halo_x_source

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This read only attribute shows which attribute defines the x component of the clock halo.
The following attributes can be used to assign x direction clock halos within CCOpt:
cts_cell_halo_x
cts_cell_density
cts_cell_halo_sites
See also:
. cts_effective_clock_halo_x
. cts_effective_clock_halo_y
. cts_effective_clock_halo_y_source
Type: string
Default: ""
Edit: No

cts_effective_clock_halo_y

This read only attribute shows the x component of the clock halo. The units are um.
The following attributes can be used to assign y direction clock halos within CCOpt:
cts_cell_halo_y
cts_adjacent_rows_legal
cts_cell_halo_rows
See also:
. cts_effective_clock_halo_x_source
. cts_effective_clock_halo_y_source
. cts_effective_clock_halo_x
Type: string
Default: ""
Edit: No

cts_effective_clock_halo_y_source

This read only attribute shows which attribute defines the y component of the clock halo.
The following attributes can be used to assign y direction clock halos within CCOpt:
cts_cell_halo_y
cts_adjacent_rows_legal
cts_cell_halo_rows
See also:
. cts_effective_clock_halo_x
. cts_effective_clock_halo_y
. cts_effective_clock_halo_x_source
Type: string
Default: ""
Edit: No

cts_node_type

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Database Objects--inst

node type of instance within cts graph

Type: string
Default: ""
Edit: No

cts_original_names

Specifies for a clockgate or clocklogic which has been merged or is a clone a list
of names from the original netlist which are equivalent to the clockgate/clocklogic.
For example:
If A and B are merged to form C then original_names for C is { A B }.
If D_clone is a clone of D then original_names for D_clone is { D }.
If E is a clone of C then original_names for E is { A B } (remembering C was a merger of A
and B).
Valid values: list string
Type: string
Default: ""
Edit: Yes

delta_temperature

temperature of the inst

Type: string
Default: ""
Edit: No

dont_invert_phase

Type: bool
Default: false
Edit: Yes

dont_merge_multibit

This attribute is denotes whether the instance can be merged during multibit optimization. This
is enabled only when the root attribute 'use_multibit_cells' is set to true.
Supported values:
true: Cannot merge
false: Can be merged
Type: bool
Default: false
Edit: Yes

dont_split_multibit

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This attribute is denotes whether the instance can be split (unmerged) during multibit
optimization. This is enabled only when the root attribute 'use_multibit_cells' is set to true.
Supported values:
true: Cannot split
false: Can be split
Type: bool
Default: false
Edit: Yes

dont_touch

This attribute defines the user preservation status of an instance during optimization.
Supported values:
none (default): Unconstrained
false: Can be mapped, sized, deleted, and constants can be propagated through it
const_prop_size_delete_ok: Can be resized or deleted and constants can be propagated
through it
const_prop_delete_ok: Can be deleted and constants can be propagated through it
size_delete_ok: Can be resized or deleted if no fanout
delete_ok: Can be deleted if it has no fanout, but cannot be resized
size_ok: Can only be resized
size_same_height_ok: Can only be resized to a cell of the same height
size_same_footprint_ok: Can only be resized to a cell of the same footprint that has exactly
the same pin shapes
map_size_ok: Can be mapped or sized (but not deleted). Applies only to sequential
instances so cannot be applied on the module or hinst object.
true: Cannot be touched
Type: enum
Enum Values: none false true delete_ok const_prop_size_delete_ok const_prop_delete_ok
size_delete_ok size_ok size_same_height_ok size_same_footprint_ok map_size_ok
Default: none
Edit: Yes

dont_touch_effective

This attribute defines the effective (most pessimistic) preservation status of an instance during
optimization based on the 'sources'.
Type: enum
Enum Values: none false true delete_ok const_prop_size_delete_ok const_prop_delete_ok
size_delete_ok size_ok size_same_height_ok size_same_footprint_ok map_size_ok
Default: ""
Edit: No

dont_touch_sources

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Database Objects--inst

Dictionary of {source <value>} pairs contributing to the dont_touch_effective attribute for this
object:
{user <value>} {lib <value>} {parent <value>} {scan <value>}
user # This inst dont_touch value
lib # The base_cell dont_touch value
parent # The effective dont_touch value from an hinst above (the closest hinst above that is
not false)
scan # Is this inst part of a scan-chain (value is either size_ok or none). There is an additional
inst attribute that holds this information.
Type: string
Default: ""
Edit: No

early_cell_check_derate_factor

Returns the derating factor on timing check values for early paths (e.g Hold checks)
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_clk_cell_derate_factor

Returns the derating factor for instances on early clock paths

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_data_cell_derate_factor

Returns the derating factor for instances on early data paths

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_fall_cell_check_derate_factor

Returns the early cell check derating factor for falling arrivals
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_fall_clk_cell_derate_factor

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Database Objects--inst

Returns the early derating factor for falling delays through clock tree instances
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_fall_data_cell_derate_factor

Returns the early derating factor for falling delays through data path instances
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_rise_cell_check_derate_factor

Returns the early cell check derating factor for rising arrivals
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_rise_clk_cell_derate_factor

Returns the early derating factor for rise delays through clock tree instances
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_rise_data_cell_derate_factor

Returns the early derating factor for rising delays through data path instances
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

escaped_name

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group

The floorplan group that contains this inst. The instances in a group will be placed close
together.
Type: obj(group)
Default: ""
Edit: No

has_lvf

Returns true if library arc(s) of libcell has LVF information

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

hierarchical_level

Returns hierarchical level for an Instance

Type: int
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_always_on

Returns true if the associated library cell is recognized as always on type cell
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_black_box

Returns a value of true if the cell is a black box cell.

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_buffer

This inst is a buffer.

Type: bool
Default: ""
Edit: No

is_clock_gating_check

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Returns true if a clock gating check is performed by this instance. The clock gating check may
be inferred from logic in netlist, asserted by SDC constraints, or may be due to this instance
being an integrated clock gating cell
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_combinational

Returns a value of true if the instance is a combinational cell (not a sequential cell).
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_disable_timing

Returns true if set_disable_timing has been set on this cell instance

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_fixed_mask

Indicates the base_cell of the inst has FIXEDMASK keyword in LEF, so mask-shifting is not
allowed, except for the layers with LAYERMASKSHIFT keyword.
Type: bool
Default: ""
Edit: No

is_flop

Returns true if the library cell is recognized as flip-flop/register type cell

Type: bool
Default: ""
Edit: No

is_genus_clock_gate

Set by the tool in the iSpatial flow to indicate that this integrated clock gating instance was
added by Genus clock gating
Type: bool
Default: false
Edit: Yes

is_inside_ilm

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This attribute denotes whether the inst is the child of a parent hinst the has an ILM specified for
it
Type: bool
Default: ""
Edit: No

is_integrated_clock_gating

Returns true if this instance's library cell has the Liberty clock_gating_integrated_cell set to
true
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_interface_timing

Returns a value of true if this instance's library cell has the Liberty interface_timing attribute set
to true
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_inverter

This inst is an inverter.

Type: bool
Default: ""
Edit: No

is_isolation

This inst is an isolation.

Type: bool
Default: ""
Edit: No

is_isolation_cell

Returns true if the associated library cell is recognized as isolation type cell
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_jtag

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The inst is a JTAG element.

Type: bool
Default: false
Edit: Yes

is_latch

Returns true if the associated library cell is recognized as latch type cell
Type: bool
Default: ""
Edit: No

is_legal

Specifies the legal status that was seen by the last place_detail or check_place.
Type: bool
Default: ""
Edit: No

is_level_shifter

Returns true if the associated library cell is recognized as level shifter type cell
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_macro

Returns a value of true if the associated library cell has the Liberty attribute is_macro_cell is
set true
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_master_slave_flop

Returns true if the Liberty clock_on_also attribute is specified for the associated library cell
Type: bool
Default: ""
Edit: No

is_master_slave_lssd_flop

Returns true if this cell has been recognized as a master/slave LSSD device
Type: bool
Default: ""
Edit: No

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is_memory

Returns true or false depending on whether the associated library cell of the inst is recognized
as a Liberty memory cell. Cells which include a Liberty memory group definition are
recognized as memory cells.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_negative_level_sensitive

Returns a value of true if the associated library cell is identified as a negative level-sensitive
latch.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_pad

Returns a value of true if the associated library cell's Liberty is_pad attribute is set to true
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_physical

is physical only of inst

Type: bool
Default: ""
Edit: No

is_place_halo

Indicates that the instance has a placement halo.

Type: bool
Default: false
Edit: Yes

is_positive_level_sensitive

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Returns a value of true if the associated library cell is identified as a positive level-sensitive
latch.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_power_switch

Returns true if the associated library cell is recognized as power switch type cell
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_retention

Returns true if the associated library cell is recognized as retention type cell
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_sequential

Returns a value of true if the library cell is a latch or flip-flop, or if the cell has sequential timing
checks.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_spare

The inst is a spare instance. These are used by post-mask ECO flows.
Type: bool
Default: false
Edit: Yes

is_tristate

Returns a value of true if the associated library cell definition includes the Liberty attribute
three_state set to true .
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

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late_cell_check_derate_factor

Returns the derating factor on timing check values for late paths (e.g Setup checks)
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_clk_cell_derate_factor

Returns the derating factor for instances on late clock paths

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_data_cell_derate_factor

Returns the derating factor for instances on late data paths

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_cell_check_derate_factor

Returns the late cell check derating factor for falling arrivals
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_clk_cell_derate_factor

Returns the late derating factor for falling delays through clock tree instances
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_data_cell_derate_factor

Returns the late derating factor for falling delays through data path instances
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_cell_check_derate_factor

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Returns the late cell check derating factor for rising arrivals
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_clk_cell_derate_factor

Returns the late derating factor for rise delays through clock tree instances
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_data_cell_derate_factor

Returns the late derating factor for rising delays through data path instances
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

leakage_power

Returns the leakage power of the instance from library cell

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

level_shifter_type

Returns the Level Shifter type for associated library cell. The supported values are LH, HL and
HL_LH.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

lib_cells

Returns a list of library cell objects associated with this instance. You can use -index to refine
this list to lib_cells associated with a specific view
Type: obj(lib_cell)*
Allowed -index values: analysis_view
Default: ""
Edit: No

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litho_halo

A litho_halo on an inst forces parallelrouting away from the block boundary to meet
lithography DRC rules on a few routing layers but allows perpendicular access to pins. It is
only allowed if LEF LITHOMACROHALO values exists for some routing layers. See the LEF
manual for figures and more details of this DRC rule. It cannot be added to standard cells
(cells with a CLASS CORE SITE).
Type: bool
Default: false
Edit: Yes

location

The location of the inst. It is always the lower-left corner of the inst bounding-box, independent
of the inst orientation.
Type: point
Default: ""
Edit: Yes

mask_shift

Digit encoded value indicates the mask shifting for the instance contents (0 = unshifted, for
other shift cases refer to the DEF COMP + MASKSHIFT documentation).
Type: string
Default: ""
Edit: Yes

name

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (inst)
Default: ""
Edit: No

orient

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Instance placement orientation.

Type: enum
Enum Values: r0 r90 r180 r270 mx mx90 my my90
Default: r0
Edit: Yes

overlap_rects

List of rectangles that define the shape of instance

Type: rect*
Default: ""
Edit: No

parent

The parent of the inst, which is either a hinst for an instance within hierarchy or the design
object for an instance at the top level.
Type: obj(design)* obj(hinst)*
Default: ""
Edit: No

partition

If this inst is a physical black_box, this partition will carry the pin constraints and related data
for the blackbox. Otherwise it is empty.
Type: obj(partition)
Default: ""
Edit: No

peak_current

Peak current value of the inst

Type: string
Default: ""
Edit: No

pg_pins

List of pg_pins for this inst. These are declared as power or ground pins in the .lib or LEF/OA
library, and separated from the signal pins of the inst.
Type: obj(pg_pin)*
Default: ""
Edit: No

pins

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The pins of this inst.

Type: obj(pin)*
Default: ""
Edit: No

place_halo_bbox

Bounding box of the inst placement halo. For a rectilinear block this might include area that is
not covered by the place halo.
Type: rect
Default: ""
Edit: No

place_halo_bottom

Specifies an extra halo of space along the bottom edges of the inst that should not be used
during placement. This area can still be used later during optimization and clock tree creation
to add repeaters. It can only be used on blocks and cannot be added to standard-cells. See
the padding attributes on the base_cell to add extra space to standard-cells.
Type: coord
Default: ""
Edit: No

place_halo_left

Specifies an extra halo of space along the left edges of the inst that should not be used during
placement. This area can still be used later during optimization and clock tree creation to add
repeaters. It can only be used on blocks and cannot be added to standard-cells. See the
padding attributes on the base_cell to add extra space to standard-cells.
Type: coord
Default: ""
Edit: No

place_halo_polygon

Specifies the polygon shape of the inst placement halo.

Type: point
Default: ""
Edit: No

place_halo_right

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Specifies an extra halo of space along the right edges of the inst that should not be used
during placement. This area can still be used later during optimization and clock tree creation
to add repeaters. It can only be used on blocks and cannot be added to standard-cells. See
the padding attributes on the base_cell to add extra space to standard-cells.
Type: coord
Default: ""
Edit: No

place_halo_top

Specifies an extra halo of space along the top edges of the inst that should not be used during
placement. This area can still be used later during optimization and clock tree creation to add
repeaters. It can only be used on blocks and cannot be added to standard-cells. See the
padding attributes on the base_cell to add extra space to standard-cells.
Type: coord
Default: ""
Edit: No

place_status

This attribute is the placement status of an instance during placement and optimization. The
placer will look at both place_status and place_status_cts and use the more restrictive value.
When this attribute is explicitly set by the user, it will reset the place_status_cts attribute so the
user intent has precedence.
Supported values:
unplaced: Unconstrained
placed: Is placed but can be moved
soft_fixed: Is fixed, but can move a short distance to legalize it
fixed: Is fixed and can only be moved by the user, will not be moved by placement or
optimization commands.
cover: Is fixed and cannot be moved by any commands, you must change the place_status
to move it.
Type: enum
Enum Values: unplaced placed fixed cover soft_fixed
Default: unplaced
Edit: Yes

place_status_cts

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Database Objects--inst

This attribute is the CTS placement status of an instance during placement and optimization.
The placer will look at both place_status and place_status_cts and use the more restrictive
value.
Supported values:
unset: Unconstrained
soft_fixed: For future use
fixed: Cannot be moved
Type: enum
Enum Values: unset fixed soft_fixed
Default: unset
Edit: Yes

place_status_effective

This attribute is the effective placement status for the instance. It is the worst case of the
instance place_status, instance place_status_cts, and hinst parent read only attribute (closest
hinst above that is not set to none). See place_status for the description of possible values.
Type: enum
Enum Values: unplaced placed fixed cover soft_fixed
Default: ""
Edit: No

power_domain

The power_domain for the inst.

Type: obj(power_domain)
Default: ""
Edit: No

power_dynamic

The switching + internal power of this inst computed by report_power.

Type: double
Default: ""
Edit: No

power_frequency_domain

signifies Frequency of the inst with which it is constrained, sdc/twf file has clock frequency
related information for the instances
Type: string
Default: ""
Edit: No

power_internal

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The internal power of this inst computed by report_power.

Type: double
Default: ""
Edit: No

power_internal_density

Internal power density of the inst which is inst power internal / inst area
Type: string
Default: ""
Edit: No

power_leakage

The leakage power of this inst computed by report_power.

Type: double
Default: ""
Edit: No

power_leakage_density

Leakage power density of the inst which is inst power leakage / inst area
Type: string
Default: ""
Edit: No

power_loading_capacitance

Loading capacitance of the inst, it signifies the output net cap + pin cap of the next instance it
is connecting to.
Type: string
Default: ""
Edit: No

power_ref_clock

The reference clock for toggle and activity calculations. By default this is the fastest clock for
multi clock domains but can be modified by some power commands.
Type: string
Default: ""
Edit: No

power_switch_type

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Returns the switch cell type associated with library cell. The supported values are
coarse_grain, fine_grain.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

power_switching

The switching power of the nets driven by this inst computed by report_power.
Type: double
Default: ""
Edit: No

power_switching_density

Switching power density of the inst which is power switching / inst area
Type: string
Default: ""
Edit: No

power_toggle_rate

The average number of toggles read from VCD,TCF,SAIF, etc. or from propagation that occur
in 1 second on all the pins of this inst. no_value is returned if it cannot be computed.
Type: double
Default: ""
Edit: No

power_total

The switching + internal + leakage power of this inst computed by report_power.

Type: double
Default: ""
Edit: No

power_total_density

Total power density of the inst which is inst power total / inst area
Type: string
Default: ""
Edit: No

rail_domain_voltage_drop

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Worst Effective drop (VDD-VSS) of the inst in elapse or timing/switching window. Values are
loaded in GUI after user loads the voltus state directory
Type: string
Default: ""
Edit: No

rail_ground_voltage_drop

Ground bounce for ground rail of the inst, Values are loaded in GUI after user loads the voltus
state directory
Type: string
Default: ""
Edit: No

rail_power_voltage_drop

Voltage drop for power rail of the inst, Values are loaded in GUI after user loads the voltus
state directory
Type: string
Default: ""
Edit: No

rail_reff

signifies equivalent resistance for the instance pin from the voltage source, values are loaded
in GUI after user load the effective resistance state directory.
Type: string
Default: ""
Edit: No

rail_rlrp

signifies least resistance path value of the inst from a voltage source to a pin of the instance,
values are loaded in GUI after user load the voltus state directory. It is enabled when
enable_rlrp_analysis option of set_rail_analysis_config is turned on
Type: string
Default: ""
Edit: No

retention_cell

Returns the retention_cell derived from Liberty

Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

route_halo_bottom_layer

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The bottom layer for the routing halo.

Type: obj(layer)
Default: ""
Edit: Yes

route_halo_polygon

Specifies the polygon shape of the inst routing halo.

Type: point
Default: ""
Edit: No

route_halo_size

Specifies the size of a routing halo around the inst. A value of 0 means there is no route_halo.
It is used to keep routes away from the block edges to reduce cross-coupling to wires inside
the block. A route_halo can only be added to blocks and is not allowed on standard-cells. The
router will only route through the halo to reach pins on the boundary of the block. The value
applies to all sides of the block and only positive values are allowed.
Type: coord
Default: no_value
Edit: Yes

route_halo_top_layer

The top layer of the routing halo.

Type: obj(layer)
Default: ""
Edit: Yes

sdp

The parent sdp group which the instance belongs to.

Type: obj(sdp)
Default: ""
Edit: No

std_cell_main_rail_name

Returns the rail name associated with pg pin for which std_cell_main_rail is enabled.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

transition_density

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Transition density of the inst

Type: string
Default: ""
Edit: No

use_cells_only

This attribute is the list of allowable cells that this instance can be resized to. Wildcards are
supported. If set, any parent (hinst) .dont_use_cells_effective values are ignored. This attribute
only applies to operations on mapped designs. The .dont_touch_effective values
size_same_height_ok and size_same_footprint_ok will filter this list further based on height
and footprint, respectively.
Type: string
Default: ""
Edit: Yes

io_constraint

Parent Objects
design, root

Definition
IO object for block (term) or chip design (inst) constraints

Attribute Description

area

Area of the instance as defined by the LEF MACRO SIZE or OVERLAP information
Type: area
Default: ""
Edit: No

bbox

Bounding box of the inst overlap rects. This is only correct if type = inst.
Type: rect
Default: ""
Edit: Yes

indent

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Indent of instance from the boundary of the design

Type: coord
Default: no_value
Edit: Yes

inst

The IO instance (null/0x0 for block design case)

Type: obj(inst)* obj(bump)*
Default: ""
Edit: No

is_assigned

Indicates that the IO location has been set by the IO placer

Type: bool
Default: false
Edit: Yes

is_corner

Indicates that the IO refers to a corner cell

Type: bool
Default: false
Edit: Yes

is_gap_fixed

Indicates that the IO spacing constraint is applied

Type: bool
Default: false
Edit: Yes

is_ground

Indicates that the IO is a Ground

Type: bool
Default: false
Edit: Yes

is_offset_fixed

Indicates that the IO offset constraint is applied

Type: bool
Default: false
Edit: Yes

is_power

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Indicates that the IO is a Power

Type: bool
Default: false
Edit: Yes

name

IO name
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (io_constraint)
Default: ""
Edit: No

offset

IO relative location from left (North & South) or bottom (East & West) die edge
Type: coord
Default: no_value
Edit: Yes

order

IO order per side. Order is left-to-right (North & South) or bottom-to-top (East & West)
Type: int
Default: ""
Edit: Yes

row

IO row/ring number (0 is outermost IO row)

Type: int
Default: 0
Edit: Yes

side

Side constraint of IO
Type: enum
Enum Values: north west south east none
Default: ""
Edit: Yes

spacing

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Spacing between IO and previous IO (left or below)

Type: coord
Default: no_value
Edit: Yes

term

The IO terminal (only used when 'type = term')

Type: obj(port)
Default: ""
Edit: Yes

type

Type of IO (endSpace indicates from last IO to corner, inst indicates real instance case, obs
indicates obstruction between IOs, term indicates block design case)
Type: string
Default: ""
Edit: No

layer

Parent Objects
marker, bump_pin, layer_shape, text, port, via_def, pin_blockage, special_wire, pg_base_pin, what_if_wire,
what_if_via, trim_grid, base_pin, partition, track_pattern, design, root, layer_rule, pin_guide, virtual_wire,
port_shape, via_def_rule, route_blockage, patch_wire, antenna_data, inst, wire, bus_guide, net, pin,
route_type, inst_obs_shape

Definition
A layer from the LEF or OA technology file.

Attribute Description

antenna_model_1

The antenna model object for Oxide1

Type: obj(antenna_model)*
Default: ""
Edit: No

antenna_model_2

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The antenna model object for Oxide2

Type: obj(antenna_model)*
Default: ""
Edit: No

antenna_model_3

The antenna model object for Oxide3

Type: obj(antenna_model)*
Default: ""
Edit: No

antenna_model_4

The antenna model object for Oxide4

Type: obj(antenna_model)*
Default: ""
Edit: No

area

Layer minimum area from LEF/OpenAccess. If AREA rule is not specified in LEF, the value of
-1 in dbu will be returned.
Type: area
Default: ""
Edit: No

backside

Indicates that the layer is a backside (underside of the die) layer.

Type: bool
Default: ""
Edit: No

backside_cut_index

An index for BACKSIDE cut layers. It is 0 for the TSV cut-layer, -1 for the BACKSIDE cut layer
between the first (.backside_route_index = -1) and second (.backside_route_index = -2)
backside routing layers below the substrate, -2 for the BACKSIDE cut layer between the
second and third backside routing layers, etc. It is 1000 for all other layers.
Type: int
Default: ""
Edit: No

backside_route_index

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An index for BACKSIDE routing layers. It is -1 for the first backside routing layer closest (just
below) the substrate (e.g. the last LEF TYPE ROUTING layer with BACKSIDE property in the
technology file), -2 for the second backside routing layer below the substrate, etc. It is 1000 for
any other layer.
Type: int
Default: ""
Edit: No

cut_index

An index into the cut layers used by vias in the routing. It is 1 for the cut-layer above the first
routing layer, 2 for the cut-layer above the second routing layer, etc. It is 0 for the cut-layer just
below the first routing layer. The cut_index is -1 for any other layer, including LEF cut layers
with TYPE MIMCAP, TSV or BACKSIDE. In OpenAccess, the cut layers are determined by
the LEFDefaultRouteSpec validVias list.
Type: int
Default: ""
Edit: No

density_step_x

Layer density window step from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

density_step_y

Layer density window step from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

density_window_x

Layer density window length from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

density_window_y

Layer density window width from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

direction

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Layer pref. direction from LEF/OpenAccess

Type: enum
Enum Values: horizontal vertical unassigned diag45 diag135
Default: ""
Edit: No

fill_active_spacing

Layer fill minimum spacing from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

fill_gap_spacing

Layer fill to fill spacing from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

max_density

Layer fill maximum density from LEF/OpenAccess

Type: double
Default: ""
Edit: No

max_width

Layer maximum wire width from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

mfg_grid

Manufacturing grid
Type: coord
Default: ""
Edit: No

min_density

Layer fill minimum density from LEF/OpenAccess

Type: double
Default: ""
Edit: No

min_spacing

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Layer minimum spacing from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

min_width

Layer minimum wire width from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

name

Layer name from LEF/OpenAccess technology file definition.

Type: string
Default: ""
Edit: No

num_masks

Indicates how many masks will be used for the layer (1 = single mask, 2 = double-patterning, 3
= triple-patterning)
Type: int
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (layer)
Default: ""
Edit: No

offset_x

Layer offset X from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

offset_y

Layer offset Y from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

pitch_x

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Layer wire pitch X from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

pitch_y

Layer wire pitch Y from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

route_index

An index into the routing layers. It is 1 for the first LEF TYPE ROUTING layer in the technology
file, 2 for the second routing layer, etc. It is 0 for the layer just below the first routing layer (e.g a
poly layer or non-routing metal layer that may have pin shapes in some cells). The
route_index is -1 for any non-routing layers, or LEF routing layers with LEF TYPE MIMCAP or
TYPE BACKSIDE. In OpenAccess, the routing layers are determined by the
LEFDefaultRouteSpec validLayers list.
Type: int
Default: ""
Edit: No

spacing_tables

A list of all the LEF spacing-table rules for this layer in the LEF SPACINGTABLE syntax. All
SPACINGTABLE and LEF58_SPACINGTABLE property values are returned.
Type: string
Default: ""
Edit: No

type

The layer type (routing, cut, etc.) from the LEF LAYER TYPE statements or OA tech for this
layer.
Type: enum
Enum Values: invalid masterslice cut overlap routing implant tsv mimcap passivation
poly_routing nwell pwell stacked_die cut_mimcap above_die_edge below_die_edge diffusion
ignore trim_poly trim_metal region cut_region routing_region trim_metal_region tsv_metal
pad_metal stacked_mimcap
Default: ""
Edit: No

width

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Layer wire width from LEF/OpenAccess

Type: coord
Default: ""
Edit: No

wrong_way_min_width

min width in the non-preferred direction (from LEF LAYER MINWIDTH WRONGDIRECTION).
A value of 0 indicates that there is no special value assigned for a wrong direction behavior.
Type: coord
Default: ""
Edit: No

wrong_way_spacing

min spacing in the non-preferred direction (from LEF LAYER SPACING

WRONGDIRECTION). A value of 0 indicates that there is no special value assigned for a
wrong direction behavior.
Type: coord
Default: ""
Edit: No

wrong_way_width

min width in the non-preferred direction (from LEF LAYER WIDTH WRONGDIRECTION). A
value of 0 indicates that there is no special value assigned for a wrong direction behavior.
Type: coord
Default: ""
Edit: No

wsp_oa_width_spacing_pattern

A list of Tcl dict style parameters that match the OA widthSpacingPattern parameters like this:
{name <string> is_from_lib <bool> offset <coord>}. The 'name' and 'offset' match the
corresponding OA parameters, and 'is_from_lib <bool>' is true if it is from the OA tech graph
and false if it is from the cellview.
Type: string
Default: ""
Edit: No

wsp_oa_width_spacing_snap_pattern_def

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A list of Tcl dict style parameters that match the OA widthSpacingSnapPatternDef parameters
like this: {name <string> is_from_lib <bool> offset <coord> offset_reference <string> wire_type
<name> purpose <name>}. The 'name', 'offset', 'wire_type', and 'purpose' match the
corresponding OA parameters. 'offset_reference' indicates whether the 'offset' is from the
lower-left corner of the boundary or the origin. 'is_from_lib <bool>' is true if it is from the OA
tech graph and false if it is from the cellview.
Type: string
Default: ""
Edit: No

wsp_offset

Offset from lower-left corner of the core box to the first track. For a horizontal routing layer
track, this is a Y offset.
Type: coord
Default: ""
Edit: No

wsp_pattern

This is set by add_tracks or by reading an OA design with widthSpacingPatterns defined. It is

a list of {width pitch repeat} values that created the tracks. For example, {1.5 2.5 1} {1.0 2.0 3}
means a track of 1.5 width, 2.5 track-to-track pitch repeated 1 time, and then a track with width
1.0, track-to-track pitch 2.0 repeated 3 times, then the full pattern repeats. If this is not an
SADP layer, there is no width assigned to the track, and a width value of 0.0 is returned. For a
horizontal routing layer, the width and pitch are Y values.
Type: string*
Default: ""
Edit: No

wsp_pattern_masks

A list of mask values for each track in the wsp_pattern after the pattern repeat sections are
expanded.
Type: int*
Default: ""
Edit: No

layer_rule

Parent Objects
route_rule

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Definition
Layer Rule

Attribute Description

layer

The layer of laye rule

Type: obj(layer)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (layer_rule)
Default: ""
Edit: No

spacing

min spacing (from NONDEFAULTRULE LAYER SPACING, LEF LAYER SPACING or

SPACINGTABLE)
Type: coord
Default: ""
Edit: No

width

wire width (from NONDEFAULTRULE LAYER WIDTH or LEF LAYER WIDTH)

Type: coord
Default: ""
Edit: No

layer_shape

Parent Objects
base_cell, physical_pin

Definition
layer shape

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Attribute Description

is_ignore_pg_net

Indicates that Power/Ground routing is ignored when checking for DRC violations (including
shorts) involving the current shape (equivalent to LEF MACRO OBS LAYER
EXCEPTPGNET)}
Type: bool
Default: ""
Edit: No

layer

The layer of blockage

Type: obj(layer)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (layer_shape)
Default: ""
Edit: No

shapes

List of shapes that define the blockage area

Type: obj(shape)*
Default: ""
Edit: No

spacing

LEF OBS SPACING equivalent min_spacing value, zero if not specified in LEF.
Type: coord
Default: ""
Edit: No

lib_arc

Parent Objects
lib_cell, arc, root, lib_pin

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Definition
cte library timing arc

Attribute Description

aocv_weight

Returns the AOCV stage weight for this library arc. By default, all library cells and library arcs
have default stage weight of 1.0. The aocv_weight property is specified as a user-defined
library attribute in the Liberty timing library explicitly - or, by asserting it via command. You can
use -index to return a value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

base_name

Returns the simple name for this library timing arc in the form:
inputPin_outputPin_uniqueIntegerSuffix
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

from_lib_pin

Returns a lib_pin object for beginning pin of this timing arc. You can use -index to return a
value for a specific view.
Type: obj(lib_pin)*
Allowed -index values: analysis_view
Default: ""
Edit: No

full_name

Returns the unique name for this library arc in the form:
librarySet/libraryName/libraryCell/inputPin_outputPin_uniqueIntegerSuffix. You can use -
index to return a value for a specific view.
Type: string
Default: ""
Edit: No

has_socv

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Returns true if library arc(s) has SOCV information

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_disabled

Returns a value of true if this library timing arc has been explicitly disabled by the user via a
set_disable_timing constraint. You can use -index to return a value for a specific view.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

lib_cell

Returns the parent library cell object for this library arc. You can use -index to return a value
for a specific view.
Type: obj(lib_cell)*
Allowed -index values: analysis_view
Default: ""
Edit: No

mode

If this timing arc is defined as part of a Liberty mode group, this attribute will return the name of
the group. You can use -index to return a value for a specific view.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

name

Returns an identifier for this library arc in the form:

libraryName/libraryCell/inputPin_outputPin_uniqueIntegerSuffix
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (lib_arc)
Default: ""
Edit: No

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sdf_cond

Returns the value of the Liberty sdf_cond attribute if specified for this arc. You can use -index
to return a value for a specific view.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

sense

Returns the Liberty timing_sense value associated with this arc. This value is one of:
positive_unate, negative_unate, or non_unate. You can use -index to return a value for a
specific view.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

timing_type

Returns the Liberty timing_type associated with this arc. You can consult the Liberty
documentation for the list of possible values for this attribute. You can use -index to return a
value for a specific view.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

to_lib_pin

Returns a lib_pin object for terminating pin of this timing arc. You can use -index to return a
value for a specific view.
Type: obj(lib_pin)*
Allowed -index values: analysis_view
Default: ""
Edit: No

when

Returns the value of the Liberty 'when' attribute if specified for this arc. You can use -index to
return a value for a specific view.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

when_end

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Returns the value of the Liberty 'when_end’ attribute if specified for this arc. You can use -
index to return a value for a specific view.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

when_library_string

Returns the exact value of the Liberty 'when' attribute if specified for this arc. You can use -
index to return a value for a specific view.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

when_start

Returns the value of the Liberty 'when_start' attribute if specified for this arc. You can use -
index to return a value for a specific view.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

lib_cell

Parent Objects
inst, base_cell, lib_arc, root, library, lib_pin

Definition
cte lib cell

Attribute Description

aocv_weight

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Returns the AOCV stage weight specified for the library cell either explicitly in the library or as
a user-defined library attribute
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

area

Returns the area of the library cell as specified by the Liberty timing library
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

async_clear_pins

Returns a list of lib_pins that have both the is_async and is_clear attributes set to true
Type: obj(lib_pin)*
Default: ""
Edit: No

async_preset_pins

Returns a list of lib_pins that have both the is_async and is_clear attributes set to true
Type: obj(lib_pin)*
Default: ""
Edit: No

base_cell

Returns a pointer the base_cell object associated with this library cell. You can use chaining
to reach the attributes of the base_cell
Type: obj(base_cell)*
Default: ""
Edit: No

base_name

The base_name of the cell.

Type: string
Default: ""
Edit: No

bit_width

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Returns the bit width of the cell

Type: int
Default: ""
Edit: No

clock_gating_integrated_cell

clock_gating_integrated_cell
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

clock_pins

Returns a list of lib_pins which have the attribute is_clock equal to true
Type: obj(lib_pin)*
Default: ""
Edit: No

data_pins

Returns a list of lib_pins which have the attribute is_data equal to true
Type: obj(lib_pin)*
Default: ""
Edit: No

early_slew_derate_factor

Returns early transition derate factor on the lib cell

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

fall_input_switching_derate_factor

Returns user or library defined value for controlling the arrival sensitivity window for
simultaneous rising inputs to this cell type
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

has_lvf

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Returns true if library arc(s) of libcell has LVF information

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

hierarchical_name

hierarchical_name
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

is_always_on

Returns a value of true if the lib_cell is identified as always on type

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_black_box

Returns a value of true if the cell is a black box cell.

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_buffer

Returns a value of true if the lib_cell is identified as a buffer type

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_combinational

Returns a value of true if the library cell is a combinational cell (not a sequential cell).
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_disable_timing

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Returns true if set_disable_timing has been set on this library cell

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_exist

Returns true if library cell present in view.

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_fall_edge_triggered

Returns a value of true if the library cell is triggered by the falling edge of the clock.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_flop

Returns true if the library cell is recognized as flip-flop/register type cell

Type: bool
Default: ""
Edit: No

is_integrated_clock_gating

Returns true if the library cell has the Liberty clock_gating_integrated_cell set to true
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_interface_timing

Returns a value of true if a library cell has the Liberty interface_timing attribute set to true
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_inverter

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Returns a value of true if the lib_cell is identified as an inverter type

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_isolation_cell

Returns a value of true if the lib_cell is identified as an isolation cell type

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_latch

Returns true if the library cell is recognized as latch type cell

Type: bool
Default: ""
Edit: No

is_level_shifter

Returns a value of true if the lib_cell is identified as a level shifter type

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_macro

Returns a value of true if the Liberty attribute is_macro_cell is set true

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_master_slave_flop

Returns true if the lib_cell is recognized as a master/slave flip-flop

Type: bool
Default: ""
Edit: No

is_master_slave_lssd_flop

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Returns true if this cell has been recognized as a master/slave LSSD device
Type: bool
Default: ""
Edit: No

is_memory

is_negative_level_sensitive

Returns a value of true if the library cell is identified as a negative level-sensitive latch.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_pad

Returns a value of true if Liberty attribute is_pad is set to true

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_pll

Returns a value of true if the Liberty library is_pll_cell attribute is set to true for this library cell.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_positive_level_sensitive

Returns a value of true if the library cell is identified as a positive level-sensitive latch.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_power_switch

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Returns a value of true if the lib_cell is identified as power switch type

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_retention

Returns a value of true if the lib_cell is identified as an retention cell type

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_rise_edge_triggered

Returns a value of true if the library cell is triggered by the rising edge of the clock.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_sequential

Returns a value of true if the library cell is a latch or flip-flop, or if the cell has sequential timing
checks.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_tristate

Returns a value of true if the library cell definition includes the Liberty attribute three_state set
to true.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

latch_enable_pins

Returns a list of lib_pin objects which function as the enable/gate pin of a latch
Type: obj(lib_pin)*
Default: ""
Edit: No

late_fall_clock_period_derate_factor

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Returns clock period derate factor for fall transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_clock_period_mean_derate_factor

Returns mean clock period derate factor for fall transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_clock_period_sigma_derate_factor

Returns sigma clock period derate factor for fall transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_pulse_width_derate_factor

Returns pulse width derate factor for fall transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_pulse_width_mean_derate_factor

Returns mean pulse width derate factor for fall transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_pulse_width_sigma_derate_factor

Returns sigma pulse width derate factor for fall transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_clock_period_derate_factor

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Returns clock period derate factor for rise transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_clock_period_mean_derate_factor

Returns mean clock period derate factor for rise transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_clock_period_sigma_derate_factor

Returns sigma clock period derate factor for rise transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_pulse_width_derate_factor

Returns pulse width derate factor for rise transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_pulse_width_mean_derate_factor

Returns mean pulse width derate factor for rise transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_pulse_width_sigma_derate_factor

Returns sigma pulse width derate factor for rise transition on the lib cell
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_slew_derate_factor

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Returns late transition derate factor on the lib cell

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

leakage

Returns a cell_leakage_power property for a lib cell

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

leakage_power

Returns the leakage power of the library cell as specified by the Liberty timing library
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

level_shifter_type

Returns the Level Shifter type for a given lib_cell. The supported values are LH, HL and
HL_LH.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

lib_arcs

Returns a list of lib_arc objects contained with the lib_cell

Type: obj(lib_arc)*
Default: ""
Edit: No

lib_pins

Returns a list of lib_pin objects for the lib_cell

Type: obj(lib_pin)*
Default: ""
Edit: No

library

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Returns the parent library object for the lib_cell

Type: obj(library)*
Default: ""
Edit: No

name

Returns the unique name of the library cell in the form

lib_cell:librarySetName/libraryName/libraryCellName
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (lib_cell)
Default: ""
Edit: No

pg_lib_pins

Returns a list of the power and ground lib_pin objects of the lib_cell
Type: obj(lib_pin)*
Default: ""
Edit: No

power_switch_type

Returns the switch cell type associated with library cell. The supported values are
coarse_grain, fine_grain.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

receiver_capacitance_type

Returns input cap group being used for delay calculations, C1C2 or C1CN
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

retention_cell

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Database Objects--lib_pin

Returns the retention_cell derived from Liberty

Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

rise_input_switching_derate_factor

std_cell_main_rail_name

Returns the rail name associated with pg pin for which std_cell_main_rail is enabled.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

timing_model_type

Returns the Liberty model type for a given cell or instance. The supported values are
abstracted , extracted , and qtm .
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

lib_pin

Parent Objects
lib_cell, pin, lib_arc, root, port

Definition
cte lib pin

Attribute Description

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Database Objects--lib_pin

base_name

Returns the simple name of this library pin. The base_name of BUFFERX1/A is 'A'.
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

base_pin

Returns the related base_pin object of this library pin. Use chaining to access the base_pin
attributes
Type: obj(base_pin)*
Default: ""
Edit: No

capacitance

Returns the capacitance for the library pin.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

capacitance_max_fall

Returns the maximum value of the falling capacitance range.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

capacitance_max_rise

Returns the maximum value of the rising capacitance range.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

capacitance_min_fall

Returns the minimum value of the falling capacitance range.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

capacitance_min_rise

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Returns the minimum value of the rising capacitance range.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

cell_name

Returns the name of the lib_cell of the lib_pin mentioned.

Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

direction

Returns the direction of the library pin: in , out , inout or internal. Internal is for a lib_pin that is
not visible in the netlist, but is used internally by the timer to model timing arcs and constraints.
These lib_pins will not appear in the GUI, or Verilog, but may appear in timing reports.
Type: enum
Enum Values: internal in out inout
Allowed -index values: analysis_view
Default: ""
Edit: No

drive_resistance_fall

Specifies the driving resistance of the cell for falling transitions

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

drive_resistance_rise

Specifies the driving resistance of the cell for falling transitions

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

fanout_load

Returns the fanout load value of the library pin.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

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Database Objects--lib_pin

from_lib_arcs

Returns the list of lib_arc objects that begin from this library pin
Type: obj(lib_arc)*
Default: ""
Edit: No

full_name

Returns a unique reference for the library cell of the form:

libset/lib_name/cell_name/pin_name
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

function

Returns the function property for a lib pin

Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

input_signal_level

Returns the rail name associated with input library pin.

Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

input_signal_level_high

Returns partial high voltage swing of an input pin.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

input_signal_level_low

Returns partial low voltage swing of an input pin.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

input_signal_level_voltage

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Returns rail voltage of signal which is driving the input pin.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

is_always_on

Returns a value of true if the Liberty library is_always_on attribute is set to true for this library
pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_async

Returns a value of true if the library pin is an asynchronous preset pin, or an asynchronous
clear pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_clear

Returns a value of true if the pin is an asynchronous clear pin.

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_clock

Returns a value of true if the library pin definition includes clock:true .

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_clock_gate_clock

Returns a value of true if the pin has the Liberty attribute clock_gate_clock_pin set to true
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

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Database Objects--lib_pin

is_clock_gate_enable

Returns a value of true if the pin has the Liberty attribute clock_gate_enable_pin set to true
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_data

Returns a value of true if the library pin is the data pin of a flip-flop.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_exist

Returns a value of true if the library pin exists in view.

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_fall_edge_triggered_clock

is_fall_edge_triggered_clock
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_fall_edge_triggered_data

Returns a value of true if the library pin is the data pin of a falling edge triggered device.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_isolated

Returns a value of true if the Liberty library is_isolated attribute is set to true for this library pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_isolation_cell_clock

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Returns true if a clock lib pin is part of an isolatoin cell,

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_isolation_cell_data

Returns a value of true if the Liberty library is_isolation_cell_data attribute is set to true for this
library pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_isolation_cell_enable

Returns a value of true if the Liberty library is_isolation_cell_enable attribute is set to true for
this library pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_level_shifter_data

Returns a value of true if the Liberty library is_level_shifter_data attribute is set to true for this
library pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_level_shifter_enable

Returns a value of true if the Liberty library is_level_shifter_enable attribute is set to true for
this library pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_negative_level_sensitive_clock

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Database Objects--lib_pin

Returns a value of true if the library pin is an enable pin of an active low level-sensitive device.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_negative_level_sensitive_data

Returns a value of true if the pin is a data pin of an active low level-sensitive device.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_pad

Returns the pad value of a pin

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_pll_feedback_pin

Returns a value of true if the Liberty library is_pll_feedback_pin attribute is set to true for this
library pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_pll_output_pin

Returns a value of true if the Liberty library is_pll_output_pin attribute is set to true for this
library pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_pll_reference_pin

Returns a value of true if the Liberty library is_pll_reference_pin attribute is set to true for this
library pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

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Database Objects--lib_pin

is_positive_level_sensitive_clock

Returns a value of true if the library pin is an enable pin of an active high level-sensitive
device.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_positive_level_sensitive_data

Returns a value of true if the pin is a data pin of an active high level-sensitive device.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_power_switch_enable

Returns a value of true if the Liberty library is_power_switch_enable attribute is set to true for
this library pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_preset

Returns a value of true if the pin is a preset pin.

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_retention_cell_enable

Returns a value of true if the Liberty library is_retention_cell_enable attribute is set to true for
this library pin.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_rise_edge_triggered_clock

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Database Objects--lib_pin

Returns a value of true if the library pin is the clock pin of a rising edge triggered device.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_rise_edge_triggered_data

Returns a value of true if the library pin is the data pin of a rising edge triggered device.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_tristate

Returns a value of true if the library pin definition includes three_state:true .

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_tristate_enable

Returns a value of true if the library pin is part of a Liberty three_state_enable logical
expression
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_tristate_output

Returns a value of true if the library pin definition includes three_state:true .

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

lib_cell

Returns the lib_cell parent object of this lib_pin

Type: obj(lib_cell)*
Default: ""
Edit: No

max_capacitance

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Database Objects--lib_pin

Returns the maximum capacitance limit for the library pin.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

max_fanout

Returns the maximum fanout value for the library pin.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

max_transition

Returns the maximum transition time limit specified for a given library pin. If the limit is not
specified for a library pin, then the limit specified at the corresponding library level will be
used.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

min_capacitance

Returns the minimum capacitance limit for the library pin.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

min_fanout

Returns the minimum fanout value for the library pin.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

min_transition

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Returns the minimum transition time limit specified for a given library pin. If the limit is not
specified for a library pin, then the limit specified at the corresponding library level will be
used.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

name

Returns the name of the library pin in the form: <library_name>/<cell_name>/<pin_name>

Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (lib_pin)
Default: ""
Edit: No

output_signal_level

Returns the rail name associated with output library pin.

Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

output_signal_level_high

Returns partial high voltage swing of an output pin.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

output_signal_level_low

Returns partial low voltage swing of an output pin.

Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

related_ground_pin_rail_voltage

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Database Objects--lib_pin

Returns rail voltage of associated ground pin for the given pin.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

related_power_pin_rail_voltage

Returns rail voltage of associated power pin for the given pin.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

slew_threshold_percent_fall_high

Specifies the upper threshold point used to model a falling transition on this pin. This value is
typically inherited from the library-level specification. This value is specified as a percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

slew_threshold_percent_fall_low

Specifies the lower threshold point used to model a falling transition on this pin. This value is
typically inherited from the library-level specification. This value is specified as a percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

slew_threshold_percent_rise_high

Specifies the upper threshold point used to model a rising transition on this pin. This value is
typically inherited from the library-level specification. This value is specified as a percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

slew_threshold_percent_rise_low

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Database Objects--library

Specifies the lower threshold point used to model a rising transition on this pin. This value is
typically inherited from the library-level specification. This value is specified as a percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

to_lib_arcs

Returns the list of lib_arc objects that terminate at this pin

Type: obj(lib_arc)*
Default: ""
Edit: No

library

Parent Objects
timing_condition, lib_cell, library_set, root

Definition
cte lib

Attribute Description

base_name

Returns the simple name of the library as defined by the Liberty library() group name
Type: string
Default: ""
Edit: No

cap_scale_in_ff

Returns the capacitance scaling of the library in femtofarads

Type: double
Default: ""
Edit: No

default_power_rail

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Database Objects--library

Returns the power rail defined by the Liberty default_power_rail attribute

Type: string
Default: ""
Edit: No

default_wireload

Returns the wire-load model defined by the Liberty default_wire_load attribute

Type: string
Default: ""
Edit: No

files

Returns the list of library files associated with this library

Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

has_cells_having_power_ground_pins

Returns a value of true if the library cells in this library have power/ground pin modeling
Type: bool
Default: ""
Edit: No

hierarchical_name

hierarchical_name
Type: string
Allowed -index values: analysis_view
Default: ""
Edit: No

input_threshold_pct_fall

Specifies the delay threshold for a falling input signal. This value is specified as a percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

input_threshold_pct_rise

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Database Objects--library

Specifies the delay threshold for a rising input signal. This value is specified as a percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

is_exist

Returns a value of true if library is present in view.

Type: bool
Default: ""
Edit: No

leakage_power_scale_in_nw

Returns the leakage power scaling used in this library in units of nanoWatts
Type: double
Default: ""
Edit: No

lib_cells

Returns a list of library cell objects contained within this library

Type: obj(lib_cell)*
Default: ""
Edit: No

name

Returns an identifier for this library of the form: library_set/library_name

Type: string
Default: ""
Edit: No

nominal_process

Returns the nominal process of the library as specified by the Liberty nom_process attribute
Type: double
Default: ""
Edit: No

nominal_temperature

Returns the nominal temperature of the library as specified by the Liberty nom_temperature
attribute
Type: double
Default: ""
Edit: No

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Database Objects--library

nominal_voltage

Returns the nominal voltage of the library as specified by the Liberty nom_voltage attribute
Type: double
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (library)
Default: ""
Edit: No

output_threshold_pct_fall

Specifies the delay threshold for a falling output signal. This value is specified as a
percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

output_threshold_pct_rise

Specifies the delay threshold for a rising output signal. This value is specified as a
percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

power_rails

Returns the power rails defined for this library

Type: string
Default: ""
Edit: No

slew_derate_from_library

Specifies the multiplier used to translate between the transition time range used during
characterization and the transition time range used in the timing library tables. A
characterization range of 30% and library range of 10% would result in a derate value of 0.5.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

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Database Objects--library

slew_lower_threshold_pct_fall

Specifies the lower threshold point used to model a falling transition on this pin. This value is
specified as a percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

slew_lower_threshold_pct_rise

Specifies the lower threshold point used to model a rising transition on this pin. This value is
specified as a percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

slew_upper_threshold_pct_fall

Specifies the upper threshold point used to model a falling transition on this pin.. This value is
specified as a percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

slew_upper_threshold_pct_rise

Specifies the upper threshold point used to model a rising transition on this pin. This value is
specified as a percentage.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

wireload_models

Returns a list of the wireload models defined in the library

Type: string
Default: ""
Edit: No

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Database Objects--library_set

library_set

Parent Objects
timing_condition, root

Definition
Specifies a group of library files to be treated as a single entity so that higher-level descriptions
(delay_corners) can simply refer to the library configuration by name. All non-physical libraries used by the
timing must be part of a library_set - including Liberty, AOCV, SOCV, and signal integrity library formats. Use
the create_library_set command to define new library_sets and the update_library_set command to update
the attributes of existing library_sets.

Attribute Description

aocv_files

Specifies the list of optional AOCV derating library files associated with the library_set
Type: string
Default: ""
Edit: No

libraries

Specifies the list of timing library objects that result from the import of the library_files
Type: obj(library)*
Default: ""
Edit: No

library_files

Specifies the list of Liberty timing library files associated with the library_set
Type: string
Default: ""
Edit: No

name

Provides the name of this library_set object as specified by create_library_set.

Type: string
Default: ""
Edit: No

obj_type

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The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (library_set)
Default: ""
Edit: No

si_files

Specifies the list of optional signal integrity (.cdb) library files associated with the library_set
Type: string
Default: ""
Edit: No

socv_files

Specifies the list of optional SOCV variation library files associated with the library_set
Type: string
Default: ""
Edit: No

marker

Parent Objects
design, root

Definition
A violation marker. All markers have a .bbox and .originator set, and optionally .polygon for polygon shapes.
Other attributes depend on the marker. Markers created by internal check or report commands will have
.originator != external and have a .layer, .type, .subtype, .message, and .message_id defined by those
commands. Markers created with read_markers or create_marker will have .originator == external and will
have .layer, .user_type, .user_subtype, .user_originator, and .message based on the external input.

Attribute Description

bbox

Bounding box of the marker shape.

Type: rect
Default: ""
Edit: No

is_false

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Indicates the marker is marked as false violation by user.

Type: bool
Default: false
Edit: Yes

is_hidden

Indicates the marker is hidden by user in violation browser.

Type: bool
Default: false
Edit: Yes

layer

The layer of marker

Type: obj(layer)
Default: ""
Edit: No

message

The message attached to the marker

Type: string
Default: ""
Edit: No

message_id

The message ID used internally for this message

Type: int
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (marker)
Default: ""
Edit: No

objects

The objects which caused the DRC. The list may be empty, and is currently limited to at most
2 objects.
Type: obj(inst)* obj(net)* obj(pin)* obj(port)* obj(bump)*
Default: ""
Edit: No

originator

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The originator of the marker from an internal command, or 'external' if the marker is from
create_marker or read_markers.
Type: enum
Enum Values: unknown check external check_place route_litho route_design
check_pin_assignment pg ccopt check_floorplan
Default: ""
Edit: No

polygon

Polygon boundary for the marker if it is not a rectangle. The first point is not repeated as the
last point in the list.
Type: polygon
Default: ""
Edit: No

subtype

The marker subtype if it was created be an internal check or report command (when .originator
!= external).
Type: string
Default: {}
Edit: No

type

The marker type if it was created by an internal check or report command (when .originator !=
external).
Type: enum
Enum Values: none drc antenna connectivity floorplan overlap density ir_drop xtalk ac_limit
mixed_signal electrical place route_litho busplanning msv ccopt
Default: ""
Edit: No

user_originator

The originator given by the user for external markers from create_marker or read_marker
(when .originator == external).
Type: string
Default: {}
Edit: No

user_subtype

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Database Objects--module

The type given by the user for external markers from create_marker or read_marker (when
.originator == external).
Type: string
Default: {}
Edit: No

user_type

The type given by the user for external markers from create_marker or read_marker (when
.originator == external).
Type: string
Default: {}
Edit: No

module

Parent Objects
hinst, design, root

Definition
Cell module

Attribute Description

allow_ilm_eco

The attribute is only valid when the module is an ILM. If true, optimizer can optimize the ILM
boundary interface logic to improve timing
Type: bool
Default: false
Edit: Yes

checkpoint_equation

Identifies the Datapath equation presence and equation itself.

Type: string
Default: ""
Edit: Yes

design

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The design that contains this module.

Type: obj(design)*
Default: ""
Edit: No

dont_touch

This attributes defines the user preservation status of the module during optimization. Setting
this attribute will set the dont_touch attribute on all hinsts of the same module. This setting will
apply to all insts within the hinst unless overridden at a lower level hinst or on the inst object
itself. The dont_touch_effective attribute on each child inst and hinst will return the resolved
value.
Use 'help inst dont_touch' to see the enum value definitions.
Type: enum
Enum Values: none false true delete_ok const_prop_size_delete_ok const_prop_delete_ok
size_delete_ok size_ok size_same_height_ok size_same_footprint_ok
Default: none
Edit: Yes

dont_touch_hports

This attribute defines the user preservation status for the module object hports during
optimization.
Supported values:
none: Unconstrained
false: Can add/remove ports
true: Cannot add/remove ports
delete_ok: Can delete ports (if they have no fanout)
add_ok: We cannot delete, or change the polarity or any hport but can add or duplicate
hports
invert_ok: We cannot delete, duplicate, or add but can change the polarity of any hport
add_invert_ok: We cannot delete any hport but can add, duplicate, and change the polarity
Type: enum
Enum Values: none false true delete_ok add_ok invert_ok add_invert_ok
Default: none
Edit: Yes

dont_use_cells

List of cell names (wildcards supported) to disallow for this module during optimization.
Setting this applies to all hinsts sharing the module. Overrides any library dont_use values
Type: string
Default: ""
Edit: Yes

dont_use_cells_effective

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The resolved list of all cell names to disallow during optimization for hinsts of this module,
based on the library dont_use and the dont_use_cells and use_cells attributes of this module
or the closest parent hinst with a non-empty list. The precedence is: use_cells of this hinst (or
closest parent if empty), then dont_use_cells of this hinst (or closets parent if empty), then the
library dont_use setting.
Type: string
Default: ""
Edit: No

hinsts

The hinsts that are derived from (instantiate) this module.

Type: obj(hinst)*
Default: ""
Edit: No

is_ilm

This attribute is true if the module is a ILM. This attribute will affect the read_only_effective and
dont_touch_effective attribute on all insts and hinsts within the hinsts of this module. It cannot
be overridden by other hinst or inst values.
Supported values:
false: This module is not an ILM
true: This module is an ILM
Type: bool
Default: false
Edit: No

name

Name of cell
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (module)
Default: ""
Edit: No

use_cells

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List of cell names to allow for this module during optimization. Setting this applies to all hinsts
sharing the module All lib_cells of each base_cell will be allowed. Overrides cells in the
dont_use_cells list and any library dont_use values.
Type: string
Default: ""
Edit: Yes

net

Parent Objects
flexible_htree, marker, bus, resistor, port, special_wire, hpin, hnet, what_if_wire, via, what_if_via, design,
clock_tree, net_group, timing_path, bump, root, power_domain, virtual_wire, pg_pin, patch_wire, wire, pin,
special_via, route_type

Definition
canonical net

Attribute Description

annotated_capacitance_max

Returns maximum annotated capacitance of the net for late path analysis. You can use -index
to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

annotated_capacitance_min

Returns the minimum annotated capacitance of the net for early path analysis. You can use -
index to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

annotated_resistance_max

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Returns the maximum annotated resistance of the net for late path analysis. You can use -
index to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

annotated_resistance_min

Returns the minimum annotated resistance of the net for early path analysis. You can use -
index to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

arcs

Returns a list of arc objects that are associated with this net.
Type: obj(arc)*
Default: ""
Edit: No

base_name

The name at the base of a hierarchical name. So the base_name of i1/i2/i3 is i3.
Type: string
Default: ""
Edit: No

bbox

Bounding box of all the wires, vias, pins, and ports of the net. Does not include special wires
or special vias.
Type: rect
Default: ""
Edit: No

bottom_preferred_layer

The preferred lowest routing layer. This attribute is a soft limit; that is, NanoRoute might use a
layer below the specified layer if necessary to complete routing.
Type: obj(layer)
Default: ""
Edit: Yes

bus

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The bus for this net.

Type: obj(bus)
Default: ""
Edit: No

capacitance_max

Returns the total capacitance of the net used for late path analysis. You can use -index to
return the capacitance for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

capacitance_min

Returns the total capacitance of the net for early path analysis. You can use -index to return
the capacitance for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

constant

Returns if this net has a 1'b0 or 1'b1 on any hpin or hnet, or a supply0/supply1 for any hnet. It
does not include timing set_case_analysis assertions, or propagation through cells, or the
effects of a constant driver on the net.
Type: enum
Enum Values: 0 1 no_constant
Default: ""
Edit: No

coupling_capacitance_max

Returns the maximum value of coupling capacitance of a net over all the views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

coupling_capacitance_min

Returns the minimum value of coupling capacitance of a net over all the views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

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cts_ideal_net

If set the clock tree timing engine will consider this net as ideal.
Type: bool
Default: false
Edit: Yes

cts_net_type

For a net, return the CTS net type.

Will be one of:
. "top" - A clock net that has fanout above cts_top_fanout_transitive_count.
. "trunk" - A CTS clock net that is not a "top" net nor a "leaf" net.
. "leaf" - A CTS clock net that has fanout to only clock sinks.
. "unknown" - A CTS clock net that has not been analyzed.
. "" - Not a CTS clock net.
See also the get_clock_tree_nets command.
Type: string
Default: ""
Edit: No

dont_touch

This attribute defines the preservation status of an net during optimization. Setting this attribute
will preserve all connections on this net. When set, this overrides any setting on hnets of this
net. Also, note that the .use attribute for the net can also cause the net to be preserved.
Supported values:
false: Unconstrained
true: Cannot touch
delete_ok: Can delete (if they have no sinks)
Type: enum
Enum Values: false true delete_ok
Default: false
Edit: Yes

driver_pins

These are the drivers of the net that are pins (no port drivers are returned). Pins that have
direction = out or inout are considered drivers.
Type: obj(pin)*
Default: ""
Edit: No

driver_ports

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These are the drivers of the net that are ports (no pin drivers are returned). Ports that have
direction = in or inout are considered drivers.
Type: obj(port)*
Default: ""
Edit: No

drivers

Ports and pins that drive the net. These are pins that have direction = out or inout, and ports
that have direction = in or inout.
Type: obj(pin)* obj(port)*
Default: ""
Edit: No

early_fall_clk_net_delta_derate_factor

Returns the early derating factor for falling SI/delta delays on data path nets. You can use -
index to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_fall_clk_net_derate_factor

Returns the early derating factor for falling static delays on clock path nets. You can use -index
to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_fall_data_net_delta_derate_factor

Returns the early derating factor for falling SI/delta delays on clock path nets. You can use -
index to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_fall_data_net_derate_factor

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Returns the early derating factor for falling static delays on data path nets. You can use -index
to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_rise_clk_net_delta_derate_factor

Returns the early derating factor for rising SI/delta delays on data path nets. You can use -
index to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_rise_clk_net_derate_factor

Returns the early derating factor for rising static delays on clock path nets. You can use -index
to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_rise_data_net_delta_derate_factor

Returns the early derating factor for rising SI/delta delays on clock path nets. You can use -
index to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

early_rise_data_net_derate_factor

Returns the early derating factor for rising static delays on data path nets. You can use -index
to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

escaped_name

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frequency

Reports the frequency of the net.

Type: double
Default: ""
Edit: No

has_detailed_parasitics

Returns a value of true if the net, or one of its parts, has detailed parasitics associated with it
from either RC extraction or SPEF annotation.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

hnets

List of hNets which make up this net.

Type: obj(hnet)*
Default: ""
Edit: No

is_clock

Indicates that net is a clock according to timing constraints and tracing. It is only valid if the
timing-graph has been created.
Type: bool
Default: ""
Edit: No

is_custom_route

Indicates that the net has Virtuoso/OA custom routing constraints that NR does not support, so
NR should not route this net.
Type: bool
Default: ""
Edit: No

is_early_global_routed

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Indicate that the net is from early global route

Type: bool
Default: false
Edit: Yes

is_edit

Indicate that the wire/via on the net has been modified. This attribute only works when "set_db
edit_wire_create_is_edit_flag 1". Please look up for more details by "help
edit_wire_create_is_edit_flag".
Type: bool
Default: false
Edit: Yes

is_external

Indicates that net is connected to a to a top-level port.

Type: bool
Default: ""
Edit: No

is_fixed_bump

Indicates that net is fixed to bump connection.

Type: bool
Default: ""
Edit: No

is_ground

Indicate that the net is ground net

Type: bool
Default: ""
Edit: No

is_ideal

Returns true if the net is part of an ideal network due to the assertion or propagation of the
set_ideal_network constraint. You can use -index to return the is_ideal value for specific
views.
Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_ilm

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Specify if a top level net is connecting to ILM (Interface Logic Model) modules and some or all
terms (either drive or sink) of the net are inside ILM module.
Type: bool
Default: ""
Edit: No

is_physical_only

Indicates that the net is a physical only net that does not get written to logical Verilog netlist.
Type: bool
Default: ""
Edit: No

is_power

Indicate that the net is power net

Type: bool
Default: ""
Edit: No

is_preserve_combinational_loop_breaker

Identifies the combinational loop breaking location.

Type: bool
Default: false
Edit: Yes

is_trunk_pattern_route

Indicates that the net is routed with a trunk pattern

Type: bool
Default: ""
Edit: No

is_voltage_asserted

Returns whether a pg net voltage is inferred by tool or user asserted.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

late_fall_clk_net_delta_derate_factor

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Returns the late derating factor for falling SI/delta delays on data path nets. You can use -
index to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_clk_net_derate_factor

Returns the late derating factor for falling static delays on clock path nets. You can use -index
to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_data_net_delta_derate_factor

Returns the late derating factor for falling SI/delta delays on clock path nets. You can use -
index to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_fall_data_net_derate_factor

Returns the late derating factor for falling static delays on data path nets. You can use -index
to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_clk_net_delta_derate_factor

Returns the late derating factor for rising SI/delta delays on data path nets. You can use -index
to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_clk_net_derate_factor

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Returns the late derating factor for rising static delays on clock path nets. You can use -index
to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_data_net_delta_derate_factor

Returns the late derating factor for rising SI/delta delays on clock path nets. You can use -
index to return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

late_rise_data_net_derate_factor

Returns the late derating factor for rising static delays on data path nets. You can use -index to
return the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

load_pins

These are the loads of the net that are pins (no port loads are returned). Pins that have
direction = in or inout are considered loads.
Type: obj(pin)*
Default: ""
Edit: No

load_ports

These are the loads of the net that are ports (no pin loads are returned). Ports that have
direction = out or inout are considered loads.
Type: obj(port)*
Default: ""
Edit: No

loads

Ports and pins that are loads for the net. These are pins that have direction = in or inout, and
ports that have direction = out or inout.
Type: obj(pin)* obj(port)*
Default: ""
Edit: No

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max_voltage

Max voltage for the net, determined by the max net voltage of all active hold views. Net voltage
is determined using the following procedure: voltage from net's driver pin, associated power
from CPF related_power_pins command or Liberty related_pg_pin attribute or LEF
SUPPLYSENSITIVITY statement; power domain operating voltage; or default system voltage.
Type: voltage
Default: ""
Edit: No

min_voltage

Min voltage for the net, determined by the min net voltage of all active setup views.Net voltage
is determined using the following procedure: voltage from net's driver pin, associated power
from CPF related_power_pins command or Liberty related_pg_pin attribute or LEF
SUPPLYSENSITIVITY statement; power domain operating voltage; or default system voltage.
Type: voltage
Default: ""
Edit: No

name

num_connections

Number of connections to the net (number of pins + number of ports)

Type: int
Default: ""
Edit: No

num_drivers

Number of drivers for the net. These are pins that have direction = out or inout, and ports that
have direction = in or inout.
Type: int
Default: ""
Edit: No

num_loads

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Number of loads for the net. These are pins that have direction = in or inout, and ports that
have direction = out or inout.
Type: int
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (net)
Default: ""
Edit: No

patch_wires

List of patch_wire
Type: obj(patch_wire)*
Default: ""
Edit: No

pin_capacitance_max

Returns the portion of the net's total capacitance which comes the library max pin capacitance
values. This is used for late path delay calculation. You can use -index to return the derate
factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

pin_capacitance_max_fall

pin_capacitance_max_fall
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

pin_capacitance_max_rise

pin_capacitance_max_rise
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

pin_capacitance_min

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Returns the portion of the net's total capacitance which comes the library min pin capacitance
values. This is used for early path delay calculation. You can use -index to return the derate
factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

pin_capacitance_min_fall

pin_capacitance_min_fall
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

pin_capacitance_min_rise

pin_capacitance_min_rise
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

power_duty_cycle

.
Type: double
Default: ""
Edit: No

power_ref_clock

The static probability of the signal to stay high during one clock cycle. It is a value between 0.0
and 1.0. no_value is returned if it cannot be computed.
Type: string
Default: ""
Edit: No

power_switching

The switching power of this net computed by report_power.

Type: double
Default: ""
Edit: No

power_toggle_per_clock

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The number of toggles per clock cycle. It is computed from power_toggle_rate * <period of
power_ref_clock>. It can be as high as 2.0 for a clock, and is between 0 and 1 for a signal net.
If there is more than one output pin, then it is the average of all the output pin
power_toggle_rates. no_value is returned if no value can be computed.
Type: double
Default: ""
Edit: No

power_toggle_rate

The average number of toggles read from VCD, TCF, SAIF, etc. or from propagation that occur
in 1 second on the net.
Type: double
Default: ""
Edit: No

power_toggle_rate_max

The average number of toggles read from VCD, TCF, SAIF, etc. or from propagation that occur
in 1 second on the net.
Type: double
Default: ""
Edit: No

power_toggle_rate_source

The source of the power_toggle_rate value. The enum values mean:asserted: the value is
user-specified by direct assertion or from a switching activity file.clock: the value is derived
from the clock waveform.computed: the value is computed by propagating internal switching
activity.constant:the value is driven by a constant value (e.g. from set_case_analysis or tie-
offs).default: the value is not user-specified, but determined from the root
power_default_toggle_rate attribute.
Type: string
Default: ""
Edit: No

resistance_max

Returns the maximum resistance of the net for late path analysis. You can use -index to return
the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

resistance_min

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Returns the minimum resistance of the net for early path analysis. You can use -index to return
the value for a specific view.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

route_user_bottom_preferred_routing_layer

The initial lowest layer set by set_route_attributes or set_db. Opt will use it as a reference to
set bottom_preferred_layer to any value equal or greater than initial_bottom_preferred_layer
and smaller than top_preferred_layer for better performance.
Type: obj(layer)
Default: ""
Edit: Yes

shield_nets

1 or 2 shield nets. Must be power or ground nets

Type: obj(net)*
Default: ""
Edit: No

shield_tap_instance_insertion_effort

Different route type for clock shielding, including high frequency(high) and low
frequency(standard) that main difference is what ground tie cell instance/via used to achieve
shield segments electrical connection. Possible attribute values:
None: default
Standard: use existing standard cell vss m0 pins as much as possible, create a new instance
of a ground tie cell under the shield route if cannot find an existing vss m0 pin within a user
controlled search distance of a required connection, the new cell vss pins can have a "max
fanout" of 2 shield nets.
High: must create ground tie cell instances, and user can specify the physical distance of
these new ground tie cells along the clock segments. new instance m0 vss pin to the clock
shield segments will be a via stack of single vias on ever layer to the shield nets. It is
acceptable for the router to create a n-1 metal shape to connect adjacent vss shield segments
together and then route this single vss shape down to m0 ground tie pin. Shield segments may
be electrically connected between adjacent route layers through vias. If this is done, there
shall be no Manhattan distance between ground tie cells that is larger than the user provided
value. Newly inserted ground tie cells cannot be shared between clocks.
Type: enum
Enum Values: none standard high
Default: none
Edit: Yes

si_post_route_repair

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Specifies that antenna violations should not be corrected by the routing as the violation will be
corrected in a different level of the design hierarchy.
Type: bool
Default: ""
Edit: No

skip_antenna_repair

Specifies that antenna violations should not be corrected by the routing as the violation will be
corrected in a different level of the design hierarchy.
Type: bool
Default: false
Edit: Yes

skip_routing

Specifies that Nanoroute should not route or re-route the net.

Type: bool
Default: false
Edit: Yes

special_vias

List of special vias.

Type: obj(special_via)*
Default: ""
Edit: No

special_wires

List of special_wires (DEF SPECIALNETS equivalent)

Type: obj(special_wire)*
Default: ""
Edit: No

top_preferred_layer

The preferred highest routing layer. This attribute is a soft limit. The router considers it high
cost to go above this layer, but might still use a higher layer in order to avoid DRC violations.
Type: obj(layer)
Default: ""
Edit: Yes

use

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Indicates how this net is used. The enum values correspond to DEF and OpenAccess enum
names. By default nets are 'signal'. Power/ground nets get marked' power' or 'ground' when
they are created. The clock tree creation commands set any net added for the clock tree to
'clock'. In practice the other values like 'scan' or 'tieoff' are not used anymore.
Type: enum
Enum Values: signal analog clock ground power scan tieoff
Default: ""
Edit: No

vias

List of viaInsts.
Type: obj(via)*
Default: ""
Edit: No

virtual_wires

List of virtual_wire
Type: obj(virtual_wire)*
Default: ""
Edit: No

weight

Net weight.
Type: int
Default: no_value
Edit: Yes

what_if_vias

List of 'what if' vias.

Type: obj(what_if_via)*
Default: ""
Edit: No

what_if_wires

List of 'what if' wires

Type: obj(what_if_wire)*
Default: ""
Edit: No

wire_capacitance_max

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Returns the portion of the net's total capacitance which comes extracted or annotated wire
capacitance values. This is used for late path delay calculation. You can use -index to return
the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

wire_capacitance_max_fall

Returns the wire capacitance of the net for the maximum value of the falling capacitance
range.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

wire_capacitance_max_rise

Returns the wire capacitance of the net for the maximum value of the rising capacitance range.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

wire_capacitance_min

Returns the portion of the net's total capacitance which comes extracted or annotated wire
capacitance values. This is used for early path delay calculation. You can use -index to return
the derate factor for specific views.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

wire_capacitance_min_fall

Returns the wire capacitance of the net for the minimum value of the falling capacitance range.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

wire_capacitance_min_rise

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Returns the wire capacitance of the net for the minimum value of the rising capacitance range.
Type: double
Allowed -index values: analysis_view
Default: ""
Edit: No

wires

List of wires
Type: obj(wire)*
Default: ""
Edit: No

net_group

Parent Objects
design, bus_guide, pin_guide, root

Definition
Net Group

Attribute Description

exclude_net

Indicates group net exclude type(all_layer, same_layer, inclusive, all_layer_in_guided_area)

Type: enum
Enum Values: all_layer_in_guided_area all_layer same_layer inclusive
Default: ""
Edit: Yes

is_compact

Indicate whether the nets in the group are assigned tightly together. By default, nets which are
part of a group and associated to a guide can be spread inside the guide based on the area
available and alignment to targets
Type: bool
Default: false
Edit: Yes

is_guided

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Indicates if net group is guided

Type: bool
Default: false
Edit: Yes

is_optimize_order

Indicates whether net order will be optimized

Type: bool
Default: false
Edit: Yes

is_spread

Indicates whether member nets distributed evenly

Type: bool
Default: false
Edit: Yes

keep_out_space

Minimum spacing with pin of foreign nets (Unit: track)

Type: int
Default: 0
Edit: Yes

name

Group name
Type: string
Default: ""
Edit: No

nets

List of member nets to this net group

Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (net_group)
Default: ""
Edit: No

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Database Objects--obj_type

obj_type

Parent Objects
attribute, root

Definition

Attribute Description

accept_user_defined_attributes

Specifies whether new attributes can be added by user.

Type: bool
Default: ""
Edit: No

attributes

list of attribute for this obj_type

Type: obj(attribute)*
Default: ""
Edit: No

help

Specifies the help text for the object

Type: string
Default: ""
Edit: No

name

obj_type name like inst, lib_cell, etc.

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (obj_type)
Default: ""
Edit: No

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Database Objects--opcond

opcond

Parent Objects
timing_condition, root

Definition
An opcond represents a named operating condition which is defined by specific process, voltage, and
temperature values. Opcond objects may preexist within a Liberty library or "virtual" opconds may be created
using the create_opcond command. Virtual opconds can also be modified by using the update_opcond
command.

Attribute Description

base_name

The base name of the opcond without any leading library_set or library names (e.g. op1 for
libset1/lib1/op1).
Type: string
Default: ""
Edit: No

is_virtual

Indicates that this opcond object is a virtual opcond created by the create_opcond command
vs. an opcond that is created by reading a Liberty timing library file.
Type: bool
Default: ""
Edit: No

name

The full name of the opcond. The opcond name from a Liberty file includes the library_set and
library names (e.g. libset1/lib1/op1) while the full name from create_opcond is just the opcond
name (e.g. op1).
Type: string
Default: ""
Edit: No

obj_type

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The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (opcond)
Default: ""
Edit: No

process

Specifies the Process value of the opcond

Type: double
Default: ""
Edit: No

temperature

Specifies the Temperature value of the opcond in Celsius.

Type: double
Default: ""
Edit: No

tree_type

The Liberty tree_type model. It is an enum with these choices: none means there is no
tree_type value given; best_case_tree models each load pin is close to the driver, so wire
capacitance is incurred, but wire resistance is ignored; balanced_tree models when all load
pins are on equal branches, so each load pin has an equal portion of the total wire cap and
resistance; worst_case_tree models when the load pin is at the extreme end of the wire, so
each load pin incurs the full wire capacitance and resistance
Type: enum
Enum Values: none best_case_tree balanced_tree worst_case_tree
Default: ""
Edit: No

voltage

Specifies the Voltage value of the opcond in units of the library it came from.
Type: double
Default: ""
Edit: No

package_component

Parent Objects
design

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Database Objects--package_component

Definition
pkg component

Attribute Description

cell_name

The name of other chip cell in the package

Type: string
Default: ""
Edit: No

inst_name

The name of other chips in the package

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (package_component)
Default: ""
Edit: No

Location of the other chips in the package

Type: point
Default: ""
Edit: No

ref_design

Another identifying name of the chip in the package

Type: string
Default: ""
Edit: No

size

Size of the cell

Type: point
Default: ""
Edit: No

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Database Objects--package_object

package_object

Parent Objects
design, root

Definition
pkg object

Attribute Description

die_net_name

the name of die net which this package object connected to

Type: string
Default: ""
Edit: No

layer_name

The package layer that this package object belongs to

Type: string
Default: ""
Edit: No

name

The name of this package object

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (package_object)
Default: ""
Edit: No

package_net_name

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the name of package net which this package object connected to

Type: string
Default: ""
Edit: No

Location of the package object

Type: point
Default: ""
Edit: No

size

Size of the package object

Type: point
Default: ""
Edit: No

type

the type of this package object

Type: enum
Enum Values: bga_ball bond_finger bond_wire route flight_line component other
Default: ""
Edit: No

partition

Parent Objects
hinst, inst, design, pin_group, pin_guide, root

Definition
Partition Object

Attribute Description

base_pins

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Database Objects--partition

List of partition pins. It is valid only if partition is in non-committed state, i.e. partition module is
instantiated as hinst. Otherwise it is set to NULL.
Type: obj(base_pin)*
Default: ""
Edit: No

clones

List of clone inst/hinsts. The obj_type returned will be inst if the partition is committed or a
blackbox, otherwise the obj_type will be hinst.
Type: obj(inst)* obj(hinst)*
Default: ""
Edit: No

core_to_bottom

Spacing between the partition boundary and core design area of the partition module
Type: coord
Default: no_value
Edit: Yes

core_to_left

Spacing between the partition boundary and core design area of the partition module
Type: coord
Default: no_value
Edit: Yes

core_to_right

Spacing between the partition boundary and core design area of the partition module
Type: coord
Default: no_value
Edit: Yes

core_to_top

Spacing between the partition boundary and core design area of the partition module
Type: coord
Default: no_value
Edit: Yes

hpins

Hierarchical instance pin of the partition. It is only valid if the partition is uncommitted and still
an hinst.
Type: obj(hpin)*
Default: ""
Edit: No

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is_black_box

Specifies if partition is a blackbox

Type: bool
Default: ""
Edit: No

is_committed

Specifies if partition is committed

Type: bool
Default: ""
Edit: No

master

The master inst/hInst. The obj_type returned will be inst if the partition is committed or a
blackbox, otherwise the objType will be hInst.
Type: obj(inst)* obj(hinst)*
Default: ""
Edit: No

min_pitch_bottom

Specifies the pin pitch (in tracks)

Type: int
Default: 0
Edit: Yes

min_pitch_left

Specifies the pin pitch (in tracks)

Type: int
Default: 0
Edit: Yes

min_pitch_right

Specifies the pin pitch (in tracks)

Type: int
Default: 0
Edit: Yes

min_pitch_top

Specifies the pin pitch (in tracks)

Type: int
Default: 0
Edit: Yes

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Database Objects--partition

name

name of the partition

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (partition)
Default: ""
Edit: No

pin_bottom_layers

List of bottom layers to use for the partition

Type: obj(layer)*
Default: ""
Edit: Yes

pin_left_layers

List of left layers to use for the partition

Type: obj(layer)*
Default: ""
Edit: Yes

pin_right_layers

List of right layers to use for the partition

Type: obj(layer)*
Default: ""
Edit: Yes

pin_to_corner_tracks

Minimum number of routing tracks between pins and each corner. It is a list of int values,
where the first value is for the lower-left corner, and the remaining corners are listed in
clockwise order.
Type: int*
Default: ""
Edit: No

pin_top_layers

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Database Objects--partition

List of top layers to use for the partition

Type: obj(layer)*
Default: ""
Edit: Yes

place_halo_bottom

Specifies extra spacing around the partition that should not be used for placement
Type: coord
Default: no_value
Edit: Yes

place_halo_left

Specifies extra spacing around the partition that should not be used for placement
Type: coord
Default: no_value
Edit: Yes

place_halo_right

Specifies extra spacing around the partition that should not be used for placement
Type: coord
Default: no_value
Edit: Yes

place_halo_top

Specifies extra spacing around the partition that should not be used for placement
Type: coord
Default: no_value
Edit: Yes

rail_width

Specifies the cell rail width

Type: coord
Default: ""
Edit: No

read_only

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Database Objects--partition

This attributes is set by set_module_view to identify if a partition is read only or not. It means
the partition cannot be optimized, and cells inside will not be moved. Setting this attribute will
set the dont_touch_effective attribute on all insts and hinsts within the partition unless
overridden at a lower level partition. It cannot be overridden by other hinst or inst values.
Supported values:
false: This partition is allowed to be optimized, even if a partition or design above has
read_only = true.
true: The partition is read_only.
none: No constraint. This partition inherits any read_only from a partition or design above.
Type: enum
Enum Values: none false true
Default: none
Edit: No

reserved_layers

List of metal layers which are used for routing in the partition and generating partition pins.
Any metal layers that are not specified, usually the top-most metal layers, are allowed to route
over the partition
Type: obj(layer)*
Default: ""
Edit: Yes

route_halo_bottom_layer

The bottom partition layer for which routing halo will be created
Type: obj(layer)
Default: ""
Edit: Yes

route_halo_to_boundary

Specifies routing halo around the partition (honored by signal router). Positive values indicate
the halo is outside the partition. Negative values indicate the halo is inside of the boundary of
the partition and will be pushed into the partition when the partition is committed.
Type: coord
Default: no_value
Edit: Yes

route_halo_top_layer

The top partition layer for which routing halo will be created
Type: obj(layer)
Default: ""
Edit: Yes

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Database Objects--patch_wire

patch_wire

Parent Objects
net

Definition
DEF NETS RECT wire

Attribute Description

has_trim_metal

Indicate the path wire has trim metal or not

Type: bool
Default: ""
Edit: No

layer

The layer of patch

Type: obj(layer)
Default: ""
Edit: No

location

Reference point to symbolic location

Type: point
Default: ""
Edit: No

mask

Indicates mask number for multiple mask layer usage. Refer to layer's .numMask attribute for
legal range, 0 indicates uncolored.
Type: int
Default: 0
Edit: Yes

net

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The net that the patch belongs to

Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (patch_wire)
Default: ""
Edit: No

rect

Rectangle that defines the patch_wire shape

Type: rect
Default: ""
Edit: No

route_rule

The non-default rule corresponding to the wire, wires with the default routing rule will return
NULL (0x0).
Type: obj(route_rule)
Default: ""
Edit: No

status

Wiring status (equivalent to DEF NETS regular wiring status)

Type: enum
Enum Values: unknown routed fixed cover noshield
Default: ""
Edit: Yes

trim_metal_color

Color of this patch wire trim metal

Type: int
Default: ""
Edit: No

trim_metal_rect

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Database Objects--path_group

The trim_metal rect if the patch_wire has a trim_metal shape attached. This only occurs for
some advanced node layers that use self-aligned patterning. {0 0 0 0} is returned if there is no
trim_metal attached.
Type: rect
Default: ""
Edit: No

path_group

Parent Objects
timing_path

Definition
cte path group

Attribute Description

name

The name of the path_group.

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (path_group)
Default: ""
Edit: No

pg_base_pin

Parent Objects
base_cell, root, pg_pin

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Database Objects--path_group

Definition
A power or ground pin for a base_cell.

Attribute Description

base_cell

The base_cell of this pg_base_pin.

Type: obj(base_cell)*
Default: ""
Edit: No

base_name

The base name of this pg_base_pin without the base_cell name (e.g. vdd).
Type: string
Default: ""
Edit: No

direction

The pin direction from .lib if available, otherwise from LEF/OA. It can be in, out, inout or
internal. Internal means it is an internal pin from a .lib file for the timing model, and is not part
of the netlist If there is no .lib for this cell, then the direction comes from the LEF PIN
DIRECTION or equivalent OA oaTermType. The LEF DIRECTION values (and equivalent
oaTermType values) are mapped this way: INPUT = in, OUTPUT = out, OUTPUT TRISTATE
= out, INOUT = inout, FEEDTHRU = inout, and the oaTermType unknown = inout.
Type: enum
Enum Values: in out inout internal
Default: ""
Edit: No

is_always_on

This pg_base_pin is an always on power pin. This attribute can be set by liberty files.
Type: bool
Default: ""
Edit: No

name

The name of this pg_base_pin with the base_cell name (e.g. and2/vdd).
Type: string
Default: ""
Edit: No

obj_type

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The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (pg_base_pin)
Default: ""
Edit: No

pg_type

The type of the power or ground pin from liberty data. PG pins with no liberty entry will have
"invalid".
Type: enum
Enum Values: primary_power primary_ground backup_power backup_ground
internal_power internal_ground pwell nwell deep_pwell deep_nwell invalid
Default: ""
Edit: No

physical_direction

Direction of this pin.

Type: enum
Enum Values: input output inout unknown feedthrough tristate
Default: ""
Edit: No

physical_pins

Physical pins for the pg_base_pin. One logical pg_base_pin can have multiple physical_pins
(equivalent to separate LEF or DEF PORT statements for one LEF or DEF PIN). Each
physical_pin normally has one shape, but may have multiple shapes that are all strongly
connected to each other. By default, at least one shape of each physical_pin should be
connected to the power-mesh.
Type: obj(physical_pin)*
Default: ""
Edit: No

route_bottom_preferred_layer

Specifies the preferred lowest routing layer. This attribute is a soft limit; that is, the router might
use a layer below the specified layer if necessary to complete routing. You can set
route_preferred_layer_effort to determine how strict the router needs to honor this limit. This
attribute is intended for usage on always-on power pins that are routed by the signal router
rather than the power router (all instances of this pg_base_pin will have the same constraint).
Type: obj(layer)
Default: ""
Edit: Yes

route_max_fanout

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Specifies the maximum fanout value for each “steiner tree” for trunk routing (e.g. route_pattern
= trunk). This attribute is intended for usage on always-on power pins that are routed by the
signal router rather than the power router (all instances of this pg_base_pin will have the same
constraint).
Type: int
Default: 0
Edit: Yes

route_pattern

Specifies the routing pattern. This attribute is intended for usage on always-on power pins that
are routed by the signal router rather than the power router (all instances of this pg_base_pin
will have the same constraint).
steiner: Routes all pins with a single Steiner tree.
trunk: Routes pins in clusters to the nearest special_route trunk on the net.
Type: enum
Enum Values: steiner trunk
Default: steiner
Edit: Yes

route_preferred_layer_effort

Determines how much effort the router uses to meet the preferred layer limits. Use this attribute
with route_top_preferred_layer and route_bottom_preferred_layer attributes. Higher values
will make the router try to obey the preferred routing layer range more strongly at the expense
of more congestion and longer total routing length. This attribute is intended for usage on
always-on power pins that are routed by the signal router rather than the power router (all
instances of this pg_base_pin will have the same constraint).
Type: enum
Enum Values: low medium high
Default: low
Edit: Yes

route_rule

The route_rule (e.g. LEF or DEF NONDEFAULTRULE) to use. This attribute is intended for
usage on always-on power pins that are routed by the signal router rather than the power
router (all instances of this pg_base_pin will have the same constraint).
Type: obj(route_rule)
Default: ""
Edit: Yes

route_stripe_layer_range

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Limits the signal routing to connect to special_wires in the given layer range.
Exactly two layers should be given for the bottom and top layers in the range. For example,
{metal3 metal5} means the router will only connect to special_wires on layers metal3 to
metal5. The <layer> names can be input as a DPO name ‘layer:metal3’ or a layer name
‘metal3’, or as a layer index ‘3’. The output is always in a DPO name format like {layer:metal3
layer:metal5}. This attribute is intended for usage on always-on power pins that are routed by
the signal router rather than the power router (all instances of this pg_base_pin will have the
same constraint).
Type: obj(layer)*
Default: {}
Edit: Yes

route_top_preferred_layer

Specifies the preferred highest layer for routing. This attribute is a soft limit; that is, the router
might use a layer above the specified layer if necessary to complete routing. You can set
route_preferred_layer_effort to determine how strictly the router should honor this limit. This
attribute is intended for usage on always-on power pins that are routed by the signal router
rather than the power router (all instances of this pg_base_pin will have the same constraint).
Type: obj(layer)
Default: ""
Edit: Yes

taper_rule

The taper route_rule for the pg_pin. By default, if tapered routing is needed to access the pin,
the default route_rule will be used unless this attribute is set (see LEF MACRO PIN
TAPERRULE).
Type: obj(route_rule)
Default: ""
Edit: No

tied_to

If this pg_base_pin is a substrate bias-pin (e.g. pg_type is nwell or pwell), and it is internally
tied-to a "master" PG pin, this specifies the PG pin name (e.g. an nwell pin might have tied_to
= vdd if it is internally connected to the vdd pin).
Type: string
Default: ""
Edit: No

use

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Database Objects--pg_pin

Indicates how this pg_base_pin is used from the LEF USE value or OA equivalent. Only
power or ground enum values make sense in normal usage, but if there are conflicts between
Liberty and LEF/OA definitions, you may have pg_base_pins that are marked in LEF/OA with
the other values.
Type: enum
Enum Values: signal analog power ground clock
Default: ""
Edit: No

pg_pin

Parent Objects
inst, design, root

Definition
Power or ground pin information

Attribute Description

base_name

The base name for this pg_pin without the base_cell name (e.g. vdd).
Type: string
Default: ""
Edit: No

escaped_name

The escaped name of this pg_pin.

Type: string
Default: ""
Edit: No

hnet

The hierarchical net connected to this pg_pin.

Type: obj(hnet)
Default: ""
Edit: No

inst

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The inst containing this pg_pin.

Type: obj(inst)
Default: ""
Edit: No

name

The pg_pin name including the inst path (e.g. i1/i2/vdd)

Type: string
Default: ""
Edit: No

net

The net connected to this pg_pin.

Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (pg_pin)
Default: ""
Edit: No

pg_base_pin

The corresponding pg_base_pin on the base_cell for this pg_pin.

Type: obj(pg_base_pin)
Default: ""
Edit: No

route_max_fanout

Specifies the maximum fanout value for each “steiner tree” for trunk routing (e.g. route_pattern
= trunk). Normally, every pg_pin instantiated by the same pg_base_pin honors the same max
fanout. So user only needs to set it on the pg_base_pin. For the few cases where pg_pin has
different requirement than the pg_base_pin, NanoRoute will honor the one on pg_pin. This is
intended for usage on always-on power pins routed by the signal router rather than the power
router, It is most commonly used during late ECO routing to meet EM and IR limits by forcing
an isolated pg_pin into its own “cluster” by setting the value to 1.
Type: int
Default: 0
Edit: Yes

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Database Objects--physical_pin

physical_pin

Parent Objects
pg_base_pin, base_pin, port

Definition
physical pin

Attribute Description

class

Physical pin class

Type: enum
Enum Values: undefined none core bump
Default: ""
Edit: No

layer_shapes

List of layer_shapes that define the terminal pin geometries.

Type: obj(layer_shape)*
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (physical_pin)
Default: ""
Edit: No

port_number

The port number for geometries under the physical_pin.

Type: int
Default: ""
Edit: No

shape_vias

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List of shape_vias that define the terminal pin geometries.

Type: obj(shape_via)*
Default: ""
Edit: No

Parent Objects
marker, clock, skew_group, hinst, arc, hnet, timing_point, design, bus_sink_group, clock_tree, root,
timing_path, inst, net

Definition
Instance terminal

Attribute Description

actual_latency_early_fall_max

Returns the computed early falling clock latency to this clock pin. If the analysis mode is set to
best-case/worst-case, the value will be the Setup capture latency. When operating in OCV
mode, the max qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_early_fall_min

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Returns the computed early falling clock latency to this clock pin. If the analysis mode is set to
best-case/worst-case, the value will be the Hold launch latency. When operating in OCV
mode, the min qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_early_rise_max

Returns the computed early rising clock latency to this clock pin. If the analysis mode is set to
best-case/worst-case, the value will be the Setup capture latency. When operating in OCV
mode, the max qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_early_rise_min

Returns the computed early rising clock latency to this clock pin. If the analysis mode is set to
best-case/worst-case, the value will be the Hold launch latency. When operating in OCV
mode, the min qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_late_fall_max

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Database Objects--pin

Returns the computed late falling clock latency to this clock pin. If the analysis mode is set to
best-case/worst-case, the value will be the Setup launch latency. When operating in OCV
mode, the max qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_late_fall_min

Returns the computed late falling clock latency to this clock pin. If the analysis mode is set to
best-case/worst-case, the value will be the Hold capture latency. When operating in OCV
mode, the min qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_late_rise_max

Returns the computed late rising clock latency to this clock pin. If the analysis mode is set to
best-case/worst-case, the value will be the Setup launch latency. When operating in OCV
mode, the max qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_late_rise_min

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Returns the computed late rising clock latency to this clock pin. If the analysis mode is set to
best-case/worst-case, the value will be the Hold capture latency. When operating in OCV
mode, the min qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_max_fall

Returns the latest falling arrival time to the specified pin across all concurrent MMMC views.
You can use -index to determine the worst arrival for a specific view. You can also use -index
to get the latest arrival time related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_max_rise

Returns the latest rising arrival time to the specified pin across all concurrent MMMC views.
You can use -index to determine the worst arrival for a specific view. You can also use -index
to get the latest arrival time related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_mean_max_fall

In SOCV analysis mode, this returns the mean value of the latest falling arrival time to the
specified pin across all concurrent MMMC views. You can use -index to determine the latest
arrival for a specific view. You can also use -index to get the worst arrival time related to a
specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_mean_max_rise

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In SOCV analysis mode, this returns the mean value of the latest rising arrival time to the
specified pin across all concurrent MMMC views. You can use -index to determine the latest
arrival for a specific view. You can also use -index to get the worst arrival time related to a
specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_mean_min_fall

In SOCV analysis mode, this returns the mean value of the earliest falling arrival time to the
specified pin across all concurrent MMMC views. You can use -index to determine the earliest
arrival for a specific view. You can also use -index to get the earliest arrival time related to a
specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_mean_min_rise

In SOCV analysis mode, this returns the mean value of the earliest rising arrival time to the
specified pin across all concurrent MMMC views. You can use -index to determine the earliest
arrival for a specific view. You can also use -index to get the earliest arrival time related to a
specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_min_fall

Returns the earliest falling arrival time to the specified pin across all concurrent MMMC views.
You can use -index to determine the worst arrival for a specific view. You can also use -index
to get the earliest arrival time related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_min_rise

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Returns the earliest falling arrival time to the specified pin across all concurrent MMMC
views.You can use -index to determine the worst arrival for a specific view. You can also use -
index to get the worst arrival time related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_sigma_max_fall

In SOCV analysis mode, this returns the variation component of the latest falling arrival time to
the specified pin across all concurrent MMMC views. You can use -index to determine the
latest arrival for a specific view. You can also use -index to get the worst arrival time related to
a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_sigma_max_rise

In SOCV analysis mode, this returns the variation component of the latest rising arrival time to
the specified pin across all concurrent MMMC views. You can use -index to determine the
latest arrival for a specific view. You can also use -index to get the worst arrival time related to
a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_sigma_min_fall

In SOCV analysis mode, this returns the variation component of the earliest falling arrival time
to the specified pin across all concurrent MMMC views. You can use -index to determine the
earliest arrival for a specific view. You can also use -index to get the earliest arrival time
related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_sigma_min_rise

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arrival_window

Returns a list of the earliest and latest, rising and falling arrival times per clock phase at the
pin across all concurrent MMMC views. You can use -index to make the arrival times specific
to a given view
Type: string
Allowed -index values: analysis_view clock
Default: ""
Edit: No

base_name

The name at the base of a hierarchical name. So the base_name of i1/i2/i3 is i3.
Type: string
Default: ""
Edit: No

base_pin

pointer to equivalent base pin

Type: obj(base_pin)
Default: ""
Edit: No

capacitance_max_fall

Returns the maximum value of the falling capacitance range of the corresponding library pin.
You can use -index to return the value from a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

capacitance_max_rise

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Returns the maximum value of the rising capacitance range of the corresponding library pin.
You can use -index to return the value from a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

capacitance_min_fall

Returns the minimum value of the falling capacitance range of the corresponding library pin.
You can use -index to return the value from a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

capacitance_min_rise

Returns the minimum value of the rising capacitance range of the corresponding library
pin.You can use -index to return the value from a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

cell_name

Returns the name of the instance of the instance pin mentioned.

Type: string
Allowed -index values: analysis_view clock
Default: ""
Edit: No

clocks

Returns a list of all of the clock objects arriving at the pin. You can use -index to return the
value from a specific analysis view.
Type: obj(clock)*
Allowed -index values: analysis_view clock
Default: ""
Edit: No

constant

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Returns if this pin has a constant logic value of 1'b0 or 1'b1 directly on the pin in the Verilog. If
it is no_constant, and it is connected to a net, you must also check the net .constant value to
see if the net driving the pin is constant.
Type: enum
Enum Values: 0 1 no_constant
Default: ""
Edit: No

constant_value

Returns a constant value of 0 or 1 if logic state has been asserted or propgated to this pin. You
can use -index to return the value from a specific analysis view.
Type: int
Allowed -index values: analysis_view clock
Default: ""
Edit: No

cts_add_port_driver

Specifies a cell type so that a cell inst can to be added above an output port or below an input
port.
The port is specified by the argument pin.
If the pin specified is not a design IO pin or it is not in the clock network then CCOpt will emit
a warning
and will not add cell insts at that position.
Type: string
Default: ""
Edit: Yes

cts_annotated_delay_to

Override any clock tree timing engine computed cell arc or net arc delays to this pin, in a
similar manner to SDC set_annotated_delay.
Type: string
Allowed -index values: delay_corner
Default: ""
Edit: Yes

cts_annotated_transition

Override any clock tree timing engine computed transition at this pin, in a similar manner to
SDC set_annotated_transition.
Type: string
Allowed -index values: delay_corner
Default: auto
Edit: Yes

cts_assign_clock_tree

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Can be used to make sure a clock tree sink pin gets driven by a particular
clock tree. The clock tree can alternatively be specified as the tree's root
pin, in case extraction renumbers the clock trees defined from a single SDC
clock.
By default CCOpt automatically selects appropriate pins.
Valid values: cts_clock_tree | list of pins
Type: string
Default: ""
Edit: Yes

cts_case_analysis

Specifies a constant value to be used as pin signal when analyzing timing

within CTS. Only applies to input pins of cells in the clock tree. If set to
'none' (the default), CTS will consider the input as non-constant.
Valid values: 0 1 none
Type: string
Default: auto
Edit: Yes

cts_clock_tree

The clock tree to which this object belongs. Flops do not belong to a clock
tree, but their clock pins do.
Valid values: cts_clock_tree
Type: obj(clock_tree)
Default: ""
Edit: No

cts_clock_trees

A list of clock trees the pin is contained within. This includes parents of
generated clock trees and all relevant parents when clock trees overlap.
Valid values: list cts_clock_tree
Type: obj(clock_tree)
Default: ""
Edit: No

cts_effective_routing_preference

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Returns the pin's effective routing preference; one of leaf, trunk, top, none. The value "none"
can be returned for pins that have no preference such as antenna diodes or load cap inputs.
The effective routing preference value for a pin does not solely determine the net_type of the
driving net if the net has multiple fanout. The fanout routing preferences for all sinks are taken
into account when determining the net_type for the net as a whole.
Type: string
Default: ""
Edit: No

cts_flexible_htree

The flexible HTree, if any, associated with the given object.

Type: obj(flexible_htree)*
Default: ""
Edit: No

cts_is_sdc_clock_root

Specifies whether the given pin is the root (source pin) of an SDC clock.
The create_clock_tree_spec populates this attribute with the
location of the SDC clock root (source) pins.
This attribute controls the behavior of clock tree definition commands
create_clock_tree and create_generated_clock_tree, when the
-stop_at_sdc_clock_roots argument is specified. In such a case, pins and ports for
which this attribute is true will be treated as being SDC clock root
pins.
Valid values: true false
Type: bool
Default: false
Edit: Yes

cts_net_unbufferable_reasons

This attribute contains a list of reasons why CCOpt was not able to buffer the
clock net attached to the specified pin.
Valid values: string
Type: string
Default: ""
Edit: No

cts_node_type

node type of pin within cts graph

Type: string
Default: ""
Edit: No

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cts_pin_capacitance_sources

List of the places the capacitance could be retrieved from.

Requesting this attribute for a pin not in the clock tree will result in an error.
The possible places are:
- library - CTS will retrieve capacitance values from the library for one or more
timing_corner/event combinations.
- cts_capacitance_override - CTS will retrieve capacitance values from the
cts_capacitance_override attribute for one or more timing_corner/event combinations.
- cts_blackbox_default_load_base_pin - CTS will retrieve capacitance values from the
cts_blackbox_default_load_base_pin attribute for one or more timing_corner/event
combinations.
Type: string
Default: ""
Edit: No

cts_pin_insertion_delay

The amount of insertion delay under this pin. Clock tree synthesis will attempt to make the
insertion delay to this pin less than that to other sinks in the same skew group by this amount if
a positive value is set. A negative value should be used if you would like the insertion delay to
this pin to be greater than that to other sinks. The value 'auto' means there is no insertion
delay offset for the pin.
Valid values: double | auto
Type: string
Allowed -index values: delay_corner
Default: auto
Edit: Yes

cts_routing_trunk_override

Prefer trunk routing rules for this pin. Only applies to clock tree sinks.
Valid values: true false
Type: bool
Default: false
Edit: Yes

cts_sink_type

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The type of sink this pin represents.

Valid values are as follows:
auto The sink type will be automatically determined by CCOpt.
through Through pin. Trace the clock tree through this pin.
stop Stop pin. When defining clock trees, CCOpt stops searching for
parts of the clock tree at stop pins.
ignore Ignore pin. CCOpt stops searching for parts of the clock tree at
ignore pins and it does not attempt to balance the insertion delay
of ignore pins.
exclude Exclude pin. Exclude this pin from the clock tree.
Valid values: auto through stop ignore exclude
Type: string
Default: auto
Edit: Yes

cts_sink_type_effective

Indicates how CCOpt will treat a given pin, taking into account both its cts_sink_type_implicit,
and any cts_sink_type settings.
Setting a non-default value for the cts_sink_type attribute will override the
cts_sink_type_implicit attribute.
Type: string
Default: auto
Edit: No

cts_sink_type_implicit

Indicates the type of sink that CCOpt classified this pin as. Note that the cts_sink_type attribute
can override these internal classifications.
Possible values are:
exclude Indicates that this pin is a sink which represents a non-clock pin.
ignore Indicates that CCOpt has determined not to search for more clock tree through this pin.
Additionally, this pin will not be balanced.
stop Indicates that CCOpt has determined not to search for more clock tree through this pin.
An empty value for this attribute indicates either that this pin is either not a sink, or that it is a
sink that is not implicitly exclude or ignore or stop.
Type: string
Default: exclude
Edit: No

cts_sink_type_reasons

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The reasons why this pin has the given cts_sink_type.

This attribute is configured by the create_clock_tree_spec command in order
to record the reasons that the cts_sink_type attribute has been configured for the
given pin.
This attribute is a list of values. Valid values are as follows:
auto The cts_sink_type attribute is set to 'auto'
implicit The pin is an implicit sink (flop/latch)
user The user has set the cts_sink_type attribute
design_io This pin is a design I/O
multiple_outputs This pin is on an instance with multiple outputs,
and the cts_spec_config_trace_through_to attribute has not been set
set_disable_timing SDC set_disable_timing stops the clock at this pin
set_case_analysis SDC set_case_analysis stops the clock at this pin
generated_clock_tree This pin is the generator input to an SDC generated clock
no_sdc_clock The SDC clock is stopped at this pin for other reasons
ilm The create_clock_tree_spec command has detected an ILM below this pin
Valid values: auto implicit user design_io multiple_outputs set_disable_timing
set_case_analysis generated_clock_tree no_sdc_clock ilm
Type: string
Default: auto
Edit: Yes

cts_skew_groups_active

Returns the list of active skew groups for this pin.

For sink pins, this attribute lists both skew groups that pass through this pin
and skew groups for which this sink is an endpoint.
For non-sink pins, shows skew groups that pass through this pin.
Valid values: list skew_groups
Type: obj(skew_group)*
Default: ""
Edit: No

cts_skew_groups_active_sink

Returns the list of skew groups for which this pin is an active sink.
For sink pins, this attribute lists the skew groups for which this sink is an
endpoint. Skew groups that pass through this pin are not included.
For non-sink pins, this attribute always returns null.
Valid values: list skew_groups
Type: obj(skew_group)*
Default: ""
Edit: No

cts_skew_groups_constraining

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The list of delay-constraining skew groups which are active at this pin.
This attribute reports similar data to
cts_skew_groups_active. The only difference is that
the reporting-only skew groups are not included in this attribute's value.
For sink pins, this attribute lists both delay-constraining skew
groups that pass through this pin and delay-constraining skew groups for which
this sink is an endpoint.
For non-sink pins, shows delay-constraining skew groups that pass through this pin.
Valid values: list skew_groups
Type: obj(skew_group)*
Default: ""
Edit: No

cts_skew_groups_constraining_sink

The list of delay-constraining skew groups for which this pin is an active sink.
This attribute lists the delay-constraining skew groups for which this pin is
an active sink. This attribute reports similar data to
cts_skew_groups_active_sink. The only difference
is that the reporting-only (constrains none) skew groups are not included in
this attribute's value.
For sink pins, this attribute lists the delay-constraining skew
groups for which this sink is an endpoint. Skew groups that pass through this
pin are not included.
For non-sink pins, this attribute always returns null.
Valid values: list skew_groups
Type: obj(skew_group)*
Default: ""
Edit: No

cts_skew_groups_ignore

The list of skew groups for which paths through this pin are ignored.
Valid values: list skew_groups
Type: obj(skew_group)*
Default: ""
Edit: No

cts_skew_groups_sink

The list of skew groups for which this pin is a sink.

Valid values: list skew_groups
Type: obj(skew_group)*
Default: ""
Edit: No

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cts_skew_groups_source_pin

The list of skew groups for which this clock tree or pin is specified as a
source.
Valid values: list skew_groups
Type: obj(skew_group)*
Default: ""
Edit: No

cts_spec_config_trace_through_to

Clock tree definition will, by default, not continue through certain types of
cell arc (for instance, the clock to Q arc in a DFF). This attribute allows
you to override this default behavior, permitting the clock tree to trace through
such a cell.
The attribute should be configured on the input pin at which the
clock arrives. The value of the attribute specifies the output
pin to which the clock should propagate. The specified output pin must be
another pin on the same instance. The output pin may be specified either by its
fully qualified name (i.e. inclusive of the instance name), or else simply by
its local (cell-relative) name.
There must be a pre-existing (library-defined) chain of one or more delay arcs
that connect the input and output pins together. It is not possible to use
trace_through_to to synthesize delay arcs.
If multiple input pins are annotated on a given instance, the value of
trace_through_to at each of those pins must select the same output pin:
i.e. the configuration must identify a single clock output for the instance. If
multiple clock outputs are required then trace_through_to should not be used:
instead define a generated clock tree at each of the clock-carrying outputs.
If the configuration of trace_through_to settings for a given instance does not
meet these requirements, a warning will be issued and the settings for that
instance will be ignored.
Note: if both trace_through_to and library_trace_through_to are applicable at a
given netlist instance pin, the trace_through_to value takes precedence.
Valid values: pin
Type: string
Default: ""
Edit: Yes

cts_top_fanout_count_override

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The number of clock sinks this sink counts for when applying the top routing rules.
Note that this attribute is only valid for sink pins, and it returns auto for non-sink pins.
For a sink pin, a non-auto value means that this sink is counted as though it were multiple
sinks, for the purposes of determining which nets should have top routing. An auto value for
a sink pin means that the sink counts as a single sink.
Valid values: integer > 0
Type: string
Default: auto
Edit: Yes

cts_top_fanout_transitive_count

The number of clock sinks in the transitive fanout of the pin as counted for applying the top
routing rules.
This attribute is very similar to the cts_transitive_fanout attribute but counts sink fanout using
the
cts_top_fanout_count_override attribute instead of always counting sinks as a single item of
fanout.
Requesting this attribute for a pin not in the clock tree will result in an error.
Valid values: integer
Type: int
Default: 0
Edit: No

cts_transitive_fanout

The number of clock sinks in the transitive fanout of the pin, within the clock tree.
Requesting this attribute for a pin not in the clock tree will result in an error.
Valid values: int
Type: int
Default: 0
Edit: No

cts_virtual_delay_early_fall

The amount of virtual delay that has been applied under this pin.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

cts_virtual_delay_early_rise

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The amount of virtual delay that has been applied under this pin.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

cts_virtual_delay_late_fall

The amount of virtual delay that has been applied under this pin.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

cts_virtual_delay_late_rise

The amount of virtual delay that has been applied under this pin.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

delay_max_fall

Returns the maximum falling delay. You can use -index to return the value from a specific
analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

delay_max_rise

Returns the maximum rising delay. You can use -index to return the value from a specific
analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

delay_min_fall

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Returns the minimum falling delay. You can use -index to return the value from a specific
analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

delay_min_rise

Returns the minimum rising delay. You can use -index to return the value from a specific
analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

direction

Pin's direction from the corresponding base_pin. It can be in, out, inout or internal. Internal
means it is an internal pin from a .lib file for the timing model, and is not part of the netlist.
Type: enum
Enum Values: internal in out inout
Default: ""
Edit: No

dont_invert_phase

Type: bool
Default: false
Edit: Yes

dont_touch

The preservation status of a pin during optimization. A preserved pin means the logical
function of the pin must be preserved to maintain a simulation or test-point pin in the netlist.
However, the name does not need to be preserved.
Supported values:
false: Unconstrained
true: Cannot add/remove ports
delete_ok: Can delete ports (if they have no fanout)
invert_ok: We cannot delete, duplicate, or add but can change the polarity
none: No user setting; will inherit from the module/hinst
Type: enum
Enum Values: none false true delete_ok invert_ok
Default: none
Edit: Yes

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effective_stack_via_rule

The stack_via_rule that is expected to be used by the router for connecting to this pin. This
value is derived from the other pin and base_pin attributes related to stack via.
Type: obj(stack_via_rule)
Default: ""
Edit: No

escaped_name

fanout_load

Returns the fanout load for the pin. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

from_arcs

Returns a list of arc objects for which this pin is the starting pin of the timing arc.
Type: obj(arc)*
Default: ""
Edit: No

hdl_name

This is the original RTL name for this pin. It is used to map RTL simulation results with RTL
names to the current netlist for switching activity analysis. It is only maintained properly on the
output pins of sequential cells. Optimization will copy this name during any multi-bit merge or
splitting transforms to the equivalent pin, but not on output pins of combinational cells. The
is_phase_inverted attribute will be flipped if the phase is inverted.
Type: string
Default: ""
Edit: Yes

hierarchical_level

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Returns hierarchical level for an Instance Pin.

Type: int
Allowed -index values: analysis_view clock
Default: ""
Edit: No

hnet

pointer to the hnet connected to the pin

Type: obj(hnet)
Default: ""
Edit: No

hold_uncertainty

Returns the most conservative uncertainty of all possible uncertainty assertions associated
with the pin. You can use -index to return the value from a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

initial_name

This will be used for verification of initial input netlist (post-synthesis) to any other netlist
generated during Innovus flow.
Type: string
Default: ""
Edit: Yes

input_signal_level

Returns the rail name associated with input pin.

Type: string
Allowed -index values: analysis_view clock
Default: ""
Edit: No

input_signal_level_voltage

Returns rail voltage of signal which is driving the input pin.

Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

inst

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pointer to the inst containing the pin

Type: obj(inst)
Default: ""
Edit: No

is_always_on

Returns a value of true if the pin is always on type pin.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_async

Returns a value of true if the pin is an asynchronous clear or preset pin.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_clear

Returns a value of true if the pin is an asynchronous clear pin.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_clock

Returns a value of true if the pin has the Liberty pin attribute: clock .
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_clock_gating

Returns a value of true if the pin is defined as a pin of a clock gating cell. You can use -index
to return the value from a specific analysis view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_clock_gating_clock

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Returns a value of true if the pin is defined as a clock pin of a clock gating cell.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_clock_gating_enable

Returns a value of true if the pin corresponds to the enable pin of a clock gating cell.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_clock_used_as_clock

Returns a value of true if the pin lies in the clock network and at least one of the clocks arriving
at the pin is used as a clock in the downstream network of the pin. You can use -index to
return the value for a specific analysis view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_clock_used_as_data

Returns a value of true if the pin lies in the clock source path and at least one of the clocks
arriving on the pin is used as data in the downstream network of the pin. You can use -index to
return the value for a specific analysis view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_constant_in_all_views

Returns true if logic state has been asserted or propgated to this pin in all the views
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_constant_in_any_view

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Returns true if logic state has been asserted or propgated to this pin in atleast one view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_data

Returns a value of true if the pin is a data pin (that is, is not a clock pin).
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_disable_timing

Returns a value of true if the pin's timing has been disabled. You can use -index to return the
value for a specific analysis view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_fall_edge_triggered_clock

Returns a value of true if the pin is a clock pin of a flop, and is triggered by the falling edge of a
clock.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_fall_edge_triggered_data

Returns a value of true if the pin corresponds to the data pin of a fall edge triggered device.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_hierarchical

is_hierarchical
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

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is_initial_phase_inverted

This indicates if the initial RTL phase has been inverted.

Type: bool
Default: false
Edit: Yes

is_inside_partition

Returns whether pin is in partition or not.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_internal_disable

Returns the internal disabled assertion on endpoints. Such endpoints will have no timing
computed on them.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_isolation_cell_clock

Returns true if a clock pin is part of an isolatoin cell,

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_isolation_cell_data

Returns a value of true if the pin is isolation data pin type.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_isolation_cell_enable

Returns a value of true if the pin is isolation enable pin type.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_latency_network_pin

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Returns a value of true if the pin has latency phase propogated to it.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_level_shifter_data

Returns a value of true if the pin is level shifter data pin type.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_level_shifter_enable

Returns a value of true if the pin is level shifter enable pin type.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_multiple_clock_fanin_point

Returns a value of true if multiple clock phases converge at the pin. You can use -index to
return the value for a specific analysis view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_mux_select_pin

Returns the is_mux_select_pin property for a pin. You can use -index to return the value for a
specific view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_negative_level_sensitive_clock

Returns a value of true if the library pin is an enable pin of an active low level-sensitive device.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

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is_negative_level_sensitive_data

Returns a value of true if the pin is a data pin of an active low level-sensitive device.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_owner

Returns true if client is the owner for pin in distributed STA.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_phase_inverted

Identifies the Instance for which phase is inverted during optimizations.

Type: bool
Default: false
Edit: Yes

is_positive_level_sensitive_clock

Returns a value of true if the library pin is an enable pin of an active high level-sensitive
device.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_positive_level_sensitive_data

Returns a value of true if the pin is a data pin of an active high level-sensitive device.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_power_mode_disabled

Returns true if power mode is disabled

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_preset

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Returns a value of true if the pin is a preset pin.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_propagated_clock

Returns a value of true if there is an explicit set_propagated_clock assertion at the pin. You
can use -index to return the value for a specific analysis view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_rise_edge_triggered_clock

Returns a value of true if the pin is a clock pin of a flop, and is triggered by the rising edge of a
clock.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_rise_edge_triggered_data

Returns a value of true if the pin corresponds to the data pin of a rise edge-triggered device.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_sequential_merged

Identifies the Instance which is cloned or duplicated and source of duplication.

Type: string
Default: ""
Edit: Yes

is_shared

Returns true if pin is shared across clients in distributed STA

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_special

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pin is belong DEF SPECIALNETS section

Type: bool
Default: false
Edit: Yes

is_tristate

Returns a value of true if the pin has the three_state attribute in the Liberty timing library.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_tristate_enable

Returns a value of true if the pin is the source pin of timing arcs with either the
three_state_enable or three_state_disable attribute in the Liberty timing library.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_tristate_output

Returns a value of true if the pin corresponds to a three-state output pin.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_valid_for_reports

Returns the pin is valid for reporting.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

latch_time_given

In latch-based analysis, this returns the value by which the arrival time on this pin is adjusted
to account for time borrowed at the previous stage. You can use -index to return the value for a
specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

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layer

Layer of the pin. For pins with more than one shape, it is the layer of the first shape found in
the DB. This is also the same shape used for the .location value. If the pin has no shapes or
vias defined, then {} is returned.
Type: obj(layer)
Default: ""
Edit: No

lib_binding_info_max

Reports the type of bindinf, i.e. Match/Interpolation/Extrapolation/UserSpecified

Type: string
Allowed -index values: analysis_view clock
Default: ""
Edit: No

lib_binding_info_min

Reports the type of bindinf, i.e. Match/Interpolation/Extrapolation/UserSpecified

Type: string
Allowed -index values: analysis_view clock
Default: ""
Edit: No

lib_pins

Returns a list of library pin (lib_pin) objects which are associated with this pin.
Type: obj(lib_pin)*
Default: ""
Edit: No

location

Location of the pin. The returned point will overlap some part of the pin shape. For pins with
more than one shape, the point overlaps the first shape found in the DB. This is also the same
shape used for the .layer value. If the pin has no shapes or vias defined, then the inst .location
is returned.
Type: point
Default: ""
Edit: No

max_capacitance

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Returns the maximum capacitance limit for the pin. You can use -index to return the value for a
specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

max_fanout

Returns the maximum fanout load that the pin can drive. This value is set using
set_max_fanout or the default_max_fanout library attribute. You can use -index to return the
value for a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

max_time_borrow

In latch-based analysis, returns the maximum time that a path arriving at this latch input can
borrow from the next stage - as specified by set_max_time_borrow. You can use -index to
return the value for a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

max_transition

Returns the maximum transition time limit specified for the pin. You can use -index to return
the value for a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

min_capacitance

Returns the minimum capacitance limit for the pin. You can use -index to return the value for a
specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

min_fanout

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Returns the minimum fanout design rule limit of the corresponding library pin. You can use -
index to return the value for a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

min_transition

Returns the minimum transition time limit specified for the pin. You can use -index to return the
value for a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

name

net

pointer to the net connected to the pin

Type: obj(net)
Default: ""
Edit: No

network_latency_fall_max

Returns the maximum fall insertion delay specified by an explicit set_clock_latency at the pin.
You can use -index to return the value for a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

network_latency_fall_min

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Returns the minimum fall insertion delay specified by an explicit set_clock_latency at the pin.
You can use -index to return the value for a specific analysis view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

network_latency_rise_max

Returns the maximum rise insertion delay specified by an explicit set_clock_latency at the pin.
You can use -index to return the value for a specific analysis view and/or clock
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

network_latency_rise_min

Returns the minimum rise insertion delay specified by an explicit set_clock_latency at the pin.
You can use -index to return the value for a specific analysis view and/or clock
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (pin)
Default: ""
Edit: No

output_signal_level

Returns the rail name associated with output pin.

Type: string
Allowed -index values: analysis_view clock
Default: ""
Edit: No

power_domain

The parent power domain of the pin (equivalent to Design Browser effPD)
Type: obj(power_domain)
Default: ""
Edit: No

power_rail_voltage_inout_input_max

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Reports power rail voltage for input part of bidi pins/ports for maximum operating
condition.You can use -index to return the value for a specific analysis view
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

power_rail_voltage_inout_input_min

Reports power rail voltage for input part of bidi pins/ports for minimum operating condition.You
can use -index to return the value for a specific analysis view
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

power_rail_voltage_max

Reports power rail voltage for maximum operating condition for bidirectional, input and output
pins. For bidirectional pins, the power rail voltage for output signal is reported. You can use -
index to return the value for a specific analysis view
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

power_rail_voltage_min

Reports power rail voltage for minimum operating condition for bidirectional, input and output
pins. For bidirectional pins, the power rail voltage for output signal is reported. You can use -
index to return the value for a specific analysis view
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

setup_uncertainty

Returns the most conservative uncertainty of all possible uncertainty assertions associated
with the pin. You can use -index to return the value for a specific analysis view
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_max

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Returns the worst slack across all concurrent MMMC views for Setup-style late data path
checks. You can use -index to return the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_max_edge

Returns the data edge of the path responsible for the slack_max value. You can use -index to
return the value for a specific view and/or clock.
Type: string
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_max_fall

Returns the worst falling slack across all concurrent MMMC views for Setup-style late data
path checks. You can use -index to return the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_max_rise

Returns the worst rising slack across all concurrent MMMC views for Setup-style late data
path checks. You can use -index to return the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_mean_max

In SOCV analysis, this returns the mean component of the worst slack across all concurrent
MMMC views for Setup-style late data path checks. You can use -index to return the value for
a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_mean_max_fall

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In SOCV analysis, this returns the mean component of the worst falling slack across all
concurrent MMMC views for Setup-style late data path checks. You can use -index to return
the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_mean_max_rise

In SOCV analysis, this returns the mean component of the worst rising slack across all
concurrent MMMC views for Setup-style late data path checks. You can use -index to return
the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_mean_min

In SOCV analysis, this returns the mean component of the worst slack across all concurrent
MMMC views for Hold-style early data path checks. You can use -index to return the value for
a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_mean_min_fall

In SOCV analysis, this returns the mean component of the worst falling slack across all
concurrent MMMC views for Hold-style early data path checks. You can use -index to return
the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_mean_min_rise

In SOCV analysis, this returns the mean component of the worst rising slack across all
concurrent MMMC views for Hold-style early data path checks. You can use -index to return
the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

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slack_min

Returns the worst slack across all concurrent MMMC views for Hold-style early data path
checks. You can use -index to return the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_min_edge

Returns the data edge of the path responsible for the slack_min value. You can use -index to
return the value for a specific view and/or clock.
Type: string
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_min_fall

Returns the worst falling slack across all concurrent MMMC views for Hold-style early data
path checks. You can use -index to return the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_min_rise

Returns the worst rising slack across all concurrent MMMC views for Hold-style early data
path checks. You can use -index to return the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_sigma_max

In SOCV analysis, this returns the variation component of the worst slack across all concurrent
MMMC views for Setup-style late data path checks.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_sigma_max_fall

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In SOCV analysis, this returns the variation component of the worst falling slack across all
concurrent MMMC views for Setup-style late data path checks. You can use -index to return
the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_sigma_max_rise

In SOCV analysis, this returns the variation component of the worst rising slack across all
concurrent MMMC views for Setup-style late data path checks. You can use -index to return
the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_sigma_min

In SOCV analysis, this returns the variation component of the worst slack across all concurrent
MMMC views for Hold-style early data path checks. You can use -index to return the value for
a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_sigma_min_fall

In SOCV analysis, this returns the variation component of the worst falling slack across all
concurrent MMMC views for Hold-style early data path checks. You can use -index to return
the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_sigma_min_rise

In SOCV analysis, this returns the variation component of the worst rising slack across all
concurrent MMMC views for Hold-style early data path checks. You can use -index to return
the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

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slew_max_fall

Returns the maximum slew time for falling transitions across all concurrent MMMC views. You
can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slew_max_rise

Returns the maximum slew time for rising transitions across all concurrent MMMC views. You
can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slew_mean_max_fall

In SOCV mode, returns the mean component of the maximum slew time for falling transitions
across all concurrent MMMC views. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slew_mean_max_rise

In SOCV mode, returns the mean component of the maximum slew time for rising transitions
across all concurrent MMMC views. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slew_mean_min_fall

In SOCV mode, returns the mean component of the minimum slew time for falling transitions
across all concurrent MMMC views. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slew_mean_min_rise

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In SOCV mode, returns the mean component of the minimum slew time for rising transitions
across all concurrent MMMC views. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slew_min_fall

Returns the minimum slew time for falling transitions across all concurrent MMMC views. You
can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slew_min_rise

Returns the minimum slew time for rising transitions across all concurrent MMMC views. You
can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slew_sigma_max_fall

In SOCV mode, returns the variation component of the maximum slew time for falling
transitions across all concurrent MMMC views. You can use -index to return the value for a
specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slew_sigma_max_rise

In SOCV mode, returns the variation component of the maximum slew time for rising
transitions across all concurrent MMMC views. You can use -index to return the value for a
specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slew_sigma_min_fall

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In SOCV mode, returns the variation component of the minimum slew time for falling
transitions across all concurrent MMMC views. You can use -index to return the value for a
specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slew_sigma_min_rise

In SOCV mode, returns the variation component of the minimum slew time for rising transitions
across all concurrent MMMC views. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_early_fall_max

Returns the maximum early fall source insertion delay specified by an explicit
set_clock_latency at the pin.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_early_fall_min

Returns the minimum early fall source insertion delay specified by an explicit
set_clock_latency at the pin. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_early_rise_max

Returns the maximum early rise source insertion delay specified by an explicit
set_clock_latency at the pin. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_early_rise_min

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Returns the minimum early rise source insertion delay specified by an explicit
set_clock_latency at the pin. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_late_fall_max

Returns the maximum late fall source insertion delay specified by an explicit
set_clock_latency at the pin. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_late_fall_min

Returns the minimum late fall source insertion delay specified by an explicit set_clock_latency
at the pin. You can use -index to return the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_late_rise_max

Returns the maximum late rise source insertion delay specified by an explicit
set_clock_latency at the pin. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_late_rise_min

Returns the minimum late rise source insertion delay specified by an explicit
set_clock_latency at the pin. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

stack_via_rule

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This value serves as a pin-specific override to use this stack_via_rule when connecting to this
pin. If set, it must match one of the elements from the stack_via_rule_list attribute of the
corresponding base_pin. The interpretation of this value depends on this pin's
stack_via_rule_required attribute.
stack_via_rule == {} && stack_via_rule_required == false: stack_via_rule does not affect the
choice.
stack_via_rule == stackrule1 && stack_via_rule_required == false: Router will prefer
stackrule1, but it may select another (or possibly none) if necessary to avoid design rule
violations.
stack_via_rule == {} && stack_via_rule_required == true: The required stack_via_rule is
empty, so the router will not use any stack_via_rule for connecting to this pin (even ignoring
stack_via_required on the base_pin if necessary).
stack_via_rule == stackrule1 && stack_via_rule_required == true: Router will use stackrule1,
even if it leads to design rule violations.
Type: obj(stack_via_rule)
Default: ""
Edit: Yes

stack_via_rule_required

Specifies whether the router must use this pin's stack_via_rule value. If false, the
stack_via_rule value will be preferred by the router, if true the stack_via_rule value is required
by the router. See the stack_via_rule attribute for more details.
Type: bool
Default: false
Edit: Yes

timing_case_computed_value

Returns the case computed value

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

timing_case_logic_value

Returns the case logic value

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

to_arcs

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Returns a list of arc objects where the current pin is the termination point of the arc
Type: obj(arc)*
Default: ""
Edit: No

user_constant_value

Returns constant values from netlist or constraints. You can use -index to return the value for a
specific view.
Type: int
Allowed -index values: analysis_view clock
Default: ""
Edit: No

pin_blockage

Parent Objects
design, root

Definition
Pin blockage objects

Attribute Description

layer

The layer that is being blocked

Type: obj(layer)
Default: ""
Edit: No

name

Partition pin blockage name

Type: string
Default: ""
Edit: No

obj_type

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The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (pin_blockage)
Default: ""
Edit: No

rect

Rectangle that define the pin_blockage shape.

Type: rect
Default: ""
Edit: No

pin_group

Parent Objects
design, pin_guide, root

Definition
Pin group

Attribute Description

base_pins

List of base pins associated with the group

Type: obj(base_pin)
Default: ""
Edit: No

exclude_pin

Indicates group pin exclude type(all_layer, same_layer, inclusive, all_layer_in_guided_area)

Type: enum
Enum Values: all_layer_in_guided_area all_layer same_layer inclusive
Default: ""
Edit: Yes

is_compact

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Indicate whether the pins in the group are assigned tightly together. By default, pins which are
part of a group and associated to a guide can be spread inside the guide based on the area
available and alignment to targets
Type: bool
Default: false
Edit: Yes

is_guided

Indicates if pin group is guided

Type: bool
Default: ""
Edit: No

is_spread

Indicates whether member pins distributed evenly

Type: bool
Default: ""
Edit: No

keep_out_space

Minimum spacing with foreign pins (Unit: track)

Type: int
Default: ""
Edit: No

name

Name of pin group

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (pin_group)
Default: ""
Edit: No

optimize_order

Name of pin group

Type: bool
Default: ""
Edit: No

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parent

The parent of the pin_group. It can be a design, a partition (if not committed yet), or base_cell
for a black_box.
Type: obj(design)* obj(partition)* obj(base_cell)*
Default: ""
Edit: No

pin_spacing

Minimum spacing between adjacent pins (Unit: track)

Type: int
Default: ""
Edit: No

pin_guide

Parent Objects
design, root

Definition
Pin guide

Attribute Description

area

Area of the pin guide as defined by the LEF MACRO SIZE or OVERLAP information
Type: area
Default: ""
Edit: No

layer_priority

layer priority
Type: bool
Default: ""
Edit: No

layers

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layers where pin_guide is present

Type: obj(layer)*
Default: ""
Edit: No

name

Name of pin guide

Type: string
Default: ""
Edit: No

net_group

net_group, if pin_guide is based on net_group otherwise NULL

Type: obj(net_group)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (pin_guide)
Default: ""
Edit: No

parent

The parent of the pin_guide. It can be a design, a partition (if not committed yet), or base_cell
for a black_box.
Type: obj(design)* obj(partition)* obj(base_cell)*
Default: ""
Edit: No

pin_group

pin_group, if pin_guide is based on pin_group otherwise NULL

Type: obj(pin_group)
Default: ""
Edit: No

rects

The rects that define the location of the pin_guide.

Type: rect*
Default: ""
Edit: No

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place_blockage

Parent Objects
design, root

Definition
Placement blockage(hard, soft, partial).

Attribute Description

density

The max placement density percent allowed inside this place_blockage. It must be in the
range of 5 to 100, in steps of 5. It is only valid if the type = partial or soft. For example, a partial
placement percentage of 75 percent means that up to 75 percent of placement density is
allowed in the area. If the type is not partial or soft, a value of 0 is returned.
Type: double
Default: ""
Edit: Yes

inst

The instance that the placement blockage is associated with (equivalent to DEF
BLOCKAGES + COMPONENT)
Type: obj(inst)
Default: ""
Edit: No

is_no_flop

Flip-flops and latches cannot be placed inside this place_blockage. Only has an effect if type
= partial.
Type: bool
Default: false
Edit: Yes

is_pushdown

This place_blockage has been pushed down from a higher level in the design hierarchy.
Type: bool
Default: false
Edit: Yes

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name

Name of placement blockage

Type: string
Default: ""
Edit: Yes

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (place_blockage)
Default: ""
Edit: No

rects

List of non-overlapping rectangles that defines the shape of place_blockage

Type: rect*
Default: ""
Edit: Yes

shapes

List of shapes of this placement blockage

Type: obj(shape)* obj(density_shape)*
Default: ""
Edit: No

type

The type of blockage. hard = no cells allowed, macro_only = standard-cells are allowed but
blocks are not allowed, partial = allow cells until reach the .density limit, soft = most logic cells
are not allowed, but 'repeater' cells like inverters, buffers, level-shifters, isolation cells, and
clock-gating cells are allowed. See the set_selective_blockage_gate command for other
methods to control what is allowed inside a soft place_blockage.
Type: enum
Enum Values: macro_only hard soft partial
Default: ""
Edit: Yes

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Database Objects--port

port

Parent Objects
bus, bump_pin, marker, clock, io_constraint, skew_group, hnet, timing_point, design, bus_sink_group,
clock_tree, timing_path, root, bump, port_shape, net

Definition
External logical ports of the design. See pg_ports for power/ground ports

Attribute Description

actual_latency_early_fall_max

Returns the computed early falling clock latency to this clock port. If the analysis mode is set to
best-case/worst-case, the value will be the Setup capture latency. When operating in OCV
mode, the max qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_early_fall_min

Returns the computed early falling clock latency to this clock port. If the analysis mode is set to
best-case/worst-case, the value will be the Hold launch latency. When operating in OCV
mode, the min qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_early_rise_max

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Returns the computed early rising clock latency to this clock port. If the analysis mode is set to
best-case/worst-case, the value will be the Setup capture latency. When operating in OCV
mode, the max qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_early_rise_min

Returns the computed early rising clock latency to this clock port. If the analysis mode is set to
best-case/worst-case, the value will be the Hold launch latency. When operating in OCV
mode, the min qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_late_fall_max

Returns the computed late falling clock latency to this clock port. If the analysis mode is set to
best-case/worst-case, the value will be the Setup launch latency. When operating in OCV
mode, the max qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_late_fall_min

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Returns the computed late falling clock latency to this clock port. If the analysis mode is set to
best-case/worst-case, the value will be the Hold capture latency. When operating in OCV
mode, the min qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_late_rise_max

Returns the computed late rising clock latency to this clock port If the analysis mode is set to
best-case/worst-case, the value will be the Setup launch latency. When operating in OCV
mode, the max qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

actual_latency_late_rise_min

Returns the computed late rising clock latency to this clock port. If the analysis mode is set to
best-case/worst-case, the value will be the Hold capture latency. When operating in OCV
mode, the min qualification is ignored. If there are multiple arrival times from different clock
phases - the most conservative latency value is reported. You can use the -index function to
return latencies with respect to a specific clock. When operating in concurrent MMMC mode,
the worst latency across all views is reported. You can use the -index function to filter
latencies based on view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

antenna_data

List of antenna data for the terminal

Type: obj(antenna_data)*
Default: ""
Edit: No

aocv_early_input_stage_weight

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Returns the number of external path stages to consider in AOCV early analysis of paths from
this port.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

aocv_early_output_stage_weight

Returns the number of external path stages to consider in AOCV early analysis of paths to this
port.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

aocv_late_input_stage_weight

Returns the number of external path stages to consider in AOCV late analysis of paths from
this port.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

aocv_late_output_stage_weight

Returns the number of external path stages to consider in AOCV late analysis of paths to this
port.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_max_fall

Returns the latest falling arrival time to the specified port across all concurrent MMMC views.
You can use -index to determine the worst arrival for a specific view. You can also use -index
to get the latest arrival time related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_max_rise

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Returns the latest rising arrival time to the specified port across all concurrent MMMC views.
You can use -index to determine the worst arrival for a specific view. You can also use -index
to get the latest arrival time related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_mean_max_fall

In SOCV analysis mode, this returns the mean value of the latest falling arrival time to the
specified port across all concurrent MMMC views. You can use -index to determine the latest
arrival for a specific view. You can also use -index to get the worst arrival time related to a
specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_mean_max_rise

In SOCV analysis mode, this returns the mean value of the latest rising arrival time to the
specified port across all concurrent MMMC views. You can use -index to determine the latest
arrival for a specific view. You can also use -index to get the worst arrival time related to a
specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_mean_min_fall

In SOCV analysis mode, this returns the mean value of the earliest falling arrival time to the
specified port across all concurrent MMMC views. You can use -index to determine the
earliest arrival for a specific view. You can also use -index to get the earliest arrival time
related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_mean_min_rise

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In SOCV analysis mode, this returns the mean value of the earliest rising arrival time to the
specified port across all concurrent MMMC views. You can use -index to determine the
earliest arrival for a specific view. You can also use -index to get the earliest arrival time
related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_min_fall

Returns the earliest falling arrival time to the specified port across all concurrent MMMC views.
You can use -index to determine the worst arrival for a specific view. You can also use -index
to get the earliest arrival time related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_min_rise

Returns the earliest falling arrival time to the specified port across all concurrent MMMC views.
You can use -index to determine the worst arrival for a specific view. You can also use -index
to get the worst arrival time related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_sigma_max_fall

In SOCV analysis mode, this returns the variation component of the latest falling arrival time to
the specified port across all concurrent MMMC views. You can use -index to determine the
latest arrival for a specific view. You can also use -index to get the worst arrival time related to
a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_sigma_max_rise

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In SOCV analysis mode, this returns the variation component of the latest rising arrival time to
the specified port across all concurrent MMMC views. You can use -index to determine the
latest arrival for a specific view. You can also use -index to get the worst arrival time related to
a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_sigma_min_fall

In SOCV analysis mode, this returns the variation component of the earliest falling arrival time
to the specified port across all concurrent MMMC views. You can use -index to determine the
earliest arrival for a specific view. You can also use -index to get the earliest arrival time
related to a specific clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

arrival_sigma_min_rise

arrival_window

Returns a list of the earliest and latest, rising and falling arrival times per clock phase at the
port across all concurrent MMMC views. You can use -index to make the arrival times specific
to a given view
Type: string
Allowed -index values: analysis_view clock
Default: ""
Edit: No

base_name

The name at the base of a hierarchical name. So the base_name of i1/i2/i3 is i3.
Type: string
Default: ""
Edit: No

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bus

Bus of port
Type: obj(bus)
Default: ""
Edit: No

clocks

Returns a list of all of the clock objects arriving at the port. You can use -index to return the
value from a specific analysis view.
Type: obj(clock)*
Allowed -index values: analysis_view clock
Default: ""
Edit: No

constant_value

context_constant_value

Returns a context_constant value of 0 or 1 if logic state has been asserted or propgated to this
pin. You can use -index to return the value from a specific analysis view.
Type: int
Allowed -index values: analysis_view clock
Default: ""
Edit: No

cts_add_port_driver

cts_annotated_delay_to

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cts_annotated_transition

Override any clock tree timing engine computed transition at this pin, in a similar manner to
SDC set_annotated_transition.
Type: string
Allowed -index values: delay_corner
Default: auto
Edit: Yes

cts_assign_clock_tree

cts_case_analysis

Specifies a constant value to be used as pin signal when analyzing timing

cts_clock_tree

The clock tree to which this object belongs. Flops do not belong to a clock
tree, but their clock pins do.
Valid values: cts_clock_tree
Type: obj(clock_tree)
Default: ""
Edit: No

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cts_clock_trees

cts_effective_routing_preference

cts_is_sdc_clock_root

cts_net_unbufferable_reasons

This attribute contains a list of reasons why CCOpt was not able to buffer the
clock net attached to the specified pin.
Valid values: string
Type: string
Default: ""
Edit: No

cts_node_type

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node type of port within cts graph

Type: string
Default: ""
Edit: No

cts_pin_capacitance_sources

List of the places the capacitance could be retrieved from.

cts_pin_insertion_delay

cts_routing_trunk_override

Prefer trunk routing rules for this pin. Only applies to clock tree sinks.
Valid values: true false
Type: bool
Default: false
Edit: Yes

cts_sink_type

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The type of sink this pin represents.

cts_sink_type_effective

cts_sink_type_implicit

cts_sink_type_reasons

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The reasons why this pin has the given cts_sink_type.

cts_skew_groups_active

Returns the list of active skew groups for this pin.

cts_skew_groups_active_sink

cts_skew_groups_constraining

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cts_skew_groups_constraining_sink

cts_skew_groups_ignore

The list of skew groups for which paths through this pin are ignored.
Valid values: list skew_groups
Type: obj(skew_group)*
Default: ""
Edit: No

cts_skew_groups_sink

The list of skew groups for which this pin is a sink.

Valid values: list skew_groups
Type: obj(skew_group)*
Default: ""
Edit: No

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cts_skew_groups_source_pin

The list of skew groups for which this clock tree or pin is specified as a
source.
Valid values: list skew_groups
Type: obj(skew_group)*
Default: ""
Edit: No

cts_spec_config_trace_through_to

Clock tree definition will, by default, not continue through certain types of
cell arc (for instance, the clock to Q arc in a DFF). This attribute allows
you to override this default behavior, permitting the clock tree to trace through
such a cell.
The attribute should be configured on the input pin at which the
clock arrives. The value of the attribute specifies the output
pin to which the clock should propagate. The specified output pin must be
another pin on the same instance. The output pin may be specified either by its
fully qualified name (i.e. inclusive of the instance name), or else simply by
its local (cell-relative) name.
There must be a pre-existing (library-defined) chain of one or more delay arcs
that connect the input and output pins together. It is not possible to use
trace_through_to to synthesize delay arcs.
If multiple input pins are annotated on a given instance, the value of
trace_through_to at each of those pins must select the same output pin:
i.e. the configuration must identify a single clock output for the instance. If
multiple clock outputs are required then trace_through_to should not be used:
instead define a generated clock tree at each of the clock-carrying outputs.
If the configuration of trace_through_to settings for a given instance does not
meet these requirements, a warning will be issued and the settings for that
instance will be ignored.
Note: if both trace_through_to and library_trace_through_to are applicable at a
given netlist instance pin, the trace_through_to value takes precedence.
Valid values: pin
Type: string
Default: ""
Edit: Yes

cts_top_fanout_count_override

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cts_top_fanout_transitive_count

cts_transitive_fanout

cts_virtual_delay_early_fall

The amount of virtual delay that has been applied under this pin.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

cts_virtual_delay_early_rise

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The amount of virtual delay that has been applied under this pin.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

cts_virtual_delay_late_fall

The amount of virtual delay that has been applied under this pin.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

cts_virtual_delay_late_rise

The amount of virtual delay that has been applied under this pin.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes

delay_max_fall

Returns the maximum falling delay. You can use -index to return the value from a specific
analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

delay_max_rise

Returns the maximum rising delay. You can use -index to return the value from a specific
analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

delay_min_fall

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Returns the minimum falling delay. You can use -index to return the value from a specific
analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

delay_min_rise

Returns the minimum rising delay. You can use -index to return the value from a specific
analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

depth

Depth constraint of the port in microns. Pin assignment commands will create a pin shape for
this port that extends 'depth' microns inside the design edge. The edit_pin command can be
used to set it.
Type: coord
Default: ""
Edit: No

design

The design of this port

Type: obj(design)
Default: ""
Edit: No

direction

Direction of the port from the Verilog netlist.

Type: enum
Enum Values: in out inout
Default: ""
Edit: No

drive_resistance_fall_max

Returns the falling linear drive resistance at the port for late timing paths. You can use -index
to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

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drive_resistance_fall_min

Returns the falling linear drive resistance at the port for early timing paths. You can use -index
to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

drive_resistance_rise_max

Returns the rising linear drive resistance at the port for late timing paths.. You can use -index
to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

drive_resistance_rise_min

Returns the rising linear drive resistance at the port for early timing paths. You can use -index
to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driver_from_pin_fall_max

Returns the driving cell input pin specified for max falling delays at the port. You can use -
index to return the value for a specific view.
Type: obj(lib_pin)*
Default: ""
Edit: No

driver_from_pin_fall_min

Returns the driving cell input pin specified for min falling delays at the port. You can use -
index to return the value for a specific view.
Type: obj(lib_pin)*
Default: ""
Edit: No

driver_from_pin_rise_max

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Returns the driving cell input pin specified for max rising delays at the port. You can use -
index to return the value for a specific view.
Type: obj(lib_pin)*
Default: ""
Edit: No

driver_from_pin_rise_min

Returns the driving cell input pin specified for min rising delays at the port. You can use -index
to return the value for a specific view.
Type: obj(lib_pin)*
Default: ""
Edit: No

driver_ignore_drc

driver_ignore_drc
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driver_input_slew_fall_to_fall_max

Returns the driver input pin slew used for the max fall-to-fall delay. You can use -index to
return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driver_input_slew_fall_to_fall_min

Returns the driver input pin slew used for the min fall-to-fall delay. You can use -index to return
the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driver_input_slew_fall_to_rise_max

Returns the driver input pin slew used for the max fall-to-rise delay. You can use -index to
return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

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driver_input_slew_fall_to_rise_min

Returns the driver input pin slew used for the min fall-to-rise delay. You can use -index to
return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driver_input_slew_rise_to_fall_max

Returns the driver input pin slew used for the max rise-to-fall delay. You can use -index to
return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driver_input_slew_rise_to_fall_min

Returns the driver input pin slew used for the min rise-to-fall delay. You can use -index to
return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driver_input_slew_rise_to_rise_max

Returns the driver input pin slew used for the max rise-to-rise delay. You can use -index to
return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driver_input_slew_rise_to_rise_min

Returns the driver input pin slew used for the min rise-to-rise delay. You can use -index to
return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driver_pin_fall_max

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Returns the driving cell output pin specified for max falling delays at the port. You can use -
index to return the value for a specific view.
Type: obj(lib_pin)*
Allowed -index values: analysis_view
Default: ""
Edit: No

driver_pin_fall_min

Returns the driving cell output pin specified for min falling delays at the port. You can use -
index to return the value for a specific view.
Type: obj(lib_pin)*
Allowed -index values: analysis_view
Default: ""
Edit: No

driver_pin_rise_max

Returns the driving cell output pin specified for max rising delays at the port. You can use -
index to return the value for a specific view.
Type: obj(lib_pin)*
Allowed -index values: analysis_view
Default: ""
Edit: No

driver_pin_rise_min

Returns the driving cell output pin specified for min rising delays at the port. You can use -
index to return the value for a specific view.
Type: obj(lib_pin)*
Allowed -index values: analysis_view
Default: ""
Edit: No

driving_cell_fall_max

Returns the name of the library cell used to compute max falling delays at the port. You can
use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_fall_min

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Returns the name of the library cell used to compute min falling delays at the port. You can
use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_from_pin_fall_max

Returns the driving cell input pin specified for max falling delays at the port. You can use -
index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_from_pin_fall_min

Returns the driving cell input pin specified for min falling delays at the port. You can use -
index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_from_pin_rise_max

Returns the driving cell input pin specified for max rising delays at the port. You can use -
index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_from_pin_rise_min

Returns the driving cell input pin specified for min rising delays at the port. You can use -index
to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_library_fall_max

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Returns the driving cell library specified for max falling delays at the port. You can use -index
to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_library_fall_min

Returns the driving cell library specified for min falling delays at the port. You can use -index
to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_library_rise_max

Returns the driving cell library specified for max rising delays at the port. You can use -index
to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_library_rise_min

Returns the driving cell library specified for min rising delays at the port. You can use -index to
return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_pin_fall_max

Returns the driving cell output pin specified for max falling delays at the port. You can use -
index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_pin_fall_min

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Returns the driving cell output pin specified for min falling delays at the port. You can use -
index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_pin_rise_max

Returns the driving cell output pin specified for max rising delays at the port. You can use -
index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_pin_rise_min

Returns the driving cell output pin specified for min rising delays at the port. You can use -
index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_rise_max

Returns the name of the library cell used to compute max rising delays at the port. You can
use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

driving_cell_rise_min

escaped_name

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external_capacitance_max

Returns the total max external loading on the port from all sources - including set_load
assertions or wireload models. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

external_capacitance_min

Returns the total min external loading on the port from all sources - including set_load
assertions or wireload models. You can use -index to return the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

external_fanout_load

Returns the external fanout load specified by set_fanout_load. You can use -index to return
the value for a specific view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

external_wireload_model

Returns the wireload model used to model external connections to the port. You can use -
index to return the value for a specific view.
Type: string
Default: ""
Edit: No

hdl_name

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This is the original RTL name for this port. It is used to map RTL simulation results with RTL
names to the current netlist for switching activity analysis. It is only maintained properly on the
output ports of sequential cells. Optimization will copy this name during any multi-bit merge or
splitting transforms to the equivalent port, but not on output ports of combinational cells. The
is_phase_inverted attribute will be flipped if the phase is inverted.
Type: string
Default: ""
Edit: Yes

hnet

hnet of this port

Type: obj(hnet)
Default: ""
Edit: No

hold_uncertainty

Returns the most conservative uncertainty of all possible uncertainty Hold assertions
associated with the port. You can use -index to return the value from a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

input_slew_max_fall

Returns the slowest falling transition on the port as specified by set_input_transition. You can
use -index to return the value from a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

input_slew_max_rise

Returns the slowest rising transition on the port as specified by set_input_transition. You can
use -index to return the value from a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

input_slew_min_fall

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Returns the fastest falling transition on the port as specified by set_input_transition. You can
use -index to return the value from a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

input_slew_min_rise

Returns the fastest rising transition on the port as specified by set_input_transition. You can
use -index to return the value from a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_clock_used_as_clock

Returns a value of true if the port lies in the clock network and at least one of the clocks
arriving at the pin is used as a clock in the downstream network of the pin. You can use -index
to return the value for a specific analysis view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_clock_used_as_data

Returns a value of true if the port lies in the clock source path and at least one of the clocks
arriving on the pin is used as data in the downstream network of the pin. You can use -index to
return the value for a specific analysis view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_constant_in_all_views

Returns true if logic state has been asserted or propgated to this pin in all the views
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_constant_in_any_view

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Returns true if logic state has been asserted or propgated to this pin in atleast one view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_disable_timing

Returns a value of true if the port's timing has been disabled. You can use -index to return the
value for a specific analysis view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_ideal_driver

Returns true if the port is an ideal driver due to the set_ideal_latency or set_ideal_transition
constraint.
Type: bool
Default: ""
Edit: No

is_ideal_network

Returns true if the port is part of an ideal network due to the set_ideal_network constraint. You
can use -index to return the value for a specific analysis view.
Type: bool
Default: ""
Edit: No

is_inside_partition

Returns whether port is inside partition or not.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_internal_disable

Return is_internal_disable property for a pin.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_owner

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Returns true if client is the owner for pin in distributed STA.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_power_mode_disabled

Returns true if power mode is disabled

Type: bool
Allowed -index values: analysis_view
Default: ""
Edit: No

is_propagated_clock

Returns a value of true if there is an explicit set_propagated_clock assertion at the port. You
can use -index to return the value for a specific analysis view.
Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_shared

Returns true if pin is shared across clients in distributed STA.

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

is_special

Indicates that the port is Special(not set for base_cell terms)

Type: bool
Default: false
Edit: Yes

is_valid_for_reports

Return whether a pin is valid for reporting or not

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

layer

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Layer of the port. For ports with more than one shape, it is the layer of the first shape (which is
the same shape used for the .location value). If there are no shapes for the port, {} is returned.
Type: obj(layer)
Default: ""
Edit: No

location

Location of port. For port with only one shape, it is the center of the port shape edge abutting
the design boundary. The edit_pin command can be used to set it. For ports that have more
than one shape, the location will overlap the first shape of the port.
Type: point
Default: ""
Edit: Yes

max_capacitance

max_capacitance
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

max_fanout

Returns the maximum fanout load that the port can drive. . You can use -index to return the
value for a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

max_transition

Returns the maximum transition time limit specified for the port. You can use -index to return
the value for a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

min_capacitance

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Returns the minimum capacitance limit for the port. You can use -index to return the value for a
specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

min_fanout

Returns the minimum fanout value for the port.

Type: int
Default: ""
Edit: No

min_transition

Returns the minimum transition time limit specified for the port.
Type: double
Default: ""
Edit: No

name

net

The canonical (flat) net connected to the terminal

Type: obj(net)
Default: ""
Edit: No

network_latency_fall_max

Returns the maximum fall insertion delay specified by an explicit set_clock_latency at the port.
You can use -index to return the value for a specific analysis view.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

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network_latency_fall_min

Returns the minimum fall insertion delay specified by an explicit set_clock_latency at the port.
You can use -index to return the value for a specific analysis view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

network_latency_rise_max

Returns the maximum rise insertion delay specified by an explicit set_clock_latency at the
port. You can use -index to return the value for a specific analysis view and/or clock
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

network_latency_rise_min

Returns the minimum rise insertion delay specified by an explicit set_clock_latency at the port.
You can use -index to return the value for a specific analysis view and/or clock
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (port)
Default: ""
Edit: No

physical_pins

List of ports
Type: obj(physical_pin)*
Default: ""
Edit: No

pin_edge

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If this port is for a design, and the port is assigned (has place_status of placed/fixed/cover), the
edge value indicates along which edge of the boundary polygon the port is assigned. The
edge number starts from the lowest Y, then left-most X vertex, staring with 0, and then counting
clock-wise. See the set_pin_constraint command document for a figure showing the edge
numbering. If the port is not assigned, or not for a design, the value of -1 is returned.
Type: int
Default: ""
Edit: No

place_status

Placement Status of terminal (not for base_cell terms)

Type: enum
Enum Values: unplaced placed fixed cover soft_fixed
Default: ""
Edit: Yes

power_domain

The power domain of the terminal (equivalent to Design Browser effPD)

Type: obj(power_domain)
Default: ""
Edit: No

power_rail_voltage_max

power_rail_voltage_max
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

power_rail_voltage_min

power_rail_voltage_min
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

related_ground_pin

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related_power_pin

setup_uncertainty

Returns the most conservative uncertainty of all possible uncertainty assertions associated
with the port. You can use -index to return the value for a specific analysis view
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

shape

Terminal shape
Type: enum
Enum Values: none ring abutment feed_through
Default: ""
Edit: No

side

Side constraint of the port. The edit_pin command can be used to set this value.
Type: enum
Enum Values: north west south east up none
Default: ""
Edit: No

slack_max

slack_max_edge

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Returns the edge (rise or fall) of the worst slack-causing path at the specified port in late mode.
Type: string
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_max_fall

slack_max_rise

slack_mean_max

slack_mean_max_fall

slack_mean_max_rise

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slack_mean_min

slack_mean_min_fall

slack_mean_min_rise

slack_min

Returns the worst slack across all concurrent MMMC views for hold-style late data path
checks
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_min_edge

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Returns the edge (rise or fall) of the worst slack-causing path at the specified port in early
mode.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_min_fall

Returns the worst hold slack for a falling signal at the port endpoint.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_min_rise

Returns the worst hold slack for a rising signal at the port endpoint.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

slack_sigma_max

slack_sigma_max_fall

slack_sigma_max_rise

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slack_sigma_min

slack_sigma_min_fall

slack_sigma_min_rise

slew_max_fall

slew_max_rise

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slew_mean_max_fall

slew_mean_max_rise

slew_mean_min_fall

slew_mean_min_rise

slew_min_fall

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slew_min_rise

slew_sigma_max_fall

slew_sigma_max_rise

slew_sigma_min_fall

slew_sigma_min_rise

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source_latency_early_fall_max

Returns the maximum early fall source insertion delay specified by an explicit
set_clock_latency at the port.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_early_fall_min

Returns the minimum early fall source insertion delay specified by an explicit
set_clock_latency at the port. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_early_rise_max

Returns the maximum early rise source insertion delay specified by an explicit
set_clock_latency at the port. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_early_rise_min

Returns the minimum early rise source insertion delay specified by an explicit
set_clock_latency at the port. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_late_fall_max

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Returns the maximum late fall source insertion delay specified by an explicit
set_clock_latency at the port. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_late_fall_min

Returns the minimum late fall source insertion delay specified by an explicit set_clock_latency
at the port. You can use -index to return the value for a specific view and/or clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_late_rise_max

Returns the maximum late rise source insertion delay specified by an explicit
set_clock_latency at the port. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

source_latency_late_rise_min

Returns the minimum late rise source insertion delay specified by an explicit
set_clock_latency at the port. You can use -index to return the value for a specific view and/or
clock.
Type: double
Allowed -index values: analysis_view clock
Default: ""
Edit: No

timing_case_computed_value

Returns the case computed value

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

timing_case_logic_value

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Returns the case logic value

Type: bool
Allowed -index values: analysis_view clock
Default: ""
Edit: No

use

Indicates how this port is used from the DEF PIN +USE value or OA equivalent. The legal
values are: analog clock ground power signal. Note that timing analysis does not use these
values, it uses the .lib data instead (e.g. is_clock, is_analog, etc.). So the signal, clock or
analog values are not normally used by applications. The power/ground values are used by
many applications. DEF PIN +USE RESET, SCAN or TIEOFF are not supported, so read_def
will ignore them, and keep the existing DB use value.
Type: enum
Enum Values: signal clock power ground analog
Default: ""
Edit: Yes

width

Width constraint of the port in microns. The edit_pin command can be used to set it.
Type: coord
Default: ""
Edit: No

port_shape

Parent Objects
design, root

Definition
This corresponds to one of a port's .physical_pins.layer_shapes.shapes, but is directly accessible from the
design and root objects. It carries a link to the port object, that a layer_shape object does not have. This
allows GUI operations that need both the layer_shape and the port object together as one object like
delete_obj or wire-editing commands.

Attribute Description

layer

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Layer of this port shape

Type: obj(layer)
Default: ""
Edit: Yes

mask

The mask number for this port_shape if this layer has multiple masks. 0 means it is uncolored.
Refer to layer .num_masks for legal range.
Type: int
Default: no_value
Edit: Yes

name

Name of the port for this port_shape. Note that all the port_shapes for one port will have the
same name.
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (port_shape)
Default: ""
Edit: No

polygon

Points of the polygon of the port_shape for type rect or polygon.

Type: point*
Default: ""
Edit: Yes

port

The port this port shape belongs to.

Type: obj(port)
Default: ""
Edit: No

rect

Bounding box of the port_shape for type rect or polygon.

Type: rect
Default: ""
Edit: Yes

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type

Type of port_shape (rect polygon).

Type: enum
Enum Values: rect polygon
Default: ""
Edit: No

power_domain

Parent Objects
hinst, inst, design, pin, root, group, port

Definition
Power domain

Attribute Description

available_supply_nets

Specifies the power nets physically available for this power domain to use for secondary
power pin connections.
Type: obj(net)*
Default: ""
Edit: No

base_domains

Specifies the base power domains (always-on domains) that supply the power to this
switchable power domain through power switch cells.
Type: obj(power_domain)*
Default: ""
Edit: No

core_to_bottom

Distance between the power domain edge and its core box
Type: coord
Default: ""
Edit: No

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core_to_left

Distance between the power domain edge and its core box
Type: coord
Default: ""
Edit: No

core_to_right

Distance between the power domain edge and its core box
Type: coord
Default: ""
Edit: No

core_to_top

Distance between the power domain edge and its core box
Type: coord
Default: ""
Edit: No

default_tech_site

default tech. site of the domain

Type: string
Default: ""
Edit: No

disjoint_hinst_box_list

List of hierarchical instances and disjoint boxes defining power domain boundary. It is defined
as an hinst and region pair. The listed hinst will be placed inside this domain
Type: string
Default: ""
Edit: No

extend_power_bottom

Maximum search distance for power connections

Type: coord
Default: ""
Edit: No

extend_power_edges

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List of maximum search distances for power extension connections in clockwise order starting
with the vertical edge at the lower-left corner (smallest Y, then smallest X)
Type: coord*
Default: ""
Edit: No

extend_power_left

Maximum search distance for power connections

Type: coord
Default: ""
Edit: No

extend_power_right

Maximum search distance for power connections

Type: coord
Default: ""
Edit: No

extend_power_top

Maximum search distance for power connections

Type: coord
Default: ""
Edit: No

first_row_site_index

Specifies the first row site index value.

Type: int
Default: ""
Edit: No

gap_bottom

Minimum spacing to other power domains or rows

Type: coord
Default: ""
Edit: No

gap_edges

List of minimum spacing values to other power domains or rows in clockwise order starting
with the vertical edge at the lower-left corner (smallest Y, then smallest X)
Type: coord*
Default: ""
Edit: No

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gap_left

Minimum spacing to other power domains or rows

Type: coord
Default: ""
Edit: No

gap_right

Minimum spacing to other power domains or rows

Type: coord
Default: ""
Edit: No

gap_top

Minimum spacing to other power domains or rows

Type: coord
Default: ""
Edit: No

group

The group of PD
Type: obj(group)
Default: ""
Edit: No

is_always_on

Indicates that the power domain is always on

Type: bool
Default: ""
Edit: No

is_default

The power domain is the default power domain or not.

Type: bool
Default: ""
Edit: No

is_internal

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Indicates that the domain is created by tool for the supply set which is not the primary set of
any domains defined in IEEE1801 file. It is created for supply set PVT specification and leaf
instance pin's domain assignment.
Type: bool
Default: false
Edit: No

is_macro_only

Indicates whether the domain member has only hardmacro members.

Type: bool
Default: ""
Edit: No

is_virtual

Specifies the power domain is a virtual domain, meaning that this domain does not have any
inst member.
Type: bool
Default: false
Edit: No

last_row_site_index

Specifies the last row site index value.

Type: int
Default: ""
Edit: No

name

Name of the power domain

Type: string
Default: ""
Edit: No

nwell_supply_net

Specifies the nwell bias net for this power_domain to use for nwell pin connections.
Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (power_domain)
Default: ""
Edit: No

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power_switch_rule_name

Indicates the domain's power switch rule name.

Type: string
Default: ""
Edit: No

primary_ground_net

Specifies the main ground rail net of the power domain.

Type: obj(net)
Default: ""
Edit: No

primary_power_net

Specifies the main power rail net of the power domain.

Type: obj(net)
Default: ""
Edit: No

pwell_supply_net

Specifies the pwell bias net for this power_domain to use for pwell pin connections.
Type: obj(net)
Default: ""
Edit: No

row_flip

Flips the orientation of either the first or second row, then follows the flipped and abutted row
pattern. Refer to "update_power_domain -row_flip" for more details.
Type: enum
Enum Values: noflip second first auto
Default: auto
Edit: Yes

row_pattern_site

Specifies the site name of the row pattern for the power doamin. For non-default power
domain, the default value is "". For default power domain, the default value is the default row
pattern site set by floorplan setting or "" if floorplan setting is not set.
Type: obj(site)
Default: ""
Edit: Yes

row_space_type

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Determines whether the row spacing value applies between no row (0), each row (1), or each
pair of rows (2).
Type: enum
Enum Values: 0 1 2
Default: 2
Edit: Yes

row_spacing

Specifies the row spacing between each row (1) or each pair of rows (2) as specified in
row_space_type.
Type: double
Default: 0
Edit: Yes

shutoff_condition

Indicates the power domain's shutoff condition. It is a logic expression with pin or hpin names.
Type: string
Default: ""
Edit: No

preferred_cell_stripe

Parent Objects

Definition
preferred cell stripe

Attribute Description

name

name of preferred_cell_stripe
Type: string
Default: ""
Edit: No

obj_type

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The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (preferred_cell_stripe)
Default: ""
Edit: No

rc_corner

Parent Objects
delay_corner, root

Definition
The rc_corner object represents a specific interconnect parasitic corner. It contains configuration information
for controlling the extraction of the parasitics and possible scaling. Parasitic files are annotated or exported
with respect to an rc_corner object name. The rc_corner object is typically referenced from one or many
higher-level delay_corner objects. Use the create_rc_corner command to define new rc_corners and the
update_rc_corner command to update the attributes of existing rc_corners.

Attribute Description

cap_table_file

Specifies the layer capacitance table file associated with the rc_corner. This is not
recommended for designs below 32nm. See the write_cap_table command for more details on
the file.
Type: string
Default: ""
Edit: No

is_active

Indicates that the rc_corner is associated with an analysis_view that is used in the active
analysis_view
Type: bool
Default: ""
Edit: No

is_dynamic

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Indicates that the rc_corner is associated with an analysis_view that is used in the active
dynamic analysis_view
Type: bool
Default: ""
Edit: No

is_hold

Indicates that the rc_corner is associated with an analysis_view that is used in the active hold
analysis_view
Type: bool
Default: ""
Edit: No

is_leakage

Indicates that the rc_corner is associated with an analysis_view that is used in the active
leakage analysis_view
Type: bool
Default: ""
Edit: No

is_setup

Indicates that the rc_corner is associated with an analysis_view that is used in the active
setup analysis_view
Type: bool
Default: ""
Edit: No

name

Provides the name of this rc_corner object as specified by create_rc_corner.

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (rc_corner)
Default: ""
Edit: No

post_route_cap

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Specifies scaling factor(s) to be used for capacitances in post_route flow steps. 1 to 3 values
may be specified to control each extraction effort level. Example: {lowEffortFactor},
{lowEffortFactor mediumEffortFactor}, {lowEffortFactor mediumEffortFactor highEffortFactor}. A
scaling value of 1.0 is assumed for any effort level without an explicit setting.
Type: double*
Default: ""
Edit: No

post_route_clock_cap

Specifies scaling factor(s) to be used for clock network capacitances in post_route flow steps.
1 to 3 values may be specified to control each extraction effort level. Example:
{lowEffortFactor}, {lowEffortFactor mediumEffortFactor}, {lowEffortFactor mediumEffortFactor
highEffortFactor}. A scaling value of 1.0 is assumed for any effort level without an explicit
setting.
Type: double*
Default: ""
Edit: No

post_route_clock_res

Specifies scaling factor(s) to be used for clock network resistances in post_route flow steps. 1
to 3 values may be specified to control each extraction effort level. Example: {lowEffortFactor},
{lowEffortFactor mediumEffortFactor}, {lowEffortFactor mediumEffortFactor highEffortFactor}. A
scaling value of 1.0 is assumed for any effort level without an explicit setting.
Type: double*
Default: ""
Edit: No

post_route_cross_cap

Specifies scaling factor(s) to be used for coupling-capacitances in post_route flow steps. 1 to 3

values may be specified to control each extraction effort level. Example: {lowEffortFactor},
{lowEffortFactor mediumEffortFactor}, {lowEffortFactor mediumEffortFactor highEffortFactor}. A
scaling value of 1.0 is assumed for any effort level without an explicit setting.
Type: double*
Default: ""
Edit: No

post_route_res

Specifies scaling factor(s) to be used for resistances in post_route flow steps. 1 to 3 values
may be specified to control each extraction effort level. Example: {lowEffortFactor},
{lowEffortFactor mediumEffortFactor}, {lowEffortFactor mediumEffortFactor highEffortFactor}. A
scaling value of 1.0 is assumed for any effort level without an explicit setting.
Type: double*
Default: ""
Edit: No

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pre_route_cap

Specifies a scaling factor to be used for capacitances in pre_route flow steps. Defaults to 1.0 if
not given.
Type: double
Default: ""
Edit: No

pre_route_clock_cap

Specifies a scaling factor to be used for clock network capacitances in pre_route flow steps.
Defaults to 1.0 if not given.
Type: double
Default: ""
Edit: No

pre_route_clock_res

Specifies a scaling factor to be used for clock network resistance in pre_route flow steps.
Defaults to 1.0 if not given.
Type: double
Default: ""
Edit: No

pre_route_res

Specifies a scaling factor to be used for resistances in pre_route flow steps. Defaults to 1.0 if
not given.
Type: double
Default: ""
Edit: No

qrc_tech_file

Specifies the QRC technology file associated with the rc_corner

Type: string
Default: ""
Edit: No

temperature

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Specifies the temperature, in units of Celsius, to use to derate resistance values for this
rc_corner. Use this parameter when you want to override the default temperature specified in
the capacitance table or the QRC technology file. By default, the RC extractor uses the
temperature of 25 degrees Celsius, unless it is specified by the capacitance table or the QRC
technology file. Note, the opcond temperature is not used for RC extraction, the temperature
for RC extraction must be set with this attribute if you want to override the techfile or captable
settings.
Type: double
Default: ""
Edit: No

via_variation_file

Specifies the via layer file so that all the VIA resistance in SPEF could be mapped to have
own variation multiplier.
Type: string
Default: ""
Edit: No

resize_blockage

Parent Objects
design, root

Definition
resize blkg

Attribute Description

is_resizeable

Specifies that the size blockage can be resized, however alignment and the minimum space
between the objects in the blockage area will be maintained during floorplan resize.(1 =
resizeable).
Type: bool
Default: false
Edit: Yes

name

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Name of the size blockage

Type: string
Default: ""
Edit: Yes

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (resize_blockage)
Default: ""
Edit: No

rect

Rectangle that defines the resize_blockage shape.

Type: rect
Default: ""
Edit: No

root

Parent Objects

Definition
root

Attribute Description

add_endcaps_avoid_two_sites_cell_abut

avoid 2 sites boundary cell abut to incorner cell in N10

Type: bool
Default: false
Edit: Yes
Reference: add_endcaps_avoid_two_sites_cell_abut

add_endcaps_bottom_edge

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EndCaps with n-well at the bottom edge

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_bottom_edge

add_endcaps_boundary_tap

New flow to add cap cell and tap cell together

Type: bool
Default: false
Edit: Yes
Reference: add_endcaps_boundary_tap

add_endcaps_boundary_tap_swap_flow

boundary tap swap flow

Type: bool
Default: true
Edit: Yes
Reference: add_endcaps_boundary_tap_swap_flow

add_endcaps_cells

Specify endCaps cell candidates for N10 that has defined in LEF
Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_cells

add_endcaps_create_rows

Create rows for endtap cell techSites which do not have rows in the floor plan
Type: bool
Default: false
Edit: Yes
Reference: add_endcaps_create_rows

add_endcaps_flip_y

Flips the orientation of the endcap instances in Y direction if the site symmetry allows it.
Type: bool
Default: false
Edit: Yes
Reference: add_endcaps_flip_y

add_endcaps_incremental_left_edge

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EndCap lists with n-well at the left edge

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_incremental_left_edge

add_endcaps_incremental_right_edge

EndCap list with n-well at the right edge

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_incremental_right_edge

add_endcaps_left_bottom_corner

EndCap with n-well at the left bottom corner

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_bottom_corner

add_endcaps_left_bottom_corner_even

EndCap with n-well at the left bottom corner, even sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_bottom_corner_even

add_endcaps_left_bottom_corner_neighbor

The cell to be abutted with the left side of leftBottomCorner in R0 orientation

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_bottom_corner_neighbor

add_endcaps_left_bottom_corner_odd

EndCap with n-well at the left bottom corner, odd sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_bottom_corner_odd

add_endcaps_left_bottom_edge

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EndCap with n-well at the left bottom edge

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_bottom_edge

add_endcaps_left_bottom_edge_even

EndCap with n-well at the left bottom edge, even sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_bottom_edge_even

add_endcaps_left_bottom_edge_neighbor

The cell to be abutted with the right edge of leftBottomEdge in R0 orientation

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_bottom_edge_neighbor

add_endcaps_left_bottom_edge_odd

EndCap with n-well at the left bottom edge, odd sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_bottom_edge_odd

add_endcaps_left_edge

EndCap with n-well at the left edge

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_edge

add_endcaps_left_edge_bottom_border

EndCaps with n-well at the left edge, poly at the bottom boundary
Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_edge_bottom_border

add_endcaps_left_edge_even

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EndCap with n-well at the left edge, even sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_edge_even

add_endcaps_left_edge_odd

EndCap with n-well at the left edge, odd sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_edge_odd

add_endcaps_left_edge_top_border

EndCaps with n-well at the left edge, poly at the top boundary
Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_edge_top_border

add_endcaps_left_top_corner

EndCap with n-well at the left top corner

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_top_corner

add_endcaps_left_top_corner_even

EndCap with n-well at the left top corner, even sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_top_corner_even

add_endcaps_left_top_corner_neighbor

The cell to be abutted with the left side of leftTopCorner in R0 orientation

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_top_corner_neighbor

add_endcaps_left_top_corner_odd

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EndCap with n-well at the left top corner, odd sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_top_corner_odd

add_endcaps_left_top_edge

EndCap with n-well at the left top edge

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_top_edge

add_endcaps_left_top_edge_even

EndCap with n-well at the left top edge, even sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_top_edge_even

add_endcaps_left_top_edge_neighbor

The cell to be abutted with the right edge of leftTopEdge in R0 orientation

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_top_edge_neighbor

add_endcaps_left_top_edge_odd

EndCap with n-well at the left top edge, odd sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_left_top_edge_odd

add_endcaps_min_horizontal_channel_width

Type: int
Default: 0
Edit: Yes
Reference: add_endcaps_min_horizontal_channel_width

add_endcaps_min_jog_height

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Type: int
Default: 0
Edit: Yes
Reference: add_endcaps_min_jog_height

add_endcaps_min_jog_width

Type: int
Default: 0
Edit: Yes
Reference: add_endcaps_min_jog_width

add_endcaps_min_vertical_channel_width

Type: int
Default: 0
Edit: Yes
Reference: add_endcaps_min_vertical_channel_width

add_endcaps_prefix

Prefix of EndCap cells

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_prefix

add_endcaps_right_bottom_corner

EndCap with n-well at the right bottom corner

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_bottom_corner

add_endcaps_right_bottom_corner_even

EndCap with n-well at the right bottom corner, even sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_bottom_corner_even

add_endcaps_right_bottom_corner_neighbor

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The cell to be abutted with the right side of rightBottomCorner in R0 orientation

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_bottom_corner_neighbor

add_endcaps_right_bottom_corner_odd

EndCap with n-well at the right bottom corner, odd sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_bottom_corner_odd

add_endcaps_right_bottom_edge

EndCap with n-well at the right bottom edge

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_bottom_edge

add_endcaps_right_bottom_edge_even

EndCap with n-well at the right bottom edge, even sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_bottom_edge_even

add_endcaps_right_bottom_edge_neighbor

The cell to be abutted with the left edge of rightBottomEdge in R0 orientation

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_bottom_edge_neighbor

add_endcaps_right_bottom_edge_odd

EndCap with n-well at the right bottom edge, odd sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_bottom_edge_odd

add_endcaps_right_edge

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EndCap with n-well at the right edge

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_edge

add_endcaps_right_edge_bottom_border

EndCaps with n-well at the right edge, poly at the bottom boundary
Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_edge_bottom_border

add_endcaps_right_edge_even

EndCap with n-well at the right edge, even sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_edge_even

add_endcaps_right_edge_odd

EndCap with n-well at the right edge, odd sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_edge_odd

add_endcaps_right_edge_top_border

EndCaps with n-well at the right edge, poly at the top boundary
Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_edge_top_border

add_endcaps_right_top_corner

EndCap with n-well at the right top corner

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_top_corner

add_endcaps_right_top_corner_even

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EndCap with n-well at the right top corner, even sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_top_corner_even

add_endcaps_right_top_corner_neighbor

The cell to be abutted with the right side of rightTopCorner in R0 orientation

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_top_corner_neighbor

add_endcaps_right_top_corner_odd

EndCap with n-well at the right top corner, odd sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_top_corner_odd

add_endcaps_right_top_edge

EndCap with n-well at the right top edge

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_top_edge

add_endcaps_right_top_edge_even

EndCap with n-well at the right top edge, even sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_top_edge_even

add_endcaps_right_top_edge_neighbor

The cell to be abutted with the left edge of rightTopEdge in R0 orientation

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_top_edge_neighbor

add_endcaps_right_top_edge_odd

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EndCap with n-well at the right top edge, odd sites

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_right_top_edge_odd

add_endcaps_top_bottom_edge

EndCaps with n-well at the both top and bottom edges

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_top_bottom_edge

add_endcaps_top_edge

EndCaps with n-well at the top edge

Type: string
Default: ""
Edit: Yes
Reference: add_endcaps_top_edge

add_endcaps_use_even_odd_sites

use even or odd poly sites

Type: enum
Enum Values: none even odd
Default: none
Edit: Yes
Reference: add_endcaps_use_even_odd_sites

add_endcaps_wall_keepout_from_vertical_boundary

Type: double
Default: 0.0
Edit: Yes
Reference: add_endcaps_wall_keepout_from_vertical_boundary

add_endcaps_wall_offset

Type: double
Default: 0.0
Edit: Yes
Reference: add_endcaps_wall_offset

add_endcaps_wall_pitch

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Type: double
Default: 0.0
Edit: Yes
Reference: add_endcaps_wall_pitch

add_endcaps_wall_to_convex_corner_spacing

Type: double
Default: 0.0
Edit: Yes
Reference: add_endcaps_wall_to_convex_corner_spacing

add_fillers_avoid_abutment_patterns

illegal abutment patterns

Type: string
Default: ""
Edit: Yes
Reference: add_fillers_avoid_abutment_patterns

add_fillers_cell_name_style

Add physical cells into hierarchical modules, or as top level cells (flat)
Type: enum
Enum Values: hier flat
Default: hier
Edit: Yes
Reference: add_fillers_cell_name_style

add_fillers_cells

List of filler cells

Type: string
Default: ""
Edit: Yes
Reference: add_fillers_cells

add_fillers_check_different_cells

Check violations between different cell types

Type: bool
Default: false
Edit: Yes
Reference: add_fillers_check_different_cells

add_fillers_check_drc

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DRC checking after filler insertion

Type: bool
Default: true
Edit: Yes
Reference: add_fillers_check_drc

add_fillers_create_rows

Create rows for filler cell techSites which do not have rows in the floor plan
Type: bool
Default: true
Edit: Yes
Reference: add_fillers_create_rows

add_fillers_distribute_implant_evenly

distribute implant evenly for fillers

Type: bool
Default: false
Edit: Yes
Reference: add_fillers_distribute_implant_evenly

add_fillers_eco_mode

Fillers inserted in eco flow

Type: bool
Default: false
Edit: Yes
Reference: add_fillers_eco_mode

add_fillers_honor_preroute_as_obs

Filler command honors place_detail_preroute_as_obs value

Type: bool
Default: false
Edit: Yes
Reference: add_fillers_honor_preroute_as_obs

add_fillers_horizontal_exception_cell

List of exceptional cells for horizontal stack checking

Type: string
Default: ""
Edit: Yes
Reference: add_fillers_horizontal_exception_cell

add_fillers_horizontal_max_length

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specify instance max length (in micron) aligned in horizontal direction

Type: double
Default: 0.0
Edit: Yes
Reference: add_fillers_horizontal_max_length

add_fillers_horizontal_repair_cell

List of filler cells to fix horizontal max length violation

Type: string
Default: ""
Edit: Yes
Reference: add_fillers_horizontal_repair_cell

add_fillers_keep_fixed

'FIXED' fillers are kepted

Type: bool
Default: false
Edit: Yes
Reference: add_fillers_keep_fixed

add_fillers_no_single_site_gap

Filler command fit 1-site gap

Type: bool
Default: true
Edit: Yes
Reference: add_fillers_no_single_site_gap

add_fillers_prefix

Prefix of filler cells

Type: string
Default: ""
Edit: Yes
Reference: add_fillers_prefix

add_fillers_preserve_user_order

Instruct tool to insert fillers by the user defined order

Type: bool
Default: false
Edit: Yes
Reference: add_fillers_preserve_user_order

add_fillers_scheme

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Instruct tool to select locationFirst|cellFirst scheme

Type: enum
Enum Values: locationFirst cellFirst
Default: locationFirst
Edit: Yes
Reference: add_fillers_scheme

add_fillers_swap_cell

swap cell pairs

Type: string
Default: ""
Edit: Yes
Reference: add_fillers_swap_cell

add_fillers_vertical_stack_exception_cell

List of exceptional cells for vertical stack checking

Type: string
Default: ""
Edit: Yes
Reference: add_fillers_vertical_stack_exception_cell

add_fillers_vertical_stack_left_edge_exception_cell

List of cells only check right edge for vertical stack violation
Type: string
Default: ""
Edit: Yes
Reference: add_fillers_vertical_stack_left_edge_exception_cell

add_fillers_vertical_stack_max_length

specify instance max length (in micron) aligned in vertical direction

Type: double
Default: 0.0
Edit: Yes
Reference: add_fillers_vertical_stack_max_length

add_fillers_vertical_stack_repair_cell

List of filler cells to fix vertical stack violation

Type: string
Default: ""
Edit: Yes
Reference: add_fillers_vertical_stack_repair_cell

add_fillers_vertical_stack_repair_edge

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specify the edge to use of vertical repair cell

Type: enum
Enum Values: left right
Default: ""
Edit: Yes
Reference: add_fillers_vertical_stack_repair_edge

add_fillers_vertical_stack_right_edge_exception_cell

List of cells only check left edge for vertical stack violation
Type: string
Default: ""
Edit: Yes
Reference: add_fillers_vertical_stack_right_edge_exception_cell

add_fillers_with_drc

call second add_fillers without drc checking

Type: bool
Default: true
Edit: Yes
Reference: add_fillers_with_drc

add_fillers_y_flip_type

Defines first or last cell with certain cell size should be y-flipped
Type: string
Default: ""
Edit: Yes
Reference: add_fillers_y_flip_type

add_reinforce_pg_critical_path_slack

Specifies a slack threshold, in nanoseconds, for critical nets during timing-driven reinforce_pg.
Type: int
Default: 0
Edit: Yes

add_reinforce_pg_respect_critical_path

Specifies reinforce_pg to be timing aware on critical paths.

Type: bool
Default: false
Edit: Yes

add_reinforce_pg_respect_routes

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Specifies whether to honor pre-existing routes check during stripe generation

Type: enum
Enum Values: none | fixed fixed_and_clock all
Default: fixed_and_clock
Edit: Yes

add_reinforce_pg_respect_stdcell_geometry

Specifies the cell type to be respected in via generation.

Type: enum
Enum Values: none sequential all
Default: all
Edit: Yes
Reference: add_reinforce_pg_respect_stdcell_geometry

add_rings_avoid_short

Specifies whether to avoid short violation

Type: bool
Default: false
Edit: Yes
Reference: add_rings_avoid_short

add_rings_break_core_ring_io_list

Specifies io instance names for which core ring wires are broken
Type: string
Default: ""
Edit: Yes
Reference: add_rings_break_core_ring_io_list

add_rings_continue_on_no_selection

Continues w/o selection

Type: bool
Default: false
Edit: Yes
Reference: add_rings_continue_on_no_selection

add_rings_detailed_log

Outputs detailed log file addring.log

Type: bool
Default: false
Edit: Yes
Reference: add_rings_detailed_log

add_rings_extend_block_ring_search_distance

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Specifies blockring extension search distance

Type: double
Default: 0.0
Edit: Yes
Reference: add_rings_extend_block_ring_search_distance

add_rings_extend_core_ring_search_distance

Specifies corering extension search distance

Type: double
Default: 0.0
Edit: Yes
Reference: add_rings_extend_core_ring_search_distance

add_rings_extend_merge_with_pre_wires

Specifies whether to merge with prerouted wires

Type: bool
Default: true
Edit: Yes
Reference: add_rings_extend_merge_with_pre_wires

add_rings_extend_over_row

Specifies whether to extend over row

Type: bool
Default: false
Edit: Yes
Reference: add_rings_extend_over_row

add_rings_extend_search_nets

Specifies search net names

Type: string
Default: ""
Edit: Yes
Reference: add_rings_extend_search_nets

add_rings_extend_stripe_search_distance

Specifies stripe extension search distance

Type: double
Default: 0.0
Edit: Yes
Reference: add_rings_extend_stripe_search_distance

add_rings_gap_width_without_io

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Specifies the max missing IO Pads area width between IO Pads

Type: double
Default: 0.0
Edit: Yes
Reference: add_rings_gap_width_without_io

add_rings_ignore_rows

Specifies whether to ignore all rows

Type: bool
Default: false
Edit: Yes
Reference: add_rings_ignore_rows

add_rings_max_via_size

the maximum size of a crossover via

Type: string
Default: ""
Edit: Yes
Reference: add_rings_max_via_size

add_rings_orthogonal_only

vias connect to orthogonal targets only

Type: bool
Default: true
Edit: Yes
Reference: add_rings_orthogonal_only

add_rings_skip_shared_inner_ring

Specifies whether to skip crossing trunks

Type: enum
Enum Values: horizontal vertical none
Default: none
Edit: Yes
Reference: add_rings_skip_shared_inner_ring

add_rings_skip_via_on_pin

prevent vias from being generated on the specified type of pins

Type: enum
Enum Values: pad block cover standardcell physicalpin
Default: standardcell
Edit: Yes
Reference: add_rings_skip_via_on_pin

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add_rings_skip_via_on_wire_shape

prevent vias from being generated on the specified wire shapes

Type: enum
Enum Values: blockring stripe followpin corewire blockwire iowire padring ring fillwire
noshape
Default: noshape
Edit: Yes
Reference: add_rings_skip_via_on_wire_shape

add_rings_spacing_from_block

Specifies the spacing from block

Type: double
Default: 0.0
Edit: Yes
Reference: add_rings_spacing_from_block

add_rings_split_long_via

Split vias longer than <threshold> into smaller vias with specified <step> and bottom/left end
<offset> and vertical/horizontal <length>
Type: string
Default: 0 0 -1 -1
Edit: Yes
Reference: add_rings_split_long_via

add_rings_stacked_via_bottom_layer

lef layer name

Type: string
Default: bottomLayer
Edit: Yes
Reference: add_rings_stacked_via_bottom_layer

add_rings_stacked_via_top_layer

lef layer name

Type: string
Default: topLayer
Edit: Yes
Reference: add_rings_stacked_via_top_layer

add_rings_target

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Specifies ring target

Type: enum
Enum Values: core_ring default first_ring pad_ring stripe
Default: default
Edit: Yes
Reference: add_rings_target

add_rings_via_using_exact_crossover_size

generate partial vias of the exact crossover size

Type: bool
Default: true
Edit: Yes
Reference: add_rings_via_using_exact_crossover_size

add_rings_wire_center_offset

offset value is from wire center to domain/core boundary

Type: bool
Default: false
Edit: Yes
Reference: add_rings_wire_center_offset

add_route_vias_auto

enable auto via generation when design is loaded

Type: bool
Default: false
Edit: Yes
Reference: add_route_vias_auto

add_route_vias_ndr_only

generate vias for non default rules only

Type: bool
Default: false
Edit: Yes
Reference: add_route_vias_ndr_only

add_stripes_allow_jog

Specifies the allowed jog type.

Type: enum
Enum Values: none padcore_ring block_ring
Default: padcore_ring block_ring
Edit: Yes
Reference: add_stripes_allow_jog

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add_stripes_allow_non_preferred_dir

Specifies whether to allow non-preferred direction to jog to target

Type: enum
Enum Values: none blockring corering padring stripe
Default: padring
Edit: Yes
Reference: add_stripes_allow_non_preferred_dir

add_stripes_area

Specify the rectangular areas or rectilinear areas or a mix of them, the correct value should be
{<lx ly ux uy> | <x1 y1 x2 y2 x3 y3 ...>}
Type: string
Default: ""
Edit: Yes
Reference: add_stripes_area

add_stripes_blocks_without_same_net

Specifies the stripe break point.

Type: enum
Enum Values: none block_ring selected_block unassigned_bump overlap_ringpin
outer_ring outside_ringmacro blocks_without_same_net
Default: none
Edit: Yes
Reference: add_stripes_blocks_without_same_net

add_stripes_break_at

Specifies the stripe break point.

Type: enum
Enum Values: none block_ring selected_block unassigned_bump overlap_ringpin
outer_ring outside_ringmacro blocks_without_same_net
Default: none
Edit: Yes
Reference: add_stripes_break_at

add_stripes_continue_on_no_selection

Specifies whether to continue w/o selection

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_continue_on_no_selection

add_stripes_detailed_log

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Specifies whether to output detailed log file addStripe.log

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_detailed_log

add_stripes_domain_offset_from_core

Specifies whether to use global offset for power domain stripes

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_domain_offset_from_core

add_stripes_extend_to_closest_target

Specifies the stripe to specified target

Type: enum
Enum Values: ring stripe same_dir_stripe area_boundary none
Default: none
Edit: Yes
Reference: add_stripes_extend_to_closest_target

add_stripes_extend_to_first_ring

Specifies whether to extend stripe antennas to closest ring

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_extend_to_first_ring

add_stripes_ignore_block_check

Specifies whether to ignore block check

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_ignore_block_check

add_stripes_ignore_block_ring_during_break

Specifies whether to break stripe outside block

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_ignore_block_ring_during_break

add_stripes_ignore_drc

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Specifies whether to ignore DRC check during stripe generation, it is always used for
prototype flow
Type: bool
Default: false
Edit: Yes
Reference: add_stripes_ignore_drc

add_stripes_ignore_non_default_domains

Specifies whether to break at non-default domain

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_ignore_non_default_domains

add_stripes_in_cell_allow_shift

Specifies to allow the created pillar inside cell can be shifted when meeting DRC
Type: bool
Default: false
Edit: Yes
Reference: add_stripes_in_cell_allow_shift

add_stripes_in_cell_only

Specifies whether to generate stripes only inside selected or specified cell

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_in_cell_only

add_stripes_keep_pitch_after_snap

Type: bool
Default: false
Edit: Yes

add_stripes_mask_color_balance

same_color would correspond to interlace with groups and alternate_color would correspond
to interlace within group
Type: enum
Enum Values: same_color alternate_color none
Default: none
Edit: Yes
Reference: add_stripes_mask_color_balance

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add_stripes_max_extension_distance

Specifies maximum extension distance(default=max integer) when -extend_to_closest_target

is specified.
Type: double
Default: 2.14748e+09
Edit: Yes
Reference: add_stripes_max_extension_distance

add_stripes_max_via_size

the maximum size of a crossover via, the correct value should be {shape width% height%
target_penetration%}
Type: string
Default: ""
Edit: Yes
Reference: add_stripes_max_via_size

add_stripes_merge_with_all_layers

Specifies whether to merge a stripe on all layers

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_merge_with_all_layers

add_stripes_mesh_via

use mesh via to reduce memory

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_mesh_via

add_stripes_offset_from_core

Specifies whether to offset first or last stripe from the core area
Type: bool
Default: true
Edit: Yes
Reference: add_stripes_offset_from_core

add_stripes_opt_stripe_for_routing_track

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move stripe location to preserve routing resource

Type: enum
Enum Values: shift none
Default: none
Edit: Yes
Reference: add_stripes_opt_stripe_for_routing_track

add_stripes_orthogonal_offset

Specifies the offsets for edges orthogonally, the correct value should be {[{edge1
orthogonal_offset1} {edge2 edge3 orthogonal_offset2} {edge4 edge5 ... orthogonal_offset3} ...]
| [all orthogonal_offset]}
Type: string
Default: {none}
Edit: Yes
Reference: add_stripes_orthogonal_offset

add_stripes_orthogonal_only

vias connect to orthogonal targets only

Type: bool
Default: true
Edit: Yes
Reference: add_stripes_orthogonal_only

add_stripes_over_row_extension

Specifies whether to extend the stripe to cover followpin at the row end
Type: bool
Default: false
Edit: Yes
Reference: add_stripes_over_row_extension

add_stripes_partial_set_through_domain

Specifies whether to go over power domain if domain contains the specified net
Type: bool
Default: false
Edit: Yes
Reference: add_stripes_partial_set_through_domain

add_stripes_remove_floating_stapling

remove floating stapling stripe if there is no via connection

Type: bool
Default: true
Edit: Yes
Reference: add_stripes_remove_floating_stapling

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add_stripes_remove_floating_stripe_over_block

Specifies whether to remove stripe fragments start and end inside same block or ring macro
Type: bool
Default: true
Edit: Yes
Reference: add_stripes_remove_floating_stripe_over_block

add_stripes_remove_stripe_under_ring

Specifies whether to remove those segments under rings.

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_remove_stripe_under_ring

add_stripes_respect_routes

Specifies whether to honor pre-existing routes check during stripe generation

Type: enum
Enum Values: none | fixed fixed_and_clock all
Default: fixed_and_clock
Edit: Yes

add_stripes_route_over_rows_only

Specifies whether to route stripe over rows within the boundary

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_route_over_rows_only

add_stripes_rows_without_stripes_only

Specifies whether to generate stripes over rows w/o stripes

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_rows_without_stripes_only

add_stripes_same_size_stack_vias

generate same-sized stacked vias

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_same_size_stack_vias

add_stripes_skip_via_on_pin

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prevent vias from being generated on the specified type of pins

Type: enum
Enum Values: pad block cover standardcell physicalpin
Default: standardcell
Edit: Yes
Reference: add_stripes_skip_via_on_pin

add_stripes_skip_via_on_wire_shape

prevent vias from being generated on the specified wire shapes

Type: enum
Enum Values: blockring stripe followpin corewire blockwire iowire padring ring fillwire
noshape
Default: noshape
Edit: Yes
Reference: add_stripes_skip_via_on_wire_shape

add_stripes_spacing_from_block

Specifies the spacing from block

Type: double
Default: 0.0
Edit: Yes
Reference: add_stripes_spacing_from_block

add_stripes_spacing_type

Specify the type of intra spacing for add_stripes -spacing

Type: enum
Enum Values: edge_to_edge center_to_center
Default: edge_to_edge
Edit: Yes
Reference: add_stripes_spacing_type

add_stripes_split_long_via

Split vias longer than <threshold> into smaller vias with specified <step> and bottom/left end
<offset> and vertical/horizontal <length>, the correct value should be {threshold step offset
length}
Type: string
Default: 0 0 -1 -1
Edit: Yes
Reference: add_stripes_split_long_via

add_stripes_split_vias

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create multiple partial vias

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_split_vias

add_stripes_split_wire_spacing

Specifies the spacing between each split wire

Type: double
Default: 0.0
Edit: Yes
Reference: add_stripes_split_wire_spacing

add_stripes_split_wire_weight

Deletes fewest IO wires to accommodate approximately n of 10 split stripe wires

Type: double
Default: 0.0
Edit: Yes
Reference: add_stripes_split_wire_weight

add_stripes_split_wire_width

Specifies the width of each split wire

Type: double
Default: 0.0
Edit: Yes
Reference: add_stripes_split_wire_width

add_stripes_stacked_via_bottom_layer

lef layer name

Type: string
Default: bottomLayer
Edit: Yes
Reference: add_stripes_stacked_via_bottom_layer

add_stripes_stacked_via_top_layer

lef layer name

Type: string
Default: topLayer
Edit: Yes
Reference: add_stripes_stacked_via_top_layer

add_stripes_stapling_extend_to_minimum_spacing

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Specified to automatically extend the adjacent stapling as long as enough to satisfy the end-
to-end minimum spacing with DRC free
Type: bool
Default: false
Edit: Yes

add_stripes_stapling_nets_style

Specify the stapling style if multiple nets are specified

Type: enum
Enum Values: end_to_end side_to_side side_to_side_full_nets
Default: end_to_end
Edit: Yes
Reference: add_stripes_stapling_nets_style

add_stripes_stapling_shift

shift stapling stripe to avoid the drc automatically

Type: bool
Default: true
Edit: Yes
Reference: add_stripes_stapling_shift

add_stripes_stop_at_closest_target

Specifies the stripe to specified target when over_pins is enabled.

Type: enum
Enum Values: none block_ring core_ring stripe
Default: none
Edit: Yes
Reference: add_stripes_stop_at_closest_target

add_stripes_stop_at_last_wire_for_area

Specifies whether to trim back stripe antennas to the closest wire or pin of the same net
Type: bool
Default: false
Edit: Yes
Reference: add_stripes_stop_at_last_wire_for_area

add_stripes_stripe_min_length

Specifies the minimum stripe length

Type: string
Default: stripe_width
Edit: Yes
Reference: add_stripes_stripe_min_length

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add_stripes_stripe_min_width

Specifies the min width of remaining stripe after being trimmed

Type: double
Default: 0.0
Edit: Yes
Reference: add_stripes_stripe_min_width

add_stripes_switch_cell_name

Specifies the switch cells to be treated as rings

Type: string
Default: none
Edit: Yes
Reference: add_stripes_switch_cell_name

add_stripes_switch_layer_overlap_length

Specifies the overlap distance used for the via between a stripe layer and the layer being
switched to
Type: double
Default: 0.0
Edit: Yes
Reference: add_stripes_switch_layer_overlap_length

add_stripes_trim_antenna_back_to_shape

Specifies the distance between the end of antenna and blocked target
Type: enum
Enum Values: none block_ring core_ring pad_ring stripe
Default: none
Edit: Yes
Reference: add_stripes_trim_antenna_back_to_shape

add_stripes_trim_antenna_max_distance

Specifies the distance between the end of antenna and blocked target
Type: double
Default: 0.0
Edit: Yes
Reference: add_stripes_trim_antenna_max_distance

add_stripes_trim_stripe

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Specifies if stripe is trimmed by the specified shape.

Type: enum
Enum Values: none design_boundary core_boundary
Default: none
Edit: Yes
Reference: add_stripes_trim_stripe

add_stripes_use_exact_spacing

Specifies whether to use exact spacing

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_use_exact_spacing

add_stripes_use_point_to_point_route

Specifies whether to use exact spacing

Type: bool
Default: false
Edit: Yes
Reference: add_stripes_use_point_to_point_route

add_stripes_use_stripe_width

Specifies whether to use stripe width

Type: bool
Default: true
Edit: Yes
Reference: add_stripes_use_stripe_width

add_stripes_via_using_exact_crossover_size

generate partial vias of the exact crossover size

Type: bool
Default: true
Edit: Yes
Reference: add_stripes_via_using_exact_crossover_size

add_stripes_width_file

Specify the values of recommended width in the file name

Type: string
Default: ""
Edit: Yes
Reference: add_stripes_width_file

add_target_pg_allow_weak_connect

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decreate specified pillar number to avoid drc

Type: bool
Default: false
Edit: Yes
Reference: add_target_pg_allow_weak_connect

add_target_pg_max_extension_distance

Specify the max distance that target PG pin can extend to target layer
Type: double
Default: 2.14748e+09
Edit: Yes
Reference: add_target_pg_max_extension_distance

add_target_pg_pins

Specify the cell pins to be connected

Type: string
Default: ""
Edit: Yes
Reference: add_target_pg_pins

add_target_pg_pins_group_distance

Specify the side_to_side distance of pins to be treated as a group during connecting target PG
pins
Type: string
Default: auto
Edit: Yes
Reference: add_target_pg_pins_group_distance

add_target_pg_respect_routes

Specifies whether to honor pre-existing routes check during stripe generation

Type: enum
Enum Values: none | fixed fixed_and_clock all
Default: fixed_and_clock
Edit: Yes
Reference: add_target_pg_respect_routes

add_target_pg_share_resource

New added PG connect to the existing PG at middle layer

Type: bool
Default: true
Edit: Yes
Reference: add_target_pg_share_resource

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add_tieoffs_cells

Set tie cell lists for set_db command

Type: string
Default: ""
Edit: Yes
Reference: add_tieoffs_cells

add_tieoffs_create_hports

Add tie-cells in different hierarchy than tie-off pins when possible

Type: bool
Default: false
Edit: Yes
Reference: add_tieoffs_create_hports

add_tieoffs_honor_dont_touch

honor dont_touch attribute on nets, insts, cells and modules

Type: bool
Default: false
Edit: Yes
Reference: add_tieoffs_honor_dont_touch

add_tieoffs_honor_dont_use

honor dont_use attribute on cells.

Type: bool
Default: false
Edit: Yes
Reference: add_tieoffs_honor_dont_use

add_tieoffs_max_distance

distance between tie-cell and tie-pins should be less than given value
Type: double
Default: 0.0
Edit: Yes
Reference: add_tieoffs_max_distance

add_tieoffs_max_fanout

the number of tie-pins a tie-net can drive. A '0' means no-limit

Type: int
Default: 0
Edit: Yes
Reference: add_tieoffs_max_fanout

add_tieoffs_module_prevention

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add tie cell for module instantiation port

Type: bool
Default: false
Edit: Yes
Reference: add_tieoffs_module_prevention

add_tieoffs_prefix

Prefix of tie cell instances

Type: string
Default: ""
Edit: Yes
Reference: add_tieoffs_prefix

add_tieoffs_report_hports

Report created ports when add_tieoffs_create_hports is set

Type: bool
Default: false
Edit: Yes
Reference: add_tieoffs_report_hports

add_well_taps_avoid_abutment

Specifies whether the inserted taps should avoid horizontal and vertical abutment
Type: bool
Default: false
Edit: Yes
Reference: add_well_taps_avoid_abutment

add_well_taps_block_boundary_only

Specifies whether inserting termination cells on the core boundary

Type: bool
Default: false
Edit: Yes
Reference: add_well_taps_block_boundary_only

add_well_taps_bottom_tap_cell

Cell to be used as bottom tap for add_endcaps boundary cell insertion flow
Type: string
Default: ""
Edit: Yes
Reference: add_well_taps_bottom_tap_cell

add_well_taps_bottom_termination_cell

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Specifies the list of bottom termination cells to be used

Type: string
Default: ""
Edit: Yes
Reference: add_well_taps_bottom_termination_cell

add_well_taps_cell

Cell to be used as well_taps

Type: string
Default: ""
Edit: Yes
Reference: add_well_taps_cell

add_well_taps_channel_offset

Specifies the offset value between taps and blockage in channel

Type: double
Default: 0.0
Edit: Yes
Reference: add_well_taps_channel_offset

add_well_taps_check_channel

Specifies whether checking blockage channel

Type: bool
Default: false
Edit: Yes
Reference: add_well_taps_check_channel

add_well_taps_column_cells

Specifies the list of cells which can be replaced by termination cell

Type: string
Default: ""
Edit: Yes
Reference: add_well_taps_column_cells

add_well_taps_create_rows

Create rows for welltap cell techSites which do not have rows in the floor plan
Type: bool
Default: false
Edit: Yes
Reference: add_well_taps_create_rows

add_well_taps_disable_check_zone_at_boundary

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disable check zone at bounadry

Type: enum
Enum Values: none vdd vss both
Default: none
Edit: Yes
Reference: add_well_taps_disable_check_zone_at_boundary

add_well_taps_in_row_offset

Specifies the distance between the first wellTap in a row and the start of the row
Type: double
Default: 0.0
Edit: Yes
Reference: add_well_taps_in_row_offset

add_well_taps_insert_cells

Insert well-taps based on cell, layer and inertval

Type: string
Default: ""
Edit: Yes
Reference: add_well_taps_insert_cells

add_well_taps_rule

Specifies the well latch-up rule

Type: double
Default: 0.0
Edit: Yes
Reference: add_well_taps_rule

add_well_taps_site_offset

Specifies the offset value in number of sites that vertical taps need to be aware of
Type: int
Default: 1
Edit: Yes
Reference: add_well_taps_site_offset

add_well_taps_termination_align

Specifies the termination cell align

Type: enum
Enum Values: left right center
Default: left
Edit: Yes
Reference: add_well_taps_termination_align

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add_well_taps_termination_cells

Specifies the list of termination cells to be used

Type: string
Default: ""
Edit: Yes
Reference: add_well_taps_termination_cells

add_well_taps_top_tap_cell

Cell to be used as top tap for add_endcaps boundary cell insertion flow
Type: string
Default: ""
Edit: Yes
Reference: add_well_taps_top_tap_cell

add_well_taps_top_termination_cell

Specifies the list of top termination cells to be used

Type: string
Default: ""
Edit: Yes
Reference: add_well_taps_top_termination_cell

add_well_taps_vertical_boundary_spacing

Specifies the spacing between center of tap cell and vertical boundary
Type: double
Default: -1.0
Edit: Yes
Reference: add_well_taps_vertical_boundary_spacing

add_well_taps_well_cut_cells

Specifies the list of cells with the well cuts

Type: string
Default: ""
Edit: Yes
Reference: add_well_taps_well_cut_cells

analysis_views

Returns the information about the analysis views in the design.

Type: obj(analysis_view)*
Default: ""
Edit: No

analyze_proto_place_design

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Runs cell placement

Type: bool
Default: true
Edit: Yes
Reference: analyze_proto_place_design

analyze_proto_read_timing_debug_report

Invokes timing debugger

Type: bool
Default: true
Edit: Yes
Reference: analyze_proto_read_timing_debug_report

analyze_proto_time_design

Invokes prototype timing analysis

Type: bool
Default: true
Edit: Yes
Reference: analyze_proto_time_design

analyze_proto_trial_route

Routes the design with specific setting

Type: string
Default: off
Edit: Yes
Reference: analyze_proto_trial_route

analyze_proto_trial_route_max_iteration

Specifies number of timing driven trialRoute iterations

Type: int
Default: 4
Edit: Yes
Reference: analyze_proto_trial_route_max_iteration

assign_pins_advanced_node_rule_support

If you use this parameter, all the pin related command will use design object shapes for
deciding pin location which will give accurate result but will have larger runtime.
Type: bool
Default: true
Edit: Yes
Reference: assign_pins_advanced_node_rule_support

assign_pins_allow_non_ndr_net_pins_on_ndr_tracks

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A true value allows general pins to be placed on ndr tracks if available. Alternately, if the value
is set to false, the ndr-track rule is followed strictly and the net's pins are placed on matching
ndr tracks only.
Type: bool
Default: true
Edit: Yes
Reference: assign_pins_allow_non_ndr_net_pins_on_ndr_tracks

assign_pins_allow_unconnected_in_abutted_edge

If you use this parameter, unconnected partition pin can be placed in abutted edge
Type: bool
Default: true
Edit: Yes
Reference: assign_pins_allow_unconnected_in_abutted_edge

assign_pins_blocked_boundary_macro_distance

This option blocks automatic pin assignment, from putting pins on the part of partition
boundary facing block on layers with OBS, in the places where channel width between
partition boundary and block is less than the value specified. For channel width below
specified value, block all pins on boundary facing this channel on layers with OBS.
Type: double
Default: 3.0
Edit: Yes
Reference: assign_pins_blocked_boundary_macro_distance

assign_pins_edit_in_batch

To enable/disable pin-editing in batch mode.

Type: bool
Default: false
Edit: Yes
Reference: assign_pins_edit_in_batch

assign_pins_force_abutment_with_fixed

For fixed abutted pins's connected pin, ignore soft constraints checks
Type: bool
Default: true
Edit: Yes
Reference: assign_pins_force_abutment_with_fixed

assign_pins_max_channel_width_as_abutted

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If you set this parameter value then all channel less than equal to specified value will be
considered as abutted and abutment rules will be applied
Type: double
Default: 3.0
Edit: Yes
Reference: assign_pins_max_channel_width_as_abutted

assign_pins_max_distance_pair

Ignores moving corresponding connected pins of 2-pin-connection nets where distance (in
microns) between the pins is equal or greater than distance specified
Type: double
Default: 50.0
Edit: Yes
Reference: assign_pins_max_distance_pair

assign_pins_off_stripe

Prevents the generation of pins on metal layers with respect to the power and ground stripe
Type: enum
Enum Values: below all none
Default: none
Edit: Yes
Reference: assign_pins_off_stripe

assign_pins_pin_to_stripe_distance

Layer specific, keep distance (in microns) from pin to stripe

Type: string
Default: ""
Edit: Yes
Reference: assign_pins_pin_to_stripe_distance

assign_pins_pin_to_via_distance_non_preferred_direction

Layer specific, keep distance (in microns) from pin to via-stack

Type: string
Default: ""
Edit: Yes
Reference: assign_pins_pin_to_via_distance_non_preferred_direction

assign_pins_pin_to_via_distance_preferred_direction

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Layer specific, keep distance (in microns) from pin to via-stack from the partition fence
boundary
Type: string
Default: ""
Edit: Yes
Reference: assign_pins_pin_to_via_distance_preferred_direction

assign_pins_promoted_macro_bottom_layer

Specifies the minimum metal layer name for promoting macro pins
Type: string
Default: 31
Edit: Yes
Reference: assign_pins_promoted_macro_bottom_layer

assign_pins_promoted_macro_top_layer

Specifies the maximum metal layer name for promoting macro pins
Type: string
Default: 31
Edit: Yes
Reference: assign_pins_promoted_macro_top_layer

assign_pins_restricted_boundary_macro_distance

This option blocks automatic pin assignment, from putting pins on the part of partition
boundary facing block on layers with OBS, in the places where channel width between
partition boundary and block is less than the value specified. For channel width below
specified value: OBS area on the layer, channel length and channel width considered to allow
suitable number of pins on boundary facing this channel.
Type: double
Default: 30.0
Edit: Yes
Reference: assign_pins_restricted_boundary_macro_distance

assign_pins_strict_abutment

To relax abutment violations, for placing multi partition pin of a net and non neighbor pins of a
net on abutted edges
Type: bool
Default: true
Edit: Yes
Reference: assign_pins_strict_abutment

attributes

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Short-cut for [get_db obj_types .attributes]

Type: obj(attribute)*
Default: ""
Edit: No

auto_file_dir

Represents the top-level directory to store files/sub-directories 'auto-generated' by the tool.

Type: string
Default: ./
Edit: Yes
Reference: auto_file_dir

auto_file_prefix

Represents the prefix to be applied to all files/sub-directories 'auto-generated' by the tool.

Type: string
Default: ""
Edit: Yes
Reference: auto_file_prefix

base_cells

All the base_cells from .lib, Verilog stubs, LEF or OA.

Type: obj(base_cell)*
Default: ""
Edit: No

base_pins

All the base_pins in all the base_cells.

Type: obj(base_pin)*
Default: ""
Edit: No

boundaries

Short-cut to all the boundary objects (fence, region, etc.) in the design.
Type: obj(boundary)*
Default: ""
Edit: No

budget_abutted

Assumes all partitions are abutted

Type: bool
Default: false
Edit: Yes
Reference: budget_abutted

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budget_accumulated

To be used for flat constraints in case of nested partitions, in conjunction with set_db
budget_use_accumulated
Type: bool
Default: false
Edit: Yes
Reference: budget_accumulated

budget_boundary_model_path

Directory path containing model files to be used with option useBoundaryCondition template
Type: string
Default: ""
Edit: Yes
Reference: budget_boundary_model_path

budget_buffer_delay_adjustment

User defined value for virtual buffer adjustment

Type: double
Default: -1.0
Edit: Yes
Reference: budget_buffer_delay_adjustment

budget_buffer_delay_lib_cell

user defined buffer which should be used for virtual buffer adjustment
Type: string
Default: ""
Edit: Yes
Reference: budget_buffer_delay_lib_cell

budget_buffer_delay_selection_effort

controls the tool effort for calculating the buffer delay adjustment internally
Type: enum
Enum Values: low high
Default: low
Edit: Yes
Reference: budget_buffer_delay_selection_effort

budget_constant_model

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Specifies the type of timing model created

Type: bool
Default: true
Edit: Yes
Reference: budget_constant_model

budget_distribute_mmmc

distributed multiple analysis views over multiple sessions

Type: bool
Default: false
Edit: Yes
Reference: budget_distribute_mmmc

budget_drive_cell

write boundary drive information

Type: bool
Default: false
Edit: Yes
Reference: budget_drive_cell

budget_fix_top_level_paths

Fixes the top-level timing budget, and proportions the remaining timing budget only for the
partitions
Type: enum
Enum Values: none all negative_only positive_only
Default: none
Edit: Yes
Reference: budget_fix_top_level_paths

budget_handle_complex_sdc

handle sdc files with complex constructs and regular expressions in push down
Type: bool
Default: false
Edit: Yes
Reference: budget_handle_complex_sdc

budget_honor_report_timing_format

honor set_global report_timing_format in justification reports

Type: bool
Default: false
Edit: Yes
Reference: budget_honor_report_timing_format

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budget_ignore_dont_touch

Specifies the handling of don't touch objects

Type: bool
Default: false
Edit: Yes
Reference: budget_ignore_dont_touch

budget_include_latency

Specifies whether the clock latency is included in the set_input_delay and set_output_delay
constraints
Type: bool
Default: true
Edit: Yes
Reference: budget_include_latency

budget_include_wire_loads_in_lib

Include the wire loads in library model pin capacitance

Type: bool
Default: false
Edit: Yes
Reference: budget_include_wire_loads_in_lib

budget_input_load

write set_load for input pins

Type: bool
Default: false
Edit: Yes
Reference: budget_input_load

budget_input_transition

write input transition using set_input_transition

Type: bool
Default: false
Edit: Yes
Reference: budget_input_transition

budget_justify

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controls the type of justification

Type: enum
Enum Values: delay exception lib_arc boundary_condition all
Default: ""
Edit: Yes
Reference: budget_justify

budget_keep_pin_list_for_block_ports

Preserve all fan-in and fan-out lists

Type: bool
Default: true
Edit: Yes
Reference: budget_keep_pin_list_for_block_ports

budget_latency_on_clocks

write set_clock_latency on clocks

Type: bool
Default: false
Edit: Yes
Reference: budget_latency_on_clocks

budget_local_latency

Write user specific set_clock_latency constraints, provided through

set_partition_user_constraints_file command, in partition constraint files
Type: bool
Default: false
Edit: Yes
Reference: budget_local_latency

budget_local_uncertainty

Use local uncertainty specified through set_partition_user_constraints_file command for

partitions
Type: bool
Default: false
Edit: Yes
Reference: budget_local_uncertainty

budget_make_negative_input_delay_zero

To be backward compatible where negative set input delays were made zero
Type: bool
Default: false
Edit: Yes
Reference: budget_make_negative_input_delay_zero

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budget_master_clone

controls the tool behaviour for master clones

Type: enum
Enum Values: master_only merged unique_view_per_hinst
Default: master_only
Edit: Yes
Reference: budget_master_clone

budget_no_false_paths_for_unconstrained_ports

do not create false paths for unconstrained ports

Type: bool
Default: false
Edit: Yes
Reference: budget_no_false_paths_for_unconstrained_ports

budget_no_hold_view

Disable hold view budgeting

Type: bool
Default: false
Edit: Yes
Reference: budget_no_hold_view

budget_no_setup_view

Disable setup view budgeting

Type: bool
Default: false
Edit: Yes
Reference: budget_no_setup_view

budget_override_net_cap

Specifies the lump capacitance value.

Type: double
Default: 100.0
Edit: Yes
Reference: budget_override_net_cap

budget_pin_load

write set_load with -pin_load information

Type: bool
Default: false
Edit: Yes
Reference: budget_pin_load

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budget_report_dir

Alternate directory name for justify reports when -justify is given with create_timing_budget
Type: string
Default: budget_justify
Edit: Yes
Reference: budget_report_dir

budget_report_negative_slack_on_ports

save warnings for ports having slack less than the specified value
Type: double
Default: 0.0
Edit: Yes
Reference: budget_report_negative_slack_on_ports

budget_report_or_update_budget

Enable the collection of data to use the update_timing_budget command

Type: bool
Default: false
Edit: Yes
Reference: budget_report_or_update_budget

budget_snap_feedthru_budget_to

Specifies the minimum delay value (in picoseconds) for the path from partition input port to
partition output port.
Type: double
Default: 0.0
Edit: Yes
Reference: budget_snap_feedthru_budget_to

budget_snap_input_budget_to

Specifies the minimum delay (in picoseconds) for the path from the partition input port to the
internal register.
Type: double
Default: 0.0
Edit: Yes
Reference: budget_snap_input_budget_to

budget_snap_negative_only

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Considers the only negative slack paths when used with budget_snap_input_budget_to and
budget_snap_output_budget_to.
Type: bool
Default: false
Edit: Yes
Reference: budget_snap_negative_only

budget_snap_output_budget_to

Specifies the min delay (in picoseconds) for the path from the internal register to the partition
output port.
Type: double
Default: 0.0
Edit: Yes
Reference: budget_snap_output_budget_to

budget_top_level

Specifies the minimum % of total available budget set aside for the top level
Type: double
Default: -1.0
Edit: Yes
Reference: budget_top_level

budget_top_level_delay_per_length

Specifies the top-level estimated delay (in picoseconds) per millimeter length.
Type: int
Default: 180
Edit: Yes
Reference: budget_top_level_delay_per_length

budget_top_level_min_delay_per_net

Specifies the top-level minimum delay-per-net value in picoseconds/millimeter units.

Type: int
Default: 100
Edit: Yes
Reference: budget_top_level_min_delay_per_net

budget_use_boundary_condition

Mechanism used for finding buffers to be used as driver/load

Type: enum
Enum Values: optimized template actual empty
Default: template
Edit: Yes
Reference: budget_use_boundary_condition

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budget_use_real_cell_for_timing_model

Use actual gate connected to the partition port to write out the model timing arc, else medium
size buffer is used
Type: bool
Default: false
Edit: Yes
Reference: budget_use_real_cell_for_timing_model

budget_virtual_opt_engine

Specifies the virtual optimization engine to be used

Type: enum
Enum Values: none opt early_timing_engine proto
Default: none
Edit: Yes
Reference: budget_virtual_opt_engine

budget_write_constraints_for_clock_output_ports

Write constraints for clock output ports

Type: bool
Default: false
Edit: Yes
Reference: budget_write_constraints_for_clock_output_ports

budget_write_false_path_for_hold

write false path -hold for all I/Os in setup budgeting

Type: bool
Default: false
Edit: Yes
Reference: budget_write_false_path_for_hold

budget_write_latency_per_clock

write latency per clock instead of per port

Type: bool
Default: false
Edit: Yes
Reference: budget_write_latency_per_clock

budget_write_virtual_io_clocks

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Write I/O Constraints using virtual clocks only

Type: bool
Default: false
Edit: Yes
Reference: budget_write_virtual_io_clocks

bumps

Short-cut for [get_db current_design .bumps]

Type: obj(bump)*
Default: ""
Edit: No

bus_sink_groups

busses

Short-cut for [get_db current_design .busses]

Type: obj(bus)*
Default: ""
Edit: No

available categories of root attributes

Type: string
Default: ""
Edit: No

ccopt_auto_limit_insertion_delay_factor

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CCOpt attempts to keep the insertion delays of each clock tree a fixed multiple
of the longest insertion delay that would result from a global skew approach.
This multiple can be modified by design timing and the presence of other clock
trees, but will start at a fixed fraction above the global skew insertion delay.
This attribute specifies that fixed fraction.
Valid values: real
See also:
. ccopt_auto_limit_insertion_delay_factor_skew_group
Type: double
Default: 1.5
Edit: Yes
Reference: ccopt_auto_limit_insertion_delay_factor

ccopt_merge_clock_gates

If set to true, clock gate merging is enabled. If this is false, merging of all
clock gates is disabled, including clock gates which may have been cloned by
CTS.
Note that this attribute has no impact on 'ccopt_design -cts'. See also attribute
cts_merge_clock_gates.
Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: ccopt_merge_clock_gates

ccopt_merge_clock_logic

If set to true, clock logic merging is enabled. If this is false, merging of all
clock logics is disabled, including clock logics which may have been cloned by
CTS.
Note that this attribute has no impact on 'ccopt_design -cts'. See also attribute
cts_merge_clock_logic.
Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: ccopt_merge_clock_logic

check_ac_limit_additional_individual_violation_report

Report calculated duty ratio in addition with applied duty ratio in report file.
Type: bool
Default: false
Edit: Yes
Reference: check_ac_limit_additional_individual_violation_report

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check_ac_limit_avg_recovery

override QRC tech em_recover factor for all layers used in Iavg limits.
Type: double
Default: 1.0
Edit: Yes
Reference: check_ac_limit_avg_recovery

check_ac_limit_check_thermal_aware_em

check thermal aware EM

Type: bool
Default: false
Edit: Yes

check_ac_limit_current_file

Specify current file to provide currents for cell/instance's pin.

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_current_file

check_ac_limit_current_scale_factor

Scale Signal EM current, syntax: -current_scale_factor { [rms <rms_value>] [peak

<peak_value>] [avg <avg_value>] }
Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_current_scale_factor

check_ac_limit_current_scale_table

Specifies the layer-based scale table for current

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_current_scale_table

check_ac_limit_default_freq_for_unconstrained_nets

Specifies the frequency for EM calculation when a net has no defined frequency or a defined
frequency of 0Hz in the design. Unit: Hz.
Type: double
Default: 1e+06
Edit: Yes
Reference: check_ac_limit_default_freq_for_unconstrained_nets

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check_ac_limit_delta_temperature

maximum change in temperature allowed in units of Celsius. Used in the QRC tech for RMS
limits. Default=5.
Type: double
Default: 5.0
Edit: Yes
Reference: check_ac_limit_delta_temperature

check_ac_limit_delta_temperature_layer_list

Specifies layer based delta temperature for EM RMS currnet limit analysis
Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_delta_temperature_layer_list

check_ac_limit_detailed

Generates a detailed report containing information for all signal nets, including those without
violations
Type: bool
Default: false
Edit: Yes
Reference: check_ac_limit_detailed

check_ac_limit_effort_level

Enum_list legal values are: low, medium, high. Default: low.

Type: enum
Enum Values: low medium high
Default: low
Edit: Yes
Reference: check_ac_limit_effort_level

check_ac_limit_em_cdf_percentage

Specify em cumulative distribution factor (cdf) percentage.

Type: double
Default: 1e-09
Edit: Yes
Reference: check_ac_limit_em_cdf_percentage

check_ac_limit_em_limit_scale_factor

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Scale Signal EM limit, syntax: -em_limit_scale_factor { [rms <rms_value>] [peak

<peak_value>] [avg <avg_value>] }
Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_em_limit_scale_factor

check_ac_limit_em_limit_scale_table

Specifies the layer-based scale table for em_limit

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_em_limit_scale_table

check_ac_limit_em_res_width

Specifies width used to get EM limit. enum_list legal values are: drawn, silicon. Default:
drawn.
Type: enum
Enum Values: drawn silicon
Default: drawn
Edit: Yes
Reference: check_ac_limit_em_res_width

check_ac_limit_em_temperature

Specifies the temperature used to lookup the temperature scaling factor. By default, no scaling
is done. Unit: Celsius.
Type: double
Default: -1.0
Edit: Yes
Reference: check_ac_limit_em_temperature

check_ac_limit_em_temperature_layer_list

Specifies layer based EM temperature for EM AVG current limit analysis

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_em_temperature_layer_list

check_ac_limit_em_threshold

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The value is the ratio of signal current (avg/peak/rms) to the respective EM limit. Default: 1.0.
Type: double
Default: 1.0
Edit: Yes
Reference: check_ac_limit_em_threshold

check_ac_limit_enable_seb

Enable SEB calculation

Type: bool
Default: false
Edit: Yes
Reference: check_ac_limit_enable_seb

check_ac_limit_env_temperature

environment temperature. Unit: Celsius.

Type: double
Default: -1.0
Edit: Yes
Reference: check_ac_limit_env_temperature

check_ac_limit_extraction_tech_file

Specify qrcTechFile name.

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_extraction_tech_file

check_ac_limit_force_hold_view

Turn this on to force hold view.

Type: bool
Default: false
Edit: Yes
Reference: check_ac_limit_force_hold_view

check_ac_limit_handle_pin_obs_via

Turn on to handle pin obs via.

Type: bool
Default: false
Edit: Yes
Reference: check_ac_limit_handle_pin_obs_via

check_ac_limit_ict_em_models

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Specify ict EM file to provide EM rule if EM rule not exists in qrcTechFile.

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_ict_em_models

check_ac_limit_lifetime

Specifies the hours of operation used to lookup the lifetime scaling factor. By default, no
scaling is done. Unit: hour.
Type: double
Default: 87600.0
Edit: Yes
Reference: check_ac_limit_lifetime

check_ac_limit_max_error

Specifies the maximam number of errors to report.

Type: int
Default: 10000
Edit: Yes
Reference: check_ac_limit_max_error

check_ac_limit_method

Specifies the current waveform calculation method, check one or more of Irms, Ipeak, and Iavg
limits. enum_list legal values are: rms, peak, avg. Default: rms.
Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_method

check_ac_limit_min_peak_duty_ratio

Do not check Ipeak for nets with duty ratio below <duty_ratio>. default = 0.05, range 0.0 to 1.0.
Type: double
Default: -1.0
Edit: Yes
Reference: check_ac_limit_min_peak_duty_ratio

check_ac_limit_min_peak_freq

Do not check Ipeak for nets with frequency below <freq> in units of hertz. default = 1e6. Unit:
Hz.
Type: double
Default: 1e+06
Edit: Yes
Reference: check_ac_limit_min_peak_freq

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check_ac_limit_net_file

Specifies from file the net to check in signalEM analysis

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_net_file

check_ac_limit_nets

Specifies whether to check named or selected nets

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_nets

check_ac_limit_out_file

Specifies the report file for the violation data

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_out_file

check_ac_limit_peak_td_method

Specifies Td calculation method for Ipeak check. enum_list legal values are:
effective_width_from_integration, effective_half_peak_width, max_equivalent_dc_peak,
sum_half_peak_width. Default: effective_width_from_integration.
Type: enum
Enum Values: effective_width_from_integration effective_half_peak_width
max_equivalent_dc_peak sum_half_peak_width
Default: effective_width_from_integration
Edit: Yes
Reference: check_ac_limit_peak_td_method

check_ac_limit_seb_lifetime

Specifies the hours of operation. By default, it's 5 years. Unit：hour.

Type: double
Default: 43800.0
Edit: Yes
Reference: check_ac_limit_seb_lifetime

check_ac_limit_seb_table

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Specify seb table file.

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_seb_table

check_ac_limit_seb_temperature

Specifies the temperature of operation. By default, it's 110c. Unit: Celsius.

Type: double
Default: -273.0
Edit: Yes
Reference: check_ac_limit_seb_temperature

check_ac_limit_selected

Specifies whether to check named or selected nets

Type: bool
Default: false
Edit: Yes
Reference: check_ac_limit_selected

check_ac_limit_skip_category_mode

Specify the mode that under which condition a net should be skipped and which category a
skipped net belongs to.
Type: int
Default: 1
Edit: Yes
Reference: check_ac_limit_skip_category_mode

check_ac_limit_skip_net

Specifies the net to be skipped in signalEM analysis

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_skip_net

check_ac_limit_skip_net_file

Specifies the net to be skipped in signalEM analysis

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_skip_net_file

check_ac_limit_toggle

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Specifies the toggle rate for signal nets

Type: double
Default: 1.0
Edit: Yes
Reference: check_ac_limit_toggle

check_ac_limit_use_db_freq

Uses the database frequency value as the effective frequency per net
Type: bool
Default: false
Edit: Yes
Reference: check_ac_limit_use_db_freq

check_ac_limit_use_qrc_tech

Turn this on to force Irms checks to use the QRC tech file rather than the LEF tech. If either
Ipeak or Iavg is also checked, then all checks will use the QRC tech file, including Irms.
Type: bool
Default: true
Edit: Yes
Reference: check_ac_limit_use_qrc_tech

check_ac_limit_use_rms_delta_t

Turn on to use rms delta temperature.

Type: bool
Default: false
Edit: Yes
Reference: check_ac_limit_use_rms_delta_t

check_ac_limit_view

Specifies the name of the view

Type: string
Default: ""
Edit: Yes
Reference: check_ac_limit_view

check_drc_area

Specifies the coordinates of the area to verify

Type: rect
Default: 0.0 0.0 0.0 0.0
Edit: Yes
Reference: check_drc_area

check_drc_check_only

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Specifies what kind of shapes to be checked.

Type: enum
Enum Values: all regular special selected_net selected cell default
Default: default
Edit: Yes
Reference: check_drc_check_only

check_drc_check_reverse

report CONVEXCORNER REVERSE violation.

Type: bool
Default: false
Edit: Yes
Reference: check_drc_check_reverse

check_drc_check_routing_halo

Check routing halo.

Type: bool
Default: false
Edit: Yes
Reference: check_drc_check_routing_halo

check_drc_check_routing_halo_corner

Check routing halo in the corner

Type: bool
Default: false
Edit: Yes
Reference: check_drc_check_routing_halo_corner

check_drc_disable_rules

Disable the rule that from the provided rule list. the rule list as follow: (jog2jog_spacing |
eol_spacing cut_spacing min_cut enclosure color min_step protrusion min_area out_of_die
off_manufacturing_grid off_routing_track)
Type: enum
Enum Values: jog2jog_spacing eol_spacing cut_spacing min_cut enclosure color min_step
protrusion min_area out_of_die off_manufacturing_grid off_routing_track
Default: ""
Edit: Yes
Reference: check_drc_disable_rules

check_drc_exclude_pg_net

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Excludes the checking of power and ground nets.

Type: bool
Default: false
Edit: Yes
Reference: check_drc_exclude_pg_net

check_drc_ignore_cell_blockage

Ignore geometries of cell blockage.

Type: bool
Default: false
Edit: Yes
Reference: check_drc_ignore_cell_blockage

check_drc_ignore_trial_route

Ignore trial route when check drc.

Type: bool
Default: false
Edit: Yes
Reference: check_drc_ignore_trial_route

check_drc_inside_via_def

Check the cut spacing from the same via

Type: bool
Default: true
Edit: Yes
Reference: check_drc_inside_via_def

check_drc_layer_range

Checks between the range of metal layers including cut layers in between
Type: string
Default: ""
Edit: Yes
Reference: check_drc_layer_range

check_drc_limit

Specifies the maximum number of errors to report

Type: int
Default: 1000
Edit: Yes
Reference: check_drc_limit

check_drc_max_wrong_way_halo

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Specifies the maximum wrong way halo

Type: double
Default: -1.0
Edit: Yes
Reference: check_drc_max_wrong_way_halo

check_drc_ndr_spacing

Specifies what kind of non-default rule spacing to be checked

Type: enum
Enum Values: true false auto
Default: auto
Edit: Yes
Reference: check_drc_ndr_spacing

check_drc_report

Specifies the report file that contains the violations information

Type: string
Default: ""
Edit: Yes
Reference: check_drc_report

check_drc_short_only

Exclude all DRC check except short.

Type: bool
Default: false
Edit: Yes
Reference: check_drc_short_only

check_drc_trim_length

Consider max length in the trim shape layer.

Type: bool
Default: false
Edit: Yes
Reference: check_drc_trim_length

check_drc_uncolored

report color change violation when the dpt layer shape is free color.
Type: bool
Default: false
Edit: Yes
Reference: check_drc_uncolored

check_drc_use_min_spacing_on_block_obs

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Use min spacing to check for block OBS.

Type: enum
Enum Values: true false auto
Default: auto
Edit: Yes
Reference: check_drc_use_min_spacing_on_block_obs

clock_tree_source_groups

list of clock_tree_source_group
Type: obj(clock_tree_source_group)*
Default: ""
Edit: No
Reference: clock_tree_source_groups

clock_trees

list of clock_tree
Type: obj(clock_tree)*
Default: ""
Edit: No
Reference: clock_trees

clocks

clocks
Type: obj(clock)*
Allowed -index values: analysis_view
Default: ""
Edit: No

cmd_file

The cmd file name of the program. It has each command run in the current session. It can be
changed during the session to direct cmd file output to a different file. Type 'man log_file' for
more details.
Type: string
Default: ""
Edit: Yes
Reference: cmd_file

constraint_modes

Returns the information about the constraint modes in the design.

Type: obj(constraint_mode)*
Default: ""
Edit: No

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cts_adjacent_rows_legal

Defines the clock halo in the y direction. If set to true the y direction clock halo is zero and
other clock instances are allowed in adjacent rows.
The following attributes can be used to assign y direction clock halos within CCOpt:
cts_cell_halo_y
cts_adjacent_rows_legal
cts_cell_halo_rows
Only one of these attributes is used to determine the clock halo in the y direction. The
following rules determine which:
. If cts_cell_halo_y is set to a non-auto value, then this defines the y direction clock halo. The
attributes cts_adjacent_rows_legal and cts_cell_halo_rows have no effect.
. If cts_cell_halo_y is set to auto and cts_adjacent_rows_legal is set to a non-auto value then
cts_adjacent_rows_legal defines the clock halo in the y direction. The attribute
cts_cell_halo_rows has no effect.
. If both cts_cell_halo_y and cts_adjacent_rows_legal are set to auto then
cts_cell_halo_rows defines the clock halo in the y direction.
Valid values: true false
See also:
. cts_cell_halo_y
. cts_cell_halo_rows
Type: string
Default: false
Edit: Yes
Reference: cts_adjacent_rows_legal

cts_allow_non_std_clock_gate_inputs

If this attribute is set, CTS will allow the use of clock gates with non-standard pins. CCOpt
considers the following pin types to be standard: clock pins, enable pins, test enable pins,
retention pins and power gating pins. Before starting CTS CCOpt will emit a warning,
indicating which pin(s) it considers non-standard.
Type: bool
Default: false
Edit: Yes
Reference: cts_allow_non_std_clock_gate_inputs

cts_balance_mode

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Replace CCOpt mode setting cts_opt_type {full | cluster | trial}. If not full, causes CCOpt and
CCOpt CTS to halt before final completion of the clock tree to facilitate clock tree inspection.
The possible values for this attribute are as follows:
- full - default value, a full CTS is performed.
- cluster - a cluster-only CTS is performed. The clock tree has no balancing delay applied.
- trial - The clock has only virtual (numeric annotation) balancing delays applied.
Type: string
Default: full
Edit: Yes
Reference: cts_balance_mode

cts_blackbox_default_driver_base_pin

Base pin that will be used for all timing and capacitance modeling for clock roots with a source
pin at a blackbox output.
Type: string
Default: ""
Edit: Yes

cts_blackbox_default_load_base_pin

Base pin that will be used for all timing and capacitance modeling for clock sinks at blackbox
inputs. Any cts_capacitance_override attribute will be used in preference to this.
Type: string
Default: ""
Edit: Yes

cts_buffer_cells

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cts_buffer_cells_leaf

cts_buffer_cells_top

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cts_cell_density

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Specifies the clock halo in the x direction.

cts_cell_halo_mode

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Specifies how clock halos are used to determine the minimum legal separation between a pair
of clock instances. There are two possible modes 'max' and 'sum'. When set to 'max' the
minimum legal separation is the larger of the two clock halos. When set to 'sum' the minimum
legal separation is the sum of the two clock halos.
Valid values: max sum
See also:
. cts_cell_halo_x
. cts_cell_halo_y
. cts_cell_density
. cts_adjacent_rows_legal
. cts_cell_halo_sites
. cts_cell_halo_rows
. cts_effective_clock_halo_x
. cts_effective_clock_halo_y
. cts_effective_clock_halo_x_source
. cts_effective_clock_halo_y_source
Type: string
Default: max
Edit: Yes
Reference: cts_cell_halo_mode

cts_cell_halo_rows

Specifies the clock halo in the y direction in rows for all clock cells.
The following attributes can be used to assign y direction clock halos within CCOpt:
cts_cell_halo_y
cts_adjacent_rows_legal
cts_cell_halo_rows
Only one of these attributes is used to determine the clock halo in the y direction. The
following rules determine which:
. If cts_cell_halo_y is set to a non-auto value, then this defines the y direction clock halo. The
attributes cts_adjacent_rows_legal and cts_cell_halo_rows have no effect.
. If cts_cell_halo_y is set to auto and cts_adjacent_rows_legal is set to a non-auto value then
cts_adjacent_rows_legal defines the clock halo in the y direction. The attribute
cts_cell_halo_rows has no effect.
. If both cts_cell_halo_y and cts_adjacent_rows_legal are set to auto then
cts_cell_halo_rows defines the clock halo in the y direction.
See also:
. cts_cell_halo_y
. cts_adjacent_rows_legal
Type: int
Default: 1
Edit: Yes
Reference: cts_cell_halo_rows

cts_cell_halo_sites

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Specifies the clock halo in the x direction in sites for all clock cells.
The following attributes can be used to assign x direction clock halos within CCOpt:
cts_cell_halo_x
cts_cell_density
cts_cell_halo_sites
Only one of these attributes is used to determine the clock halo in the x direction. The
following rules determine which:
. If cts_cell_halo_x is set to a non-auto value, then this defines the x direction clock halo. The
attributes cts_cell_density and cts_cell_halo_sites have no effect.
. If cts_cell_halo_x is set to auto and cts_cell_density is set to a non-auto value then
cts_cell_density defines the clock halo in the x direction. The attribute cts_cell_halo_sites has
no effect.
. If both cts_cell_halo_x and cts_cell_density are set to auto then cts_cell_halo_sites defines
the clock halo in the x direction.
See also:
. cts_cell_halo_x
. cts_cell_density
Type: int
Default: 4
Edit: Yes
Reference: cts_cell_halo_sites

cts_cell_halo_x

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cts_cell_halo_y

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cts_clock_gate_movement_limit

Each clock gate is restricted to a Manhattan ball centered on its original location with CTS
flow.
The radius of the ball is a multiple of the clock gate height.
This controls the default value of that multiple.
Type: string
Default: 10
Edit: Yes
Reference: cts_clock_gate_movement_limit

cts_clock_gating_cells

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cts_clock_source_cells

cts_clock_tree_source_group_clock_trees

A list of the clock trees relevant to this source group.

Valid values: list cts_clock_trees
Type: string
Default: ""
Edit: Yes
Reference: cts_clock_tree_source_group_clock_trees

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cts_clock_tree_source_input_max_transition_time

The slew which will be assumed at the input of the root driver.
Valid values: double
Type: double
Allowed -index values: delay_corner
Default: 0
Edit: Yes
Reference: cts_clock_tree_source_input_max_transition_time

cts_cloning_inst_name_suffix

If set, the suffix will be used generally for all insts cloned by CTS, else the suffix will default to
"clone".
Type: string
Default: clone
Edit: Yes

cts_cloning_inst_name_suffix_source_group_assignment

Specifically controls the suffix used for multi tap cloning, and will default to whatever the
cts_cloning_inst_name_suffix attribute value is, which defaults to "clone".
Type: string
Default: clone
Edit: Yes

cts_delay_cells

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cts_detailed_cell_warnings

If set to true, CCOpt outputs detailed cell warning diagnostics when it

encounters issues with library cell selection, power domains and/or signal
levels.
Valid values: true false
Type: bool
Default: false
Edit: Yes
Reference: cts_detailed_cell_warnings

cts_exit_if_no_placeable_area

Specifies that CTS should exit if the design has zero placeable area.
Setting this attribute may be useful to temporarily work-around problems with row
definition and/or blockages causing placeable area to be zero.
Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: cts_exit_if_no_placeable_area

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cts_exit_if_skew_target_over_constrained

Specifies that CCOpt should exit as current skew targets are

likely to lead to poor results. By default, CCOpt computes a minimum skew
target which should not lead to excessive buffering, and does not allow any
skew target to be set lower than this minimum. This attribute overrides that
check, and allows any skew target to be used.
Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: cts_exit_if_skew_target_over_constrained

cts_exit_if_stage_delay_sigma_target_over_constrained

If set, allows any max stage delay sigma target to be set. If the target is too low, it is likely to
lead to runtime problems.
Type: bool
Default: true
Edit: Yes
Reference: cts_exit_if_stage_delay_sigma_target_over_constrained

cts_exit_if_transition_target_over_constrained

Specifies that CCOpt should exit, as with current slew targets it is

likely to lead to runtime problems. By default, CCOpt computes a minimum slew
target which should not lead to runtime problems, and does not allow any slew
target to be set lower than this minimum. This attribute overrides that check,
and allows any slew target to be used.
Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: cts_exit_if_transition_target_over_constrained

cts_fix_clock_sinks

If set to true, we will DEF lock clock tree sinks after routing in addition to any clock node
locking (fixed).
If set to soft, we will DEF lock clock tree sinks after routing in addition to any clock node
soft_locking (softFixed).
Valid values: true false soft
Type: string
Default: false
Edit: Yes
Reference: cts_fix_clock_sinks

cts_flexible_htree_placement_legalization_effort

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The legalization effort for finding placement unblocked points on the synthesis grid for flexible
H-trees. High placement legalization effort can avoid having to relax placement constraints
when implementing H-trees but may lead to increased runtime.
Valid values: low, high (default low)
Type: string
Default: low
Edit: Yes
Reference: cts_flexible_htree_placement_legalization_effort

cts_ignore_problematic_skew_as_result_of_dont_touch_nets

If set, sinks directly connected to nets that are causing unfixable skew problems will be
ignored for skew balancing.
Type: bool
Default: false
Edit: Yes
Reference: cts_ignore_problematic_skew_as_result_of_dont_touch_nets

cts_inst_name_prefix

The name prefix of instances created by CTS. The default value is

"CTS". The default names of instances are CTS_*.
Valid values: string
Type: string
Default: CTS
Edit: Yes
Reference: cts_inst_name_prefix

cts_inverter_cells

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cts_inverter_cells_leaf

cts_inverter_cells_top

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cts_load_capacitance_cells

cts_logic_cells

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cts_manage_power_intent_violations

If this attribute is set, the CTS algorithm will work around power management
illegalities in the clock tree, as opposed to failing with an error when it
encounters them. This allows the clock tree to be synthesized, but any power
management illegalities will remain in the exported design.
Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: cts_manage_power_intent_violations

cts_max_fanout

The maximum fanout at any point in the clock tree.

Valid values: integer ranged between 2 and 1000 inclusive
Type: int
Default: 100
Edit: Yes
Reference: cts_max_fanout

cts_max_source_to_sink_net_length

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The maximum routing length in microns between driving source pin and driven
sink pin on each net that clock tree synthesis should observe.
This constraint can be applied to either a pin, a clock tree, or a net type.
By default (if this attribute is not set) no explicit clock tree net length
constraint is enforced. However, other clock tree constraints such as maximum
slew (transition) and maximum capacitance will indirectly limit the maximum
net length.
Valid values: double
Type: string
Default: top auto trunk auto leaf auto
Edit: Yes
Reference: cts_max_source_to_sink_net_length

cts_max_source_to_sink_net_length_leaf

The maximum routing length in microns between driving source pin and driven
sink pin on each net that clock tree synthesis should observe.
This constraint can be applied to either a pin, a clock tree, or a net type.
By default (if this attribute is not set) no explicit clock tree net length
constraint is enforced. However, other clock tree constraints such as maximum
slew (transition) and maximum capacitance will indirectly limit the maximum
net length.
Valid values: double
Type: string
Default: auto
Edit: Yes
Reference: cts_max_source_to_sink_net_length_leaf

cts_max_source_to_sink_net_length_top

The maximum routing length in microns between driving source pin and driven
sink pin on each net that clock tree synthesis should observe.
This constraint can be applied to either a pin, a clock tree, or a net type.
By default (if this attribute is not set) no explicit clock tree net length
constraint is enforced. However, other clock tree constraints such as maximum
slew (transition) and maximum capacitance will indirectly limit the maximum
net length.
Valid values: double
Type: string
Default: auto
Edit: Yes
Reference: cts_max_source_to_sink_net_length_top

cts_max_source_to_sink_net_length_trunk

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The maximum routing length in microns between driving source pin and driven
sink pin on each net that clock tree synthesis should observe.
This constraint can be applied to either a pin, a clock tree, or a net type.
By default (if this attribute is not set) no explicit clock tree net length
constraint is enforced. However, other clock tree constraints such as maximum
slew (transition) and maximum capacitance will indirectly limit the maximum
net length.
Valid values: double
Type: string
Default: auto
Edit: Yes
Reference: cts_max_source_to_sink_net_length_trunk

cts_merge_clock_gates

If set to true, clock gate merging is enabled. If this is false, merging of all
clock gates is disabled, including clock gates which may have been cloned by
CTS.
Note that this attribute only impacts 'ccopt_design -cts'. See also attribute
ccopt_merge_clock_gates.
Valid values: true false
Type: bool
Default: false
Edit: Yes
Reference: cts_merge_clock_gates

cts_merge_clock_logic

If set to true, clock logic merging is enabled. If this is false, merging of all
clock logics is disabled, including clock logics which may have been cloned by
CTS.
Note that this attribute only impacts 'ccopt_design -cts'. See also attribute
ccopt_merge_clock_logic.
Valid values: true false
Type: bool
Default: false
Edit: Yes
Reference: cts_merge_clock_logic

cts_mixed_fanout_net_type

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Controls how CCOpt considers nets that have fanout consisting partially but not entirely of
sinks. By default, having any sinks (eg. DFFs) will make the net be considered leaf, but when
set to trunk, a net has to drive only sinks to be considered leaf. For example, a net driving a
clock gate and a DFF would no longer count as a leaf net.
Valid values: leaf trunk
Type: string
Default: leaf
Edit: Yes
Reference: cts_mixed_fanout_net_type

cts_move_clock_gates

If this attribute is set, the CTS algorithm will move clock gates that appear in the clock tree.
Setting this attribute may cause the clock tree to have a lower insertion delay, but might break
datapath timing. During optimization, this is not a problem, because the timing will be
automatically recovered during the optimization process. If this attribute is false, CTS permits
small movements of ICGs for legalization.
Type: bool
Default: true
Edit: Yes
Reference: cts_move_clock_gates

cts_move_logic

If this attribute is set, the CTS algorithm will move logic that appears in the
clock tree. "Logic" does not include clock gates, buffers, and inverters in a
clock tree, which are always moved unless they are locked, or clock generators
that are above the root of the clock tree. Usually, this will affect
multiplexers used for selecting one of a number of clocks, or for switching
between a test clock and the main clock. Setting this attribute may cause the
clock tree to have a lower insertion delay, but might break datapath timing.
During optimization, this is not a problem, because the timing will be
automatically recovered during the optimization process.
Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: cts_move_logic

cts_net_name_prefix

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The name prefix of nets created by CTS. The default value is

"CTS". The default names of nets are CTS, CTS_1, CTS_2... ...
Valid values: string
Type: string
Default: CTS
Edit: Yes
Reference: cts_net_name_prefix

cts_override_vias

When specified, this attribute defines the vias to be used in RC extraction

from routing estimates. The listed vias will be used in place of those configured
on the routing rules for the clock network.
The order of the list is irrelevant.
The vias may also be overridden for each non-default rule (NDR). In this
case, the name of the NDR is given as the first element in the list with subsequent
entries being the via names. Multiple NDRs can be specified, e.g.
{via1d {NDR1 via2d} {NDR2 via2d}} will override via1d in the default rule, and
both via1d and via2d in NDR1 and NDR2.
Valid values: list via_call
Type: string
Default: ""
Edit: Yes
Reference: cts_override_vias

cts_post_route_enable

Enable post-conditioning optimization after clock nets are routed.

Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: cts_post_route_enable

cts_post_route_enable_routing_eco

If set to false, post-conditioning will skip its ECO-routing step.

Valid values: true false
Type: bool
Default: false
Edit: Yes
Reference: cts_post_route_enable_routing_eco

cts_post_route_repair_drv

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If set to false, post-conditioning will skip its DRV-fixing step.

Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: cts_post_route_repair_drv

cts_post_route_repair_skew_by_buffering

If set to true, post-conditioning will attempt skew-fixing using rebuffering.

Valid values: true false
Type: bool
Default: false
Edit: Yes
Reference: cts_post_route_repair_skew_by_buffering

cts_primary_delay_corner

This specifies the delay corner in which clock tree balancing applies the
slew and insertion delay targets. If more than one timing corner is defined,
this must be set before running CCOpt. By default, this is set to the delay corner
contained in the first member of the list of setup views provided to the
set_analysis_view command.
Valid values: corner name, or empty
Type: string
Default: ""
Edit: Yes
Reference: cts_primary_delay_corner

cts_primary_reporting_skew_groups

The primary skew groups used for reporting.

By default, the value is specified as auto that automatically takes the skew group with
maximum number of sinks
as the primary reporting skew group. For invalid values, the default (auto) will be considered.
Valid values: a list of existing skew group names, auto or none
Type: string
Default: auto
Edit: Yes
Reference: cts_primary_reporting_skew_groups

cts_primary_reporting_skew_groups_log_min_max_sinks

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If set to on, the sinks with the shortest and longest paths in each primary reporting skew group
will be logged. If set to logv, they will be logged only to the logv file.
Valid values: on, off, logv
Type: string
Default: logv
Edit: Yes
Reference: cts_primary_reporting_skew_groups_log_min_max_sinks

cts_repair_drv_by_buffering

If set, the standalone clock_post_route_repair command called after route_design and the
clock_post_route_repair called inside opt_design -post_route will fix clock DRVs by adding
buffers, otherwise the tool will not add buffers to fix DRVs.
Valid values: true false
Type: bool
Default: false
Edit: Yes
Reference: cts_repair_drv_by_buffering

cts_report_skew_groups_only_with_targets

The skew groups report (run using the report_skew_groups command) displays
insertion delay, skew, and min/max path information for different combinations of skew group,
timing corner, and early/late path.
Set the cts_report_skew_groups_only_with_targets attribute to false (the default) to report on
all skew group/timing corner/path
combinations regardless of whether a skew target has been set.
Set the cts_report_skew_groups_only_with_targets attribute to true to report only on skew
group/timing corner/path
combinations where a skew target has been set (either explicitly or using the 'auto' setting).
Type: bool
Default: false
Edit: Yes
Reference: cts_report_skew_groups_only_with_targets

cts_route_clock_tree_nets

Perform detailed routing, during the final implementation clock routing phase.
Valid values: true or false
Type: bool
Default: true
Edit: Yes
Reference: cts_route_clock_tree_nets

cts_route_type_leaf

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cts_route_type_top

cts_route_type_trunk

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cts_routing_preferred_layer_effort

Control preferred layer effort for clock routing.

Type: string
Default: standard
Edit: Yes
Reference: cts_routing_preferred_layer_effort

cts_size_clock_gates

When set to true (the default), the CTS algorithm sizes clock gates that appear in the clock
tree. Setting this attribute may cause the clock tree to have a lower insertion delay, but might
change the cell types of logic gates in the clock tree, which in turn may require them to be
moved slightly to find a legal location for the new cell.
Type: bool
Default: true
Edit: Yes
Reference: cts_size_clock_gates

cts_size_clock_sources

When set to true, CTS will try to size the clock source. Only clock sources that are buffers,
inverters, logic and clock gating cells with a single output will be sized. The cells available for
CTS to size clock sources can be set specified using the attribute 'cts_clock_source_cells'.
Valid values: true false
Type: bool
Default: false
Edit: Yes
Reference: cts_size_clock_sources

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cts_size_logic

When set to true (the default), the CTS algorithm sizes logic that appears in
the clock tree. "Logic" does not include clock gates, buffers, and inverters
in a clock tree, which are always sized unless they are locked, or clock
generators that are above the root of the clock tree. Usually, this affects
multiplexers used for selecting one of a number of clocks, or for switching
between a test clock and the main clock. Setting this attribute may cause the
clock tree to have a lower insertion delay, but might change the cell types of
logic gates in the clock tree, which in turn may require them to be moved
slightly to find a legal location for the new cell.
Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: cts_size_logic

cts_skew_group_report_columns

A Tcl list of columns to include in skew group reports produced by the

skew group report. You can use this attribute to specify the columns you
would like to include in the skew group report, and the order in which the
columns should appear.
Most of the legal values are straightforward. However, the set of legal values
of the following form deserve further explanation:
summaryType_summaryLocation[_event]
These values let you report the delay value for other paths that go through
the pin.
summaryType is one of: max (show the longest delay), min (show the shortest
delay), or skew (show the skew, that is the difference between the longest and
the shortest delay).
summaryLocation is one of: above (show the delay/skew above this pin), below
(show the delay/skew below this pin), or through (show the delay/skew for
paths through this pin).
event is one of: rise (show the delay/skew for the rise event at this pin),
fall (show the delay/skew for the fall event at this pin), or both (show the
delay/skew for both events at this pin).
Valid values:
capacitance
distance
event
fanout
increment
length
lib_cell
load_capacitance

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location
max_above
max_above_fall
max_above_rise
max_below
max_below_fall
max_below_rise
max_through
max_through_fall
max_through_rise
min_above
min_above_fall
min_above_rise
min_below
min_below_fall
min_below_rise
min_through
min_through_fall
min_through_rise
name
net
pin
resistance
skew_above
skew_above_fall
skew_above_rise
skew_below
skew_below_fall
skew_below_rise
skew_through
skew_through_fall
skew_through_rise
slew
status
time
wire_capacitance
Type: string
Default: name lib_cell event increment time slew capacitance location distance fanout status
Edit: Yes
Reference: cts_skew_group_report_columns

cts_skew_group_report_histogram_bin_size

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When set to a numeric value, that numeric value will be used as the histogram
range size (in library units). For example, if the library time units are set
to 1 nanosecond, a value of 0.010 for report_skew_groups_histogram_bin_size
will result in histogram ranges of 10 picoseconds.
When set to auto, the size of the histogram ranges are dependent on the skew
targets that are set. If a skew target is set for a given half corner and skew
group combination, then the histogram range size will be 10% of the skew
target for that half corner and skew target combination. If no skew target is
set for a half corner and skew group combination but a skew target is set for
the primary half corner and skew group combination, then the histogram range
size will be 10% of the skew target for the primary half corner and skew group
combination.
In the event that no skew targets are set and
report_skew_groups_histogram_bin_size is set to auto, a default value of 10
picoseconds will be used for the histogram range size.
Valid values: auto | string
Type: string
Default: auto
Edit: Yes
Reference: cts_skew_group_report_histogram_bin_size

cts_spec_config_base_pin_trace_through_to

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cts_spec_config_create_clock_tree_source_groups

Causes create_clock_tree_spec to set up a clock tree source group for SDC clocks with
multiple source pins. If this attribute is set to true, create_clock_tree_spec defines one clock
tree for each
source pin and then uses the create_clock_tree_source_group command to collect those
clock trees together, so that
CTS can distribute sinks between the clock trees.
Type: bool
Default: false
Edit: Yes
Reference: cts_spec_config_create_clock_tree_source_groups

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cts_spec_config_create_generator_skew_groups

This attribute will cause the create_clock_tree_spec command to create skew groups for
sequential generators and their adjacent registers. Such skew groups will be specified with
the same highest rank so that they can be balanced from the other normal skew groups that
share some sinks of them. The adjacent registers of a generator are registers that have a
datapath timing path to talk with the generator directly. When this attribute is set to true, one
skew group will be created per sequential generator instance, master clock and generated
clock tree triple. The resulting skew groups will by default be named in the pattern:
_clock_gen_<master_clock_name>_<generator_local_name>
<_optional_number>/<constraint_mode_name>.
For example, for a pair of generators, with the same local name "reg_clkgen", CCOpt creates
generated clock trees from the same master clock named "fclk" in a constraint mode named
"func" the skew groups emitted into the clock tree specification file would be named:
_clock_gen_fclk_reg_clkgen_1/func
_clock_gen_fclk_reg_clkgen_2/func
The prefix for the names of such skew groups is controlled by the
cts_spec_config_create_generator_skew_groups_name_prefix CCOpt attribute and defaults
to "_clock_gen" (the start underscore is used to group such skew groups at the end of any
skew group listing ordered by name).
Type: bool
Default: true
Edit: Yes
Reference: cts_spec_config_create_generator_skew_groups

cts_spec_config_create_generator_skew_groups_name_prefix

This attribute controls the skew group name prefix used for skew groups generated to balance
generator flops with their adjacent flops. Default is "_clock_gen". The default has a start
underscore at the beginning to cause listings of skew groups ordered by name to collect such
skew groups together at the end of a list.
Type: string
Default: _clock_gen
Edit: Yes
Reference: cts_spec_config_create_generator_skew_groups_name_prefix

cts_spec_config_create_reporting_only_skew_groups

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Controls whether spec creation will synthesize reporting-only skew groups.

A reporting-only skew group is a skew group whose cts_skew_group_constrains attribute is
set to 'none'. Such a skew
group imposes no clock balancing constraint and will not be considered by CTS.
The typical example is a generated clock that is synchronous to its master
clock. The relationship between the two clocks implies that the sinks of both
clocks should be balanced together. To model this, a clock spec created for
such a design will have the skew group corresponding to the master clock span
the domain of both the master clock and also the generated clock. The skew
group of the generated clock is then a subset of the master clock skew group:
as such it is a redundant constraint, and may be safely omitted. If is
synthesized, such a skew group will be created as a reporting-only skew group.
When this attribute is set to false, reporting-only skew groups
are completely omitted from the generated spec. When set to true,
reporting-only skew groups are included in the generated spec, but are marked
with the cts_skew_group_constrains attribute set to
'none'. Either way, they impose no balancing constraint.
Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: cts_spec_config_create_reporting_only_skew_groups

cts_target_max_capacitance

The target maximum capacitive load to allow during clock tree synthesis. This
attribute specifies a maximum (combined pin and wire) capacitance that the clock
tree synthesis algorithm will allow any given base_pin to drive in a given
clock tree when driving a given net_type. It is specified in library units. It
currently only constrains the primary delay corner capacitance values - other
delay corners can be specified but will not be constrained. This attribute is
applied in addition to the max_capacitance constraints read from the liberty
library data - the tightest (lowest) of the constraint specified by this
attribute and the constraint present in the liberty data will be used. It also
does not apply at the root pins of clock trees - to constrain those nets the
cts_clock_tree_source_max_capacitance CCOpt attribute should be used instead.
Valid values: auto | double
Type: string
Allowed -index values: delay_corner
Default: top auto trunk auto leaf auto
Edit: Yes
Reference: cts_target_max_capacitance

cts_target_max_capacitance_leaf

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The target maximum capacitive load to allow during clock tree synthesis. This
attribute specifies a maximum (combined pin and wire) capacitance that the clock
tree synthesis algorithm will allow any given base_pin to drive in a given
clock tree when driving a given net_type. It is specified in library units. It
currently only constrains the primary delay corner capacitance values - other
delay corners can be specified but will not be constrained. This attribute is
applied in addition to the max_capacitance constraints read from the liberty
library data - the tightest (lowest) of the constraint specified by this
attribute and the constraint present in the liberty data will be used. It also
does not apply at the root pins of clock trees - to constrain those nets the
cts_clock_tree_source_max_capacitance CCOpt attribute should be used instead.
Valid values: auto | double
Type: string
Allowed -index values: delay_corner
Default: auto
Edit: Yes
Reference: cts_target_max_capacitance_leaf

cts_target_max_capacitance_top

The target maximum capacitive load to allow during clock tree synthesis. This
attribute specifies a maximum (combined pin and wire) capacitance that the clock
tree synthesis algorithm will allow any given base_pin to drive in a given
clock tree when driving a given net_type. It is specified in library units. It
currently only constrains the primary delay corner capacitance values - other
delay corners can be specified but will not be constrained. This attribute is
applied in addition to the max_capacitance constraints read from the liberty
library data - the tightest (lowest) of the constraint specified by this
attribute and the constraint present in the liberty data will be used. It also
does not apply at the root pins of clock trees - to constrain those nets the
cts_clock_tree_source_max_capacitance CCOpt attribute should be used instead.
Valid values: auto | double
Type: string
Allowed -index values: delay_corner
Default: auto
Edit: Yes
Reference: cts_target_max_capacitance_top

cts_target_max_capacitance_trunk

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The target maximum capacitive load to allow during clock tree synthesis. This
attribute specifies a maximum (combined pin and wire) capacitance that the clock
tree synthesis algorithm will allow any given base_pin to drive in a given
clock tree when driving a given net_type. It is specified in library units. It
currently only constrains the primary delay corner capacitance values - other
delay corners can be specified but will not be constrained. This attribute is
applied in addition to the max_capacitance constraints read from the liberty
library data - the tightest (lowest) of the constraint specified by this
attribute and the constraint present in the liberty data will be used. It also
does not apply at the root pins of clock trees - to constrain those nets the
cts_clock_tree_source_max_capacitance CCOpt attribute should be used instead.
Valid values: auto | double
Type: string
Allowed -index values: delay_corner
Default: auto
Edit: Yes
Reference: cts_target_max_capacitance_trunk

cts_target_max_stage_delay_sigma

The max per-stage SOCV delay sigma target to use for CTS.
Type: string
Allowed -index values: delay_corner
Default: auto
Edit: Yes
Reference: cts_target_max_stage_delay_sigma

cts_target_max_transition_time

cts_target_max_transition_time_leaf

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cts_target_max_transition_time_top

cts_target_max_transition_time_trunk

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cts_target_skew

This specifies the target skew for clock tree balancing. This may be set to a
numeric value, or one of 'auto', 'ignore' or 'default'.
If set to 'auto' this indicates that an appropriate skew target should be
computed.
If set to 'ignore' this indicates that skew should not be balanced for
this corner/path combination.
If unspecified then the value of this attribute is 'default'.
If the value of the attribute is 'default' the target skew for late delays in the
primary delay corner is interpreted as 'auto' and as 'ignore' otherwise.
Valid values: default | auto | ignore | double
Type: string
Allowed -index values: delay_corner
Default: default
Edit: Yes
Reference: cts_target_skew

cts_timing_connectivity_based_skew_groups

SDC false path assertions may render a generated SDC clock asynchronous to its
master clock. Under such a condition, the sinks of the generated clock need not
be balanced against the sinks of the master clock: there are no timing paths
between the two clocks that can be affected by inter-clock skew. This
balancing 'relaxation' is realized by adjusting the skew groups that are
generated for the two clocks.
This attribute specifies which SDC assertions are considered when deciding
whether a generated clock is asynchronous to its master. Valid values for this
attribute are as follows:
off In this mode, every generated SDC clock is treated as
being synchronous to its master SDC clock.
clock_false_path Only Clock/clock set_false_path and set_clock_group assertions
are considered.
Valid values: off clock_false_path
Type: string
Default: off
Edit: Yes
Reference: cts_timing_connectivity_based_skew_groups

cts_timing_connectivity_based_skew_groups_balance_master_clocks

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This attribute has no effect if cts_timing_connectivity_based_skew_groups is set to 'off'.

With timing connectivity based skew groups enabled, this attribute controls how
CCOpt will address the synchrony of disjoint (i.e. non-overlapping) master
(i.e. non-generated) SDC clocks.
When this attribute is set to false, all disjoint master clocks are assumed to
be mutually asynchronous. The skew groups generated by create_clock_tree_spec
will not constrain the sinks of two such clocks to be balanced together.
When this attribute is set to true, the synchrony of disjoint master clocks is
determined by consulting the SDC assertions in accordance with the value of
attribute cts_timing_connectivity_based_skew_groups.
Additional skew groups will be generated by create_clock_tree_spec,
such that the sinks of each pair of synchronous disjoint master clocks
will be balanced together by CTS.
Valid values true false
Type: bool
Default: false
Edit: Yes
Reference: cts_timing_connectivity_based_skew_groups_balance_master_clocks

cts_timing_connectivity_info

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This attribute is populated by clock spec creation when timing

connectivity based skew groups are enabled. Configuration of this attribute
will be written to the generated spec. It documents the clock/clock balancing
relationships that were determined for the production of timing connectivity
based skew groups. This attribute is documenting only.
If timing connectivity based skew groups are not enabled, this
attribute is not populated by spec creation.
The value of the attribute is a set of nested Tcl dictionaries,
four levels in total. The top-level dictionary indicates the information
category. Currently there is only one such category: 'clock_relationships'. The
second level is keyed on constrained mode name; the lowest level dictionaries
are both keyed on SDC clock name. These keys taken together identify two SDC
clocks in a given constraint mode. The leaf value specifies the resolved
balancing relationships between the two SDC clocks. It an enum with the
following members:
- direct - The two clocks are determined to belong to the same clock group
and must be balanced together.
- indirect - The two clocks do not belong to the same clock group; however
by transitive closure they must balance together.
Clocks in a direct or indirect balancing relationship will share one or more
skew groups so as to ensure that their sinks are balanced together by CTS.
Missing entries should be taken as 'need not balance'; i.e. the pair of SDC
clocks have neither a direct nor indirect balancing relationship.
The indirect balancing relationship can be explored in more detail using this
same Tcl dictionary to probe out the transitive closure over the direct
balancing relationships that link two indirect balance clocks together. For
example if clock A directly balances with clock B only, and clock B directly
balances with clock C only; then clock A indirectly balances with clock C.
Below is an example dict value, corresponding to clock groups {clkA clkB} {clkB
clkC} in constraint mode cm1, and clock groups {clkP clkQ} {clkR clkS} in
constraint mode cm2.
{clock_relationships {cm1 {clkA {clkB direct clkC indirect} clkB {clkA direct clkC direct} clkC
{clkA indirect clkB direct}} cm2 {clkP {clkQ direct} clkQ {clkP direct} clkR {clkS direct} clkS
{clkR direct}}}}
Notice that although they are in separate clock groups, clkA and clkC
nevertheless indirectly balance. This is due to fact that clkB is present in
both clock groups. Note also that we omit information about the relationship
between clkP and clkS: they are 'need not balance'.
Type: string
Default: ""
Edit: Yes
Reference: cts_timing_connectivity_info

cts_top_fanout_threshold

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cts_update_clock_latency

Determine whether to update IO latencies within ccopt_design.

Valid values: true false
Type: bool
Default: true
Edit: Yes
Reference: cts_update_clock_latency

cts_use_inverters

Specifies whether clock tree synthesis should prefer to use inverters rather
than buffers when balancing the clock tree. If set to true, CTS will use
inverters for the clock tree balancing process. If set to false, CTS will use
the minimum number of levels of inverters required to maintain logical
correctness. If set to auto (the default) CTS will use what it considers to be
the best combination of buffers and inverters to get optimal quality of
results.
Valid values: auto true false
Type: string
Default: auto
Edit: Yes
Reference: cts_use_inverters

cts_use_receiver_model_capacitance_for_drv

If true, CCOpt will use receiver model capacitance for drv.

Type: bool
Default: false
Edit: Yes
Reference: cts_use_receiver_model_capacitance_for_drv

current_design

current design
Type: obj(design)
Default: ""
Edit: No

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dataflow_hinsts

specify hinst to be placed

Type: string
Default: ""
Edit: Yes

delay_corners

Returns the information about the delay corners in the design.

Type: obj(delay_corner)*
Default: ""
Edit: No

delaycal_accuracy_level

set accuracy level for delay calculation

Type: int
Default: 0
Edit: Yes
Reference: delaycal_accuracy_level

delaycal_advanced_node_pin_cap_settings

Enable advanced node pin cap settings.

Type: bool
Default: false
Edit: Yes
Reference: delaycal_advanced_node_pin_cap_settings

delaycal_advanced_pin_cap_mode

Enable advanced receiver pin cap mode for base delay.

Type: enum
Enum Values: 0 1 2 3
Default: 0
Edit: Yes
Reference: delaycal_advanced_pin_cap_mode

delaycal_combine_mmmc

Specifies whether delay calculation runs are to be combined for delay calculation simulations
Type: enum
Enum Values: none early_late early_late_corner
Default: early_late_corner
Edit: Yes
Reference: delaycal_combine_mmmc

delaycal_default_net_delay

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set default net delay.

Type: string
Default: 1000ps
Edit: Yes
Reference: delaycal_default_net_delay

delaycal_default_net_load

set default net load.

Type: string
Default: 0.5pf
Edit: Yes
Reference: delaycal_default_net_load

delaycal_degrade_slew_on_early_nets

Controls interconnect slew degradation for early paths.

Type: bool
Default: true
Edit: Yes
Reference: delaycal_degrade_slew_on_early_nets

delaycal_early_irdrop_data_type

IRDrop EIV DB EivMethod for early corner

Type: enum
Enum Values: best_average worst best average worst_average
Default: worst
Edit: Yes
Reference: delaycal_early_irdrop_data_type

delaycal_enable_high_fanout

Enables the default net delay which will be annotated on high fanout nets
Type: bool
Default: false
Edit: Yes
Reference: delaycal_enable_high_fanout

delaycal_enable_quiet_receivers_for_hold

Type: bool
Default: false
Edit: Yes
Reference: delaycal_enable_quiet_receivers_for_hold

delaycal_enable_si

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Enables SIAware delay calculation that also includes cross-talk induced delays.
Type: enum
Enum Values: true false
Default: false
Edit: Yes
Reference: delaycal_enable_si

delaycal_enable_wire_load_model

Enables support of Liberty wire-load models and related SDC commands.

Type: int
Default: 0
Edit: Yes
Reference: delaycal_enable_wire_load_model

delaycal_equivalent_waveform_model

Controls the equivalent waveform model to be used

Type: enum
Enum Values: none no_propagation propagation
Default: none
Edit: Yes
Reference: delaycal_equivalent_waveform_model

delaycal_equivalent_waveform_model_for_timing_check

Enable EWM for timing check delay.

Type: bool
Default: false
Edit: Yes
Reference: delaycal_equivalent_waveform_model_for_timing_check

delaycal_equivalent_waveform_type

Equivalent waveform model type to be used

Type: enum
Enum Values: moments simulation
Default: moments
Edit: Yes
Reference: delaycal_equivalent_waveform_type

delaycal_honor_slew_propagate_constraint

Determines whether to propagate the slew from the disabled timing arcs to the output pin.
Type: bool
Default: true
Edit: Yes
Reference: delaycal_honor_slew_propagate_constraint

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delaycal_ignore_net_load

Uses zero-cap, zero-resistance wire-load model for estimating delays.

Type: bool
Default: false
Edit: Yes
Reference: delaycal_ignore_net_load

delaycal_input_transition_delay

set default input transition time.

Type: string
Default: 0ps
Edit: Yes
Reference: delaycal_input_transition_delay

delaycal_irdrop_data_type

IRDrop EIV DB EivMethod

Type: enum
Enum Values: best_average worst best average worst_average
Default: worst
Edit: Yes
Reference: delaycal_irdrop_data_type

delaycal_irdrop_window_based

Fetch window based EIV values from EIV DB

Type: enum
Enum Values: none late early both
Default: both
Edit: Yes
Reference: delaycal_irdrop_window_based

delaycal_late_irdrop_data_type

IRDrop EIV DB EivMethod for late corner

Type: enum
Enum Values: best_average worst best average worst_average
Default: worst
Edit: Yes
Reference: delaycal_late_irdrop_data_type

delaycal_library_interpolation_mode

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library scaling mode for interpolation flow

Type: enum
Enum Values: linear non_linear
Default: linear
Edit: Yes

delaycal_report_out_bound

Generates a report that contains a list of index values (input transition) in the delay tables that
are beyond the index range.
Type: bool
Default: false
Edit: Yes
Reference: delaycal_report_out_bound

delaycal_signoff_alignment_settings

Turn on/off signoff alignment settings

Type: bool
Default: false
Edit: Yes

delaycal_slew_out_bound_limit_high

Limits the maximum slew used in the analysis to the specified value.
Type: double
Default: 3.40282e+38
Edit: Yes
Reference: delaycal_slew_out_bound_limit_high

delaycal_slew_out_bound_limit_low

Limits the minimum slew used in the analysis to the specified value.
Type: double
Default: 0.5
Edit: Yes
Reference: delaycal_slew_out_bound_limit_low

delaycal_socv_accuracy_mode

level-based-accuracy-effort in AAE for delays and slews

Type: enum
Enum Values: low medium high ultra
Default: low
Edit: Yes
Reference: delaycal_socv_accuracy_mode

delaycal_socv_lvf_mode

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Controls interpretation of LVF data.

Type: enum
Enum Values: moments early_late
Default: early_late
Edit: Yes
Reference: delaycal_socv_lvf_mode

delaycal_socv_machine_learning_level

Enable socv machine learning mode

Type: int
Default: 0
Edit: Yes
Reference: delaycal_socv_machine_learning_level

delaycal_socv_use_lvf_tables

Controls which type of variations are considered during analysis.

Type: string
Default: all
Edit: Yes
Reference: delaycal_socv_use_lvf_tables

delaycal_support_output_pin_cap

useOutputPinCap
Type: bool
Default: true
Edit: Yes
Reference: delaycal_support_output_pin_cap

delaycal_support_wire_load_model

Enables support of Liberty wire-load models and related SDC commands.

Type: int
Default: 0
Edit: Yes
Reference: delaycal_support_wire_load_model

delaycal_timing_create_clock_use_ideal_slew

July 2021 495 Product Version 21.11

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When set to true, the software detects created clocks and uses zero input slew. Other slew
values, including those set using set_annotated_transition command, will be ignored. When
set to false, the software honors set_annotated_transition command settings. By default, this
global variable is set to false.
Type: bool
Default: false
Edit: Yes
Reference: delaycal_timing_create_clock_use_ideal_slew

delaycal_use_default_delay_limit

set threshold to apply the default delay

Type: int
Default: 1000
Edit: Yes
Reference: delaycal_use_default_delay_limit

design_bottom_routing_layer

Specifies the lowest LEF layer name or layer number for global and detail routing. Layer
number is from the LEF layer sequence. For example, 2 is equivalent to the second routing
layer defined in LEF.
Type: string
Default: ""
Edit: Yes
Reference: design_bottom_routing_layer

design_compressed_pg_db

Specifies whether the compressed pg feature is enabled. When it's true, read_db will
automatically compress the PG data when load the design. You can use "get_db
current_design .is_pg_compressed" to check if PG in this design is compressed.
Type: bool
Default: false
Edit: Yes
Reference: design_compressed_pg_db

design_cong_effort

Specify congestion effort level

Type: enum
Enum Values: low medium high auto
Default: auto
Edit: Yes
Reference: design_cong_effort

design_dual_rail_via_pitch

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Min stacked-via pitch for dual std-cell power-rails on first and third routing layers. Space
separated min stacked-via pitch for dual std-cell power-rails on first and third routing layers.
Type: string
Default: ""
Edit: Yes
Reference: design_dual_rail_via_pitch

design_early_clock_flow

Enable early clock flow

Type: bool
Default: false
Edit: Yes
Reference: design_early_clock_flow

design_express_route

With "-flow_effort express", should routing-stage be forced.

Type: bool
Default: false
Edit: Yes
Reference: design_express_route

design_flow_effort

Specify flow effort level

Type: enum
Enum Values: express standard extreme
Default: standard
Edit: Yes
Reference: design_flow_effort

design_high_freq_interposer_flow

Specifies the flow is a high frequency interposer flow. When set to true,
set_integration_route_constraint will auto turn off the options which are not suitable for
interposer routing.
Type: bool
Default: false
Edit: Yes
Reference: design_high_freq_interposer_flow

design_ignore_followpin_vias

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if true, ignore followpin vias during detailed placement, optimization and routing.
Type: bool
Default: false
Edit: Yes
Reference: design_ignore_followpin_vias

design_pessimistic_mode

Enable pessimistic mode

Type: enum
Enum Values: true false
Default: false
Edit: Yes
Reference: design_pessimistic_mode

design_power_effort

Specify power effort level

Type: enum
Enum Values: none low high
Default: none
Edit: Yes
Reference: design_power_effort

design_process_node

Process technology
Type: int
Default: 90
Edit: Yes
Reference: design_process_node

design_slack_weighting_method

Specify slack weighting to be used in implementation flow

Type: enum
Enum Values: unity_weighting view_based_weighting
Default: unity_weighting
Edit: Yes
Reference: design_slack_weighting_method

design_tech_node

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set design tech node

Type: enum
Enum Values: N12 N10 N7 N7Plus N6 N5 N5PlusPlus N4 N3 N2 S11 S10 S8 S7 S5 S4 S3
S2 G7 G5 ICF I7 I5 P1278 P1280 C12 C7 unspecified
Default: unspecified
Edit: Yes
Reference: design_tech_node

design_top_routing_layer

Specifies the highest LEF layer name or layer number for global and detail routing. Layer
number is from the LEF layer sequence. For example, 2 is equivalent to the second routing
layer defined in LEF.
Type: string
Default: ""
Edit: Yes
Reference: design_top_routing_layer

design_trim_grid_group

Specifies the GROUP name of which set of trim metal grid to be used for placement and
routing. See the LEF documentation on the TRIMMETALTRACK keyword for more details.
Type: string
Default: ""
Edit: Yes
Reference: design_trim_grid_group

designs

All the designs

Type: obj(design)*
Default: ""
Edit: No

distributed_mmmc_disable_reports_auto_redirection

setting 'true' will preserve path specified in report command. User need to specify unique path
for each view to avoid all clients writing to same report file. With default setting (false),
distributed mmmc run automatically updates report paths to a view unique directory structure.
Type: string
Default: false
Edit: Yes
Reference: distributed_mmmc_disable_reports_auto_redirection

eco_batch_mode

July 2021 499 Product Version 21.11

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Enter/Exit batch mode

Type: bool
Default: false
Edit: Yes
Reference: eco_batch_mode

eco_check_logical_equivalence

Do logical-equivalence checking
Type: bool
Default: true
Edit: Yes
Reference: eco_check_logical_equivalence

eco_disable_change_net_name_for_flat_netlist

Specifies whether nets would be renamed in eco report of eco_compare_netlist for flat netlist.
Type: int
Default: 0
Edit: Yes
Reference: eco_disable_change_net_name_for_flat_netlist

eco_disable_constraints_loading_from_clients

Disable Loading Constraints from Clients

Type: bool
Default: false
Edit: Yes

eco_disable_derates_loading_from_clients

Disable Loading Derates from Clients

Type: bool
Default: false
Edit: Yes

eco_disable_parasitic_loading_from_clients

Disable Loading Parasitics from Clients

Type: bool
Default: false
Edit: Yes

eco_disable_power_format_loading_from_clients

Disable Loading Power Format from Clients

Type: bool
Default: true
Edit: Yes

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eco_honor_dont_touch

Check dont_touch on instances, cells and nets

Type: bool
Default: true
Edit: Yes
Reference: eco_honor_dont_touch

eco_honor_dont_use

Skip library cells marked dont_use

Type: bool
Default: true
Edit: Yes
Reference: eco_honor_dont_use

eco_honor_fixed_status

Honor fixed (placement) instances

Type: bool
Default: true
Edit: Yes
Reference: eco_honor_fixed_status

eco_honor_fixed_wires

Honor fixed wires of nets

Type: bool
Default: true
Edit: Yes
Reference: eco_honor_fixed_wires

eco_honor_power_intent

Perform MSV checks during ECO: Do not allow resize of regular cell with always-on cell (and
vice-versa), do not change cells belonging to different power domains, do not allow adding
buffer to a power domain it doesn't belong to, do not buffer a cross power domain net, do not
allow deletion of an always-on buffer, a level-shifter, or a buffer which will cause redundant
isolation cell.
Type: bool
Default: true
Edit: Yes
Reference: eco_honor_power_intent

eco_inherit_net_attribute

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New net inherits attributes of buffered net

Type: bool
Default: true
Edit: Yes
Reference: eco_inherit_net_attribute

eco_prefix

Prefix name to be used by ECO commands

Type: string
Default: ECO
Edit: Yes
Reference: eco_prefix

eco_preserve_hpin_function

Determines whether to preserve logical functions at hierarchical module ports. It only works for
manual ECO commands.
Type: bool
Default: false
Edit: Yes

eco_refine_place

Refine placement after ECO

Type: bool
Default: true
Edit: Yes
Reference: eco_refine_place

eco_spread_inverter

Spread inverters on buffered net

Type: bool
Default: true
Edit: Yes
Reference: eco_spread_inverter

eco_update_timing

Update timing results after ECO

Type: bool
Default: true
Edit: Yes
Reference: eco_update_timing

edit_wire_align

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Specifies whether to support align objects.

Type: bool
Default: true
Edit: Yes
Reference: edit_wire_align

edit_wire_allow_45_degree

Specifies whether to allow creation of a 45-degree wire.

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_allow_45_degree

edit_wire_arrow_incremental

Specifies the step increments in microns to move wires with the arrow keys.
Type: double
Default: 1.0
Edit: Yes
Reference: edit_wire_arrow_incremental

edit_wire_assign_multi_pattern_color

Specifies how to assign the mask color on the DPT layer of the wire segment to be created.
Type: enum
Enum Values: auto mask1 mask2 mask3
Default: auto
Edit: Yes
Reference: edit_wire_assign_multi_pattern_color

edit_wire_auto_split_bus

Splits buses automatically to avoid DRC violations.

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_auto_split_bus

edit_wire_bus_honor_start_parameters

Specifies that the wire width and spacing of the start points (pins) should be honored when
drawing routes for a bus.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_bus_honor_start_parameters

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edit_wire_bus_honor_width_setting

Specifies whether the tool should adjust the wire width when snapping bus wires to pin.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_bus_honor_width_setting

edit_wire_change_order_at_turn

Specifies whether the order of the wires changes or stays the same when the wire makes a
90-degree turn. (Reverse Order | Keep Order)
Type: string
Default: keep_order
Edit: Yes
Reference: edit_wire_change_order_at_turn

edit_wire_check_design_boundary

Specifies whether stop user to stretch the wire in the forbidden area which defined by
edit_wire_pull_back_distance.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_check_design_boundary

edit_wire_close_polygons

Specifies whether to close a special route structure toward itself.

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_close_polygons

edit_wire_color_align_with_track

Specifies whether the wire color is to be changed to match the track color during a move or
copy operation.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_color_align_with_track

edit_wire_connect_pin

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Specifies whether or not generate a via on the pin for specified pin type.
Type: enum
Enum Values: in out inout nodir
Default: in out inout nodir
Edit: Yes
Reference: edit_wire_connect_pin

edit_wire_connect_with_specified_layer

Specifies whether or not the layer of connecting wires should be changed as per the
edit_wire_layer_horizontal or edit_wire_layer_vertical setting when moving wires.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_connect_with_specified_layer

edit_wire_create_crossover_vias

Specifies whether the software creates a via when you draw a wire that crosses a wire or pin
of the same net that is on a different layer.
Type: bool
Default: true
Edit: Yes
Reference: edit_wire_create_crossover_vias

edit_wire_create_is_edit_flag

Specifies whether to create is_edit flag for wire edit

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_create_is_edit_flag

edit_wire_create_via_on_pin

Specifies whether the software creates vias at pins.

Type: bool
Default: true
Edit: Yes
Reference: edit_wire_create_via_on_pin

edit_wire_cut_class

Specifies the cut class name of the generated via when editing wires.
Type: string
Default: ""
Edit: Yes
Reference: edit_wire_cut_class

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edit_wire_cut_wire_overlap

Specifies whether or not overlaps are created while cutting specified type of wires.
Type: enum
Enum Values: regular special
Default: regular
Edit: Yes
Reference: edit_wire_cut_wire_overlap

edit_wire_debug_file

Specifies the report file name.

Type: string
Default: ""
Edit: Yes
Reference: edit_wire_debug_file

edit_wire_delete_pin_with_wire

Delete Pin with Wire

Type: bool
Default: true
Edit: Yes
Reference: edit_wire_delete_pin_with_wire

edit_wire_delete_wire_via_through_layers

Delete Wire Via in deep through mode

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_delete_wire_via_through_layers

edit_wire_display_wire_length_with_cursor

Specifies whether display the total/current wire length with mouse when editing wires.
Type: bool
Default: true
Edit: Yes
Reference: edit_wire_display_wire_length_with_cursor

edit_wire_draw_shield

Specifies whether draw a shield net only.

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_draw_shield

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edit_wire_drawing_wire

Specifies which of the nets used with the -nets parameter corresponding to the mouse pointer
location when adding an array of wires.
Type: int
Default: 1
Edit: Yes
Reference: edit_wire_drawing_wire

edit_wire_drc_aware_cross_metal

Specifies whether to stretch or move wires back to the closest location available before a
violation occurs with the crossing metal. This option only work if "setEditMode -stop_at_drc"
set to 1.
Type: bool
Default: true
Edit: Yes
Reference: edit_wire_drc_aware_cross_metal

edit_wire_drc_on

Specifies whether to check DRC rules during wire editing.

Type: bool
Default: true
Edit: Yes
Reference: edit_wire_drc_on

edit_wire_drc_use_non_default_spacing

Specifies whether non-default spacing defined in the Non-Default Rule of the editing net
should be used for spacing check during wire editing.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_drc_use_non_default_spacing

edit_wire_extend_wires

Specifies whether, after completing a signal or power route, the specified boundary of wire
segment extends and connects to the first logical target
Type: enum
Enum Values: start end start_cell_boundary end_cell_boundary
Default: ""
Edit: Yes
Reference: edit_wire_extend_wires

edit_wire_final_check_with_verify

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Specifies whether to do final check with verify

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_final_check_with_verify

edit_wire_ignore_drc

Specifies which violation type should be ignored during wire editing.

Type: enum
Enum Values: conn_antenna max_via_stack min_cut min_enclosed_area min_step
protrusion
Default: ""
Edit: Yes
Reference: edit_wire_ignore_drc

edit_wire_jog_connect_layer

Specifies the number of layers for connecting wires above the layers for moving wires. If set
the parameter of 'set_db edit_wire_jog_connect_layer' to 1, disable this option.
Type: int
Default: 0
Edit: Yes
Reference: edit_wire_jog_connect_layer

edit_wire_keep_status

Specifies whether to keep object status during editing.

Type: bool
Default: true
Edit: Yes
Reference: edit_wire_keep_status

edit_wire_keep_via

Specifies whether keep original via in wire move or change width.

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_keep_via

edit_wire_lateral_movement_range

Specified the max lateral movement distance to avoid DRC when add a wire.
Type: double
Default: 0.0
Edit: Yes
Reference: edit_wire_lateral_movement_range

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edit_wire_layer

Specifies the layer for patch wires or polygon wires.

Type: string
Default: M1
Edit: Yes
Reference: edit_wire_layer

edit_wire_layer_horizontal

Specifies the layer for horizontal wires.

Type: string
Default: M1
Edit: Yes
Reference: edit_wire_layer_horizontal

edit_wire_layer_max

Specifies the maximum layer for routing.

Type: string
Default: UNINITIALIZED
Edit: Yes
Reference: edit_wire_layer_max

edit_wire_layer_min

Specifies the minimum layer for routing.

Type: string
Default: UNINITIALIZED
Edit: Yes
Reference: edit_wire_layer_min

edit_wire_layer_vertical

Specifies the layer for vertical wires.

Type: string
Default: M2
Edit: Yes
Reference: edit_wire_layer_vertical

edit_wire_look_down_layers

Specifies the number of layers below the current layer that added wires will connect to with a
via.
Type: int
Default: 100
Edit: Yes
Reference: edit_wire_look_down_layers

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edit_wire_look_up_layers

Specifies the number of layers above the current layer that added wires will connect to with a
via.
Type: int
Default: 100
Edit: Yes
Reference: edit_wire_look_up_layers

edit_wire_max_pointer_number

Specifies the maximum number of pointers to be returned by wire edit commands.

Type: int
Default: 100
Edit: Yes
Reference: edit_wire_max_pointer_number

edit_wire_mirror_bus_route

Specifies that whether to reverse the net order for bus route.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_mirror_bus_route

edit_wire_nets

Specifies one or more nets for editing.

Type: string
Default: ""
Edit: Yes
Reference: edit_wire_nets

edit_wire_no_merge_special_wire

Specifies whether automatically merge the added special wires with any existing special
wires.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_no_merge_special_wire

edit_wire_only_show_edit_layer

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Turn on this option, when user editing any wires/vias, only show the layer from edit objects,
and dim other objects.
Type: bool
Default: true
Edit: Yes
Reference: edit_wire_only_show_edit_layer

edit_wire_orthogonal_connection_only

Specifies whether to consider wires and pins that are in the same direction as a target for
connection. Only special wire is supported.
Type: bool
Default: true
Edit: Yes
Reference: edit_wire_orthogonal_connection_only

edit_wire_outer_shield_spacing

Specifies a spacing value in microns to be used by the edit_wire_shield_low and

edit_wire_shield_high parameters.
Type: double
Default: 0.0
Edit: Yes
Reference: edit_wire_outer_shield_spacing

edit_wire_outer_shield_width

Specifies a width value in microns to be used for outer shield(s) depending on the values of
edit_wire_shield_low or edit_wire_shield_high parameters.
Type: double
Default: 0.0
Edit: Yes
Reference: edit_wire_outer_shield_width

edit_wire_override

Specifies whether to use the override specification.

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_override

edit_wire_partial_overlap_threshold

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Specifies ratio threshold of special via creation on partial overlap wires.

Type: int
Default: 0
Edit: Yes
Reference: edit_wire_partial_overlap_threshold

edit_wire_pull_back_distance

Specify the value for forbidden distance. Default is Auto, it means use the largest min spacing
of the layer.
Type: string
Default: auto
Edit: Yes
Reference: edit_wire_pull_back_distance

edit_wire_reshape

Specifies that when you add new wires, existing redundant wires within the route are
automatically removed.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_reshape

edit_wire_return_obj_pointer

Specifies whether return pointers after wire edit operations.

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_return_obj_pointer

edit_wire_rule

Uses the specified LEF rule for regular wires.

Type: string
Default: ""
Edit: Yes
Reference: edit_wire_rule

edit_wire_search_route_rule_vias_only

Specifies that when the Shift + N/P bindkey is used, the tool should circle through NDR vias
only.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_search_route_rule_vias_only

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edit_wire_shape

Specifies the shape associated with the wire you draw.

Type: enum
Enum Values: ring stripe followpin iowire corewire blockwire padring blockring fillwire
fillwireopc drcfill none
Default: stripe
Edit: Yes
Reference: edit_wire_shape

edit_wire_shield

Specifies whether to add a minimum width shield wire for specified side.
Type: enum
Enum Values: high low adjacent
Default: ""
Edit: Yes
Reference: edit_wire_shield

edit_wire_shield_look_down_layers

Specifies the number of layers below the current layer that an added shield wire can connect
using a via.
Type: int
Default: 100
Edit: Yes
Reference: edit_wire_shield_look_down_layers

edit_wire_shield_look_up_layers

Specifies the number of layers above the current layer that an added shield wire can connect
using a via.
Type: int
Default: 100
Edit: Yes
Reference: edit_wire_shield_look_up_layers

edit_wire_shield_shape

Specifies the shape associated with the shield wire you draw.
Type: enum
Enum Values: ring stripe followpin iowire corewire blockwire padring blockring fillwire drcfill
none
Default: none
Edit: Yes
Reference: edit_wire_shield_shape

edit_wire_shielding_nets

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Specifies net names for shield wires, usually power or ground names.
Type: string
Default: ""
Edit: Yes
Reference: edit_wire_shielding_nets

edit_wire_show_drc_info_for_edit_shape

Turn on this option, when user editing any wires/vias and generate a violation, tool can
display the detail information nearby marker.
Type: bool
Default: true
Edit: Yes
Reference: edit_wire_show_drc_info_for_edit_shape

edit_wire_sibling_look_down_layers

Specifies the number of layers below the sibling layers that an added shield wire can connect
using a via.
Type: int
Default: 1
Edit: Yes
Reference: edit_wire_sibling_look_down_layers

edit_wire_sibling_look_up_layers

Specifies the number of layers above the sibling layers that an added shield wire can connect
using a via.
Type: int
Default: 1
Edit: Yes
Reference: edit_wire_sibling_look_up_layers

edit_wire_snap

Specifies whether to enable wire and via snap.

Type: bool
Default: true
Edit: Yes
Reference: edit_wire_snap

edit_wire_snap_align_to

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Specifies how to align with a pin when ending a route.

Type: enum
Enum Values: center low high auto
Default: auto
Edit: Yes
Reference: edit_wire_snap_align_to

edit_wire_snap_bus_to_pin

Specifies whether to change wire width, spacing and order according to the connected pin
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_snap_bus_to_pin

edit_wire_snap_end_to

Specifies whether to snap the end of wire to specified objects.

Type: enum
Enum Values: track_regular track_special manufacturing_grid
Default: ""
Edit: Yes
Reference: edit_wire_snap_end_to

edit_wire_snap_objects_to_track

Specifies whether to snap added or moved specified wires to the closest routing track in the
preferred direction for the layer automatically.
Type: enum
Enum Values: special regular patch pin
Default: regular patch
Edit: Yes
Reference: edit_wire_snap_objects_to_track

edit_wire_snap_to

Specifies whether to snap added or moved wires to specified objects.

Type: enum
Enum Values: special pg pin row
Default: special pg pin
Edit: Yes
Reference: edit_wire_snap_to

edit_wire_snap_to_track_honor_color

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Specifies whether to snap wires to a track with the same color automatically.
Type: bool
Default: true
Edit: Yes
Reference: edit_wire_snap_to_track_honor_color

edit_wire_snap_trim_metal_to_trim_grid

Specify whether snap the trim metal to the closest trim grid during trim metal editing.
Type: bool
Default: true
Edit: Yes
Reference: edit_wire_snap_trim_metal_to_trim_grid

edit_wire_spacing

Specifies the distance between wires.

Type: string
Default: ""
Edit: Yes
Reference: edit_wire_spacing

edit_wire_spacing_horizontal

Specifies the distance between horizontal wires.

Type: string
Default: ""
Edit: Yes
Reference: edit_wire_spacing_horizontal

edit_wire_spacing_vertical

Specifies the distance between vertical wires.

Type: string
Default: ""
Edit: Yes
Reference: edit_wire_spacing_vertical

edit_wire_status

Specifies the status associated with the wire you draw.

Type: enum
Enum Values: cover fixed noshield routed shield auto
Default: fixed
Edit: Yes
Reference: edit_wire_status

edit_wire_stop_at_drc

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Specifies whether the software can cause a DRC violation by moving or stretching a wire.
Type: bool
Default: true
Edit: Yes
Reference: edit_wire_stop_at_drc

edit_wire_stretch_end

Specifies the direction in which to stretch or reduce wires.

Type: enum
Enum Values: high low
Default: high
Edit: Yes
Reference: edit_wire_stretch_end

edit_wire_stretch_with_intersection

Enables wires with intersects to be stretched easily.

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_stretch_with_intersection

edit_wire_sub_class

Specifies the subclass name of wires and vias.

Type: string
Default: ""
Edit: Yes
Reference: edit_wire_sub_class

edit_wire_turn_at

Specifies the start location of new wire when do turn.

Type: enum
Enum Values: center_line wire_edge
Default: center_line
Edit: Yes
Reference: edit_wire_turn_at

edit_wire_type

Specifies the type of creating wire.

Type: enum
Enum Values: regular special patch
Default: ""
Edit: Yes
Reference: edit_wire_type

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edit_wire_unrestricted_regular_wire_width

Specifies whether the regular wire width is unrestricted when changing width.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_unrestricted_regular_wire_width

edit_wire_update_shield_net

Specifies whether automatically update shield net attribute on the signal net.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_update_shield_net

edit_wire_use_fix_via

Specifies whether to use fix_via for special via with minStep DRC violation.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_use_fix_via

edit_wire_use_interleaving_wire_group

Alternates the specified wires in the wire group.

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_use_interleaving_wire_group

edit_wire_use_wire_group

Groups multiple wires from the same net.

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_use_wire_group

edit_wire_use_wire_group_bits

Specifies the number of times to replicate a wire in the wire group.

Type: int
Default: 0
Edit: Yes
Reference: edit_wire_use_wire_group_bits

edit_wire_use_wire_group_reinforcement

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Creates slots in the wire group by creating wires that connect the wires in the wire group, but
are orthogonal to them.
Type: bool
Default: false
Edit: Yes
Reference: edit_wire_use_wire_group_reinforcement

edit_wire_use_wire_group_reinforcement_group_via

Specifies that the wire group uses group vias.

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_use_wire_group_reinforcement_group_via

edit_wire_use_wire_group_reinforcement_spacing

Specifies the spacing for the orthogonal wires in the wire groups.
Type: double
Default: 0.0
Edit: Yes
Reference: edit_wire_use_wire_group_reinforcement_spacing

edit_wire_use_wire_group_reinforcement_width

Specifies the width of the orthogonal wires in the wire groups.

Type: double
Default: 0.0
Edit: Yes
Reference: edit_wire_use_wire_group_reinforcement_width

edit_wire_verbose

Type: bool
Default: false
Edit: Yes
Reference: edit_wire_verbose

edit_wire_via_allow_geometry_drc

Check Geometry DRC

Type: bool
Default: true
Edit: Yes
Reference: edit_wire_via_allow_geometry_drc

edit_wire_via_auto_snap

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Controls whether to snap vias to the intersection of wires on the same net or to the
manufacturing grid.
Type: bool
Default: true
Edit: Yes
Reference: edit_wire_via_auto_snap

edit_wire_via_auto_update

Controls whether to replace existing vias.

Type: bool
Default: true
Edit: Yes
Reference: edit_wire_via_auto_update

edit_wire_via_cell_name

Specifies the name of the via cell from the LEF or DEF file.
Type: string
Default: ""
Edit: Yes
Reference: edit_wire_via_cell_name

edit_wire_via_columns

Specify the rows of via cut.

Type: int
Default: 0
Edit: Yes
Reference: edit_wire_via_columns

edit_wire_via_create_by

Controls whether to create vias based on the edit_wire_via_cell_name parameter or to create

vias based on the other parameters.
Type: enum
Enum Values: viacell parameters
Default: parameters
Edit: Yes
Reference: edit_wire_via_create_by

edit_wire_via_cut_layer

Specifies the via layer name for the via to created or modify.
Type: string
Default: V12
Edit: Yes
Reference: edit_wire_via_cut_layer

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edit_wire_via_exclude_spec

Specifies the vias to be ignored by wire editor.

Type: string
Default: ""
Edit: Yes
Reference: edit_wire_via_exclude_spec

edit_wire_via_override_spec

Specifies the default vias to be used by wire editor.

Type: string
Default: ""
Edit: Yes
Reference: edit_wire_via_override_spec

edit_wire_via_rows

Specify the columns of via cut.

Type: int
Default: 0
Edit: Yes
Reference: edit_wire_via_rows

edit_wire_via_scale_height

Specify the via height scale.

Type: int
Default: 100
Edit: Yes
Reference: edit_wire_via_scale_height

edit_wire_via_scale_width

Specify the via width scale.

Type: int
Default: 100
Edit: Yes
Reference: edit_wire_via_scale_width

edit_wire_via_snap_honor_color

Specifies whether to snap the same mask automatically

Type: bool
Default: true
Edit: Yes
Reference: edit_wire_via_snap_honor_color

edit_wire_via_snap_to_intersection

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Specifies whether to snap vias to the intersection of wires

Type: bool
Default: true
Edit: Yes
Reference: edit_wire_via_snap_to_intersection

edit_wire_via_type

Specifies the type of creating via.

Type: enum
Enum Values: auto regular special
Default: auto
Edit: Yes
Reference: edit_wire_via_type

edit_wire_width

Specifies the width of patch wires.

Type: double
Default: 0.0
Edit: Yes
Reference: edit_wire_width

edit_wire_width_horizontal

Specifies the width for horizontal wires.

Type: double
Default: 0.0
Edit: Yes
Reference: edit_wire_width_horizontal

edit_wire_width_vertical

Specifies the width of vertical wires.

Type: double
Default: 0.0
Edit: Yes
Reference: edit_wire_width_vertical

edit_wire_wire_override_spec

Contains the details of the override specification.

Type: string
Default: ""
Edit: Yes
Reference: edit_wire_wire_override_spec

eeq_variant_site_start

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Site variant_id of the first site on rows in core area. This is specified in library
LEF58_CELLVARIANTS property by value of STARTVARIANT in 'CELLVARIANTS
totalNum [STARTVARIANT num] YFLIPMAP {flippedVariantNum siteVariantNum} ...'
Type: int
Default: no_value
Edit: Yes

enable_distributed_flow

Enables the distributed flow, and changes '::Rda_Distributed::useModel' to 0

Type: int
Default: 0
Edit: Yes

exclusive_group_min_gap

This is the minimum gap should be maintained between exclusive_groups (all exclusive
groups). The value is measured in microns. It can be set by command
create_exclusive_groups -min_gap.
Type: coord
Default: 5
Edit: Yes

extract_rc_assume_metal_fill

Assume metal fill

Type: double
Default: 0.0
Edit: Yes
Reference: extract_rc_assume_metal_fill

extract_rc_cap_filter_mode

Coupling Capacitance Filtering Mode

Type: enum
Enum Values: relative_only relative_and_coupling relative_or_coupling
Default: relative_only
Edit: Yes
Reference: extract_rc_cap_filter_mode

extract_rc_compress_rcdb

Create compressed RCDB

Type: bool
Default: false
Edit: Yes
Reference: extract_rc_compress_rcdb

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extract_rc_coupled

Extract coupling cap

Type: bool
Default: false
Edit: Yes
Reference: extract_rc_coupled

extract_rc_coupling_cap_threshold

Coupling C threshold value

Type: double
Default: 3.0
Edit: Yes
Reference: extract_rc_coupling_cap_threshold

extract_rc_def_via_cap

Consider via caps for extraction

Type: bool
Default: false
Edit: Yes
Reference: extract_rc_def_via_cap

extract_rc_effort_level

Specifies the effort level of the post-route extraction engine

Type: enum
Enum Values: low medium high signoff
Default: undefined
Edit: Yes
Reference: extract_rc_effort_level

extract_rc_engine

Extraction engine
Type: enum
Enum Values: pre_route post_route
Default: pre_route
Edit: Yes
Reference: extract_rc_engine

extract_rc_extra_cmd_file

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Extra command file for Quantus QRC

Type: string
Default: ""
Edit: Yes
Reference: extract_rc_extra_cmd_file

extract_rc_hard_block_obs

Makes obstructions and power/ground pin shapes visible to the extractor for hard blocks only
Type: bool
Default: false
Edit: Yes
Reference: extract_rc_hard_block_obs

extract_rc_incremental

Use incremental signoff mode

Type: bool
Default: true
Edit: Yes
Reference: extract_rc_incremental

extract_rc_layer_independent

Enable layer independent extraction

Type: int
Default: 1
Edit: Yes
Reference: extract_rc_layer_independent

extract_rc_lef_tech_file_map

LEF-QRCTechfile layer map file

Type: string
Default: ""
Edit: Yes
Reference: extract_rc_lef_tech_file_map

extract_rc_local_cpu

Type: int
Default: 0
Edit: Yes
Reference: extract_rc_local_cpu

extract_rc_pvs_fill

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Use to send the PVS fill data attached to the Innovus DB (see set_pvs_fill) to Quantus
Type: bool
Default: false
Edit: Yes
Reference: extract_rc_pvs_fill

extract_rc_qrc_cmd_file

Quantus QRC user command file name

Type: string
Default: ""
Edit: Yes
Reference: extract_rc_qrc_cmd_file

extract_rc_qrc_cmd_type

Quantus QRC command input type

Type: enum
Enum Values: auto partial custom
Default: auto
Edit: Yes
Reference: extract_rc_qrc_cmd_type

extract_rc_qrc_output_mode

Quantus QRC output mode

Type: enum
Enum Values: spef rcdb
Default: spef
Edit: Yes
Reference: extract_rc_qrc_output_mode

extract_rc_qrc_run_mode

Quantus QRC MMMC run mode

Type: enum
Enum Values: concurrent sequential
Default: concurrent
Edit: Yes
Reference: extract_rc_qrc_run_mode

extract_rc_qrc_stream_map_file

Quantus stream/oasis file

Type: string
Default: ""
Edit: Yes
Reference: extract_rc_qrc_stream_map_file

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extract_rc_relative_cap_threshold

Relative C threshold value

Type: double
Default: 0.03
Edit: Yes
Reference: extract_rc_relative_cap_threshold

extract_rc_shrink_factor

Sets the shrink factor used by the extract_rc command.(Double, default=1)

Type: double
Default: 1.0
Edit: Yes
Reference: extract_rc_shrink_factor

extract_rc_signoff_stream_layer_map

QRC stream map file

Type: string
Default: ""
Edit: Yes
Reference: extract_rc_signoff_stream_layer_map

extract_rc_total_cap_threshold

Total C threshold value

Type: double
Default: 5.0
Edit: Yes
Reference: extract_rc_total_cap_threshold

extract_rc_tquantus_model_file

TQuantus model file name

Type: string
Default: ""
Edit: Yes
Reference: extract_rc_tquantus_model_file

extract_rc_tsv_subckt_file

TSV subckt file name

Type: string
Default: ""
Edit: Yes
Reference: extract_rc_tsv_subckt_file

extract_rc_turbo_reduce

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Reduce XCap (IQuantus)

Type: enum
Enum Values: true false auto
Default: auto
Edit: Yes
Reference: extract_rc_turbo_reduce

extract_rc_use_qrc_oa_interface

Use OA interface for invoking Quantus QRC extraction

Type: bool
Default: false
Edit: Yes
Reference: extract_rc_use_qrc_oa_interface

extract_rc_use_shielding_in_detail_mode

Considers shielding for a wire segment

Type: bool
Default: false
Edit: Yes
Reference: extract_rc_use_shielding_in_detail_mode

extract_rc_via_cap

Consider via caps for extraction

Type: bool
Default: true
Edit: Yes
Reference: extract_rc_via_cap

finish_floorplan_active_objs

active_object list
Type: enum
Enum Values: macro macro_halo core io_pad io_cell fence hard_blockage soft_blockage
partial_blockage route_blockage row
Default: macro macro_halo core
Edit: Yes
Reference: finish_floorplan_active_objs

finish_floorplan_add_blockage_direction

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direction
Type: enum
Enum Values: x y xy
Default: xy
Edit: Yes
Reference: finish_floorplan_add_blockage_direction

finish_floorplan_drc_region_objs

drc_region object list

Type: enum
Enum Values: macro macro_halo hard_blockage min_gap core_spacing non_row_area
Default: macro macro_halo hard_blockage min_gap core_spacing
Edit: Yes
Reference: finish_floorplan_drc_region_objs

finish_floorplan_override

override or not
Type: bool
Default: false
Edit: Yes
Reference: finish_floorplan_override

flexible_htrees

list of flexible_htree
Type: obj(flexible_htree)*
Default: ""
Edit: No
Reference: flexible_htrees

flip_chip_allow_layer_change

Specifies if turning on layer change feature

Type: bool
Default: false
Edit: Yes
Reference: flip_chip_allow_layer_change

flip_chip_allow_routed_bump_edit

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By default bumps are allowed to be edited (moved, deleted, reassigned, swapped). If this
variable is set to FALSE, any bump edit command for a bump with routing connected to it will
give an error message and fail.
Type: bool
Default: true
Edit: Yes
Reference: flip_chip_allow_routed_bump_edit

flip_chip_auto_pairing_file

Specifies the output file name to dump out route_flip_chip auto pairing information for bump to
I/O connection
Type: string
Default: ""
Edit: Yes
Reference: flip_chip_auto_pairing_file

flip_chip_bottom_layer

Specifies the bottom-most metal layer by layer number or layer name that the software can use
when routing bumps
Type: string
Default: ""
Edit: Yes
Reference: flip_chip_bottom_layer

flip_chip_bump_use_octagon_shape

route_flip_chip use circumferential octagon to replace the complex pin shape

Type: bool
Default: false
Edit: Yes
Reference: flip_chip_bump_use_octagon_shape

flip_chip_check_bump_access_directions

Specifies whether check the special bump access directions

Type: bool
Default: false
Edit: Yes
Reference: flip_chip_check_bump_access_directions

flip_chip_compaction

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Specifies if turning on compaction routing

Type: bool
Default: false
Edit: Yes
Reference: flip_chip_compaction

flip_chip_connect_power_cell_to_bump

Connects all power bumps to the I/O cell pin. It does not connect to a power or ground stripe or
ring
Type: bool
Default: false
Edit: Yes
Reference: flip_chip_connect_power_cell_to_bump

flip_chip_constraint_file

Specifies the file that contains constraints for flip chip routing
Type: string
Default: ""
Edit: Yes
Reference: flip_chip_constraint_file

flip_chip_drop_via_on_all_shapes

route_flip_chip drop via on all geometries

Type: bool
Default: false
Edit: Yes
Reference: flip_chip_drop_via_on_all_shapes

flip_chip_drop_via_on_power_mesh

Specifies the metal layer by layer number or layer name that the software can use to drop via
Type: string
Default: ""
Edit: Yes
Reference: flip_chip_drop_via_on_power_mesh

flip_chip_extra_config

Specifies the name of an extra configuration file for flip chip routing
Type: string
Default: ""
Edit: Yes
Reference: flip_chip_extra_config

flip_chip_finger_direction

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Specifies main expansion direction for finger routing

Type: enum
Enum Values: n e s w
Default: n
Edit: Yes
Reference: flip_chip_finger_direction

flip_chip_finger_max_width

Specifies the max routing width for one wire segment

Type: double
Default: 0.0
Edit: Yes
Reference: flip_chip_finger_max_width

flip_chip_finger_min_width

Specifies the min routing width for one wire segment

Type: double
Default: 0.0
Edit: Yes
Reference: flip_chip_finger_min_width

flip_chip_finger_target_mesh_layer_range

Target mesh layer range for finger routing

Type: string
Default: ""
Edit: Yes
Reference: flip_chip_finger_target_mesh_layer_range

flip_chip_honor_bump_connect_target_constraint

Specifies if enabling port numbering routing

Type: bool
Default: false
Edit: Yes
Reference: flip_chip_honor_bump_connect_target_constraint

flip_chip_ignore_pad_type_check

Specifies if supporting CLASS PAD cells in flipchip flow

Type: bool
Default: true
Edit: Yes
Reference: flip_chip_ignore_pad_type_check

flip_chip_lower_layer_prevent_diagonal_routing

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Specifies if preventing 45-degree routing for lower layer

Type: bool
Default: false
Edit: Yes
Reference: flip_chip_lower_layer_prevent_diagonal_routing

flip_chip_lower_layer_route_width

Specifies the different value for lower routing layer

Type: double
Default: 0.0
Edit: Yes
Reference: flip_chip_lower_layer_route_width

flip_chip_multi_pad_routing_style

Specifies the routing style for multi-pads routing

Type: enum
Enum Values: default serial star
Default: default
Edit: Yes
Reference: flip_chip_multi_pad_routing_style

flip_chip_multiple_connection

Specifies routing connections between multiple pads and bumps. Default is no multiple
connection
Type: enum
Enum Values: multiple_pads_to_bump multiple_bumps_to_pad default
Default: default
Edit: Yes
Reference: flip_chip_multiple_connection

flip_chip_pg_mesh_direction

Specifies the main routing direction of PG mesh

Type: enum
Enum Values: default horizontal vertical
Default: default
Edit: Yes
Reference: flip_chip_pg_mesh_direction

flip_chip_pg_mesh_main_width

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Specifies the main width of PG mesh

Type: double
Default: 0.0
Edit: Yes
Reference: flip_chip_pg_mesh_main_width

flip_chip_pg_mesh_max_width

Specifies the max width of PG mesh

Type: double
Default: 0.0
Edit: Yes
Reference: flip_chip_pg_mesh_max_width

flip_chip_pg_mesh_width

Specify the exact width of PG mesh. One value for both horizontal and vertical width. And with
two values, the first value for horizontal width and the second value for vertical width
Type: string
Default: ""
Edit: Yes
Reference: flip_chip_pg_mesh_width

flip_chip_prevent_via_under_bump

Specifies if generating vias directly under the bump

Type: bool
Default: false
Edit: Yes
Reference: flip_chip_prevent_via_under_bump

flip_chip_prevent_via_under_bump_extension

specifies the spacing value around bump to avoid dropping vias

Type: double
Default: 0.0
Edit: Yes
Reference: flip_chip_prevent_via_under_bump_extension

flip_chip_route_pg_style

Specifies the routing pattern for route_flip_chip power routing

Type: enum
Enum Values: none finger mesh
Default: none
Edit: Yes
Reference: flip_chip_route_pg_style

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flip_chip_route_style

Specifies routing style

Type: enum
Enum Values: manhattan diagonal
Default: diagonal
Edit: Yes
Reference: flip_chip_route_style

flip_chip_route_width

Specifies routing width

Type: double
Default: 0.0
Edit: Yes
Reference: flip_chip_route_width

flip_chip_serial_pad_routing

route_flip_chip try to make bump-pad-pad routing

Type: bool
Default: false
Edit: Yes

flip_chip_top_layer

Specifies the top-most metal layer by layer number or layer name that the software can use
when routing bumps
Type: string
Default: ""
Edit: Yes
Reference: flip_chip_top_layer

floorplan_check_types

Specify the check types for check_floorplan. Default is the basic.

Type: enum
Enum Values: basic fence odd_even_site_row macro_pin color alignment_following_pin
alignment_partition_clone bus_guide_connectivity feed_through partition_in_partition
multi_layer_pin power_domain partition place same_length_site narrow_channel block_only
all
Default: basic
Edit: Yes
Reference: floorplan_check_types

floorplan_cut_off_place_blockage_outside_die

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When creating placement blockages, will cut the part outside of die and snap it by default.
Type: bool
Default: true
Edit: Yes
Reference: floorplan_cut_off_place_blockage_outside_die

floorplan_cut_off_route_blockage_outside_die

When creating routing blockages around inst/Hinst/Partition, will cut the part outside of die and
snap it by default. If this option is set to false, don't cut and snap it.
Type: bool
Default: true
Edit: Yes
Reference: floorplan_cut_off_route_blockage_outside_die

floorplan_default_blockage_name_prefix

Name prefix for placement blockage and routing blockage.

Type: string
Default: ""
Edit: Yes
Reference: floorplan_default_blockage_name_prefix

floorplan_default_power_domain_site

Create rows based on default power domain site instead of the design’s default site.
Type: bool
Default: false
Edit: Yes
Reference: floorplan_default_power_domain_site

floorplan_default_tech_site

Specify a site as default technical site. After setting a forced one, the auto-calculating default-
technical-site functionality will be disabled.
Type: string
Default: ""
Edit: Yes
Reference: floorplan_default_tech_site

floorplan_enable_rectilinear_design

Specify whether design boundary can be changed to rectilinear shape.

Type: bool
Default: false
Edit: Yes
Reference: floorplan_enable_rectilinear_design

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floorplan_finfet_inst_grid

The finfet_inst grid {x_origin y_origin x_pitch y_pitch}. The x_origin y_origin is lower left corner
of core box. (e.g. the core rows). The x_pitch is default technical site's width and separates the
vertical grid lines. The y_pitch is FinFET pitch as defined in LEF and separates the horizontal
grid lines.
Type: rect
Default: 0.0 0.0 0.0 0.0
Edit: Yes
Reference: floorplan_finfet_inst_grid

floorplan_finfet_manufacturing_grid

The finfet_manufacturing grid {x_origin y_origin x_pitch y_pitch}. The x_origin y_origin is
lower left corner of die box (the design .boundary). The x_pitch is Manufacture Grid value and
defined in LEF. The y_pitch is FinFET pitch and defined in LEF.
Type: rect
Default: 0.0 0.0 0.0 0.0
Edit: Yes
Reference: floorplan_finfet_manufacturing_grid

floorplan_finfet_placement_grid

The finfet_placement grid {x_origin y_origin x_pitch y_pitch}. The x _origin y_origin is lower
left corner of die box (the design .boundary). The x_pitch is the pitch of lowest vertical metal
layer and separates the vertical grid lines. The y_pitch is FinFET pitch as defined in LEF and
separates the horizontal grid lines.
Type: rect
Default: 0.0 0.0 0.0 0.0
Edit: Yes
Reference: floorplan_finfet_placement_grid

floorplan_include_io_when_init_area

Include IO cells when calculating the area of modules.

Type: bool
Default: false
Edit: Yes
Reference: floorplan_include_io_when_init_area

floorplan_initial_all_compatible_core_site_rows

If true, initCoreRow will create all SITE with type core.

Type: bool
Default: false
Edit: Yes
Reference: floorplan_initial_all_compatible_core_site_rows

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floorplan_inst_grid

The inst grid {x_origin y_origin x_pitch y_pitch}. The x_origin y_origin is lower left corner of
core box (e.g. the core rows). The x_pitch is default technical site's width and separates the
vertical grid lines. The y_pitch is default technical site¡¯s height and separates the horizontal
grid lines.
Type: rect
Default: 0.0 0.0 0.0 0.0
Edit: Yes
Reference: floorplan_inst_grid

floorplan_keep_rows_when_moving_power_domain

specify whether to keep all existing rows in disjoint power domain when moving, resizing or
reshaping a power domain on GUI or by command.
Type: bool
Default: false
Edit: Yes
Reference: floorplan_keep_rows_when_moving_power_domain

floorplan_layer_track_grid

The layer_track grid {x_origin y_origin x_pitch y_pitch}. The x_origin y_origin is lower left
corner of die box (the design .boundary). The x_pitch is the pitch of lowest vertical metal layer
and separates the vertical grid lines. The y_pitch is the pitch of lowest horizontal metal layer
and separates the horizontal grid lines.
Type: rect
Default: 0.0 0.0 0.0 0.0
Edit: Yes
Reference: floorplan_layer_track_grid

floorplan_manufacturing_grid

The manufacturing grid is in the format {x_origin y_origin x_pitch y_pitch} from the LEF global
MANUFACTURINGGRID statement. The x_origin y_origin is lower left corner of die box(the
design .boundary). See the layer .mfg_grid values if the mfg_grid varies per layer.
Type: rect
Default: 0.0 0.0 0.0 0.0
Edit: Yes
Reference: floorplan_manufacturing_grid

floorplan_max_io_height

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Use maximum IO height to calculate a die box with IO placement. By default, minimum IO
height is used.
Type: bool
Default: false
Edit: Yes
Reference: floorplan_max_io_height

floorplan_minimum_sites

Specify the number of minimal sites (N) that check_floorplan will check for the same length
site rule. When same_length_site is specified in floorplan_check_types, this option is
required.
Type: int
Default: 0
Edit: Yes
Reference: floorplan_minimum_sites

floorplan_move_macros_with_constraint

Specify macros move with constraint modules at the same time.

Type: enum
Enum Values: guide region fence none all
Default: fence
Edit: Yes
Reference: floorplan_move_macros_with_constraint

floorplan_move_preplaced_std_cell_only

Specify only pre-placed std cells move with constraint modules at the same time.
Type: bool
Default: false
Edit: Yes
Reference: floorplan_move_preplaced_std_cell_only

floorplan_move_std_cell_with_constraint

Specify std cells move with constraint modules at the same time.
Type: enum
Enum Values: guide region fence none all
Default: none
Edit: Yes
Reference: floorplan_move_std_cell_with_constraint

floorplan_narrow_channel_threshold

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Reports narrow channels whose width (in micros) is smaller than the specified value. When
narrow_channel is specified in floorplan_check_types, this option is required.
Type: double
Default: 0.0
Edit: Yes
Reference: floorplan_narrow_channel_threshold

floorplan_no_cut_row

Specify no need to do cut row before other operations.

Type: bool
Default: false
Edit: Yes
Reference: floorplan_no_cut_row

floorplan_placement_grid

The placement grid {x_origin y_origin x_pitch y_pitch}. The x_origin y_origin is lower left
corner of die box (the design .boundary). The x_pitch is the pitch of lowest vertical metal layer
and separates the vertical grid lines. The y_pitch is pitch of lowest horizontal metal layer and
separates the horizontal grid lines.
Type: rect
Default: 0.0 0.0 0.0 0.0
Edit: Yes
Reference: floorplan_placement_grid

floorplan_power_rail_layer

Specify the layers for calculating power/ground on bottom attribute of cell or techsite. By
default, the lowest metal layer is used.
Type: string
Default: ""
Edit: Yes
Reference: floorplan_power_rail_layer

floorplan_row_site_height

Specify the odd even row height constraints.

Type: enum
Enum Values: any odd even
Default: any
Edit: Yes
Reference: floorplan_row_site_height

floorplan_row_site_width

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Specify the odd even row width constraints.

Type: enum
Enum Values: any odd even
Default: any
Edit: Yes
Reference: floorplan_row_site_width

floorplan_snap_all_corners_to_grid

Specify to snap all corners of object to grid.

Type: bool
Default: false
Edit: Yes
Reference: floorplan_snap_all_corners_to_grid

floorplan_snap_block_grid

Specify the block snap rules. It can be set to snap to manufacture grid, instance grid,
placement grid, user-define grid, layer_track grid, finfet manufacture grid, finfet instance grid,
finfet placement grid. The default is manufacturing_grid. For Finfet design, the default is
finfet_manufacturing_grid.
Type: enum
Enum Values: manufacturing inst placement user_define layer_track finfet_inst
finfet_manufacturing finfet_placement
Default: manufacturing
Edit: Yes
Reference: floorplan_snap_block_grid

floorplan_snap_constraint_grid

Specify the constraint snap rules. It can be set to snap to manufacture grid, instance grid,
placement grid, user-define grid, layer_track grid, finfet manufacture grid, finfet instance grid,
finfet placement grid. The default is inst_grid. For Finfet design, the default is finfet_inst_grid.
Type: enum
Enum Values: manufacturing inst placement user_define layer_track finfet_inst
finfet_manufacturing finfet_placement
Default: inst
Edit: Yes
Reference: floorplan_snap_constraint_grid

floorplan_snap_core_grid

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Specify the core snap rules. It can be set to snap to manufacture grid, instance grid, placement
grid, user-define grid, layer_track grid, finfet manufacture grid, finfet instance grid, finfet
placement grid. The default is placement_grid. For Finfet design, the default is
finfet_placement_grid.
Type: enum
Enum Values: manufacturing inst placement user_define layer_track finfet_inst
finfet_manufacturing finfet_placement
Default: placement
Edit: Yes
Reference: floorplan_snap_core_grid

floorplan_snap_die_grid

Specify the die snap rules. It can be set to snap to manufacture grid, instance grid, placement
grid, user-define grid, layer_track grid, finfet manufacture grid, finfet instance grid, finfet
placement grid. The default is placement_grid. For Finfet design, the default is
finfet_placement_grid.
Type: enum
Enum Values: manufacturing inst placement user_define layer_track finfet_inst
finfet_manufacturing finfet_placement
Default: placement
Edit: Yes
Reference: floorplan_snap_die_grid

floorplan_snap_io_grid

Specify the IO snap rules. It can be set to snap to manufacture grid, instance grid, placement
grid, user-define grid, layer_track grid, finfet manufacture grid, finfet instance grid, finfet
placement grid. The default is manufacturing_grid. For Finfet design, the default is
finfet_manufacturing_grid.
Type: enum
Enum Values: manufacturing inst placement user_define layer_track finfet_inst
finfet_manufacturing finfet_placement
Default: manufacturing
Edit: Yes
Reference: floorplan_snap_io_grid

floorplan_snap_place_blockage_grid

Specify the placement blockage snap rules. The default is inst_grid.

Type: enum
Enum Values: manufacturing inst finfet_inst finfet_manufacturing
Default: inst
Edit: Yes
Reference: floorplan_snap_place_blockage_grid

floorplan_user_define_grid

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Specify the user-define grid. Format is {x_origin y_origin x_pitch y_pitch}. The x_origin
y_origin is the coordinate of user-define grid origin. The x_pitch separates the vertical grid
lines. The y_pitch separates the horizontal grid lines. The values are in microns.
Type: rect
Default: 0.0 0.0 0.0 0.0
Edit: Yes
Reference: floorplan_user_define_grid

floorplan_vertical_row

Specifies that the rows in the floorplan are vertical (1) or horizontal (0).
Type: int
Default: 0
Edit: Yes
Reference: floorplan_vertical_row

flow_branch

Branch being run for a hierarchical flow.

Type: string
Default: ""
Edit: Yes
Reference: flow_branch

flow_caller_data

Data used by the caller of the tool to identify this flow.

Type: string
Default: ""
Edit: Yes
Reference: flow_caller_data

flow_db_directory

Flow directory where results databases are stored.

Type: string
Default: dbs
Edit: Yes
Reference: flow_db_directory

flow_error_errorinfo

Tcl error stack in error database.

Type: string
Default: ""
Edit: Yes
Reference: flow_error_errorinfo

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flow_error_message

Tcl error message in error database.

Type: string
Default: ""
Edit: Yes
Reference: flow_error_message

flow_error_write_db

Write a database when a flow step results in an error condition.

Type: bool
Default: true
Edit: Yes
Reference: flow_error_write_db

flow_exit_when_done

Exit after running final step.

Type: bool
Default: false
Edit: Yes
Reference: flow_exit_when_done

flow_feature_values

Global feature settings.

Type: string
Default: ""
Edit: Yes
Reference: flow_feature_values

flow_features

Global feature definitions.

Type: string
Default: ""
Edit: Yes
Reference: flow_features

flow_footer_tcl

TCL script to run when a flow ends.

Type: string
Default: ""
Edit: Yes
Reference: flow_footer_tcl

flow_header_tcl

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TCL script to run when a flow starts.

Type: string
Default: ""
Edit: Yes
Reference: flow_header_tcl

flow_hier_path

Path of current flow within the flow hierarchy.

Type: string
Default: ""
Edit: Yes
Reference: flow_hier_path

flow_history

Complete flow run history.

Type: string
Default: ""
Edit: Yes
Reference: flow_history

flow_log_directory

Flow directory where log files are stored.

Type: string
Default: logs
Edit: Yes
Reference: flow_log_directory

flow_log_prefix_generator

TCL script to create log filenames in Flow tool.

Type: string
Default: ""
Edit: Yes
Reference: flow_log_prefix_generator

flow_mail_on_error

Email to flow_mail_to if an error is detected.

Type: bool
Default: false
Edit: Yes
Reference: flow_mail_on_error

flow_mail_to

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Email address where results are sent.

Type: string
Default: ""
Edit: Yes
Reference: flow_mail_to

flow_metrics_file

Flow metrics file for reporting results.

Type: string
Default: ""
Edit: Yes
Reference: flow_metrics_file

flow_metrics_snapshot_parent_uuid

The snapshot uuid the results from this flow will be appended to.
Type: string
Default: ""
Edit: Yes
Reference: flow_metrics_snapshot_parent_uuid

flow_metrics_snapshot_uuid

The snapshot uuid of the most recent flow step executed.

Type: string
Default: ""
Edit: Yes
Reference: flow_metrics_snapshot_uuid

flow_overwrite_db

Enables overwriting databases when saving.

Type: bool
Default: false
Edit: Yes
Reference: flow_overwrite_db

flow_plugin_names

Names of all internal plug-in points.

Type: string
Default: ""
Edit: Yes
Reference: flow_plugin_names

flow_plugin_steps

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List of plug-in steps that have been added through edit_flow.

Type: string
Default: ""
Edit: Yes
Reference: flow_plugin_steps

flow_post_db_overwrite

If set within a skip_db flow_step, it allows the user to identify the name and type of database to
present to future flows as the flow_starting_db.
Type: string
Default: ""
Edit: Yes
Reference: flow_post_db_overwrite

flow_remark

Remark from the last flow yaml file loaded.

Type: string
Default: ""
Edit: Yes
Reference: flow_remark

flow_report_directory

Flow directory where reports are written.

Type: string
Default: reports
Edit: Yes
Reference: flow_report_directory

flow_reset_time_after_flow_init

Reset all time measures after flow init.

Type: bool
Default: false
Edit: Yes
Reference: flow_reset_time_after_flow_init

flow_run_tag

Tags for this particular flow run.

Type: string
Default: ""
Edit: Yes
Reference: flow_run_tag

flow_schedule

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Set of flows to execute after the current flow completes.

Type: string
Default: ""
Edit: Yes
Reference: flow_schedule

flow_starting_db

Starting database for the flow run.

Type: string
Default: ""
Edit: Yes
Reference: flow_starting_db

flow_startup_directory

Directory where the tool was started.

Type: string
Default: /home/manishk/dbschema/novus/newscript
Edit: Yes
Reference: flow_startup_directory

flow_status_file

File for flow status.

Type: string
Default: ""
Edit: Yes
Reference: flow_status_file

flow_step_begin_tcl

Defines the Tcl to run before running the body of each step.
Type: string
Default: ""
Edit: Yes

flow_step_canonical_current

Currently running canonical flow step.

Type: string
Default: ""
Edit: Yes
Reference: flow_step_canonical_current

flow_step_check_tcl

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Procedure to check the steps.

Type: string
Default: ""
Edit: Yes
Reference: flow_step_check_tcl

flow_step_current

Currently running flow step.

Type: string
Default: ""
Edit: Yes
Reference: flow_step_current

flow_step_end_tcl

Defines the Tcl to run after running the body of each step.
Type: string
Default: ""
Edit: Yes

flow_step_last

Last flow step to have been completed.

Type: string
Default: ""
Edit: Yes
Reference: flow_step_last

flow_step_last_msg

Message provided for the last step that was run.

Type: string
Default: ""
Edit: Yes
Reference: flow_step_last_msg

flow_step_last_status

Status for the last flow step run.

Type: string
Default: not_run
Edit: Yes
Reference: flow_step_last_status

flow_step_next

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Next step to run in the flow.

Type: string
Default: ""
Edit: Yes
Reference: flow_step_next

flow_steps

List of all created flow_steps

Type: obj(flow_step)*
Default: ""
Edit: No

flow_summary_tcl

TCL script to run during run_flow summary.

Type: string
Default: ""
Edit: Yes
Reference: flow_summary_tcl

flow_template_feature_definition

Features list and status for the current template.

Type: string
Default: ""
Edit: Yes
Reference: flow_template_feature_definition

flow_template_tools

List of tools included in flow templates being run.

Type: string
Default: ""
Edit: Yes
Reference: flow_template_tools

flow_template_type

Type of template being run.

Type: string
Default: ""
Edit: Yes
Reference: flow_template_type

flow_template_version

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Version of the template being run.

Type: string
Default: ""
Edit: Yes
Reference: flow_template_version

flow_top

Flow to execute by default.

Type: string
Default: ""
Edit: Yes
Reference: flow_top

flow_user_templates

Flow user template definitions.

Type: string
Default: ""
Edit: Yes
Reference: flow_user_templates

flow_verbose

Enables printing run information in the logfile.

Type: bool
Default: true
Edit: Yes
Reference: flow_verbose

flow_working_directory

Flow directory where the flow is being run.

Type: string
Default: .
Edit: Yes
Reference: flow_working_directory

flow_yamllint_exec

Yamllint executable command and arguments for checking yaml files.

Type: string
Default: yamllint
Edit: Yes
Reference: flow_yamllint_exec

flows

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List of all created flows

Type: obj(flow)*
Default: ""
Edit: No

flowtool_exit_timeout

Maximum amount of time in seconds Flow tool will wait after a tool exits for a completed
status.
Type: int
Default: 30
Edit: Yes
Reference: flowtool_exit_timeout

flowtool_extra_arguments

Extra arguments passed to Flowtool when running in tool mode.

Type: string
Default: ""
Edit: Yes
Reference: flowtool_extra_arguments

flowtool_metrics_qor_excel

Metrics file to write after tools exit.

Type: string
Default: ""
Edit: Yes
Reference: flowtool_metrics_qor_excel

flowtool_metrics_qor_html

Metrics file to write after tools exit.

Type: string
Default: ""
Edit: Yes
Reference: flowtool_metrics_qor_html

flowtool_metrics_qor_text

Metrics file to write after tools exit.

Type: string
Default: ""
Edit: Yes
Reference: flowtool_metrics_qor_text

flowtool_metrics_qor_vivid

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Metrics file to write after tools exit.

Type: string
Default: ""
Edit: Yes
Reference: flowtool_metrics_qor_vivid

flowtool_predict_full_names

Show skip_metric flow name in prediction.

Type: bool
Default: false
Edit: Yes
Reference: flowtool_predict_full_names

flowtool_summary_tcl

Tcl script to run at the end of flowtool.

Type: string
Default: puts [report_metric -format text]
Edit: Yes
Reference: flowtool_summary_tcl

foreign_cells

Short-cut for [get_db base_cells .foreign_cells]

Type: obj(foreign_cell)*
Default: ""
Edit: No

gcell_grids

Short-cut to all the gcell_grid objects in the design.

Type: obj(gcell_grid)*
Default: ""
Edit: No

gcells

The gcells for this design. The gcells are only created after global route has occurred.
Type: obj(gcell)*
Default: ""
Edit: No

generate_special_via_accuracy_effort

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Specifies viagen effort to generate vias.

Type: enum
Enum Values: low high
Default: high
Edit: Yes
Reference: generate_special_via_accuracy_effort

generate_special_via_add_pin_to_pin_vias

Inserts vias to connect pins between cover macros

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_add_pin_to_pin_vias

generate_special_via_align_merged_stack_via_metal

Aligns merged stack vias

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_align_merged_stack_via_metal

generate_special_via_allow_via_expand

Allows via expansion to meet LEF rules

Type: bool
Default: true
Edit: Yes
Reference: generate_special_via_allow_via_expand

generate_special_via_allow_wire_shape_change

Allows via to change the metal shape of existing wire

Type: bool
Default: true
Edit: Yes
Reference: generate_special_via_allow_wire_shape_change

generate_special_via_area_only

adds via only within the specified area

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_area_only

generate_special_via_check_signal_routes

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Honors pre-existing signal routes

Type: enum
Enum Values: 0 1 2
Default: 0
Edit: Yes
Reference: generate_special_via_check_signal_routes

generate_special_via_create_double_row_cut_via

Expands vias to have an additional cut than original for one-row or one-column vias if possible
Type: enum
Enum Values: no_extra_cut add_extra_cut add_extra_cut_and_metal
Default: no_extra_cut
Edit: Yes
Reference: generate_special_via_create_double_row_cut_via

generate_special_via_create_max_row_cut_via

Creates max rows of via cuts

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_create_max_row_cut_via

generate_special_via_cut_class_preference

Specifies via cut class preference

Type: string
Default: default
Edit: Yes
Reference: generate_special_via_cut_class_preference

generate_special_via_disable_via_merge

Disables via merging

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_disable_via_merge

generate_special_via_enable_check_drc

Invokes check_drc
Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_enable_check_drc

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generate_special_via_extend_out_wire_end

Extends via outside of existing wires end

Type: bool
Default: true
Edit: Yes
Reference: generate_special_via_extend_out_wire_end

generate_special_via_full_cut_via_only

allows to create full cut via only

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_full_cut_via_only

generate_special_via_hookup_contact_max

Sets the max distance to create hookup via from contact, and the max distance between two
hookup via on a continuous M0 PG pin.
Type: string
Default: 0, 0
Edit: Yes
Reference: generate_special_via_hookup_contact_max

generate_special_via_hookup_contact_pg_track

Sets start point and the pitch of PG track used by hookup contact.
Type: string
Default: 0, 0
Edit: Yes
Reference: generate_special_via_hookup_contact_pg_track

generate_special_via_hookup_fixed_grid

Specifies to add hookup via over the fixed Grid.

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_hookup_fixed_grid

generate_special_via_hookup_min_distance

min distance between two pg vias

Type: string
Default: min
Edit: Yes
Reference: generate_special_via_hookup_min_distance

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generate_special_via_hookup_rail_pair

Create hookup vias over pairing followpins

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_hookup_rail_pair

generate_special_via_hookup_via_distance

Sets via hookup distance and boundary spacing

Type: string
Default: 4pitch 4pitch 0
Edit: Yes
Reference: generate_special_via_hookup_via_distance

generate_special_via_hookup_via_rule

Specifies the viarule used in specified area

Type: string
Default: ""
Edit: Yes
Reference: generate_special_via_hookup_via_rule

generate_special_via_hookup_via_style

Sets via hookup style

Type: enum
Enum Values: none loose compact moderate
Default: none
Edit: Yes
Reference: generate_special_via_hookup_via_style

generate_special_via_hookup_virtual_trim_grid

Specifies the virtual trim grid for pg hookup

Type: string
Default: ""
Edit: Yes

generate_special_via_ignore_drc

Ignores DRC
Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_ignore_drc

generate_special_via_ignore_rule_enclosure

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Ignores enclosures defined in VIARULE GENERATE

Type: bool
Default: true
Edit: Yes
Reference: generate_special_via_ignore_rule_enclosure

generate_special_via_inherit_wire_status

Inherits wire status

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_inherit_wire_status

generate_special_via_keep_existing_via

Keeps existing vias

Type: enum
Enum Values: remove keep_with_new_via keep_with_no_new_via
Default: remove
Edit: Yes
Reference: generate_special_via_keep_existing_via

generate_special_via_keep_fixed_via

Keeps fixed vias not modifiable

Type: bool
Default: true
Edit: Yes
Reference: generate_special_via_keep_fixed_via

generate_special_via_opt_cross_via

Controls the creation of additional via cuts

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_opt_cross_via

generate_special_via_opt_via_on_routing_track

Frees up via tracks

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_opt_via_on_routing_track

generate_special_via_parameterized_via_only

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generate parameterized vias only, auto sets true for OA flow, false for non-OA flow.
Type: enum
Enum Values: auto true false
Default: auto
Edit: Yes
Reference: generate_special_via_parameterized_via_only

generate_special_via_partial_overlap_threshold

Specifies ratio threshold of via creation on partial overlap wires

Type: double
Default: 0.0
Edit: Yes
Reference: generate_special_via_partial_overlap_threshold

generate_special_via_preferred_vias_only

Generate only vias set in -viarule_preference

Type: enum
Enum Values: use_lef open keep
Default: use_lef
Edit: Yes
Reference: generate_special_via_preferred_vias_only

generate_special_via_prefix

Specifies prefix name for all vias

Type: string
Default: ""
Edit: Yes
Reference: generate_special_via_prefix

generate_special_via_reference_boundary

Sets reference boundary

Type: enum
Enum Values: design core
Default: design
Edit: Yes
Reference: generate_special_via_reference_boundary

generate_special_via_respect_stdcell_geometry

Respects all standard cell patterns

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_respect_stdcell_geometry

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generate_special_via_rule_preference

Specifies via rule preference

Type: string
Default: default
Edit: Yes
Reference: generate_special_via_rule_preference

generate_special_via_set_via_expand_dir

Sets via expansion direction

Type: enum
Enum Values: auto horizontal vertical
Default: auto
Edit: Yes
Reference: generate_special_via_set_via_expand_dir

generate_special_via_snap_via_center_to_grid

Specifies the via center alignment style per routing layer

Type: string
Default: ""
Edit: Yes
Reference: generate_special_via_snap_via_center_to_grid

generate_special_via_split_long_via_global_grid

Controls global grids so vias on them are in line

Type: string
Default: 0 0 0 0 0 0 0 0
Edit: Yes
Reference: generate_special_via_split_long_via_global_grid

generate_special_via_symmetrical_via_only

adds symmetrical via only, auto sets true for OA flow, false for non-OA flow.
Type: enum
Enum Values: auto true false
Default: auto
Edit: Yes
Reference: generate_special_via_symmetrical_via_only

generate_special_via_use_track_offset

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Uses track offset

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_use_track_offset

generate_special_via_use_trim_metal_enclosure

Force tool to use enclosures with trim layer

Type: bool
Default: false
Edit: Yes
Reference: generate_special_via_use_trim_metal_enclosure

get_db_display_limit

Controls the number of objects that will be displayed when using get_db with an attribute
pattern like '*' rather than single attribute name. If the value is 10, 'get_db insts .*' will only
display 10 inst objects with all their attributes, and will only display the first 10 objects for any
attribute that is an object list (e.g. the first 10 pins for each inst .pins value).
Type: int
Default: 10
Edit: Yes
Reference: get_db_display_limit

group_hinst_suffix

new hinst name is created from the module name with a suffix added as defined by this tcl
global
Type: string
Default: i
Edit: Yes
Reference: group_hinst_suffix

groups

Short-cut for [get_db current_design .groups]

Type: obj(group)*
Default: ""
Edit: No

gui_lines

Short-cut to all the gui_line objects in the design.

Type: obj(gui_line)*
Default: ""
Edit: No

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gui_polygons

Short-cut to all the gui_polygon objects in the design.

Type: obj(gui_polygon)*
Default: ""
Edit: No

gui_rects

Short-cut to all the gui_rect objects in the design.

Type: obj(gui_rect)*
Default: ""
Edit: No

gui_shapes

Short-cut to all the gui_shape objects in the design.

Type: obj(gui_rect)* obj(gui_line)*
Default: ""
Edit: No

gui_texts

Short-cut to all the gui_text objects in the design.

Type: obj(gui_text)*
Default: ""
Edit: No

gui_verbose

Controls which GUI actions are logged. The choices are:

all: all GUI actions;
db: GUI actions that affect the DB like gui_select, set_layer_preference, but not display-only
actions like gui_zoom, gui_pan;
none: no gui_* commands are logged, so the .log and .cmd file are incomplete
Type: enum
Enum Values: all db none
Default: db
Edit: Yes
Reference: gui_verbose

hinsts

Short-cut for [get_db current_design .hinsts]

Type: obj(hinst)*
Default: ""
Edit: No

hnets

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Short-cut for [get_db current_design .hnets]

Type: obj(hnet)*
Default: ""
Edit: No

hpins

Short-cut for [get_db current_design .hpins]

Type: obj(hpin)*
Default: ""
Edit: No

hports

Short-cut for [get_db hinsts .hports]

Type: obj(hport)*
Default: ""
Edit: No

hybrid_hier_feedthru_disable

To enable or disable feed-though insertion

Type: bool
Default: false
Edit: Yes
Reference: hybrid_hier_feedthru_disable

hybrid_hier_feedthru_exclude_nets_file

Specifies the file name with net names. Feedthrough insertion will not be tried on these nets
Type: string
Default: ""
Edit: Yes
Reference: hybrid_hier_feedthru_exclude_nets_file

hybrid_hier_feedthru_include_nets_file

Specifies the file name with net names. Feedthrough insertion if any will be done only on
these nets
Type: string
Default: ""
Edit: Yes
Reference: hybrid_hier_feedthru_include_nets_file

hybrid_hier_feedthru_plugin_tcl

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Specifies the file name having customized feed-through flow from user
Type: string
Default: ""
Edit: Yes
Reference: hybrid_hier_feedthru_plugin_tcl

hybrid_hier_out_dir

Specifies directory name for feedthru, budget and pin assignment reports
Type: string
Default: .
Edit: Yes

hybrid_hier_partition_place_halo

Specifies placement halo in microns to be applied around all partition in design. Default:
"pinDepth + 2*minSpacing" of rouing layer M4
Type: double
Default: -1.0
Edit: Yes
Reference: hybrid_hier_partition_place_halo

hybrid_hier_partition_route_halo

Specifies routing halo in microns to be applied around all partition in design. Default:
"pinDepth + 2*minSpacing" of rouing layer M4
Type: double
Default: -1.0
Edit: Yes
Reference: hybrid_hier_partition_route_halo

hybrid_hier_pin_assign_plugin_tcl

Specifies the file name having customized pin-assignment flow from user
Type: string
Default: ""
Edit: Yes
Reference: hybrid_hier_pin_assign_plugin_tcl

hybrid_hier_pin_assign_timing_aware_priority

Specifies timing aware priority of pin assignment.

Type: enum
Enum Values: tns wns
Default: wns
Edit: Yes

hybrid_hier_timing_budget_plugin_tcl

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Specifies the file name having customized time-budgeting flow from user
Type: string
Default: ""
Edit: Yes
Reference: hybrid_hier_timing_budget_plugin_tcl

ilm_filter_internal_path

filterInternalPath
Type: bool
Default: false
Edit: Yes
Reference: ilm_filter_internal_path

ilm_keep_async

Keep paths from asynchronous input ports

Type: bool
Default: false
Edit: Yes
Reference: ilm_keep_async

ilm_keep_flatten

Instruct Innovus to keep in flattened state

Type: bool
Default: true
Edit: Yes
Reference: ilm_keep_flatten

ilm_keep_high_fanout_ports

Keep high fanout input port paths

Type: bool
Default: true
Edit: Yes
Reference: ilm_keep_high_fanout_ports

ilm_keep_inst_in_sdc

Keep instances which have constraints on it

Type: bool
Default: false
Edit: Yes
Reference: ilm_keep_inst_in_sdc

ilm_keep_loopback

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Keep loop back paths

Type: bool
Default: false
Edit: Yes
Reference: ilm_keep_loopback

ilm_max_num_insts

Specify the maximum number of instances

Type: int
Default: 1000
Edit: Yes
Reference: ilm_max_num_insts

ilm_max_num_registers

Specify the maximum number of registers

Type: int
Default: 40
Edit: Yes
Reference: ilm_max_num_registers

ilm_slack_driven

slackDriven
Type: bool
Default: false
Edit: Yes
Reference: ilm_slack_driven

init_check_netlist

After reading in the netlist, will do the same checks as check_design -netlist
Type: bool
Default: false
Edit: Yes
Reference: init_check_netlist

init_check_output_pin_constant

Stops the Verilog reader if any output (or inout) signal pins have any 1'b0 or 1'b1 constants
that would cause shorts to power/ground.
Type: bool
Default: true
Edit: Yes
Reference: init_check_output_pin_constant

init_delete_floating_hnets

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If true, an hnet (Verilog wire statement) that has nothing connected to it, is deleted from the
netlist. The default value is false in Innovus to allow for netlist repair, but true in Tempus to
delete non-timed nets and reduce memory.
Type: bool
Default: false
Edit: Yes
Reference: init_delete_floating_hnets

init_design_netlist_type

Specifies the source of the design netlist. You can specify either "Verilog" or "OA".
Type: string
Default: Verilog
Edit: Yes
Reference: init_design_netlist_type

init_design_uniquify

Specifies whether the top is uniquified. When set to 1 (true) the design will be uniquified
during the read and flatten process. Optimization is not allowed on a non-unique design. For
use in a master/clone partitioning flow, the value should be 0 (false). Default = 0 (false).
Type: bool
Default: false
Edit: Yes
Reference: init_design_uniquify

init_ground_nets

List of global Ground nets.

Type: string
Default: ""
Edit: Yes
Reference: init_ground_nets

init_ignore_pg_pin_polarity_check

List of leaf cell pin names to ignore power/ground pin polarity check. By default
connect_global_net and CPF check for matching polarity between the net and pin.
Type: string
Default: ""
Edit: Yes
Reference: init_ignore_pg_pin_polarity_check

init_keep_empty_modules

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By default, usage of an empty Verilog module that has no matching library cell name becomes
an empty hinst. If this value is false, a dummy library cell is created, and usage of it becomes
an inst. You should then use other commands to 'fix' the dummy library cell before proceeding
in the flow.
Type: bool
Default: true
Edit: Yes
Reference: init_keep_empty_modules

init_lef_files

List of LEF files to be read. Mutually exclusive with init_oa_ref_lib.

Type: string
Default: ""
Edit: Yes
Reference: init_lef_files

init_min_dbu_per_micron

Minimum DBU per micron

Type: int
Default: 0
Edit: Yes
Reference: init_min_dbu_per_micron

init_mmmc_files

Path to MMMC View Definition file.

Type: string
Default: ""
Edit: Yes
Reference: init_mmmc_files

init_no_new_assigns

Turns on an assign-free flow. By default, applications like optimization can add Verilog
assigns to remove unnecessary buffers and reduce power. If you have external tools that do
not support Verilog assigns, you can set this value to true to prevent applications from adding
any new assign statements to the Verilog netlist. If there are existing assigns in the Verilog
netlist you can remove them with the delete_assigns command.
Type: bool
Default: false
Edit: Yes
Reference: init_no_new_assigns

init_oa_abstract_views

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List of OpenAccess view names to be processed as abstracts (LEF MACRO equivalent). The
read_netlist command uses init_oa_abstract_views list for on-demand loading of missing
cells. Used by the read_physical and read_netlist commands.
Type: string
Default: ""
Edit: Yes
Reference: init_oa_abstract_views

init_oa_default_rule

The default rule to be used in OpenAccess. Typically used to specify a metal stack
LEFDefaultRouteSpec type constraint group to read from the technology library if the library
contains multiple metal stacks. Used by the read_physical command.
Type: string
Default: ""
Edit: Yes
Reference: init_oa_default_rule

init_oa_design_cell

OpenAccess design cell name that was read. Set by the read_netlist -oa_cell_view command.
Type: string
Default: ""
Edit: Yes
Reference: init_oa_design_cell

init_oa_design_lib

OpenAccess design lib name that was read. Set by the read_netlist -oa_cell_view command.
Type: string
Default: ""
Edit: Yes
Reference: init_oa_design_lib

init_oa_design_view

OpenAccess design view name that was read. Set by the read_netlist -oa_cell_view
command.
Type: string
Default: ""
Edit: Yes
Reference: init_oa_design_view

init_oa_foundry_rule

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The foundry constraint group to be used in OpenAccess. Typically used to specify a

foundry_innovus_XXXX constraint group to read from the technology library if the library
contains multiple foundry_innovus_XXXX constraint groups. Used by the read_physical
command.
Type: string
Default: ""
Edit: Yes
Reference: init_oa_foundry_rule

init_oa_layout_views

List of OpenAccess view names to be processed for cell layout viewing (GDSII equivalent).
Also used in the case where a Verilog netlist is read and views from the init_oa_layout_views
list are used in the Quick Abstract Inference flow to derive abstract information from layout
views for cells that were not processed from the libraries in the read_physical -oa_ref_libs list.
The read_netlist command uses init_oa_layout_view list for on-demand loading of missing
cells. Used by the read_physical and read_netlist commands.
Type: string
Default: ""
Edit: Yes
Reference: init_oa_layout_views

init_oa_ref_libs

List of OpenAccess reference libraries. The first library in the list indicates the library that was
used for technology information unless read_physical -oa_tech_lib is specified. All cells from
the specified libraries are read. It is important to include the standard cell library in the list to
make sure that cells that are not in the current netlist are read and available for optimization.
The init_oa_abstract_views and init_oa_layout_views lists specify which views of the cells are
read. Set by the read_physical -oa_ref_libs command.
Type: string
Default: ""
Edit: Yes
Reference: init_oa_ref_libs

init_oa_search_libs

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List of OpenAccess reference libraries to be searched when cells are used in the Verilog
netlist that are not found in the list of cells read from the libraries specified by read_physical -
oa_ref_libs command, by default all libraries in the cds.lib are searched. The
init_oa_abstract_views and init_oa_layout_views lists are used to indicate which view names
are looked for during the search. Applies only when read_netlist command is used to process
a Verilog netlist specify the connectivity to be read. Set by the read_physical -oa_search_libs
command and used by the read_netlist command.
Type: string
Default: *
Edit: Yes
Reference: init_oa_search_libs

init_oa_special_rule

The special rule to be used in OpenAccess to define the via search order for power routing.
Typically used to specify a metal stack LEFSpecialRouteRouteSpec type constraint group to
read from the technology library if the library contains multiple metal stacks. Used by the
read_physical command.
Type: string
Default: ""
Edit: Yes
Reference: init_oa_special_rule

init_oa_tech_lib

OpenAccess library to use as source of technology information. If not specified, the first library
in the read_physical -oa_ref_libs list will be used. Applies only when read_netlist is used to
process a Verilog netlist. Set by the read_physical -oa_tech_lib command.
Type: string
Default: ""
Edit: Yes
Reference: init_oa_tech_lib

init_power_intent_files

Power intent files(s) read by last 'read_power_intent' command.

Type: string*
Default: ""
Edit: No
Reference: init_power_intent_files

init_power_nets

List of global Power nets.

Type: string
Default: ""
Edit: Yes
Reference: init_power_nets

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init_read_netlist_allow_port_mismatch

If false, a Verilog instance with ports that do not match the Verilog module or library cell
definition will cause an error and exit. If true, an error message occurs, but the extra ports are
added to the module or library cell definition to allow the inconsistent netlist to be read in and
debugged further. The default is true for Innovus to allow repair of 'dirty netlists', but false for
Tempus that normally does not tolerate 'dirty netlists'.
Type: bool
Default: false
Edit: Yes
Reference: init_read_netlist_allow_port_mismatch

init_read_netlist_allow_undefined_cells

If false, a Verilog reference to an undefined cell (e.g. a Verilog module name that has no
matching library cell and no Verilog module definition) causes an error and an exit after
parsing the netlist. If true, an empty Verilog module is created with a warning. The default
value is true in Innovus to allow repair of 'dirty netlists' while it is false in Tempus to stop on
'dirty netlists'. An empty module will become an hinst or inst depending on the value of
init_keep_empty_modules.
Type: bool
Default: true
Edit: Yes
Reference: init_read_netlist_allow_undefined_cells

init_read_netlist_files

A list of Verilog files read in during initialization. read_netlist will set this root attribute to the list
of input files given to it. The original input file names are retained thru the flow for reference,
and used by write_do_lec for the default golden netlist comparison file names.
Type: string
Default: ""
Edit: Yes
Reference: init_read_netlist_files

init_sync_relative_path

Synchronize Relative paths

Type: bool
Default: false
Edit: Yes
Reference: init_sync_relative_path

init_timing_enabled

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If read_physical is issued before read_mmmc or read_libs in RC and Tempus, an error will be

issued. In EDI, doing this will result in init_timing_enabled being set to false by the tool. EDI is
now in physical only mode, and any attempt to set timing data will result in an error. By default,
init_timing_enabled is set to true.
Type: bool
Default: true
Edit: No
Reference: init_timing_enabled

insts

insts of current design

Type: obj(inst)*
Default: ""
Edit: No

io_constraints

Short-cut for [get_db current_design .io_constraints]

Type: obj(io_constraint)*
Default: ""
Edit: No

is_ilm_flattened

Is true if you have ILMs, and the flatten_ilm command has flattened them so the internal ILM
insts are visible. unflatten_ilm will set it back to false.
Type: bool
Default: false
Edit: No

is_ilm_read

Is true if you have read in any ILMs with read_ilm. It is not affected by flatten_ilm/unflatten_ilm.
Type: bool
Default: false
Edit: No

layer_name_no_abbreviation

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By default this value is true, and most command -layer <layer> options require a LEF/OA layer
name, or a routing-layer index value (e.g. 1 for the first routing layer, 2 for the second, etc.) for
input. If this global is false, then an older style abbreviation is also allowed (e.g. M1 for the first
routing layer, M2 for the second routing layer, etc.).This layer abbreviation style is not
recommended, and is only allowed for backward compatibility to migrate older scripts.
Eventually this global will be removed, so you should modify your scripts to use LEF/OA layer
names, or routing-layer index values for -layer options to avoid problems in the future.
Type: bool
Default: true
Edit: Yes
Reference: layer_name_no_abbreviation

layers

All the layers defined in the LEF or OA techfile.

Type: obj(layer)*
Default: ""
Edit: No

lib_arcs

lib_arcs
Type: obj(lib_arc)*
Default: ""
Edit: No

lib_cells

lib_cells
Type: obj(lib_cell)*
Default: ""
Edit: No

lib_pins

lib_pins
Type: obj(lib_pin)*
Default: ""
Edit: No

libraries

Returns the information about the libraries in the design.

Type: obj(library)*
Default: ""
Edit: No

library_sets

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Returns the information about the library sets in the design.

Type: obj(library_set)*
Default: ""
Edit: No

log_file

The log file name of the program. It can be changed in the session to direct log file output to a
different file. Type 'man log_file' for more details.
Type: string
Default: ""
Edit: Yes
Reference: log_file

log_verbose_style

When verbose logging is enabled (see source_verbose, flow_verbose, or set_proc_verbose),

the logging style for each command is controllable. It is sometimes helpful to include line
numbers and comments for script debug and other times this is too much information. You can
switch between settings in the middle of a script. 'debug' will output the file name, line number,
commands, comments, and empty lines. 'echo' will output only the commands and line
number. 'echo_comments' will output commands, comments, empty lines, and line number.
Type: enum
Enum Values: debug echo echo_comments
Default: echo
Edit: Yes
Reference: log_verbose_style

log_verbose_type

When verbose logging is enabled (see source_verbose, flow_verbose, or set_proc_verbose),

the default logging of each commands is pre-Tcl expansion. In some cases it is helpful to see
post-Tcl expansion, or even both pre-Tcl and post-Tcl expansion when doing detailed
debugging. You can switch between settings in the middle of a script. Type 'man log_file' for
more details.
Type: enum
Enum Values: pre post both
Default: pre
Edit: Yes
Reference: log_verbose_type

logv_file

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The verbose log file name of the program. It can be changed in the session to direct logv file
output to a different file. Type 'man log_file' for more details.
Type: string
Default: ""
Edit: Yes
Reference: logv_file

machine_learning_deployment

Specify machine learning model file name of each model type

Type: string
Default: ""
Edit: Yes
Reference: machine_learning_deployment

machine_learning_slew

predict pin slew

Type: bool
Default: false
Edit: Yes
Reference: machine_learning_slew

machine_learning_training

Specify machine learning training model type.

Type: enum
Enum Values: none net_delay net_cell_delay
Default: none
Edit: Yes
Reference: machine_learning_training

machine_learning_write_in_post_route_opt

dump training data in post route optimization

Type: bool
Default: true
Edit: Yes

markers

Short-cut to all the marker objects in the design.

Type: obj(marker)
Default: ""
Edit: No

messages

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A list of all the message objects.

Type: obj(message)*
Default: ""
Edit: No

metric_advanced_url_endpoint

Base URL for the advanced metric server.

Type: string
Default: ""
Edit: Yes
Reference: metric_advanced_url_endpoint

metric_capture_depth

Depth for capturing hinst design and power metrics.

Type: int
Default: 1
Edit: Yes
Reference: metric_capture_depth

metric_capture_design_image

Capture design image.

Type: bool
Default: true
Edit: Yes
Reference: metric_capture_design_image

metric_capture_max_drc_markers

Maximum number of DRC markers to include in metric image.

Type: int
Default: 1000
Edit: Yes
Reference: metric_capture_max_drc_markers

metric_capture_min_count

Minimum instance count for capturing hinst design and power metrics.
Type: int
Default: 1000
Edit: Yes
Reference: metric_capture_min_count

metric_capture_overwrite

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Overwrite pending metrics during create_snapshot category capture.

Type: bool
Default: false
Edit: Yes
Reference: metric_capture_overwrite

metric_capture_pba_tns_histogram

Capture path based analysis histogram data for TNS.

Type: bool
Default: false
Edit: Yes
Reference: metric_capture_pba_tns_histogram

metric_capture_per_view

Capture timing metrics per analysis_view.

Type: bool
Default: true
Edit: Yes
Reference: metric_capture_per_view

metric_capture_timing_path_groups

Defines user path groups to capture for detailed display.

Type: string
Default: ""
Edit: Yes
Reference: metric_capture_timing_path_groups

metric_capture_timing_paths

Number of paths to capture for detailed display.

Type: int
Default: 10
Edit: Yes
Reference: metric_capture_timing_paths

metric_capture_tns_histogram

Capture histogram data for TNS.

Type: bool
Default: true
Edit: Yes
Reference: metric_capture_tns_histogram

metric_capture_tns_histogram_buckets

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Number of buckets for the TNS histogram.

Type: int
Default: 50
Edit: Yes
Reference: metric_capture_tns_histogram_buckets

metric_capture_tns_histogram_max_slack

Maximum slack for the TNS histogram.

Type: int
Default: 0
Edit: Yes
Reference: metric_capture_tns_histogram_max_slack

metric_capture_tns_histogram_paths

Number of paths to capture for the TNS histogram.

Type: int
Default: 10000
Edit: Yes
Reference: metric_capture_tns_histogram_paths

metric_category_default

Default metric categories to capture if none are provided.

Type: string
Default: design
Edit: Yes
Reference: metric_category_default

metric_current_run_id

Current unique run ID returned by the advanced metric server.

Type: string
Default: ""
Edit: Yes
Reference: metric_current_run_id

metric_enable

enable metric snapshot capture with create_snapshot

Type: bool
Default: false
Edit: Yes
Reference: metric_enable

metric_summary_metrics

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Summary metrics to show when creating snapshots.

Type: string
Default: flow.cputime flow.realtime timing.setup.tns timing.setup.wns
Edit: Yes
Reference: metric_summary_metrics

modules

Short-cut for [get_db current_design .modules]

Type: obj(module)*
Default: ""
Edit: No

net_groups

Short-cut for [get_db current_design .net_groups]

Type: obj(net_group)*
Default: ""
Edit: No

nets

Short-cut for [get_db current_design .nets]. All the nets inside this design, including logical
Verilog nets, physical-only nets, Verilog supply0/supply1, and Verilog 1'b0/1'b1 nets.
Type: obj(net)*
Default: ""
Edit: No

num_eeq_variants

Maximum number of EEQ variants of any cell in library, from LIBRARY

LEF58_CELLVARIANTS property 'CELLVARIANTS variantTotalNum YFLIPMAP
{flippedVariantNum siteVariantNum} ...'
Type: int
Default: ""
Edit: No

oa_allow_analysis_only

Allow analysis only flow

Type: bool
Default: false
Edit: Yes
Reference: oa_allow_analysis_only

oa_allow_bit_connection

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Whether to create instance terminal creations bitwise, if bus not found in OA.
Type: bool
Default: false
Edit: Yes
Reference: oa_allow_bit_connection

oa_allow_tech_update

Whether to allow the tech.db to be updated or not.

Type: bool
Default: true
Edit: Yes
Reference: oa_allow_tech_update

oa_bindkey_file

Virtuoso bind key file

Type: string
Default: ""
Edit: Yes
Reference: oa_bindkey_file

oa_cell_view_dir

System defined transient global referring to origin of restored design.

Type: string
Default: ""
Edit: Yes
Reference: oa_cell_view_dir

oa_convert_diagonal_path_to

Whether to convert non-conforming pathsegs/paths to polygon or convert the endStyle to

truncate on orthogonal and to custom on diagonal pathsegs
Type: enum
Enum Values: polygon default_style
Default: polygon
Edit: Yes
Reference: oa_convert_diagonal_path_to

oa_cut_rows

Whether to use oa_cut_rows or not

Type: bool
Default: false
Edit: Yes
Reference: oa_cut_rows

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oa_display_resource_file

Display resource file

Type: string
Default: ""
Edit: Yes
Reference: oa_display_resource_file

oa_display_resource_file_in_library

Whether to use display resource file in the tech library

Type: bool
Default: false
Edit: Yes
Reference: oa_display_resource_file_in_library

oa_drc_fill_purpose

Whether to save drcFill shapes to gap_fill or drawing purpose. By default DEF routes with +
SHAPE DRCFILL are mapped to the OA 'gapFill' purpose. Some OA techfiles do not have this
purpose defined, and require these shapes be mapped to 'drawing' purpose. In that case, they
get an additional internal attribute so they can round-trip back to DRCFILL shapes properly.
Type: enum
Enum Values: gap_fill drawing
Default: gap_fill
Edit: Yes
Reference: oa_drc_fill_purpose

oa_enclose_quick_abstract_pins

Include shapes that enclose layout pin shapes

Type: bool
Default: true
Edit: Yes
Reference: oa_enclose_quick_abstract_pins

oa_full_layer_list

Whether to support full list of layer import

Type: bool
Default: true
Edit: Yes
Reference: oa_full_layer_list

oa_full_path

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Whether to use full path or not

Type: bool
Default: false
Edit: Yes
Reference: oa_full_path

oa_inst_placed_if_none

Whether to map OA Placement status oacNonePlacementStatus of an instance to

Placed(true)/ Unplaced(false).
Type: bool
Default: true
Edit: Yes
Reference: oa_inst_placed_if_none

oa_lib_create_mode

Library creation method during write_db for newly created libraries

Type: enum
Enum Values: none attach copy reference
Default: reference
Edit: Yes
Reference: oa_lib_create_mode

oa_lock

Whether to lock the OA database during read_db

Type: enum
Enum Values: false true error_if_locked
Default: false
Edit: Yes
Reference: oa_lock

oa_logic_only_import

Whether to run read_oa after init_design or not

Type: bool
Default: false
Edit: Yes
Reference: oa_logic_only_import

oa_new_lib_compress_level

OA Database compression level

Type: int
Default: 1
Edit: Yes
Reference: oa_new_lib_compress_level

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oa_pin_purpose

Whether to set Pin Purpose as Pin or not

Type: bool
Default: false
Edit: Yes
Reference: oa_pin_purpose

oa_push_pin_constraint

whether write_db to push interoperable pin constraint into its corresponding blackbox abstract
cellview.
Note: Interoperable pin constraint means pin constraints that are understood by Innovus,
Virtuoso and PVS.
Type: bool
Default: false
Edit: Yes
Reference: oa_push_pin_constraint

oa_quick_abstract_for_custom_pcells

Trim design shapes of custom PCells

Type: bool
Default: true
Edit: Yes

oa_silently_ignore_unsupported_vias

Whether read_db should issue messages about vias that are not supported in Innovus.
Type: bool
Default: false
Edit: Yes
Reference: oa_silently_ignore_unsupported_vias

oa_text_purpose

Specify the purpose name that will be used when text labels (add_text) are written.
Type: string
Default: drawing
Edit: Yes
Reference: oa_text_purpose

oa_tie_net

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tieHigh tieLow net names

Type: string
Default: ""
Edit: Yes
Reference: oa_tie_net

oa_update_mode

Whether to use (save/restore)OaDesign in update mode or not

Type: enum
Enum Values: false true auto
Default: false
Edit: Yes
Reference: oa_update_mode

oa_use_virtuoso_bindkey

Whether to use Virtuoso bind keys

Type: bool
Default: false
Edit: Yes
Reference: oa_use_virtuoso_bindkey

oa_use_virtuoso_color

Whether to use Virtuoso color and stipple

Type: bool
Default: false
Edit: Yes
Reference: oa_use_virtuoso_color

oa_view_sub_type

Subtype of view of the OA design

Type: enum
Enum Values: vce vxl none
Default: vxl
Edit: Yes
Reference: oa_view_sub_type

oa_write_mask_data_locked

Whether to save colored shapes with locked attribute

Type: bool
Default: false
Edit: Yes
Reference: oa_write_mask_data_locked

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oa_write_net_voltage

Whether to allow write_db to write voltage information to the oaBitNet's voltage attribute
Type: bool
Default: false
Edit: Yes
Reference: oa_write_net_voltage

oa_write_relative_path

Whether to save relative path in config file.

Type: bool
Default: true
Edit: Yes
Reference: oa_write_relative_path

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (root)
Default: ""
Edit: No

obj_types

object definitions
Type: obj(obj_type)*
Default: ""
Edit: No

opconds

Returns the information about the opconds in the design.

Type: obj(opcond)*
Default: ""
Edit: No

opt_add_always_on_feed_through_buffers

Activates adding Always On Feed Thru buffers

Type: bool
Default: false
Edit: Yes
Reference: opt_add_always_on_feed_through_buffers

opt_add_insts

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Enables adding of new instances

Type: bool
Default: true
Edit: Yes
Reference: opt_add_insts

opt_add_ports

Enables adding ports for optimal buffering

Type: bool
Default: true
Edit: Yes
Reference: opt_add_ports

opt_add_repeater_report_failure_reason

To enable printing detailed failure reason report file for addRepeaterByRule

Type: bool
Default: false
Edit: Yes
Reference: opt_add_repeater_report_failure_reason

opt_all_end_points

Enables the all end points optimization mode

Type: bool
Default: false
Edit: Yes
Reference: opt_all_end_points

opt_allow_only_cell_swapping

Forces the post_route optimization to perform only same-size Vth swapping for timing
improvements
Type: bool
Default: false
Edit: Yes
Reference: opt_allow_only_cell_swapping

opt_area_recovery

Enables area reclamation step

Type: enum
Enum Values: true false default
Default: default
Edit: Yes
Reference: opt_area_recovery

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opt_area_recovery_setup_target_slack

Specifies target slack value (in nano secs) for area and power reclaim during setup timing
optimization
Type: double
Default: 0.0
Edit: Yes
Reference: opt_area_recovery_setup_target_slack

opt_concatenate_default_and_user_prefixes

Enables combining default prefix for instances(nets) with the prefix specified by
opt_new_inst_prefix(opt_new_net_prefix)
Type: bool
Default: true
Edit: Yes
Reference: opt_concatenate_default_and_user_prefixes

opt_consider_routing_congestion

Enables routing congestion check at the post_route stage during optimization of setup, hold,
drv, & glitch. It also impacts post_cts hold fixing.
Type: enum
Enum Values: auto false true
Default: auto
Edit: Yes
Reference: opt_consider_routing_congestion

opt_constant_inputs

Force optimization of instances with constant inputs, even if it worsens objective gain
Type: bool
Default: false
Edit: Yes
Reference: opt_constant_inputs

opt_constant_nets

Enables optimization of constant nets

Type: bool
Default: true
Edit: Yes
Reference: opt_constant_nets

opt_delete_insts

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Enables instance deletion on all paths

Type: bool
Default: true
Edit: Yes
Reference: opt_delete_insts

opt_detail_drv_failure_reason

To enable printing detailed drv failure reason report file

Type: bool
Default: false
Edit: Yes
Reference: opt_detail_drv_failure_reason

opt_detail_drv_failure_reason_max_num_nets

Specify how many violating nets printed

Type: int
Default: 50
Edit: Yes
Reference: opt_detail_drv_failure_reason_max_num_nets

opt_down_size_insts

Enables instance downsizing

Type: bool
Default: true
Edit: Yes
Reference: opt_down_size_insts

opt_drv

Enables fixing max cap/max tran violations on constrained nets

Type: bool
Default: true
Edit: Yes
Reference: opt_drv

opt_drv_margin

Used for scaling max cap/max tran constraints

Type: double
Default: 0.0
Edit: Yes
Reference: opt_drv_margin

opt_drv_with_miller_cap

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Type: bool
Default: false
Edit: Yes
Reference: opt_drv_with_miller_cap

opt_enable_data_to_data_checks

enable library data to data checks during optimization for gigaopt

Type: enum
Enum Values: true false
Default: false
Edit: Yes
Reference: opt_enable_data_to_data_checks

opt_enable_restructure

Enables netlist restructuring

Type: bool
Default: true
Edit: Yes
Reference: opt_enable_restructure

opt_fix_fanout_load

Enables fixing fanOut load violations

Type: bool
Default: false
Edit: Yes
Reference: opt_fix_fanout_load

opt_flop_pins_report

print full hierarchical flop pins names for flops deleted in simplifyNetlist
Type: enum
Enum Values: false true
Default: false
Edit: Yes
Reference: opt_flop_pins_report

opt_flops_report

print full hierarchical flop names for flops deleted in simplifyNetlist

Type: enum
Enum Values: false true
Default: false
Edit: Yes
Reference: opt_flops_report

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opt_hier_add_antenna_cell

add antenna diode to interface load

Type: bool
Default: false
Edit: Yes
Reference: opt_hier_add_antenna_cell

opt_hier_opt_stage

Turn on default settings for hierarchical flows at different optimization stage.

Type: enum
Enum Values: pre_cts post_cts unset
Default: unset
Edit: Yes
Reference: opt_hier_opt_stage

opt_hier_trial_route_honor_read_only

trailRoute to honor partition or top read-only settings

Type: bool
Default: false
Edit: Yes
Reference: opt_hier_trial_route_honor_read_only

opt_high_effort_cells

Provide a list of cells to be used for high effort optimization. Dont-use and Dont-touch
constraints for these cells will be ignored for high effort optimization.
Type: string
Default: ""
Edit: Yes
Reference: opt_high_effort_cells

opt_hold_allow_overlap

Enables hold optimization to insert cells with overlaps when inadequate free space is
available. The placement will then be legalized before ECO routing.
Type: enum
Enum Values: auto false true
Default: auto
Edit: Yes
Reference: opt_hold_allow_overlap

opt_hold_allow_resize

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Enables the resizing capability inside hold optimization.

Type: enum
Enum Values: false true
Default: true
Edit: Yes
Reference: opt_hold_allow_resize

opt_hold_allow_setup_tns_degradation

Allows setup total negative slack to degrade during hold optimization.

Type: bool
Default: true
Edit: Yes
Reference: opt_hold_allow_setup_tns_degradation

opt_hold_cells

Provide a list of buffer & delay cells to be used for hold buffering. The dont_use constraints for
these cells will be ignored.
Type: string
Default: ""
Edit: Yes
Reference: opt_hold_cells

opt_hold_ignore_path_groups

Specifies path groups to be excluded in hold timing optimization

Type: string
Default: ""
Edit: Yes
Reference: opt_hold_ignore_path_groups

opt_hold_on_excluded_clock_nets

Do hold fixing on the excluded clock nets

Type: bool
Default: false
Edit: Yes
Reference: opt_hold_on_excluded_clock_nets

opt_hold_slack_threshold

Specifies target slack value (in nano secs) for hold timing optimization
Type: double
Default: -1000.0
Edit: Yes
Reference: opt_hold_slack_threshold

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opt_hold_target_slack

Specifies target slack value (in nano secs) for hold timing optimization
Type: double
Default: 0.0
Edit: Yes
Reference: opt_hold_target_slack

opt_honor_density_screen

Control density screen

Type: bool
Default: false
Edit: Yes
Reference: opt_honor_density_screen

opt_honor_fences

Specifies that the timing optimization takes fences constraints into account. Placement of cells
will be legalized within each fence.
Type: bool
Default: false
Edit: Yes
Reference: opt_honor_fences

opt_leakage_to_dynamic_ratio

relative effort for leakage and dynamic power optimization in the range [0.0 - 1.0]
Type: double
Default: 1.0
Edit: Yes
Reference: opt_leakage_to_dynamic_ratio

opt_max_density

Specifies maximum area utilization

Type: double
Default: 0.95
Edit: Yes
Reference: opt_max_density

opt_max_length

Enables max length constraints in opt_design

Type: double
Default: -1.0
Edit: Yes
Reference: opt_max_length

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opt_move_insts

Enables moving instances while fixing setup violations

Type: bool
Default: true
Edit: Yes
Reference: opt_move_insts

opt_multi_bit_flop_ignore_sdc

ignore sdc check when do flop merge and split

Type: bool
Default: true
Edit: Yes
Reference: opt_multi_bit_flop_ignore_sdc

opt_multi_bit_flop_merge_timing_effort

Timing effort level for MBFF merging

Type: enum
Enum Values: low medium high
Default: medium
Edit: Yes
Reference: opt_multi_bit_flop_merge_timing_effort

opt_multi_bit_flop_opt

specifies multi bit flop merge/split opt

Type: enum
Enum Values: false true mergeOnly splitOnly
Default: splitOnly
Edit: Yes
Reference: opt_multi_bit_flop_opt

opt_multi_bit_flop_split_report_failure_reason

To enable printing split failure reasons

Type: bool
Default: true
Edit: Yes
Reference: opt_multi_bit_flop_split_report_failure_reason

opt_multi_bit_flop_split_timing_effort

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Timing effort level for MBFF splitting

Type: enum
Enum Values: low medium high
Default: low
Edit: Yes
Reference: opt_multi_bit_flop_split_timing_effort

opt_multibit_critical_path

Support using MBFF on critical path during optimization.

Type: bool
Default: false
Edit: Yes

opt_new_inst_prefix

Prefix string for name of new instances

Type: string
Default: ""
Edit: Yes
Reference: opt_new_inst_prefix

opt_new_net_prefix

Prefix string for name of new nets

Type: string
Default: ""
Edit: Yes
Reference: opt_new_net_prefix

opt_pin_swapping

Enables pin swapping

Type: bool
Default: true
Edit: Yes
Reference: opt_pin_swapping

opt_post_route_allow_overlap

Enables post_route optimization to insert cells with overlaps when inadequate free space is
available. The placement will then be legalized before ECO routing.
Type: bool
Default: true
Edit: Yes
Reference: opt_post_route_allow_overlap

opt_post_route_area_reclaim

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To enable area reclaim in post_route optimization

Type: enum
Enum Values: none setup_aware hold_and_setup_aware
Default: none
Edit: Yes
Reference: opt_post_route_area_reclaim

opt_post_route_art_flow

Enables optimizing the top-level interface logic for a hierarchical floorplan

Type: bool
Default: false
Edit: Yes
Reference: opt_post_route_art_flow

opt_post_route_check_antenna_rules

Allows optimization to check/ignore antenna rules in lefsafe swaps

Type: bool
Default: true
Edit: Yes
Reference: opt_post_route_check_antenna_rules

opt_post_route_drv_recovery

Enables post_route drv recovery in gigaopt.

Type: enum
Enum Values: auto true false
Default: auto
Edit: Yes
Reference: opt_post_route_drv_recovery

opt_post_route_fix_clock_drv

enables DRV fixing on clock net

Type: bool
Default: true
Edit: Yes
Reference: opt_post_route_fix_clock_drv

opt_post_route_fix_glitch

Enables glitch fixing in AAE flow

Type: bool
Default: true
Edit: Yes
Reference: opt_post_route_fix_glitch

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opt_post_route_fix_si_transitions

Enables sislew fixing in AAE flow

Type: bool
Default: false
Edit: Yes
Reference: opt_post_route_fix_si_transitions

opt_post_route_hold_recovery

Type: enum
Enum Values: false true auto
Default: false
Edit: Yes
Reference: opt_post_route_hold_recovery

opt_post_route_report_si_transitions

report sislew violations

Type: bool
Default: false
Edit: Yes
Reference: opt_post_route_report_si_transitions

opt_post_route_setup_recovery

Enables post_route SI setup timing recovery in gigaopt.

Type: enum
Enum Values: auto true false
Default: auto
Edit: Yes
Reference: opt_post_route_setup_recovery

opt_power_effort

Effort level for power aware mode in optimization

Type: enum
Enum Values: none low high
Default: none
Edit: Yes
Reference: opt_power_effort

opt_pre_route_ndr_aware

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Provide a list of NDR names that will be used NDR-based optimization

Type: string
Default: ""
Edit: Yes
Reference: opt_pre_route_ndr_aware

opt_preserve_all_sequential

Preserve sequential element during the simplify netlist optimization step

Type: bool
Default: false
Edit: Yes
Reference: opt_preserve_all_sequential

opt_preserve_hpin_function

Enables preserving logical functions at hierarchical ports

Type: bool
Default: false
Edit: Yes
Reference: opt_preserve_hpin_function

opt_remove_redundant_insts

Enables simplifying the netlist during optimization

Type: bool
Default: true
Edit: Yes
Reference: opt_remove_redundant_insts

opt_resize_flip_flops

Enables FF resizing
Type: bool
Default: true
Edit: Yes
Reference: opt_resize_flip_flops

opt_resize_level_shifter_and_iso_insts

Enables resizing of shifters and isolation instances

Type: bool
Default: false
Edit: Yes
Reference: opt_resize_level_shifter_and_iso_insts

opt_resize_power_switch_insts

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Enables resizing of power switch instances during optimization

Type: bool
Default: false
Edit: Yes
Reference: opt_resize_power_switch_insts

opt_sequential_genus_restructure_report_failure_reason

To enable printing SeqCRR failure reasons

Type: bool
Default: false
Edit: Yes
Reference: opt_sequential_genus_restructure_report_failure_reason

opt_setup_target_slack

Specifies target slack value (in nano secs) for setup timing optimization
Type: double
Default: 0.0
Edit: Yes
Reference: opt_setup_target_slack

opt_signoff_add_inst

Specifies whether timing optimizer is allowed to add buffer/delay/inverter cell instances.

Type: bool
Default: true
Edit: Yes
Reference: opt_signoff_add_inst

opt_signoff_add_load

Specifies whether Hold optimizer is allowed to add dummy cell instances

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_add_load

opt_signoff_allow_skewing

useful skew based setup opt

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_allow_skewing

opt_signoff_along_route_buffering

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Allow buffer/inverter to be inserted along the route and not only at driver or sink terms.
Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_along_route_buffering

opt_signoff_buffer_cell_list

Specifies a list of buffer/delay cells that can be used for DRV and Hold optimizers, regardless
of whether those cells have a "dont_use" attribute.
Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_buffer_cell_list

opt_signoff_check_drv_from_hold_views

consider DRVs from hold views

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_check_drv_from_hold_views

opt_signoff_check_type

Check type for path based analysis.

Type: enum
Enum Values: early late both
Default: both
Edit: Yes
Reference: opt_signoff_check_type

opt_signoff_clock_cell_list

Restricts the list of buffers/inverter/gating cells that are allowed to be used by ECO on the
clock tree.
Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_clock_cell_list

opt_signoff_clock_max_level

max level allowed for clock tree

Type: int
Default: 0
Edit: Yes
Reference: opt_signoff_clock_max_level

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opt_signoff_delete_inst

delete buffer for optimization

Type: bool
Default: true
Edit: Yes
Reference: opt_signoff_delete_inst

opt_signoff_disable_geometry_checks

Performs Vth swapping without checking pins geometry.

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_disable_geometry_checks

opt_signoff_drv_margin

Specifies a margin value by which ratio the drv check would be relaxed or tightened
Type: double
Default: 0.0
Edit: Yes
Reference: opt_signoff_drv_margin

opt_signoff_eco_file_prefix

Specifies the prefix name for the ECO files generated.

Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_eco_file_prefix

opt_signoff_fix_clock_drv

fix max_cap/max_tran violations on clock nets

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_fix_clock_drv

opt_signoff_fix_data_drv

fix max_cap/max_tran violations on data nets

Type: bool
Default: true
Edit: Yes
Reference: opt_signoff_fix_data_drv

opt_signoff_fix_glitch

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fix nets with glitch

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_fix_glitch

opt_signoff_fix_hold_allow_setup_optimization

simultaneous hold and setup fixing

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_fix_hold_allow_setup_optimization

opt_signoff_fix_hold_allow_setup_tns_degrade

When active, the Setup Total Negative Slack can be degraded during Hold time violations
fixing while still maintaining the Setup Worst Negative Slack in every Setup active views.
Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_fix_hold_allow_setup_tns_degrade

opt_signoff_fix_hold_with_margin

Specifies a slack margin value in nanoseconds for Hold time violations fixing. The purpose is
to overfix any Hold violations by the amount of the margin value. This margin is not applied on
nets that are already meeting the Hold target slack.
Type: double
Default: 0.0
Edit: Yes
Reference: opt_signoff_fix_hold_with_margin

opt_signoff_fix_ir_drop

fix ir-drop hotspots

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_fix_ir_drop

opt_signoff_fix_max_cap

Enables max_cap violations fixing during DRV optimization.

Type: bool
Default: true
Edit: Yes
Reference: opt_signoff_fix_max_cap

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opt_signoff_fix_max_transition

Enables max_tran violations fixing during DRV optimization.

Type: bool
Default: true
Edit: Yes
Reference: opt_signoff_fix_max_transition

opt_signoff_fix_si_slew

Performs SI Slew fixing during DRV fixing using resizing and buffering techniques.
Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_fix_si_slew

opt_signoff_fix_xtalk

Reduces the crosstalk on the net that violates the thresholds set by the user.
Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_fix_xtalk

opt_signoff_hold_target_slack

Specifies a target slack value in nanoseconds for hold timing optimize

Type: double
Default: 0.0
Edit: Yes
Reference: opt_signoff_hold_target_slack

opt_signoff_hold_xtalk_delta_threshold

Crosstalk delta delay threshold for selecting nets in hold timing views when running Xtalk
fixing.
Type: double
Default: 0.3
Edit: Yes
Reference: opt_signoff_hold_xtalk_delta_threshold

opt_signoff_hold_xtalk_slack_threshold

Slack threshold for selecting nets in hold timing views when running Xtalk fixing.
Type: double
Default: 1000.0
Edit: Yes
Reference: opt_signoff_hold_xtalk_slack_threshold

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opt_signoff_ignore_drv_checks

Ignores DRV checks during timing/area/power optimization.

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_ignore_drv_checks

opt_signoff_keep_tmp_files

To keep all the temporary files generated by D-MMMC and Tempus clients for debugging
purposes.
Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_keep_tmp_files

opt_signoff_legal_only

Enables/disables legal location checks during resizing and buffering

Type: bool
Default: true
Edit: Yes
Reference: opt_signoff_legal_only

opt_signoff_load_cell_list

Specifies the list of load cells

Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_load_cell_list

opt_signoff_max_cap_margin

Specifies the ratio by which the max_cap check would be relaxed or tightened
Type: double
Default: 0.0
Edit: Yes
Reference: opt_signoff_max_cap_margin

opt_signoff_max_paths

Specifies how many paths are getting retimed for ECO DB generation in PBA mode.
Type: int
Default: -1
Edit: Yes
Reference: opt_signoff_max_paths

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opt_signoff_max_runtime

If set to a positive value, would restrict the command runtime by that value, in minutes.
Type: int
Default: 0
Edit: Yes
Reference: opt_signoff_max_runtime

opt_signoff_max_slack

Specifies the maximum GBA slack value to be used when selecting paths to be retimed for
ECO DB generation in PBA mode.
Type: double
Default: 0.0
Edit: Yes
Reference: opt_signoff_max_slack

opt_signoff_max_transition_margin

Specifies the ratio by which the max_tran check would be relaxed or tightened
Type: double
Default: 0.0
Edit: Yes
Reference: opt_signoff_max_transition_margin

opt_signoff_num_report_paths

Number of paths printed after signoff timing analysis per view

Type: int
Default: 50
Edit: Yes
Reference: opt_signoff_num_report_paths

opt_signoff_nworst

Specifies the number of paths to be retimed per endpoints for ECO DB generation in PBA
mode.
Type: int
Default: -1
Edit: Yes
Reference: opt_signoff_nworst

opt_signoff_optimize_core_only

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Enables the tool to optimize timing or recover area/power only on register to register paths.
Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_optimize_core_only

opt_signoff_optimize_replicated_modules

Allows the tool to perform timing optimization inside replicated hierarchies while generating
only one ECO file per sets of clones. The cell name of the replicated hierarchies have to be
listed in a file pointed by the opt_signoff_partition_list_file option.
Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_optimize_replicated_modules

opt_signoff_optimize_sequential_cells

Specifies whether the timing/area/power optimizer is allowed to optimize sequential cells.

Type: bool
Default: true
Edit: Yes
Reference: opt_signoff_optimize_sequential_cells

opt_signoff_partition_list_file

File containing list of partitions in the design

Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_partition_list_file

opt_signoff_pba_eco_route

Enables PBA timing to be passed to ecoRoute for higher timing driven routing accuracy
Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_pba_eco_route

opt_signoff_pba_effort

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When enabling "high" effort mode, all the optimization engines will perform more aggressive
timing closure or area/power recovery with respect to PBA timing and the expectation is to get
better quality of results.
Type: enum
Enum Values: medium high
Default: medium
Edit: Yes
Reference: opt_signoff_pba_effort

opt_signoff_post_mask

enable post mask ECO mode

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_post_mask

opt_signoff_post_sta_tcl

File containing the TCL code that will be executed immediately after signoff timing analysis
per view
Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_post_sta_tcl

opt_signoff_power_aware

power awareness in all optimizers and transforms

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_power_aware

opt_signoff_power_opt_focus

focus for power optimization

Type: enum
Enum Values: total leakage dynamic leakageOnly dynamicOnly
Default: total
Edit: Yes
Reference: opt_signoff_power_opt_focus

opt_signoff_pre_sta_tcl

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File containing the TCL code that will be executed immediately prior to signoff timing analysis
per view
Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_pre_sta_tcl

opt_signoff_prefix

Specifies the prefix to be assigned to the new instances inserted.

Type: string
Default: ESO
Edit: Yes
Reference: opt_signoff_prefix

opt_signoff_preserve_filler

To enable preserve and restore of fillers

Type: bool
Default: true
Edit: Yes
Reference: opt_signoff_preserve_filler

opt_signoff_read_eco_opt_db

Path of directory where ECO Timing DB files must be loaded from.

Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_read_eco_opt_db

opt_signoff_read_irdrop_db

Path of directory where command debug_irdrop generated IR drop DB files are kept
Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_read_irdrop_db

opt_signoff_resize_inst

enable/disable resizing transform

Type: bool
Default: true
Edit: Yes
Reference: opt_signoff_resize_inst

opt_signoff_retime

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To enable PBA-based timing report and optimization for of all optimizers.

Type: enum
Enum Values: none aocv path_slew_propagation aocv_path_slew_propagation
Default: none
Edit: Yes
Reference: opt_signoff_retime

opt_signoff_routing_congestion_aware

Check routing congestion before adding buffers

Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_routing_congestion_aware

opt_signoff_select_drv_net_file

list of nets to be optimized during DRV fixing

Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_select_drv_net_file

opt_signoff_select_hold_endpoints

select end points for hold fixing

Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_select_hold_endpoints

opt_signoff_select_setup_endpoints

select end points for setup fixing

Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_select_setup_endpoints

opt_signoff_set_hold_endpoints_margin

specify end point specific margin for hold fixing

Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_set_hold_endpoints_margin

opt_signoff_set_setup_endpoints_margin

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specify end point specific margin for setup fixing

Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_set_setup_endpoints_margin

opt_signoff_setup_recovery

Forces Setup fixing to perform Setup timing recovery by using Vth swapping only. Useful
feature to recover timing degradation after large ECO change during Power optimization.
Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_setup_recovery

opt_signoff_setup_target_slack

Specifies a target slack value in nanoseconds for setup timing optimize

Type: double
Default: 0.0
Edit: Yes
Reference: opt_signoff_setup_target_slack

opt_signoff_setup_xtalk_delta_threshold

Crosstalk delta delay threshold for selecting nets in setup timing views when running Xtalk
fixing.
Type: double
Default: 0.3
Edit: Yes
Reference: opt_signoff_setup_xtalk_delta_threshold

opt_signoff_setup_xtalk_slack_threshold

Slack threshold for selecting nets in setup timing views when running Xtalk fixing.
Type: double
Default: 1000.0
Edit: Yes
Reference: opt_signoff_setup_xtalk_slack_threshold

opt_signoff_skip_drv_net_file

list of nets to be excluded during DRV fixing

Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_skip_drv_net_file

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opt_signoff_swap_inst

Enables/disables VT swap resizing. Setup/leakage optimizers do not honor this option and
always perform VT-swapping.
Type: bool
Default: true
Edit: Yes
Reference: opt_signoff_swap_inst

opt_signoff_use_gate_array_filler_list

enable post mask mode to use cells from the specified list at GA filler sites
Type: string
Default: ""
Edit: Yes
Reference: opt_signoff_use_gate_array_filler_list

opt_signoff_verbose

Specifies whether the command should output log file reporting with verbosity or not.
Type: bool
Default: false
Edit: Yes
Reference: opt_signoff_verbose

opt_signoff_write_eco_opt_db

Path of directory where ECO Timing DB files are saved.

Type: string
Default: ecoTimingDB
Edit: Yes
Reference: opt_signoff_write_eco_opt_db

opt_skew

Enables triggering the skew_clock command from within opt_design

Type: bool
Default: true
Edit: Yes
Reference: opt_skew

opt_skew_ccopt

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Effort for useful skew optimization within ccopt_design

Type: enum
Enum Values: none standard extreme
Default: standard
Edit: Yes
Reference: opt_skew_ccopt

opt_skew_delay_pre_cts

delaying mode in pre_cts

Type: bool
Default: true
Edit: Yes
Reference: opt_skew_delay_pre_cts

opt_skew_macro_only

skew hard blocks

Type: bool
Default: false
Edit: Yes
Reference: opt_skew_macro_only

opt_skew_max_allowed_delay

max allowed skewing delay, unit is 'ns'

Type: double
Default: 1.0
Edit: Yes
Reference: opt_skew_max_allowed_delay

opt_skew_min_allowed_delay

min allowed skewing delay, unit is 'ns'

Type: double
Default: 0.0
Edit: Yes
Reference: opt_skew_min_allowed_delay

opt_skew_no_boundary

consider boundary sequential elements

Type: bool
Default: false
Edit: Yes
Reference: opt_skew_no_boundary

opt_skew_post_route

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Enables useful skew optimization during post_route timing optimization.

Type: bool
Default: true
Edit: Yes
Reference: opt_skew_post_route

opt_skew_pre_cts

Enables useful skew optimization during pre_cts timing optimization.

Type: bool
Default: true
Edit: Yes
Reference: opt_skew_pre_cts

opt_target_based_opt_file

Target based opt input file

Type: string
Default: ""
Edit: Yes
Reference: opt_target_based_opt_file

opt_target_based_opt_file_only

Use data from target based opt file for optimization

Type: enum
Enum Values: false true
Default: true
Edit: Yes
Reference: opt_target_based_opt_file_only

opt_target_based_opt_hold_file

Target based opt input file for hold

Type: string
Default: ""
Edit: Yes
Reference: opt_target_based_opt_hold_file

opt_tied_inputs

Force optimization of instances with inputs tied together, even if it worsens objective gain
Type: bool
Default: false
Edit: Yes
Reference: opt_tied_inputs

opt_time_design_compress_reports

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save reports in compressed format

Type: bool
Default: true
Edit: Yes
Reference: opt_time_design_compress_reports

opt_time_design_expanded_view

To report expanded views in time_design

Type: bool
Default: false
Edit: Yes
Reference: opt_time_design_expanded_view

opt_time_design_num_paths

Report specified number of paths in time_design

Type: int
Default: 50
Edit: Yes
Reference: opt_time_design_num_paths

opt_time_design_report_net

To report net delays in time_design

Type: bool
Default: true
Edit: Yes
Reference: opt_time_design_report_net

opt_unfix_clock_insts

Enables unfixing clock instances flow

Type: bool
Default: true
Edit: Yes
Reference: opt_unfix_clock_insts

opt_verbose

Enables verbose information logging

Type: bool
Default: false
Edit: Yes
Reference: opt_verbose

package_objects

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Short-cut for [get_db current_design .package_objects]

Type: obj(package_object)*
Default: ""
Edit: No

partition_floorplan_export

Export setting
Type: enum
Enum Values: macro special_route pin_constraint
Default: special_route
Edit: Yes
Reference: partition_floorplan_export

partition_floorplan_import

Import setting
Type: enum
Enum Values: macro special_route pin_constraint
Default: ""
Edit: Yes
Reference: partition_floorplan_import

partitions

Short-cut for [get_db current_design .partitions]

Type: obj(partition)*
Default: ""
Edit: No

pg_base_pins

All the base_pins in all the base_cells.

Type: obj(pg_base_pin)*
Default: ""
Edit: No

pg_nets

Short-cut for [get_db current_design .pg_nets]. List of power/ground nets in the design. This
include physical-only PG nets, and Verilog supply0/supply1 nets. Note that Verilog nets
assigned to 1'b0/1'b1 are returned by the nets attribute, not the pg_nets attribute.
Type: obj(net)*
Default: ""
Edit: No

pg_pins

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Short-cut for [get_db current_design .pg_pins].

Type: obj(pg_pin)*
Default: ""
Edit: No

phys_insts

Short-cut for [get_db current_design .phys_insts]

Type: obj(inst)*
Default: ""
Edit: No

pin_blockages

Short-cut for [get_db current_design .pin_blockages]

Type: obj(pin_blockage)*
Default: ""
Edit: No

pin_groups

Short-cut for [get_db current_design .pin_groups]

Type: obj(pin_group)*
Default: ""
Edit: No

pin_guides

Short-cut for [get_db current_design .pin_guides]

Type: obj(pin_guide)*
Default: ""
Edit: No

pins

Short-cut for [get_db current_design .pins]

Type: obj(pin)*
Default: ""
Edit: No

place_blockages

Short-cut for [get_db current_design .place_blockages]

Type: obj(place_blockage)*
Default: ""
Edit: No

place_cell_edge_spacing

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List of cell edge-type spacing values from LEF CELLEDGESPACINGTABLE or OA techfile

that affects the placer. It specifies the min-spacing between different edge-types of std-cells, in
a list format: {cell_edge_type1 cell_edge_type2 spacing}. The edge-type names match the
base_cell's right_edge_type and left_edge_type attribute values.
Type: string
Default: ""
Edit: No
Reference: place_cell_edge_spacing

place_design_floorplan_mode

run placement in floorplan mode

Type: bool
Default: false
Edit: Yes
Reference: place_design_floorplan_mode

place_design_refine_macro

specify whether to run refine_macro_place after place_design -concurrent_macro

Type: bool
Default: false
Edit: Yes
Reference: place_design_refine_macro

place_design_refine_place

if set to false, calls to refinePlace from other apps (such as place_opt_design, opt_design) will
not run refinePlace
Type: bool
Default: true
Edit: Yes
Reference: place_design_refine_place

place_detail_activity_power_driven

Type: bool
Default: false
Edit: Yes
Reference: place_detail_activity_power_driven

place_detail_allow_border_pin_abut

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allow instance abut with its neighbors when it has pins near by the cell boundary
Type: bool
Default: false
Edit: Yes
Reference: place_detail_allow_border_pin_abut

place_detail_check_cut_spacing

Check via cut spacing during DRC checking

Type: bool
Default: false
Edit: Yes
Reference: place_detail_check_cut_spacing

place_detail_check_inst_space_group

check inst space group

Type: bool
Default: false
Edit: Yes
Reference: place_detail_check_inst_space_group

place_detail_check_route

do DRV checks against FIXED wires during legalization, along with preroutes
Type: bool
Default: false
Edit: Yes
Reference: place_detail_check_route

place_detail_color_aware_legal

enable adjacent cell color conflict check in legalization

Type: bool
Default: false
Edit: Yes
Reference: place_detail_color_aware_legal

place_detail_context_aware_legal

specify the types of cell context rules the placer needs to honor. The argument values
[optional, required, user ignore_soft] can be used separately or combined, but they are
exclusive to all | none (default=all)
Type: enum
Enum Values: none all optional required user ignore_soft
Default: all
Edit: Yes
Reference: place_detail_context_aware_legal

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place_detail_eco_max_distance

specify max distance (in micron) for refinePlace ECO mode

Type: double
Default: 0.0
Edit: Yes
Reference: place_detail_eco_max_distance

place_detail_eco_priority_insts

select instance priority for refinePlace ECO mode

Type: enum
Enum Values: placed fixed eco
Default: placed
Edit: Yes
Reference: place_detail_eco_priority_insts

place_detail_fixed_shifter

mark shifters FIXED once placed

Type: bool
Default: false
Edit: Yes
Reference: place_detail_fixed_shifter

place_detail_honor_inst_pad

honor padding from set_inst_padding in detail placement

Type: bool
Default: false
Edit: Yes
Reference: place_detail_honor_inst_pad

place_detail_io_pin_blockage

ioPins from top-level are treated as pre-routes during DRV checks in legalization
Type: bool
Default: false
Edit: Yes
Reference: place_detail_io_pin_blockage

place_detail_iraware_max_drive_strength

Type: double
Default: 0.0
Edit: Yes
Reference: place_detail_iraware_max_drive_strength

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place_detail_irdrop_aware_effort

selects which IR drop optimization effort level to use during refinePlace

Type: enum
Enum Values: none low medium high
Default: none
Edit: Yes
Reference: place_detail_irdrop_aware_effort

place_detail_irdrop_aware_timing_effort

selects which timing effort level to use during refinePlace

Type: enum
Enum Values: none standard high
Default: high
Edit: Yes
Reference: place_detail_irdrop_aware_timing_effort

place_detail_irdrop_region_number

value for debug_irdrop -nregion in native API

Type: int
Default: 100
Edit: Yes
Reference: place_detail_irdrop_region_number

place_detail_legalization_inst_gap

minimum gap between instances (unit sites)

Type: int
Default: 0
Edit: Yes
Reference: place_detail_legalization_inst_gap

place_detail_m3_stripe_push_down

Width threshold in site-units for 'virtual' push-down of M3 stripe to M2 for M1 pin-access. Value
of 0 means all M3 stripes will be pushed-down.
Type: int
Default: -1
Edit: Yes
Reference: place_detail_m3_stripe_push_down

place_detail_m3_stripe_shrink

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Shrink the virtual M2 stripe (see spgM3StripePushDown) by given total site units, splitting
value to each side, starting on left. e.g. value of 1 shrinks by 1 site on left, 2 shrinks by 1 site
on each side, value of 3 shrinks 2 sites on left and 1 on right.
Type: int
Default: 0
Edit: Yes
Reference: place_detail_m3_stripe_shrink

place_detail_max_shifter_column_depth

maximum distance from vertical power domain boundary that a shifter can be placed
Type: double
Default: 9999.0
Edit: Yes
Reference: place_detail_max_shifter_column_depth

place_detail_max_shifter_depth

maximum distance from a horizontal or vertical power domain boundary that a shifter can be
placed
Type: double
Default: 9999.0
Edit: Yes
Reference: place_detail_max_shifter_depth

place_detail_max_shifter_row_depth

maximum distance from a horizontal power domain bounary that a shifter can be placed
Type: double
Default: 9999.0
Edit: Yes
Reference: place_detail_max_shifter_row_depth

place_detail_no_filler_without_implant

there is no cell which has no implant obs

Type: bool
Default: false
Edit: Yes
Reference: place_detail_no_filler_without_implant

place_detail_pad_fixed_insts

honor cell-padding for FIXED instances in refinePlace

Type: bool
Default: false
Edit: Yes
Reference: place_detail_pad_fixed_insts

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place_detail_pad_physical_cells

padding overlap with physcial cells would be honored

Type: bool
Default: false
Edit: Yes
Reference: place_detail_pad_physical_cells

place_detail_preroute_as_obs

specify layers on which preroute are taken as OBS

Type: string
Default: ""
Edit: Yes
Reference: place_detail_preroute_as_obs

place_detail_preserve_routing

do not delete routed wires during refinePlace

Type: bool
Default: true
Edit: Yes
Reference: place_detail_preserve_routing

place_detail_remove_affected_routing

delete only wires whose nets were touched due to moved cells
Type: bool
Default: false
Edit: Yes
Reference: place_detail_remove_affected_routing

place_detail_sdp_alignment_in_refine

call sdp alignment in every refinePlace

Type: bool
Default: false
Edit: Yes
Reference: place_detail_sdp_alignment_in_refine

place_detail_swap_eeq_cells

replace master cells by its EEQ cell during legalization, to keep max-dist move low
Type: bool
Default: false
Edit: Yes
Reference: place_detail_swap_eeq_cells

place_detail_use_check_drc

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Use FGC based DRC engine in legalization

Type: bool
Default: false
Edit: Yes
Reference: place_detail_use_check_drc

place_detail_use_diffusion_transition_fill

insert OD transition filler in 1X gap

Type: bool
Default: false
Edit: Yes
Reference: place_detail_use_diffusion_transition_fill

place_detail_use_gate_array_filler_groups

filler cell insts will only be replaced by logic insts that belong to same GA groups.
Type: bool
Default: false
Edit: Yes
Reference: place_detail_use_gate_array_filler_groups

place_detail_use_no_diffusion_one_site_filler

override -fillerGapMinGap to 0 and all source-drain spacing rule to 1 site during legalizing
Type: bool
Default: false
Edit: Yes
Reference: place_detail_use_no_diffusion_one_site_filler

place_detail_wire_length_opt_effort

selects which wire-length optimization effort level to use during refinePlace

Type: enum
Enum Values: none medium high
Default: medium
Edit: Yes
Reference: place_detail_wire_length_opt_effort

place_global_activity_power_driven

identifies and constrains power-critical nets to reduce switching power

Type: enum
Enum Values: false true
Default: false
Edit: Yes
Reference: place_global_activity_power_driven

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place_global_activity_power_driven_effort

-place_global_activity_power_driven_effort mode
Type: enum
Enum Values: standard high
Default: standard
Edit: Yes
Reference: place_global_activity_power_driven_effort

place_global_align_macro

enable mixed-placer to align nearby same-size macros during global placement

Type: bool
Default: false
Edit: Yes
Reference: place_global_align_macro

place_global_allow_3d_stack

Type: bool
Default: false
Edit: Yes
Reference: place_global_allow_3d_stack

place_global_auto_blockage_in_channel

Placement will (temporarily) block channels between areas with limited routing capacity
Type: enum
Enum Values: none soft partial
Default: partial
Edit: Yes
Reference: place_global_auto_blockage_in_channel

place_global_clock_gate_aware

find better placement for clock gating elements towards the center of gravity for fanout
Type: bool
Default: true
Edit: Yes
Reference: place_global_clock_gate_aware

place_global_clock_power_driven

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clock power driven

Type: bool
Default: true
Edit: Yes
Reference: place_global_clock_power_driven

place_global_clock_power_driven_effort

-place_global_clock_power_driven_effort mode
Type: enum
Enum Values: low standard high
Default: low
Edit: Yes
Reference: place_global_clock_power_driven_effort

place_global_cong_effort

level of effort for congestion driven global placer

Type: enum
Enum Values: low medium high extreme auto
Default: auto
Edit: Yes
Reference: place_global_cong_effort

place_global_cpg_effort

level of effort for CPG

Type: enum
Enum Values: low medium high
Default: low
Edit: Yes
Reference: place_global_cpg_effort

place_global_cpg_file

Type: string
Default: ""
Edit: Yes
Reference: place_global_cpg_file

place_global_enable_distributed_place

enable distributed placement platform

Type: bool
Default: false
Edit: Yes
Reference: place_global_enable_distributed_place

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place_global_ignore_scan

ignore scan net during placement

Type: enum
Enum Values: true 1 false 0 auto
Default: true
Edit: Yes
Reference: place_global_ignore_scan

place_global_ignore_spare

discard spare cell connections during global placement

Type: bool
Default: false
Edit: Yes
Reference: place_global_ignore_spare

place_global_max_density

placement strives to not let density exceed given value, in any part of design
Type: double
Default: -1.0
Edit: Yes
Reference: place_global_max_density

place_global_module_aware_spare

Spare insts are placed randomly along with the containing module's insts
Type: bool
Default: false
Edit: Yes
Reference: place_global_module_aware_spare

place_global_module_padding

define the padding factor for the given module to reduce the local density and congestion
Type: string
Default: ""
Edit: Yes
Reference: place_global_module_padding

place_global_place_io_pins

place IO Pins concurrently with std.cell placement, and do layer assignment

Type: bool
Default: false
Edit: Yes
Reference: place_global_place_io_pins

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place_global_reorder_scan

turn on reorder scan during placement

Type: bool
Default: true
Edit: Yes
Reference: place_global_reorder_scan

place_global_sdp_alignment

ensure SDP alignment during placement

Type: bool
Default: false
Edit: Yes
Reference: place_global_sdp_alignment

place_global_sdp_place

honor SDP groups and places SDP cells closely during placement
Type: enum
Enum Values: false true
Default: false
Edit: Yes
Reference: place_global_sdp_place

place_global_soft_guide_strength

level of effort for user definded softGuide for global placer

Type: enum
Enum Values: low medium high
Default: low
Edit: Yes
Reference: place_global_soft_guide_strength

place_global_timing_effort

level of effort for timing driven global placer

Type: enum
Enum Values: medium high
Default: medium
Edit: Yes
Reference: place_global_timing_effort

place_global_uniform_density

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enable even cell distribution for designs with less than 70% utilization
Type: enum
Enum Values: false true
Default: false
Edit: Yes
Reference: place_global_uniform_density

place_hard_fence

honor fence and region constraints in refinePlace

Type: bool
Default: true
Edit: Yes
Reference: place_hard_fence

place_opt_post_place_tcl

a tcl script to be sourced after initial placement and before preCTS optimization in
place_opt_design
Type: string
Default: ""
Edit: Yes
Reference: place_opt_post_place_tcl

place_opt_run_global_place

place opt run global place

Type: enum
Enum Values: none seed full
Default: full
Edit: Yes
Reference: place_opt_run_global_place

place_sdp_clock_location

ICG cell location

Type: string
Default: center
Edit: Yes
Reference: place_sdp_clock_location

place_sdp_disable_extend_core

disable the extended core flag

Type: bool
Default: true
Edit: Yes
Reference: place_sdp_disable_extend_core

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place_sdp_fix_overlap_column_cell

-resolve_overlap_column_cell {cell...}. Use empty string to reset the value

Type: string
Default: ""
Edit: Yes
Reference: place_sdp_fix_overlap_column_cell

place_sdp_fix_overlap_row_cell

-resolve_overlap_row_cell {cell...}. Use empty string to reset the value

Type: string
Default: ""
Edit: Yes
Reference: place_sdp_fix_overlap_row_cell

place_sdp_flow

Specifies the flow generation.

Type: enum
Enum Values: default 2G
Default: default
Edit: Yes
Reference: place_sdp_flow

place_sdp_honor_dont_use

honor dont_use on base_cells during EEQ swapping in SDP legalization

Type: bool
Default: false
Edit: Yes
Reference: place_sdp_honor_dont_use

place_sdp_honor_orient

honor user specified orient during legalization

Type: bool
Default: false
Edit: Yes
Reference: place_sdp_honor_orient

place_sdp_legalization

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Specify fixed corner of sdp box during legalizing sdp instance

Type: enum
Enum Values: NONE SW SE NW NE AUTO
Default: NONE
Edit: Yes
Reference: place_sdp_legalization

place_sdp_legalization_effort

Specifies the legalization effort in placing SDP groups

Type: enum
Enum Values: low medium high
Default: low
Edit: Yes
Reference: place_sdp_legalization_effort

place_sdp_max_move_action

-max_move_action {leave_overlap | delete_sdp_group | create_inst_group}

Type: enum
Enum Values: leave_overlap delete_sdp_group create_inst_group
Default: create_inst_group
Edit: Yes
Reference: place_sdp_max_move_action

place_sdp_max_move_distance

max sdp group move distance, default is half perimeter of the core box
Type: double
Default: 0.0
Edit: Yes
Reference: place_sdp_max_move_distance

place_sdp_num_column

number of column for sdp group

Type: int
Default: 2
Edit: Yes
Reference: place_sdp_num_column

place_sdp_place_report

Output a detailed sdp placement data. Use empty string to reset to no output
Type: string
Default: ""
Edit: Yes
Reference: place_sdp_place_report

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place_sdp_pre_fixed_cells_blockage_direction

Specify the direction when covering preplaced std cells using placement blockages
Type: enum
Enum Values: NONE X Y
Default: NONE
Edit: Yes
Reference: place_sdp_pre_fixed_cells_blockage_direction

place_spare_update_timing_graph

update timing graph during place_spare_modules

Type: bool
Default: true
Edit: Yes
Reference: place_spare_update_timing_graph

plan_design_domain

Format: -domain {{PD1 <value1> net1} {PD2 <value2> net2}..}

Type: string
Default: ""
Edit: Yes
Reference: plan_design_domain

plan_design_rail_model

Seletc rail model: virtual/existing.

Type: enum
Enum Values: virtual existing
Default: existing
Edit: Yes
Reference: plan_design_rail_model

plan_design_total_power

total power defined by user.

Type: double
Default: 0.0
Edit: Yes
Reference: plan_design_total_power

port_shapes

Short-cut for [get_db current_design .port_shapes]

Type: obj(port_shape)*
Default: ""
Edit: No

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ports

Short-cut for [get_db current_design .ports]

Type: obj(port)*
Default: ""
Edit: No

power_adjust_input_activity_in_iterations

Adjust input activity in state propagation.

Type: bool
Default: true
Edit: Yes
Reference: power_adjust_input_activity_in_iterations

power_adjust_macro_activity_in_iterations

Adjust macro activity in state propagation.

Type: bool
Default: true
Edit: Yes
Reference: power_adjust_macro_activity_in_iterations

power_analysis_temperature

Sets the temperature for static power calculation. If not set, then uses the current opcond
temperature
Type: double
Default: no_value
Edit: Yes
Reference: power_analysis_temperature

power_average_rise_fall_cap

When set to true, the software uses the average of rise and fall capacitance from the liberty
file.
Type: bool
Default: false
Edit: Yes
Reference: power_average_rise_fall_cap

power_bulk_pins

Defines power and ground bulk LEF pins for the design.
Type: string
Default: ""
Edit: Yes
Reference: power_bulk_pins

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power_capacity

Specifies the segment count for profiler

Type: enum
Enum Values: low medium high
Default: low
Edit: Yes
Reference: power_capacity

power_clock_source_as_clock

Specifies to use the correct clock frequency for activity calculation.

Type: bool
Default: false
Edit: Yes
Reference: power_clock_source_as_clock

power_constant_override

Specifies to give higher precedence to propagated constants defined using the

set_case_analysis command.
Type: bool
Default: false
Edit: Yes
Reference: power_constant_override

power_corner

Defines the library corner (for non-MMMC setup).

Type: string
Default: ""
Edit: Yes
Reference: power_corner

power_create_driver_db

Specifies to determine all the drivers/receivers on the ground net.

Type: bool
Default: false
Edit: Yes
Reference: power_create_driver_db

power_current_generation_method

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choose avg or peak current generation method

Type: string
Default: avg
Edit: Yes
Reference: power_current_generation_method

power_db_name

Specifies the name of the binary power database file ( filename.db ).

Type: string
Default: ""
Edit: Yes
Reference: power_db_name

power_decap_cell_list

Specifies the physical only cells, such as decap cells, to include in the power report.
Type: string
Default: ""
Edit: Yes
Reference: power_decap_cell_list

power_default_frequency

Specifies to set the default frequency in the MHz unit for net not annotated by TWF.
Type: double
Default: -1.0
Edit: Yes
Reference: power_default_frequency

power_default_slew

Specifies to set the default slew in the ns unit for net not annotated by TWF.
Type: string
Default: ""
Edit: Yes
Reference: power_default_slew

power_default_supply_voltage

Specifies to set a default voltage for power nets in a scenario where the power engine cannot
determine the voltage of these nets.
Type: string
Default: ""
Edit: Yes
Reference: power_default_supply_voltage

power_disable_clock_gate_clipping

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Specifies to enable clock gate output clipping so that the output transition density of an ICG
cell does not exceed the input clock pin transition density.
Type: bool
Default: true
Edit: Yes
Reference: power_disable_clock_gate_clipping

power_disable_leakage_scaling

Specifies to exclude leakage power during scaling factor computation when target power is
specified using the set_power command.
Type: bool
Default: false
Edit: Yes
Reference: power_disable_leakage_scaling

power_disable_static

When set to true in the dynamic vector-based or dynamic vectorless flows, the command
performs only dynamic analysis and turns-off static power calculation.
Type: bool
Default: false
Edit: Yes
Reference: power_disable_static

power_distributed_setup

Specifies a file containing the customized setup details for running power analysis in the
distributed mode.
Type: string
Default: ""
Edit: Yes
Reference: power_distributed_setup

power_domain_based_clipping

Determines the frequency to be used to clip propagated activity that is too high.
Type: bool
Default: false
Edit: Yes
Reference: power_domain_based_clipping

power_domains

Short-cut for [get_db current_design .power_domains]

Type: obj(power_domain)*
Default: ""
Edit: No

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power_dynamic_glitch_filter

set absolute time threshold value (in ns) for dynamic glitch filter
Type: double
Default: -1.0
Edit: Yes
Reference: power_dynamic_glitch_filter

power_dynamic_power_view

Specifies a separate dynamic analysis view for power calculation.

Type: string
Default: ""
Edit: Yes
Reference: power_dynamic_power_view

power_dynamic_vectorless_ranking_methods

choose ranking options from: load, slack, clock and vector_activity

Type: string
Default: ""
Edit: Yes
Reference: power_dynamic_vectorless_ranking_methods

power_enable_auto_mapping

Specifies to automatically perform instance name mapping between the RTL netlist and GATE
level netlist.
Type: bool
Default: false
Edit: Yes
Reference: power_enable_auto_mapping

power_enable_duty_propagation_with_global_activity

Specifies to propagate duty cycle with the global switching activity setting for all data nets in
the dynamic vectorless analysis flow.
Type: bool
Default: false
Edit: Yes
Reference: power_enable_duty_propagation_with_global_activity

power_enable_dynamic_scaling

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Enables set_power scaling for dynamic power analysis.

Type: bool
Default: false
Edit: Yes
Reference: power_enable_dynamic_scaling

power_enable_generated_clock

Specifies to get generated clock frequency during activity propagation for static power
analysis.
Type: bool
Default: true
Edit: Yes
Reference: power_enable_generated_clock

power_enable_input_net_power

Specifies to calculate the switching power of input nets.

Type: bool
Default: false
Edit: Yes
Reference: power_enable_input_net_power

power_enable_pba_for_tempus_pi

ensure path based timing analysis in tempus-pi flow.

Type: bool
Default: true
Edit: Yes
Reference: power_enable_pba_for_tempus_pi

power_enable_power_target_flow

enable vectorless state propagation with power target

Type: bool
Default: false
Edit: Yes
Reference: power_enable_power_target_flow

power_enable_rtl_dynamic_vector_based

Specifies to take an RTL or partial VCD/FSDB file as input and use that for dynamic vector-
based flow.
Type: bool
Default: false
Edit: Yes
Reference: power_enable_rtl_dynamic_vector_based

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power_enable_scan_report

enable scan report automatical generation

Type: bool
Default: false
Edit: Yes
Reference: power_enable_scan_report

power_enable_state_propagation

enable vectorless state propagation dynamic analysis

Type: bool
Default: false
Edit: Yes
Reference: power_enable_state_propagation

power_enable_tempus_pi

enable timing critical path analysis in state propagation based vectorless flow.
Type: bool
Default: false
Edit: Yes
Reference: power_enable_tempus_pi

power_enable_xp

standalone power analysis in voltus-XP

Type: bool
Default: false
Edit: Yes
Reference: power_enable_xp

power_enhanced_blackbox_avg

Specifies to use the average toggle rate of related inputs for enhanced blackbox propagation.
Type: bool
Default: false
Edit: Yes
Reference: power_enhanced_blackbox_avg

power_enhanced_blackbox_max

Specifies to use the maximum toggle rate of related inputs for enhanced blackbox
propagation.
Type: bool
Default: false
Edit: Yes
Reference: power_enhanced_blackbox_max

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power_extraction_tech_file

technology file for exaction

Type: string
Default: ""
Edit: Yes
Reference: power_extraction_tech_file

power_extractor_include

extraction include file

Type: string
Default: ""
Edit: Yes

power_fanout_limit

Specifies the fanout limit for nets.

Type: int
Default: -1
Edit: Yes
Reference: power_fanout_limit

power_force_library_merging

force library merging even if there is some error during merging

Type: bool
Default: false
Edit: Yes

power_from_x_transition_factor

activity count for x to 0/1 transition

Type: double
Default: 0.5
Edit: Yes
Reference: power_from_x_transition_factor

power_from_z_transition_factor

activity count for z to 0/1 transition

Type: double
Default: 0.25
Edit: Yes
Reference: power_from_z_transition_factor

power_generate_activity_mapping_report

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turn on/off generation of activity_mapping.rpt

Type: bool
Default: false
Edit: Yes
Reference: power_generate_activity_mapping_report

power_generate_current_for_rail

Generates current files for the specified rail.

Type: string
Default: ""
Edit: Yes
Reference: power_generate_current_for_rail

power_generate_flop_ranking_data

Specifies the name of the dir containing the ranking data.

Type: string
Default: ""
Edit: Yes
Reference: power_generate_flop_ranking_data

power_generate_leakage_power_map_based_on_calculated_leakage

Print leakage power table based on calculated leakage power.

Type: bool
Default: false
Edit: Yes
Reference: power_generate_leakage_power_map_based_on_calculated_leakage

power_generate_static_report_from_state_propagation

generate static report from state propagation flow

Type: bool
Default: false
Edit: Yes
Reference: power_generate_static_report_from_state_propagation

power_grid_libraries

Specifies the name of the Cadence power cell libraries ( .cl ).

Type: string
Default: ""
Edit: Yes
Reference: power_grid_libraries

power_handle_glitch

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A transition is defined as a glitch when the time difference between two sequential toggles are
less than half of the rise transition time + fall transition time in the vector-based static power
calculation.
Type: bool
Default: false
Edit: Yes
Reference: power_handle_glitch

power_handle_tristate

When set to true , all tristate device enable pin values will be taken into account when
determining the propagation of the activity through tristate gates.
Type: bool
Default: false
Edit: Yes
Reference: power_handle_tristate

power_hier_delimiter

Specifies the hierarchical delimiter in the DEF file. The default hierarchical delimiter is a
forward slash ( / ) but can be changed by setting the -hier_delimiter parameter.
Type: string
Default: ""
Edit: Yes
Reference: power_hier_delimiter

power_honor_combinational_logic_on_clock_net

Specifies the behavior of combination logic on clock net.

Type: bool
Default: true
Edit: Yes
Reference: power_honor_combinational_logic_on_clock_net

power_honor_negative_energy

A value of true specifies that Voltus will keep negative internal energy numbers from the .lib
internal power table.
Type: bool
Default: true
Edit: Yes
Reference: power_honor_negative_energy

power_honor_net_activity

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honor net activity from activity file

Type: bool
Default: true
Edit: Yes
Reference: power_honor_net_activity

power_ignore_control_signals

A value of true specifies that control signals will be ignored when propagating activity.
Type: bool
Default: true
Edit: Yes
Reference: power_ignore_control_signals

power_ignore_data_phase_for_clock

Type: bool
Default: false
Edit: Yes
Reference: power_ignore_data_phase_for_clock

power_ignore_end_toggles_in_profile

ignore toggles on end boundary in profiler analysis

Type: bool
Default: false
Edit: Yes
Reference: power_ignore_end_toggles_in_profile

power_ignore_glitches_at_same_time_stamp

Specifies to ignore glitches at the same transient time in the vector-based static and dynamic
power analysis flow.
Type: bool
Default: true
Edit: Yes
Reference: power_ignore_glitches_at_same_time_stamp

power_ignore_inout_pin_cap

When set to true , ignores the bidirectional pin capacitances ( direction : inout ) defined for I/O
cells in the .lib file, when calculating switching power and internal power.
Type: bool
Default: false
Edit: Yes
Reference: power_ignore_inout_pin_cap

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power_include_file

Used for adding additional setting for power analysis

Type: string
Default: ""
Edit: Yes
Reference: power_include_file

power_include_initial_x_transitions

Controls how the initial X state toggle should be counted.

Type: bool
Default: true
Edit: Yes
Reference: power_include_initial_x_transitions

power_include_sequential_clock_pin_power

Reports the clock pin power of flip-flops as part of the clock network power.
Type: bool
Default: false
Edit: Yes
Reference: power_include_sequential_clock_pin_power

power_include_timing_in_current_file

enable timing bit writing in current file

Type: bool
Default: false
Edit: Yes
Reference: power_include_timing_in_current_file

power_intent_allow_back_to_back_isolation

Supports back-to-back isolation insertion along cross-domain net based on power intent ISO
rule
Type: bool
Default: false
Edit: Yes
Reference: power_intent_allow_back_to_back_isolation

power_intent_allow_nested_default_domain

Allows a non-default power domain member to be logically nested in a default power domain
Type: bool
Default: true
Edit: Yes
Reference: power_intent_allow_nested_default_domain

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power_intent_allow_power_domain_min_gap_zero

Type: bool
Default: true
Edit: Yes
Reference: power_intent_allow_power_domain_min_gap_zero

power_intent_allow_shifter_voltage_mismatch

Type: bool
Default: true
Edit: Yes
Reference: power_intent_allow_shifter_voltage_mismatch

power_intent_assume_iso_enable_pin_is_always_on

To mark all Isolation cell's enable pin as always on

Type: bool
Default: true
Edit: Yes
Reference: power_intent_assume_iso_enable_pin_is_always_on

power_intent_check_all_nets_for_domain_crossing

Checks all the nets for domain crossings

Type: bool
Default: true
Edit: Yes
Reference: power_intent_check_all_nets_for_domain_crossing

power_intent_do_not_use_top_domain_for_port_voltage

Controls voltage using top fterm domain for IO pin voltage

Type: bool
Default: false
Edit: Yes
Reference: power_intent_do_not_use_top_domain_for_port_voltage

power_intent_honor_power_domain_for_domain_crossing_route

to handle nets belong to multiple power domains

Type: bool
Default: true
Edit: Yes
Reference: power_intent_honor_power_domain_for_domain_crossing_route

power_intent_honor_power_domain_for_intra_domain_route

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To route intra-power domain nets only within their power domains

Type: bool
Default: true
Edit: Yes
Reference: power_intent_honor_power_domain_for_intra_domain_route

power_intent_include_dot_lib_related_pg_pin

Honors timing library related PG pins

Type: bool
Default: true
Edit: Yes
Reference: power_intent_include_dot_lib_related_pg_pin

power_intent_share_well_always_on_buffering_support

Type: bool
Default: false
Edit: Yes
Reference: power_intent_share_well_always_on_buffering_support

power_intent_use_cpf_global_connect_for_always_on_buffer

Honors connection specs for AO buffer based on the power intent rules
Type: bool
Default: false
Edit: Yes
Reference: power_intent_use_cpf_global_connect_for_always_on_buffer

power_intent_use_cpf_global_connect_for_shifter

Honors connection specs for shifters based on the CPF rules

Type: bool
Default: false
Edit: Yes
Reference: power_intent_use_cpf_global_connect_for_shifter

power_intent_use_effective_domain_for_iso_shifter_insertion

Honors effective domains for ISO/LS insertions

Type: bool
Default: true
Edit: Yes
Reference: power_intent_use_effective_domain_for_iso_shifter_insertion

power_ir_derated_timing_view

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set timing view in tempus-pi flow.

Type: string
Default: ""
Edit: Yes
Reference: power_ir_derated_timing_view

power_keep_clock_gate_ratio_in_iterations

Keep clock gate ratio in state propagation.

Type: bool
Default: false
Edit: Yes
Reference: power_keep_clock_gate_ratio_in_iterations

power_leakage_power_view

Specifies a separate leakage analysis view for power calculation.

Type: string
Default: ""
Edit: Yes
Reference: power_leakage_power_view

power_leakage_scale_factor_for_temperature

Performs a linear scaling of the leakage power for temperature in all libraries.
Type: double
Default: 1.0
Edit: Yes
Reference: power_leakage_scale_factor_for_temperature

power_lib_files

Specify the lib files to be used for power Analysis. Libs specified through this option are not
read in during design loading
Type: string
Default: ""
Edit: Yes
Reference: power_lib_files

power_library_preference

option to choose instance binding to closest voltage or ecsm/ccsp library.

Type: string
Default: voltage
Edit: Yes
Reference: power_library_preference

power_match_state_for_logic_x

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Controls how the logic X will be evaluated in the boolean function of the 'when' state of a
power table.
Type: string
Default: x
Edit: Yes
Reference: power_match_state_for_logic_x

power_merge_switched_net_currents

Specifies to merge switched net currents into always-on currents.

Type: bool
Default: false
Edit: Yes
Reference: power_merge_switched_net_currents

power_method

Specifies the type of analysis to be performed.

Type: enum
Enum Values: static dynamic dynamic_vectorless dynamic_vectorbased
dynamic_mixed_mode vector_profile
Default: static
Edit: Yes
Reference: power_method

power_min_leaf_count

min number of leaf instances count

Type: int
Default: 0
Edit: Yes
Reference: power_min_leaf_count

power_modes

List of the power mode names in the design.

Type: string
Default: ""
Edit: No

power_multibit_flop_toggle_behavior

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select mbff toggle: simultaneous | independent(default) | sbff during vectorless state

propagation dynamic analysis
Type: enum
Enum Values: simultaneous independent sbff
Default: independent
Edit: Yes
Reference: power_multibit_flop_toggle_behavior

power_off_pg_nets

The name of the power rails that will be turned off.

Type: string
Default: ""
Edit: Yes
Reference: power_off_pg_nets

power_output_current_data_prefix

Specifies a prefix to the static or dynamic current files generated by the software.
Type: string
Default: ""
Edit: Yes
Reference: power_output_current_data_prefix

power_output_dir

Used to save power engine output to the defined directory. If not set, will use the current
working dir.
Type: string
Default: ""
Edit: Yes
Reference: power_output_dir

power_partition_twf

turn on/off twf partitioning in distributed flow

Type: bool
Default: false
Edit: Yes
Reference: power_partition_twf

power_pin_based_twf

turn on/off generation of pin based TWF in dynamic method

Type: bool
Default: false
Edit: Yes
Reference: power_pin_based_twf

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power_precision

Specifies precision of decimal range [1-8] to ensure consistent decimal places are displayed
for each power component.
Type: int
Default: 8
Edit: Yes
Reference: power_precision

power_quit_on_activity_coverage_threshold

Specifies the activity (VCD/FSDB/TCF) coverage threshold value.

Type: double
Default: 0.0
Edit: Yes
Reference: power_quit_on_activity_coverage_threshold

power_read_rcdb

Specifies to write a SPEF file containing only the total C for signal nets and pass it to the
Dynamic Power engine.
Type: bool
Default: false
Edit: Yes
Reference: power_read_rcdb

power_report_black_boxes

Specify this parameter to report cells that are used as black boxes.
Type: bool
Default: false
Edit: Yes
Reference: power_report_black_boxes

power_report_idle_instances

report non-switching instances in vectorless state propagation dynamic analysis

Type: bool
Default: false
Edit: Yes
Reference: power_report_idle_instances

power_report_instance_switching_info

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all or output_logic or none

Type: enum
Enum Values: all output_logic none
Default: none
Edit: Yes
Reference: power_report_instance_switching_info

power_report_instance_switching_list

specify file which is having list of instances

Type: string
Default: ""
Edit: Yes
Reference: power_report_instance_switching_list

power_report_library_usage

generate report for lib usage

Type: bool
Default: false
Edit: Yes
Reference: power_report_library_usage

power_report_missing_bulk_connectivity

Specifies to report missing bulk pins in the missing input report ( -report_missing_input ).
Type: bool
Default: false
Edit: Yes
Reference: power_report_missing_bulk_connectivity

power_report_missing_input

Specifies to report missing netlist information in input files, such as library, LEF/DEF, PGV,
SPEF, TWF, and missing logical connectivity for cell instance (PGNET).
Type: bool
Default: false
Edit: Yes
Reference: power_report_missing_input

power_report_missing_nets

Controls reporting of missing nets in both static and dynamic power analysis.
Type: bool
Default: false
Edit: Yes
Reference: power_report_missing_nets

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power_report_scan_chain_statistics

report scan chain analysis statistics

Type: bool
Default: false
Edit: Yes
Reference: power_report_scan_chain_statistics

power_report_statistics

Reports a set of statistics on the instance power, instance power density, clock power, or
transition density.
Type: bool
Default: false
Edit: Yes
Reference: power_report_statistics

power_report_time_display_fraction_digits

specify display fraction digits of reporting time

Type: int
Default: -1
Edit: Yes
Reference: power_report_time_display_fraction_digits

power_report_twf_attributes

TWF attributes report format

Type: string
Default: ""
Edit: Yes
Reference: power_report_twf_attributes

power_reuse_flop_ranking_data

Specifies the name of the dir containing the ranking data.

Type: string
Default: ""
Edit: Yes
Reference: power_reuse_flop_ranking_data

power_reuse_flop_ranking_data_hier

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A hierarchy name from the user that will be used to search the ranking data for the block level
being analyzed.
Type: string
Default: ""
Edit: Yes
Reference: power_reuse_flop_ranking_data_hier

power_scale_to_sdc_clock_frequency

Specifies to enable the VCD clock frequency to be scaled up to the SDC clock frequency.
Type: bool
Default: false
Edit: Yes
Reference: power_scale_to_sdc_clock_frequency

power_scan_chain_name_pattern

define scan chain name and pattern

Type: string
Default: ""
Edit: Yes
Reference: power_scan_chain_name_pattern

power_scan_control_file

Specifies the scan control file name required to run the Scan Mode Analysis flow.
Type: string
Default: ""
Edit: Yes
Reference: power_scan_control_file

power_scan_multi_bit_flop_chain_type

Specifies the type of multi-bit scan flip-flop.

Type: string
Default: liberty
Edit: Yes
Reference: power_scan_multi_bit_flop_chain_type

power_settling_buffer

Specifies the settling buffer time (in ps unit) between multiple windows of a VCD file.
Type: string
Default: ""
Edit: Yes
Reference: power_settling_buffer

power_split_bus_power

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A value of false applies the internal power number to each individual bit.
Type: bool
Default: false
Edit: Yes
Reference: power_split_bus_power

power_start_time_alignment

Specifies to align all the signals of the activity file at time zero.
Type: bool
Default: true
Edit: Yes
Reference: power_start_time_alignment

power_state_dependent_leakage

When set to false , power analysis performs state independent leakage power calculation.
Type: bool
Default: true
Edit: Yes
Reference: power_state_dependent_leakage

power_static_multi_mode_scenario_file

set static multi-mode scenario file name

Type: string
Default: ""
Edit: Yes
Reference: power_static_multi_mode_scenario_file

power_static_netlist

Specifies to perform static power analysis using a Verilog or DEF only neltist.
Type: string
Default: verilog
Edit: Yes
Reference: power_static_netlist

power_thermal_input_file

Specifies to read a power map file to perform thermal analysis.

Type: string
Default: ""
Edit: Yes
Reference: power_thermal_input_file

power_thermal_leakage_temperature_scale_table_file

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Defines library/cell/instance based leakage power scaling factors on each temperature point.
Type: string
Default: ""
Edit: Yes
Reference: power_thermal_leakage_temperature_scale_table_file

power_to_x_transition_factor

activity count for 0/1 to x transition

Type: double
Default: 0.5
Edit: Yes
Reference: power_to_x_transition_factor

power_to_z_transition_factor

activity count for 0/1 to z transition

Type: double
Default: 0.25
Edit: Yes
Reference: power_to_z_transition_factor

power_transition_time_method

Specifies the minimum, maximum, or average transition time method that will be used with the
integrated timer or the external TWF.
Type: string
Default: max
Edit: Yes
Reference: power_transition_time_method

power_twf_delay_annotation

Allows you to choose between min, max, or avg arrival times from the timing window file
(TWF).
Type: string
Default: avg
Edit: Yes
Reference: power_twf_delay_annotation

power_twf_load_cap

Allows you to select minimum, maximum, or average value of TWF external load or
capacitance for power calculation.
Type: string
Default: max
Edit: Yes
Reference: power_twf_load_cap

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power_use_cell_leakage_power_density

Specifies to use library leakage density times area (default_leakage_power_density).

Type: bool
Default: true
Edit: Yes
Reference: power_use_cell_leakage_power_density

power_use_fastest_clock_for_dynamic_scheduling

Specifies to use only the respective fastest clock associated with each net or pin to schedule
events for a given simulation period.
Type: bool
Default: false
Edit: Yes
Reference: power_use_fastest_clock_for_dynamic_scheduling

power_use_lef_for_missing_cells

Allows a combination of LEF and PGV in the dynamic analysis flow.

Type: bool
Default: false
Edit: Yes
Reference: power_use_lef_for_missing_cells

power_use_zero_delay_vector_file

Enables zero delay mode in vector-based dynamic analysis to avoid pessimism in current
estimation.
Type: bool
Default: false
Edit: Yes
Reference: power_use_zero_delay_vector_file

power_vector_based_multithread

Specifies to enable multi-threading for the VCD/FSDB based dynamic vector-based flows.
Type: bool
Default: true
Edit: Yes
Reference: power_vector_based_multithread

power_vector_profile_mode

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activity or density
Type: enum
Enum Values: activity event_based power_density transient
Default: event_based
Edit: Yes
Reference: power_vector_profile_mode

power_view

Specifies the power analysis library view (for MMMC setup).

Type: string
Default: ""
Edit: Yes
Reference: power_view

power_worst_case_vector_activity

Specifies to use the worst activity value when multiple vectors are specified in the static power
calculation flow.
Type: bool
Default: false
Edit: Yes
Reference: power_worst_case_vector_activity

power_worst_step_size

Set worst step size for power analysis

Type: string
Default: ""
Edit: Yes
Reference: power_worst_step_size

power_worst_window_count

Set worst window count for power analysis

Type: int
Default: 1
Edit: Yes
Reference: power_worst_window_count

power_worst_window_reports

generate Power reports for full simuation and worst power window
Type: string
Default: full
Edit: Yes

power_worst_window_size

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Set worst window size for power analysis

Type: string
Default: ""
Edit: Yes
Reference: power_worst_window_size

power_worst_window_type

Set worst window type for power analysis

Type: string
Default: ""
Edit: Yes
Reference: power_worst_window_type

power_write_db

A value of true creates a binary database of power results.

Type: bool
Default: false
Edit: Yes
Reference: power_write_db

power_write_default_pti_files

For instances that are not hooked to any power/ground rail, the current for these instances are
reflected in the default static current files.
Type: bool
Default: true
Edit: Yes
Reference: power_write_default_pti_files

power_write_gui_db

A value of true creates a binary database of power results for gui.

Type: bool
Default: true
Edit: Yes
Reference: power_write_gui_db

power_write_profiling_db

turn on/off profiling database writing

Type: bool
Default: false
Edit: Yes
Reference: power_write_profiling_db

power_write_static_currents

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A value of true tells Voltus to generate the current data files per net.
Type: bool
Default: false
Edit: Yes
Reference: power_write_static_currents

power_x_transition_factor

When using VCD/FSDB one can specify how transitions to and from X are counted.
Type: double
Default: 0.5
Edit: Yes
Reference: power_x_transition_factor

power_z_transition_factor

When using VCD/FSDB one can specify how transitions to and from Z are counted.
Type: double
Default: 0.25
Edit: Yes
Reference: power_z_transition_factor

power_zero_delay_vector_toggle_shift

Specifies to shift the current waveform in the zero-delay VCD flow.

Type: string
Default: ""
Edit: Yes
Reference: power_zero_delay_vector_toggle_shift

print_full_message_summary

Used to control the format of message summary. If true, print full message, otherwith, print
truncated message.
Type: bool
Default: false
Edit: Yes
Reference: print_full_message_summary

program_major_version

The major version plus one digit. So if program_version = 19.11-e062_1 it would return '19.1'.
Type: double
Default: ""
Edit: No
Reference: program_major_version

program_name

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name of the program

Type: string
Default: ""
Edit: No
Reference: program_name

program_short_name

short name of the program

Type: string
Default: ""
Edit: No
Reference: program_short_name

program_version

version of the program

Type: string
Default: ""
Edit: No
Reference: program_version

proto_allow_model_with_io

Supports model with I/Os.

Type: bool
Default: false
Edit: Yes
Reference: proto_allow_model_with_io

proto_allow_power_domain_in_flexmodel

Allow powerdomain in flexmodel

Type: bool
Default: false
Edit: Yes
Reference: proto_allow_power_domain_in_flexmodel

proto_create_dir

Specifies the directory to save created models.

Type: string
Default: proto_model
Edit: Yes
Reference: proto_create_dir

proto_create_high_fanout_ps_per_micron

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Create high fanout psPM models.

Type: bool
Default: true
Edit: Yes
Reference: proto_create_high_fanout_ps_per_micron

proto_create_lib

Specifies the OA library to save created models.

Type: string
Default: proto_model_lib
Edit: Yes
Reference: proto_create_lib

proto_create_metal_fill_ndr

Will be used by create_proto_net_delay_model for creating psPM model for nets with non
default rules.
Type: double
Default: 0.0
Edit: Yes
Reference: proto_create_metal_fill_ndr

proto_create_metal_fill_nominal

Will be used by create_proto_net_delay_model for creating psPM model for normal nets.
Type: double
Default: 0.5
Edit: Yes
Reference: proto_create_metal_fill_nominal

proto_create_multi_corner_ps_per_micron

Create multi corner psPM models.

Type: bool
Default: false
Edit: Yes
Reference: proto_create_multi_corner_ps_per_micron

proto_create_ndr_ps_per_micron

Control whether create_proto_net_delay_model should generate psPM model for non default
rule or not
Type: enum
Enum Values: auto on off
Default: auto
Edit: Yes
Reference: proto_create_ndr_ps_per_micron

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proto_create_no_flex_filler

Create proto model without adding flex filler.

Type: bool
Default: false
Edit: Yes
Reference: proto_create_no_flex_filler

proto_create_partition_as_flexmodel

Create partition specified as flexmodel automatically.

Type: bool
Default: false
Edit: Yes
Reference: proto_create_partition_as_flexmodel

proto_create_pipeline_flop

Specifies a list of pipeline flop instance patterns that are used in the design.
Type: string
Default: ""
Edit: Yes
Reference: proto_create_pipeline_flop

proto_create_power_domain_ps_per_micron

Create power domain psPM models.

Type: bool
Default: false
Edit: Yes
Reference: proto_create_power_domain_ps_per_micron

proto_design_congestion_aware

aware of congestion when using new plan_design algorithm

Type: bool
Default: false
Edit: Yes
Reference: proto_design_congestion_aware

proto_design_cover_fixed_macros

force flexModel cover fixed macros belong to it when using new plan_design algorithm
Type: bool
Default: false
Edit: Yes
Reference: proto_design_cover_fixed_macros

proto_design_flexmodel_constraint_type

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Convert flexModel to the specified constraint type in proto_design.

Type: enum
Enum Values: guide region fence
Default: region
Edit: Yes
Reference: proto_design_flexmodel_constraint_type

proto_design_keep_guide

-keep_guide {true|false} #default=true

Type: bool
Default: true
Edit: Yes
Reference: proto_design_keep_guide

proto_design_place_macro

control if do macro placement in plan_design

Type: bool
Default: true
Edit: Yes
Reference: proto_design_place_macro

proto_design_remove_overlap

control if do remove overlap in plan_design

Type: bool
Default: true
Edit: Yes
Reference: proto_design_remove_overlap

proto_design_timing_aware

aware of timing when using new plan_design algorithm

Type: bool
Default: false
Edit: Yes
Reference: proto_design_timing_aware

proto_identify_engine

identify_proto algorithm <default=auto>

Type: enum
Enum Values: auto module_based instgroup_based
Default: auto
Edit: Yes
Reference: proto_identify_engine

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proto_identify_estimated_flexmodel_number

Specified the estimated flexModel number to identify for the design when using instance group
based identify_proto_model.
Type: int
Default: 20
Edit: Yes
Reference: proto_identify_estimated_flexmodel_number

proto_identify_exclude_module

Excludes specified module(s) but not its sub-modules for being marked as models.
Type: string
Default: ""
Edit: Yes
Reference: proto_identify_exclude_module

proto_identify_exclude_module_and_parent

Excludes specified module(s) and their parents for being marked as models.
Type: string
Default: ""
Edit: Yes
Reference: proto_identify_exclude_module_and_parent

proto_identify_exclude_module_tree

Excludes specified module(s) and its sub-modules for being marked as models.
Type: string
Default: ""
Edit: Yes
Reference: proto_identify_exclude_module_tree

proto_identify_honor_objects_hierarchy

Specified the list of objects which instance group based identify_proto_model will honor its
hierarchy.
Type: string
Default: ""
Edit: Yes
Reference: proto_identify_honor_objects_hierarchy

proto_identify_max_inst

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Specifies the maximum instance count threshold of a module to be marked as model.

(default=8% of total instance count and no lower than 300K instances)
Type: int
Default: -1
Edit: Yes
Reference: proto_identify_max_inst

proto_identify_min_inst

Specifies the minimum instance count threshold of a module to be marked as model.

Type: int
Default: 1000
Edit: Yes
Reference: proto_identify_min_inst

proto_keep_inst_file_only

FlexModel only contains inst in keep_inst_file.

Type: bool
Default: false
Edit: Yes
Reference: proto_keep_inst_file_only

proto_keep_instance_defined_in_sdc

FlexModel will keep inst defined in sdc file

Type: bool
Default: false
Edit: Yes
Reference: proto_keep_instance_defined_in_sdc

proto_keep_slack_improve_ndr

Will be used by report_NDR_WNS_gain to keep top critical nets as non default rule nets .
Type: bool
Default: false
Edit: Yes
Reference: proto_keep_slack_improve_ndr

proto_max_report_ndr_net

Will be used by create_proto_net_delay_model for creating psPM model for nets with non
default rules.
Type: double
Default: 0.05
Edit: Yes
Reference: proto_max_report_ndr_net

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proto_place_effort

set place effort

Type: enum
Enum Values: fp default center
Default: fp
Edit: Yes
Reference: proto_place_effort

proto_route_net_ndr

Will be used by create_proto_net_delay_model for creating psPM model for nets with non
default rules.
Type: string
Default: ""
Edit: Yes
Reference: proto_route_net_ndr

proto_timing_net_delay

Specifies the estimated delay per micron for each routing layer. Layer range is from 1 to
maximum routing layers.
Type: string
Default: ""
Edit: Yes
Reference: proto_timing_net_delay

proto_use_timing_net_delay_model

set mode of calculating wire delay

Type: enum
Enum Values: best_layer_no_detour best_layer_blockage_aware use_actual_wire
Default: best_layer_no_detour
Edit: Yes
Reference: proto_use_timing_net_delay_model

proto_verbose

Output detailed information into .log file.

Type: bool
Default: false
Edit: Yes
Reference: proto_verbose

rc_corners

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Returns the information about the rc corners in the design.

Type: obj(rc_corner)*
Default: ""
Edit: No

read_db_directory

Specifies the directory of current loaded DB.

Type: string
Default: ""
Edit: Yes
Reference: read_db_directory

read_db_file_check

By default, read_db will check all files inside the saved DB directory are unchanged. If any
files have been edited, renamed or deleted, then an error will occur unless this value is set to
false.
Type: bool
Default: true
Edit: Yes
Reference: read_db_file_check

read_db_stop_at_design_in_memory

By default, tool will error and stop if call read_db more than once in the same Innovus session
unless this value is set to false.
Type: bool
Default: true
Edit: Yes
Reference: read_db_stop_at_design_in_memory

read_db_tool_name

Indicates the tool name of the tool that created the restored db on the disk database
Type: string
Default: ""
Edit: Yes
Reference: read_db_tool_name

read_db_version

Indicates the version of the tool that generates an on disk database

Type: string
Default: ""
Edit: Yes
Reference: read_db_version

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read_def_check_mask_shifts

If on/bypass, will check for conflicts between DEF COMPONENT MASKSHIFT and MACRO
MASKSHIFT values with the LEF FIXEDMASK and LAYERMASKSHIFT values in the
technology and MACRO sections, error out if on and error without out if bypass
Type: enum
Enum Values: off on bypass
Default: off
Edit: Yes
Reference: read_def_check_mask_shifts

read_physical_check_mask_shifts

If on/bypass, will check for conflicts between LEF FIXEDMASK and LAYERMASKSHIFT
values in the technology section and MACRO section when reading in any LEF files, error out
if on and error without out if bypass
Type: enum
Enum Values: off on bypass
Default: off
Edit: Yes
Reference: read_physical_check_mask_shifts

read_physical_extend_cell_obs_shapes_under_trim

A list of routing layer. LEF OBS shapes on each <layer> that are overlapped partially by a
shape on TRIMMETAL layer that trims the routing layer, will be extended in the preferred
routing direction to be fully covered by the trim shape. This is a workaround for some
advanced node libraries to avoid trim/OBS short violations.
Type: string
Default: ""
Edit: Yes

read_physical_extend_polygon_cell_shapes

A list of {{<layer> <value>} ...} pairs. LEF PIN/OBS shapes on each <layer> that are polygons
(not simple rects), will be extended with OBS SPACING 0 rects by <value> (in microns) in the
preferred routing direction. This is a workaround for some advanced node libraries to avoid
spacing violations during routing.
Type: string
Default: ""
Edit: Yes
Reference: read_physical_extend_polygon_cell_shapes

read_physical_merge_multi_port_to_single_port

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if true, multiple ports in a LEF PIN will be merged into single port.
Type: bool
Default: false
Edit: Yes

read_physical_must_join_all_ports

if false, the LEF_MUSTJOINALLPORTS property on a LEF PIN auto-creates MUSTJOIN pins

for each PORT. If true, the MUSTJOIN pins are not created, but the router must connect to
every port with a signal wire or signal via that physically overlaps all the ports.
Type: bool
Default: true
Edit: Yes
Reference: read_physical_must_join_all_ports

read_write_lef_check_uncolored_shapes

Specifies whether to check for uncolored LEF PIN and OBS shapes on multi-mask routing
layers when reading or writing LEF files. If the check is on, LEF read or write commands will
error out if there are any uncolored routing layer shapes (cut layers are not checked). If set to
pin_only, only check LEF PIN shapes and ignore LEF OBS shapes.
Type: enum
Enum Values: on off pin_only
Default: off
Edit: Yes
Reference: read_write_lef_check_uncolored_shapes

reorder_scan_add_scan_port_prefix

prefix of scan hport

Type: string
Default: ""
Edit: Yes
Reference: reorder_scan_add_scan_port_prefix

reorder_scan_allow_swapping

reorder with new swap mode

Type: bool
Default: false
Edit: Yes
Reference: reorder_scan_allow_swapping

reorder_scan_clock_aware

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Clock tree aware reorder

Type: bool
Default: false
Edit: Yes
Reference: reorder_scan_clock_aware

reorder_scan_comp_logic

trace considering multiple input logic

Type: bool
Default: false
Edit: Yes
Reference: reorder_scan_comp_logic

reorder_scan_effort

Specifies effort level for reorder_scan

Type: enum
Enum Values: low medium high auto
Default: auto
Edit: Yes
Reference: reorder_scan_effort

reorder_scan_enable_for_partition

enable scanReorder for design with partition

Type: bool
Default: false
Edit: Yes
Reference: reorder_scan_enable_for_partition

reorder_scan_keep_hinst_port_name

Specifies filename which contains HInsts

Type: string
Default: ""
Edit: Yes
Reference: reorder_scan_keep_hinst_port_name

reorder_scan_keep_hport

Maintains hierarchical ports without adding or deleting shifters

Type: bool
Default: true
Edit: Yes
Reference: reorder_scan_keep_hport

reorder_scan_prefer_horizontal

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Makes horizontal scan chain connections if possible

Type: bool
Default: false
Edit: Yes
Reference: reorder_scan_prefer_horizontal

reorder_scan_prefer_vertical

Makes vertical scan chain connections if possible

Type: bool
Default: false
Edit: Yes
Reference: reorder_scan_prefer_vertical

reorder_scan_skip_mode

Specifies method for handling buffers and inverters

Type: enum
Enum Values: skip_none skip_buffer skip_floating_buffer
Default: skip_none
Edit: Yes
Reference: reorder_scan_skip_mode

reorder_scan_swap_effort

Specifies effort level for reorder_scan different chains swapping

Type: enum
Enum Values: low medium high
Default: high
Edit: Yes
Reference: reorder_scan_swap_effort

report_obj_display_limit

Controls the number of objects that will be displayed when using report_obj. If the value is 10,
'report_obj insts' will only display 10 inst objects with all their non-default attributes.
Type: int
Default: 1000
Edit: Yes
Reference: report_obj_display_limit

report_pin_density_map_display_step

range step for displaying the pin density map

Type: double
Default: 0.05
Edit: Yes
Reference: report_pin_density_map_display_step

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report_pin_density_map_grid_size

specify the value (in row-height) of side of square grid for pin density calculations.
Type: int
Default: 10
Edit: Yes
Reference: report_pin_density_map_grid_size

report_pin_density_map_grid_unit

specify the value (in micron) of side of square grid for pin density calculations.
Type: double
Default: 50.0
Edit: Yes
Reference: report_pin_density_map_grid_unit

report_pin_density_map_threshold

threshold value over which the densities must be reported.

Type: double
Default: 0.5
Edit: Yes
Reference: report_pin_density_map_threshold

report_place_density_map_grid_size

specify the value (in row-height) of side of square grid for density calculations.
Type: int
Default: 10
Edit: Yes
Reference: report_place_density_map_grid_size

report_place_density_map_grid_unit

specify the value (in micron) of side of square grid for density calculations.
Type: double
Default: 50.0
Edit: Yes
Reference: report_place_density_map_grid_unit

report_place_density_map_ignore_filler

Type: bool
Default: false
Edit: Yes
Reference: report_place_density_map_ignore_filler

report_place_density_map_threshold

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threshold value over which the densities must be reported.

Type: double
Default: 0.75
Edit: Yes
Reference: report_place_density_map_threshold

resize_blockages

Short-cut for [get_db current_design .resize_blockages]

Type: obj(resize_blockage)*
Default: ""
Edit: No

resize_floorplan_cong_aware

resizes and shifts the floorplan objects by estimating the congestion for the floorplan and
automatically deciding where to draw a resize line to avoid the congested area.
Type: bool
Default: false
Edit: Yes
Reference: resize_floorplan_cong_aware

resize_floorplan_honor_halo

honors placement halo and preserves the space between macros held by halo after the
floorplan resize.
Type: bool
Default: true
Edit: Yes
Reference: resize_floorplan_honor_halo

resize_floorplan_io_fix

fixes I/Os at current location.

Type: bool
Default: false
Edit: Yes
Reference: resize_floorplan_io_fix

resize_floorplan_io_move_with_edge

moves pins on the moved edge orthogonally to edge direction so pins stay on edge after
movement.
Type: bool
Default: false
Edit: Yes
Reference: resize_floorplan_io_move_with_edge

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resize_floorplan_io_relative

resize the space among I/Os proportionally.

Type: bool
Default: true
Edit: Yes
Reference: resize_floorplan_io_relative

resize_floorplan_maintain_resource_ratio

Enable to maintain the resource ratio after resize_floorplan in shift-based mode.

Type: bool
Default: false
Edit: Yes
Reference: resize_floorplan_maintain_resource_ratio

resize_floorplan_relative

resizes the space among floorplan objects proportionally.

Type: bool
Default: false
Edit: Yes
Reference: resize_floorplan_relative

resize_floorplan_shift_based

shifts floorplan objects at appropriate location(s) without changing the proportional spacing.
Type: bool
Default: true
Edit: Yes
Reference: resize_floorplan_shift_based

resize_floorplan_shrink_fence

enables resized lines to go through fences and regions in floorplan.

Type: bool
Default: false
Edit: Yes
Reference: resize_floorplan_shrink_fence

resize_floorplan_snap_to_track

snaps resize values (shrink/expand) of the floorplan to a multiple integer of the metal layer
pitch.
Type: bool
Default: true
Edit: Yes
Reference: resize_floorplan_snap_to_track

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route_blockages

Short-cut for [get_db current_design .route_blockages]

Type: obj(route_blockage)*
Default: ""
Edit: No

route_design_add_antenna_inst_prefix

prefix for the diode insts added to fix antenna

Type: string
Default: ""
Edit: Yes
Reference: route_design_add_antenna_inst_prefix

route_design_adjust_auto_via_weight

adjust auto via weight for via swapping

Type: bool
Default: true
Edit: Yes
Reference: route_design_adjust_auto_via_weight

route_design_allow_inst_overlaps

don't do instance overlap check

Type: bool
Default: true
Edit: Yes
Reference: route_design_allow_inst_overlaps

route_design_allow_pin_as_feedthru

allow pin as feedthrough

Type: enum
Enum Values: true TRUE false FALSE none NONE output input inout
Default: true
Edit: Yes
Reference: route_design_allow_pin_as_feedthru

route_design_antenna_cell_name

specify the antenna diode cell names for antenna fixing

Type: string
Default: ""
Edit: Yes
Reference: route_design_antenna_cell_name

route_design_antenna_diode_insertion

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insert antenna diode to fix antenna violation

Type: bool
Default: false
Edit: Yes
Reference: route_design_antenna_diode_insertion

route_design_concurrent_minimize_via_count_effort

specify the effort of concurrent via minimization

Type: string
Default: medium
Edit: Yes
Reference: route_design_concurrent_minimize_via_count_effort

route_design_connect_to_bumps

connect to bumps in native NanoRoute in Innovus

Type: bool
Default: false
Edit: Yes
Reference: route_design_connect_to_bumps

route_design_detail_add_passive_fill_only_on_layers

specify layers where passive fill will be added

Type: string
Default: ""
Edit: Yes
Reference: route_design_detail_add_passive_fill_only_on_layers

route_design_detail_antenna_eco_list_file

set file name for antenna eco list

Type: string
Default: ""
Edit: Yes
Reference: route_design_detail_antenna_eco_list_file

route_design_detail_auto_stop

control whether Nanoroute continues routing if there are many violations

Type: bool
Default: true
Edit: Yes
Reference: route_design_detail_auto_stop

route_design_detail_check_mar_on_cell_pin

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Enable mar checking on used cell pins

Type: bool
Default: false
Edit: Yes
Reference: route_design_detail_check_mar_on_cell_pin

route_design_detail_end_iteration

specify the last iteration pass in a detailed routing step

Type: int
Default: 0
Edit: Yes
Reference: route_design_detail_end_iteration

route_design_detail_fix_antenna

fix antenna violation by jumping metal layers

Type: bool
Default: true
Edit: Yes
Reference: route_design_detail_fix_antenna

route_design_detail_fix_antenna_on_secondary_pg_nets

fix antenna violation on sencondary pg nets

Type: bool
Default: false
Edit: Yes
Reference: route_design_detail_fix_antenna_on_secondary_pg_nets

route_design_detail_fix_antenna_with_gate_array_filler_mode

detect GA filler flow while doing antenna violation fixing

Type: bool
Default: false
Edit: Yes
Reference: route_design_detail_fix_antenna_with_gate_array_filler_mode

route_design_detail_merge_abutting_cut

merge two abutting cell cut shapes into a new one

Type: bool
Default: true
Edit: Yes
Reference: route_design_detail_merge_abutting_cut

route_design_detail_min_length_for_spread_wire

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specify the min. length of a spreaded wire

Type: string
Default: 0
Edit: Yes
Reference: route_design_detail_min_length_for_spread_wire

route_design_detail_min_length_for_widen_wire

specify the min. length of a widened wire

Type: double
Default: 1.0
Edit: Yes
Reference: route_design_detail_min_length_for_widen_wire

route_design_detail_min_slack_for_opt_wire

specify the min slack for a net wire optimization

Type: double
Default: 0.0
Edit: Yes
Reference: route_design_detail_min_slack_for_opt_wire

route_design_detail_no_taper_in_layers

Specifies the range of the layer where taper is not allowed

Type: string
Default: ""
Edit: Yes
Reference: route_design_detail_no_taper_in_layers

route_design_detail_no_taper_on_output_pin

forbid wire tapering at output pin

Type: enum
Enum Values: false true auto
Default: false
Edit: Yes
Reference: route_design_detail_no_taper_on_output_pin

route_design_detail_on_grid_only

route on grid only

Type: string
Default: none
Edit: Yes
Reference: route_design_detail_on_grid_only

route_design_detail_post_route_litho_repair

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litho hotspot repair in post route stage

Type: bool
Default: false
Edit: Yes
Reference: route_design_detail_post_route_litho_repair

route_design_detail_post_route_spread_wire

spread wire in post route stage

Type: string
Default: auto
Edit: Yes
Reference: route_design_detail_post_route_spread_wire

route_design_detail_post_route_swap_via

to enforce post route via swapping mode in detail route command.

Type: string
Default: false
Edit: Yes
Reference: route_design_detail_post_route_swap_via

route_design_detail_post_route_via_pillar_effort

Set opt effort/range for opportunistic via pillar

Type: string
Default: low
Edit: Yes
Reference: route_design_detail_post_route_via_pillar_effort

route_design_detail_post_route_wire_widen

widen wire in post route stage

Type: string
Default: none
Edit: Yes
Reference: route_design_detail_post_route_wire_widen

route_design_detail_post_route_wire_widen_rule

specify the rule used to widen wire

Type: string
Default: ""
Edit: Yes
Reference: route_design_detail_post_route_wire_widen_rule

route_design_detail_postroute_via_priority

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Set net priority for via swapping based on timing

Type: string
Default: auto
Edit: Yes
Reference: route_design_detail_postroute_via_priority

route_design_detail_search_and_repair

run search-and-repair step after the initial detailed routing

Type: bool
Default: true
Edit: Yes
Reference: route_design_detail_search_and_repair

route_design_detail_shield_with_high_effort

option for prevent big ratio drop between cts and signal route
Type: bool
Default: false
Edit: Yes
Reference: route_design_detail_shield_with_high_effort

route_design_detail_signoff_effort

specify when to give up on irresolvable violations

Type: string
Default: high
Edit: Yes
Reference: route_design_detail_signoff_effort

route_design_detail_use_multi_cut_via_effort

specify the effort to use multi-cut via during routing

Type: string
Default: low
Edit: Yes
Reference: route_design_detail_use_multi_cut_via_effort

route_design_diode_insertion_for_clock_nets

allow diode insertion on clock nets

Type: bool
Default: false
Edit: Yes
Reference: route_design_diode_insertion_for_clock_nets

route_design_enable_route_rule_si_limit_length

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use MAR wire length as NDR PRL requirement for metal spacing check
Type: string
Default: false
Edit: Yes
Reference: route_design_enable_route_rule_si_limit_length

route_design_enforce_route_rule_on_special_net_wire

enforce ndr rule on all special wire segments of specified nets

Type: string
Default: false
Edit: Yes
Reference: route_design_enforce_route_rule_on_special_net_wire

route_design_extra_via_enclosure

specify an extra via enclosure to use when connecting to block pins and special net wires
Type: double
Default: 0.0
Edit: Yes
Reference: route_design_extra_via_enclosure

route_design_fix_clock_nets

set clock nets routing status to fixed or routed

Type: bool
Default: false
Edit: Yes
Reference: route_design_fix_clock_nets

route_design_high_freq_constraint_groups

only route specified constraint groups, legal values are {net match bus pair shield}, add "order"
in front to control route order
Type: string
Default: ""
Edit: Yes
Reference: route_design_high_freq_constraint_groups

route_design_high_freq_match_report_file

specify match report file name

Type: string
Default: ""
Edit: Yes
Reference: route_design_high_freq_match_report_file

route_design_high_freq_num_reserved_layers

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number of layers reserved for standard cell pin access

Type: int
Default: 1
Edit: Yes
Reference: route_design_high_freq_num_reserved_layers

route_design_high_freq_remove_floating_shield

remove floating shield segments for high frequency nets

Type: bool
Default: false
Edit: Yes
Reference: route_design_high_freq_remove_floating_shield

route_design_high_freq_search_repair

run search and repair to remove violations, legal value is one of {auto false true only}
Type: string
Default: auto
Edit: Yes
Reference: route_design_high_freq_search_repair

route_design_high_freq_shield_trim_length

specify minimum length of shielding wire to be kept

Type: double
Default: 0.0
Edit: Yes
Reference: route_design_high_freq_shield_trim_length

route_design_honor_exclusive_region

honor exclusive region routing

Type: bool
Default: true
Edit: Yes
Reference: route_design_honor_exclusive_region

route_design_honor_power_domain

honor power domain routing

Type: bool
Default: false
Edit: Yes
Reference: route_design_honor_power_domain

route_design_ignore_antenna_top_cell_pin

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ignore antenna check on block I/O pins

Type: bool
Default: true
Edit: Yes
Reference: route_design_ignore_antenna_top_cell_pin

route_design_ignore_follow_pin_shapes

Ignore follow pin via shapes

Type: bool
Default: false
Edit: Yes
Reference: route_design_ignore_follow_pin_shapes

route_design_interposer_allow_diagonal_trunk

allow_diagonal_trunk
Type: string
Default: ""
Edit: Yes
Reference: route_design_interposer_allow_diagonal_trunk

route_design_interposer_interlayer_shielding_layers

interlayer shielding layers

Type: string
Default: ""
Edit: Yes
Reference: route_design_interposer_interlayer_shielding_layers

route_design_interposer_interlayer_shielding_nets

interlayer shielding nets

Type: string
Default: ""
Edit: Yes
Reference: route_design_interposer_interlayer_shielding_nets

route_design_interposer_interlayer_shielding_offsets

interlayer shielding offsets

Type: string
Default: ""
Edit: Yes
Reference: route_design_interposer_interlayer_shielding_offsets

route_design_interposer_interlayer_shielding_widths

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interlayer shielding widths

Type: string
Default: ""
Edit: Yes
Reference: route_design_interposer_interlayer_shielding_widths

route_design_interposer_same_layer_shielding_net

same_layer_shielding_net
Type: string
Default: ""
Edit: Yes

route_design_interposer_same_layer_shielding_width_spacing

same_layer_shielding_width_spacing
Type: string
Default: ""
Edit: Yes

route_design_interposer_trunk_routing_layers

trunk_routing_layers
Type: string
Default: ""
Edit: Yes

route_design_interposer_trunk_routing_width_spacing

trunk_routing_width_spacing
Type: string
Default: ""
Edit: Yes

route_design_number_fail_limit

set limit for number of fails

Type: int
Default: 0
Edit: Yes
Reference: route_design_number_fail_limit

route_design_number_thread

set the number of processors to be used in one workstation for multi-threading

Type: int
Default: 1
Edit: Yes
Reference: route_design_number_thread

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route_design_number_warning_limit

set limit for number of warnings

Type: int
Default: 0
Edit: Yes
Reference: route_design_number_warning_limit

route_design_process_node

Specify the process node

Type: string
Default: ""
Edit: Yes
Reference: route_design_process_node

route_design_rc_extraction_corner

specific which RC extraction corner to use in routing

Type: string
Default: ""
Edit: Yes
Reference: route_design_rc_extraction_corner

route_design_relaxed_route_rule_spacing_to_power_ground_nets

relax the spacing requirement from NDR spacing for the layers
Type: string
Default: none
Edit: Yes
Reference: route_design_relaxed_route_rule_spacing_to_power_ground_nets

route_design_reserve_space_for_multi_cut

Reserves space to insert multicut vias in postroute stage. This option has to be set before
routing. After routing with this parameter specified, you can add double-cut vias or larger
overhang vias by using the "route_design -via_opt" command. For examples, see
route_design.
Type: bool
Default: false
Edit: Yes
Reference: route_design_reserve_space_for_multi_cut

route_design_reverse_direction

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reverse routing direction in area: (lx ly ux uy [bot_lyr : top_lyr]) ... , top_lyr and bot_lyr could be
either layer name or layer routing id
Type: string
Default: ""
Edit: Yes
Reference: route_design_reverse_direction

route_design_route_clock_nets_first

route clock nets first

Type: bool
Default: true
Edit: Yes
Reference: route_design_route_clock_nets_first

route_design_selected_net_only

route selected net only

Type: bool
Default: false
Edit: Yes
Reference: route_design_selected_net_only

route_design_shield_crosstie_offset

Specifies the offset in terms of number of tracks for adding crossties. The default is 0 for all
layers. The syntax is 'layer_name:numTrack1 layer_name2:numTrack2... '.
Type: string
Default: ""
Edit: Yes
Reference: route_design_shield_crosstie_offset

route_design_shield_tap_cell_insertion

insert tap cell for shielding

Type: bool
Default: false
Edit: Yes
Reference: route_design_shield_tap_cell_insertion

route_design_shield_tap_cell_name

specify the tap cell names for shielding

Type: string
Default: ""
Edit: Yes

route_design_skip_analog

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skip routing nets or pins marked + USE ANALOG in the DEF file
Type: bool
Default: false
Edit: Yes
Reference: route_design_skip_analog

route_design_strict_honor_route_rule

Strictly enforce non-default rules

Type: string
Default: false
Edit: Yes
Reference: route_design_strict_honor_route_rule

route_design_stripe_layer_range

specify the target layer range of stripes for tie net connection
Type: string
Default: ""
Edit: Yes
Reference: route_design_stripe_layer_range

route_design_third_party_data

Allow third party data as input

Type: bool
Default: false
Edit: Yes
Reference: route_design_third_party_data

route_design_tieoff_to_shapes

specify the target special wire shapes or target instance pin for tie net connection: [auto stripe
ring powergroundpin]
Type: string
Default: auto
Edit: Yes
Reference: route_design_tieoff_to_shapes

route_design_trim_pull_back_distance_from_boundary

route_trim_pull_back_distance_from_boundary {<layer>:<value> ...}

Type: string
Default: ""
Edit: Yes
Reference: route_design_trim_pull_back_distance_from_boundary

route_design_trunk_with_cluster_target_size

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global control of trunk routing pattern for nets with TRUNK pattern attribute. 0: nets with
TRUNK pattern will be routed as Steiner tree; 1: default, nets will be routed as traditional trunk
pattern, i.e., each pin directly connects to SNET trunk separately; >1: define a proximate max
cluster size (in number of pins), and nets will be routed as fishbone style, i.e., several pins in a
column are clustered together, and then connects to SNET trunk.
Type: int
Default: 1
Edit: Yes
Reference: route_design_trunk_with_cluster_target_size

route_design_unconnected_ports

Route unconnected ports

Type: bool
Default: false
Edit: Yes
Reference: route_design_unconnected_ports

route_design_use_auto_via

allow to use internal generated vias

Type: string
Default: auto
Edit: Yes
Reference: route_design_use_auto_via

route_design_via_weight

set weight for vias

Type: string
Default: ""
Edit: Yes
Reference: route_design_via_weight

route_design_with_eco

enable eco routing

Type: bool
Default: false
Edit: Yes
Reference: route_design_with_eco

route_design_with_litho_driven

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enable the litho-driven routing

Type: bool
Default: false
Edit: Yes
Reference: route_design_with_litho_driven

route_design_with_si_driven

enable si driven routing

Type: bool
Default: false
Edit: Yes
Reference: route_design_with_si_driven

route_design_with_timing_driven

enable timing driven routing

Type: bool
Default: false
Edit: Yes
Reference: route_design_with_timing_driven

route_design_with_trim_metal

set cut metal dgrid for short pin extension generated

Type: string
Default: ""
Edit: Yes
Reference: route_design_with_trim_metal

route_design_with_via_in_pin

enclose via in pin shape

Type: string
Default: false
Edit: Yes
Reference: route_design_with_via_in_pin

route_design_with_via_only_for_block_cell_pin

enclose via in pin shape for macro cell pins

Type: string
Default: false
Edit: Yes
Reference: route_design_with_via_only_for_block_cell_pin

route_design_with_via_only_for_stdcell_pin

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disable planar access to standard cell pins

Type: string
Default: false
Edit: Yes
Reference: route_design_with_via_only_for_stdcell_pin

route_early_global_effort_level

Specifies the congestion effort level. Default is "standard", where congestion is more accurate
and runtime is larger. If set to "medium", runtime will be much smaller and congestion report
will have less accuracy. Setting to "low", it will be faster than "medium" however less accurate.
Type: enum
Enum Values: low medium standard
Default: standard
Edit: Yes
Reference: route_early_global_effort_level

route_early_global_honor_partition_allow_feedthru

Honor partition fences with feedthrough for <list_of_ptn_cell_names>.

Type: string
Default: ""
Edit: Yes
Reference: route_early_global_honor_partition_allow_feedthru

route_early_global_honor_partition_fence

Honor partition fences for <list_of_ptn_cell_names>.

Type: string
Default: ""
Edit: Yes
Reference: route_early_global_honor_partition_fence

route_early_global_honor_partition_pin

Honor partition fences and single-entry constraint for <list_of_ptn_cell_names>.

Type: string
Default: ""
Edit: Yes
Reference: route_early_global_honor_partition_pin

route_early_global_honor_partition_pin_guide

Honor partition pin guides. Default is true

Type: bool
Default: true
Edit: Yes
Reference: route_early_global_honor_partition_pin_guide

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route_early_global_honor_power_domain

consider MSV constraints while routing

Type: bool
Default: false
Edit: Yes
Reference: route_early_global_honor_power_domain

route_early_global_horizontal_supply_scale_factor

Horizontal supply scale factor

Type: double
Default: 1.0
Edit: Yes
Reference: route_early_global_horizontal_supply_scale_factor

route_early_global_num_tracks_per_clock_wire

Specify special number of tracks per clock wires.

Type: int
Default: 0
Edit: Yes
Reference: route_early_global_num_tracks_per_clock_wire

route_early_global_reverse_direction_regions

Reverse routing direction in the given region on the specified layer-range. Example: "(x1 y1 x2
y2) M1:M2 (x3 y3 x4 y4) M3:M4 ..."
Type: string
Default: ""
Edit: Yes
Reference: route_early_global_reverse_direction_regions

route_early_global_route_selected_net_only

Only route the nets which are selected in the DB.

Type: bool
Default: false
Edit: Yes
Reference: route_early_global_route_selected_net_only

route_early_global_secondary_pg

Specifies whether secondary PG pins needs to be routed or not

Type: bool
Default: false
Edit: Yes
Reference: route_early_global_secondary_pg

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route_early_global_secondary_pg_max_fanout

Specifies the max fanout limit for each secondary PG subnet

Type: int
Default: no_value
Edit: Yes
Reference: route_early_global_secondary_pg_max_fanout

route_early_global_stripe_layer_range

Route secondary PG pins to access to the PG stripes in the given layer range.
Type: string
Default: ""
Edit: Yes
Reference: route_early_global_stripe_layer_range

route_early_global_vertical_supply_scale_factor

Vertical supply scale factor

Type: double
Default: 1.0
Edit: Yes
Reference: route_early_global_vertical_supply_scale_factor

route_rules

All the route_rules. It is initialized from LEF NONDEFAULTRULES section or from OA

equivalents. It includes the reserved name "default" for the implicit LEF default rule or the OA
LEFDefaultRouteSpec. It also includes design specific route_rules from create_route_rule or
read in from DEF or an OA cellview.
Type: obj(route_rule)*
Default: ""
Edit: No

route_special_allow_non_preferred_direction_route

allow wrong way route

Type: bool
Default: false
Edit: Yes
Reference: route_special_allow_non_preferred_direction_route

route_special_avoid_over_core_row_layer

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specify number of layers to avoid routing over core row area

Type: string
Default: max layer of standard cell pin
Edit: Yes
Reference: route_special_avoid_over_core_row_layer

route_special_block_pin_connect_ring_pin_corners

Extend the ring pins at the corners

Type: bool
Default: false
Edit: Yes
Reference: route_special_block_pin_connect_ring_pin_corners

route_special_block_pin_route_with_pin_width

Connect using pin width only

Type: bool
Default: false
Edit: Yes
Reference: route_special_block_pin_route_with_pin_width

route_special_connect_broken_core_pin

Break followpin for standard cell pin or obs

Type: bool
Default: false
Edit: Yes
Reference: route_special_connect_broken_core_pin

route_special_core_pin_ignore_obs

ignore specified blockage when connecting follow pin

Type: enum
Enum Values: none placement_blockage overlap_obs block_halo
Default: none
Edit: Yes
Reference: route_special_core_pin_ignore_obs

route_special_core_pin_length

connect core pins of at least specified length

Type: double
Default: 0.0
Edit: Yes
Reference: route_special_core_pin_length

route_special_core_pin_length_as_inst

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connect core pins if their lengths are the same as the instances
Type: bool
Default: false
Edit: Yes
Reference: route_special_core_pin_length_as_inst

route_special_core_pin_max_via_scale

Maximum via width and height at stripe crossover for standcell pins (%)
Type: string
Default: ""
Edit: Yes
Reference: route_special_core_pin_max_via_scale

route_special_core_pin_merge_limit

gaps smaller than this variable cause followpin rails to be joined

Type: double
Default: 0.0
Edit: Yes
Reference: route_special_core_pin_merge_limit

route_special_core_pin_refer_to_follow_pin

M2 followpin generation uses follow pin wire

Type: bool
Default: false
Edit: Yes
Reference: route_special_core_pin_refer_to_follow_pin

route_special_core_pin_reference_macro

use specified macro as reference for followpin creation

Type: string
Default: ""
Edit: Yes
Reference: route_special_core_pin_reference_macro

route_special_core_pin_site_rail_width

follow pin width at layer for specified site

Type: string
Default: ""
Edit: Yes
Reference: route_special_core_pin_site_rail_width

route_special_core_pin_snap_to

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snap M2 followpin referred to M1 pin to position

Type: enum
Enum Values: m1_pin opt_routing_track grid half_grid
Default: m1_pin
Edit: Yes
Reference: route_special_core_pin_snap_to

route_special_core_pin_stop_route

Type: enum
Enum Values: RowEnd CellPinEnd
Default: RowEnd
Edit: Yes
Reference: route_special_core_pin_stop_route

route_special_endcap_as_core

route_special treat Endcap macro as Core macro

Type: bool
Default: false
Edit: Yes
Reference: route_special_endcap_as_core

route_special_extend_nearest_target

extend nearest target so that it can be connected

Type: bool
Default: false
Edit: Yes
Reference: route_special_extend_nearest_target

route_special_jog_threshold_ratio

distance ratio between a jogging target and a straight target

Type: double
Default: 10.0
Edit: Yes
Reference: route_special_jog_threshold_ratio

route_special_layer_non_preferred_direction_cost

layer cost of non-preferred direction

Type: string
Default: ""
Edit: Yes
Reference: route_special_layer_non_preferred_direction_cost

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route_special_layer_preferred_direction_cost

layer cost of preferred direction

Type: string
Default: ""
Edit: Yes
Reference: route_special_layer_preferred_direction_cost

route_special_pad_pin_min_via_size

Minimum via width percent between pad and ring.

Type: double
Default: 20.0
Edit: Yes
Reference: route_special_pad_pin_min_via_size

route_special_pad_pin_split

Split width and spacing for wide pad pins

Type: string
Default: ""
Edit: Yes
Reference: route_special_pad_pin_split

route_special_pad_ring_use_lef

Keep user LEF input for pad rings

Type: bool
Default: true
Edit: Yes
Reference: route_special_pad_ring_use_lef

route_special_pg_pin_as_signal

List of cell/pin information NOT extract from CPF

Type: string
Default: ""
Edit: Yes
Reference: route_special_pg_pin_as_signal

route_special_secondary_pin_max_gap

gaps bigger than this variable cause level shifter rail to break for them
Type: double
Default: 0.0
Edit: Yes
Reference: route_special_secondary_pin_max_gap

route_special_secondary_pin_rail_width

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width of followpin rail

Type: double
Default: 0.0
Edit: Yes
Reference: route_special_secondary_pin_rail_width

route_special_signal_pin_as_pg

signal pins as PG pins

Type: bool
Default: false
Edit: Yes
Reference: route_special_signal_pin_as_pg

route_special_split_long_via

Split vias longer than <threshold> into smaller vias with specified <step> and bottom/left end
<offset> and vertical/horizontal <height>
Type: string
Default: 0 0 -1 -1
Edit: Yes
Reference: route_special_split_long_via

route_special_target_number

number of target to connect

Type: int
Default: 0
Edit: Yes
Reference: route_special_target_number

route_special_target_search_distance

target search distance

Type: double
Default: 0.0
Edit: Yes
Reference: route_special_target_search_distance

route_special_time_limit

time limit (in seconds) that the router is allowed in routing each port
Type: double
Default: 0.0
Edit: Yes
Reference: route_special_time_limit

route_special_via_connect_to_shape

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Make via connection to specified shapes

Type: enum
Enum Values: padring ring stripe blockring blockpin coverpin noshape blockwire corewire
followpin iowire
Default: padring ring stripe blockring blockpin coverpin noshape blockwire corewire followpin
iowire
Edit: Yes
Reference: route_special_via_connect_to_shape

route_special_via_through_to_closest_ring

A via should connect only to closest ring layer when multiple rings overlap
Type: bool
Default: false
Edit: Yes
Reference: route_special_via_through_to_closest_ring

route_special_welltap_as_endcap

route_special treat Welltap macro as Endcap macro

Type: string
Default: ""
Edit: Yes
Reference: route_special_welltap_as_endcap

route_trial_max_print_ignored_pad_nets

Number of nets to be printed connecting a pad term to a fterm without geometry

Type: int
Default: 0
Edit: Yes
Reference: route_trial_max_print_ignored_pad_nets

route_types

All the route_types from create_route_type command.

Type: obj(route_type)*
Default: ""
Edit: No

rows

Short-cut for [get_db current_design .rows]

Type: obj(row)*
Default: ""
Edit: No

run_abstract_abstract_blockage_cut_around_pin

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For std cell, we do not want cover obs on pin. So:

If -input_cell_type {std}, setting the value to all metal and via layer name list.
If -input_cell_type {block} or -input_cell_type {io}, setting the value to all via layer name list.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_abstract_blockage_cut_around_pin

run_abstract_antenna_connectivity

Specifies the layers for which connectivity is to be extracted. The syntax is {<layer1>
<connect_layer> <layer2>}.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_antenna_connectivity

run_abstract_antenna_diffusion_geometry

Specifies diffusion layer, followed by expression to remove gate channel area from diffusion
region.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_antenna_diffusion_geometry

run_abstract_antenna_gate_geometry

Specifies poly layer that forms a gate, and then the layer expression to derive the gate area.
This option also triggers the creation of antenna models.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_antenna_gate_geometry

run_abstract_blockage_detailed_layers

Specifies the layers for which a detailed blockage model is to be created. The detailed
blockage model generates blockages only where there are real shapes in the cell on the layer.
This only applies to IO cells and block cells, it does not apply to standard cells.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_blockage_detailed_layers

run_abstract_boundary_layers

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By default this list is empty, and the prBoundary is used. The prBoundary comes from an
explicit GDS layer that is used to compute the LEF SIZE (and OVERLAP OBS shapes for
rectilinear boundaries). If there is no explicit GDS prBoundary layer, the boundary can be
computed from the bounding box of geometries on this list of layers. Note, this option is almost
never correct for core standard cells.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_boundary_layers

run_abstract_cell_symmetry

Specifies a property value for cell symmetry. The valid values for the property symmetry
include: {R0 | X | Y | R90 | X Y | X R90 | Y R90 | X Y R90}. Default {X Y}
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_cell_symmetry

run_abstract_export_lef_version

Version of LEF to export. The default version is the same as the version of technology LEF file
being imported.
Type: enum
Enum Values: 5.3 5.4 5.5 5.6 5.7 5.8
Default: 5.7
Edit: Yes
Reference: run_abstract_export_lef_version

run_abstract_extract_layers_power

Specifies the layers through which the extractor extracts each power net. This is used to
reduce the search space if abstract is taking too much run time for each cell. Usually not
applicable to standard cells. For blocks it is common to only extract the power nets on the top
one or two metal layers.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_extract_layers_power

run_abstract_extract_layers_signal

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Specifies the layers through which the extractor extracts each net. This is used to reduce the
search space if abstract is taking too much run time for each cell. Usually not applicable to
standard cells.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_extract_layers_signal

run_abstract_extract_pin_layers_power

Determines which of the shapes found by the extractor should be turned into pins. This
argument is valid only if the associated layer, geometry specification and connectivity have
been provided in the technology LEF. Usually not applicable to standard cells.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_extract_pin_layers_power

run_abstract_extract_pin_layers_signal

run_abstract_input_cell_type

Choose the cell type being translated with abstract. The tool adjusts its settings based on this
selection. Optional.
Type: enum
Enum Values: std io block
Default: std
Edit: Yes
Reference: run_abstract_input_cell_type

run_abstract_input_lef_tech_file

Input technology LEF file. This is used to get all the layer names, their types (routing, cut, etc.)
and the layer order for extracting connectivity. Required.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_input_lef_tech_file

run_abstract_input_stream_layer_map_file

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Specify the file that maps GDS layer number / data type to LEF layer names in the Virtuoso
format. Required.
For example, the gds file is not colorized, you could use the common virtuoso format gds
layer map to stream gds file.
#layer name #purpose name #stream layer #stream data type
V0 drawing 35 0
V0 drawing 35 235
V0 drawing 35 236
M1 drawing 15 0
M1 drawing 15 235
M1 drawing 15 236
M1 drawing 15 239
For example, the gds file is colorized, you could specify the mask color in gds layer map to
stream gds file.
#layer name #purpose name #stream layer #stream data type #photo mask color #color state
V0 drawing 35 0
V0 drawing 35 235 mask1Color unlocked
V0 drawing 35 236 mask2Color unlocked
M1 drawing 15 0
M1 drawing 15 235 mask1Color unlocked
M1 drawing 15 236 mask2Color unlocked
M1 drawing 15 239 mask3Color unlocked
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_input_stream_layer_map_file

run_abstract_keep_output_files

Do not clean up temporary files/libraries that are created in the process after command
finishes.
Type: bool
Default: false
Edit: Yes
Reference: run_abstract_keep_output_files

run_abstract_pins_analog_names

Identifies analog pin names based on label strings in the Abstract to set the LEF "USE
ANALOG" property. Enter a list of possible names for the analog pins. This can be a list of
regular expressions, each separated by a space.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_pins_analog_names

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run_abstract_pins_clock_names

Identifies clock pin names based on label strings in the Abstract to set the LEF "USE CLOCK"
property. Enter a list of possible names for the clock pins. This can be a list of regular
expressions, each separated by a space.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_pins_clock_names

run_abstract_pins_ground_names

Identifies ground pins based on label strings in the Abstract to set the LEF "USE GROUND"
property. Enter a list of possible names for the ground pins. This can be a list of regular
expressions, each separated by a space.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_pins_ground_names

run_abstract_pins_output_names

Identifies output pins based on label strings in the GDS to set the LEF direction to OUTPUT.
Enter a list of regular expressions separated by spaces.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_pins_output_names

run_abstract_pins_power_names

Identifies power pin names based on label strings in the Abstract to set the LEF "USE
POWER" property. Enter a list of possible names for the power pins. This can be a list of
regular expressions, each separated by a space.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_pins_power_names

run_abstract_pins_text_pin_map

Maps text labels to pins on nets. Specify the layer purpose pairs based on which you want the
abstract generator to search for geometry of any given layer-purpose pair with a text label.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_pins_text_pin_map

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run_abstract_pre_abstract_script

a skill file that will be executed in abstract before the auto-generated script is executed.
Optional.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_pre_abstract_script

run_abstract_selected_cells

Select cells to create abstract for using regex style expressions. Optional.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_selected_cells

run_abstract_site_name

Site to be used for macros. This site will be added to all the cells.
Type: string
Default: ""
Edit: Yes
Reference: run_abstract_site_name

run_abstract_verbose

Verbose mode with extra print.

Type: bool
Default: false
Edit: Yes
Reference: run_abstract_verbose

script_search_path

The variable provides a set of directories for the software to search for files that sourced using
the Tcl 'source' command. The software will search in each search path directory for the
specified file.
Type: string
Default: .
Edit: Yes
Reference: script_search_path

selected

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The list of currently selected objects. It can be set to a list of objects as long as they are
selectable.
Type: string
Default: ""
Edit: Yes
Reference: selected

set_db_verbose

Specifies additional messages are issued describing what attribute is being set on what
object.
Type: bool
Default: false
Edit: Yes
Reference: set_db_verbose

setup_views

Returns the information about the setup analysis views in the design.
Type: obj(analysis_view)*
Default: ""
Edit: No

si_accumulated_small_aggressor_factor

Specifies the multiplication factor that controls the effect of the cap mode accumulated small
attacker.
Type: double
Default: 1.0
Edit: Yes
Reference: si_accumulated_small_aggressor_factor

si_accumulated_small_aggressor_mode

Specifies the multiplication factor that controls the effect of the cap mode accumulated small
attacker.
Type: enum
Enum Values: cap current zero_mean
Default: ""
Edit: Yes
Reference: si_accumulated_small_aggressor_mode

si_accumulated_small_aggressor_threshold

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Specifies whether to use the current-matching based method for accumulated small attackers.
Type: double
Default: 10.01
Edit: Yes
Reference: si_accumulated_small_aggressor_threshold

si_aggressor_alignment

Specifies the attacker alignment.

Type: enum
Enum Values: path path_overlap timing_aware_edge
Default: path
Edit: Yes
Reference: si_aggressor_alignment

si_clock_synchronicity

Specifies the value above which the clock delta delay should be calculated.
Type: enum
Enum Values: asynchronous synchronous
Default: synchronous
Edit: Yes
Reference: si_clock_synchronicity

si_delay_clock_delta_threshold

Specifies the value above which the clock delta delay should be calculated.
Type: double
Default: -1.0
Edit: Yes
Reference: si_delay_clock_delta_threshold

si_delay_delta_annotation_mode

Calculates the delay for each arc (cell arc and net arc) in a path.
Type: enum
Enum Values: lumpedOnNet arc
Default: arc
Edit: Yes
Reference: si_delay_delta_annotation_mode

si_delay_delta_threshold

delta delay analysis threshold

Type: double
Default: -1.0
Edit: Yes
Reference: si_delay_delta_threshold

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si_delay_enable_double_clocking_check

Enables double clocking check in AAE.

Type: enum
Enum Values: true false
Default: false
Edit: Yes
Reference: si_delay_enable_double_clocking_check

si_delay_enable_logical_correlation

Enables the AAE-SI logical correlation.

Type: enum
Enum Values: true false
Default: false
Edit: Yes
Reference: si_delay_enable_logical_correlation

si_delay_enable_report

Enables SI delay reports.

Type: bool
Default: false
Edit: Yes
Reference: si_delay_enable_report

si_delay_separate_on_data

Separates the delta delay on data (delta delay is always separated for clock).
Type: string
Default: false
Edit: Yes
Reference: si_delay_separate_on_data

si_enable_bus_attacker_correlation

Type: bool
Default: false
Edit: Yes
Reference: si_enable_bus_attacker_correlation

si_enable_drv_with_delta_slew

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Enables SI slews reporting.

Type: bool
Default: false
Edit: Yes
Reference: si_enable_drv_with_delta_slew

si_enable_glitch_overshoot_undershoot

Enables overshoot/undershoot analysis and reporting.

Type: bool
Default: false
Edit: Yes
Reference: si_enable_glitch_overshoot_undershoot

si_enable_glitch_propagation

Enables glitch propagation and driver weakening through single stage cells.
Type: bool
Default: false
Edit: Yes
Reference: si_enable_glitch_propagation

si_enable_glitch_propagation_spice_deck

Enables glitch propagation in spice deck.

Type: bool
Default: false
Edit: Yes
Reference: si_enable_glitch_propagation_spice_deck

si_enable_two_stage_driver_weakening

Type: bool
Default: true
Edit: Yes
Reference: si_enable_two_stage_driver_weakening

si_enable_user_defined_bus_merging

Enables bus merging feature - if a net is in two groups, then the groups are merged
Type: bool
Default: false
Edit: Yes

si_enable_virtual_attacker_constituent_report

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Type: bool
Default: false
Edit: Yes
Reference: si_enable_virtual_attacker_constituent_report

si_glitch_constrained_input_threshold_failure_point

Type: enum
Enum Values: input both
Default: input
Edit: Yes
Reference: si_glitch_constrained_input_threshold_failure_point

si_glitch_enable_dynamic_receiver_peak_limits

Type: bool
Default: false
Edit: Yes
Reference: si_glitch_enable_dynamic_receiver_peak_limits

si_glitch_enable_report

Enables AAE SI glitch analysis.

Type: bool
Default: false
Edit: Yes
Reference: si_glitch_enable_report

si_glitch_input_threshold

Specifies the input glitch failure threshold value during AAE analysis.
Type: double
Default: 0.4
Edit: Yes
Reference: si_glitch_input_threshold

si_glitch_input_voltage_high_threshold

Specifies the input glitch vh failure threshold value during AAE analysis.
Type: double
Default: 0.4
Edit: Yes
Reference: si_glitch_input_voltage_high_threshold

si_glitch_input_voltage_low_threshold

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Specifies the input glitch vl failure threshold value during AAE analysis.
Type: double
Default: 0.4
Edit: Yes
Reference: si_glitch_input_voltage_low_threshold

si_glitch_receiver_clock_peak_limit

Defines the glitch check limit for clock inputs in receiver peak mode. This parameter is
specified as a ratio of vdd.
Type: double
Default: 0.05
Edit: Yes
Reference: si_glitch_receiver_clock_peak_limit

si_glitch_receiver_latch_peak_limit

Defines the glitch check limit for latch inputs in receiver peak mode. This parameter is
specified as a ratio of vdd.
Type: double
Default: 0.1
Edit: Yes
Reference: si_glitch_receiver_latch_peak_limit

si_glitch_receiver_peak_limit

Defines the receiver peak/glitch peak limit at all nodes. The value specified for this parameter
is a ratio of vdd.
Type: double
Default: 0.15
Edit: Yes
Reference: si_glitch_receiver_peak_limit

si_individual_aggressor_clock_threshold

Sets the glitch tolerance for individual attacker nets on victim clock nets.
Type: double
Default: 0.015
Edit: Yes
Reference: si_individual_aggressor_clock_threshold

si_individual_aggressor_simulation_filter

Enables electrical filtering based on attackers' simulated glitch peaks.

Type: bool
Default: true
Edit: Yes
Reference: si_individual_aggressor_simulation_filter

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si_individual_aggressor_threshold

AAE virtual attacker threshold

Type: double
Default: 0.015
Edit: Yes
Reference: si_individual_aggressor_threshold

si_max_virtual_attacker_constituents

Type: int
Default: 5
Edit: Yes
Reference: si_max_virtual_attacker_constituents

si_nonlinear_aggressor_slew

Uses a non-linear attacker. If set to false , it uses a linear attacker.

Type: enum
Enum Values: true false
Default: true
Edit: Yes
Reference: si_nonlinear_aggressor_slew

si_num_iteration

Specifies the maximum number of timing window iterations that should be performed during SI
delay analysis.
Type: int
Default: 2
Edit: Yes
Reference: si_num_iteration

si_pessimistic_mode

Pessimistic Mode Settings

Type: enum
Enum Values: advanced reduced_optimism reduced_pessimism increased_pessimism
high_pessimism
Default: advanced
Edit: Yes
Reference: si_pessimistic_mode

si_reselection

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Specifies the SI reselection criteria during timing window iterations.

Type: enum
Enum Values: delta_delay slack xcap_ratio
Default: slack
Edit: Yes
Reference: si_reselection

si_reselection_delay_threshold

Allows to change the delay reselection criteria.

Type: double
Default: 1e-11
Edit: Yes
Reference: si_reselection_delay_threshold

si_reselection_hold_slack

Specifies the slack reselection threshold for hold.

Type: double
Default: -1e-12
Edit: Yes
Reference: si_reselection_hold_slack

si_reselection_setup_slack

Specifies the slack reselection threshold for setup.

Type: double
Default: -1e-12
Edit: Yes
Reference: si_reselection_setup_slack

si_secondary_attacker_decoupling_factor

Specifies decoupling factor for secondary aggressors.

Type: double
Default: 1.0
Edit: Yes
Reference: si_secondary_attacker_decoupling_factor

si_skip_noise_model_check

Specifies a list of pins for which noise model check will not take place.
Type: string
Default: ""
Edit: Yes
Reference: si_skip_noise_model_check

si_skip_timing_window

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Specifies the list of nets for which timing window is to be skipped.

Type: string
Default: ""
Edit: Yes
Reference: si_skip_timing_window

si_switch_probability

Sets the attacker switching probability.

Type: double
Default: 0.3
Edit: Yes
Reference: si_switch_probability

si_unconstrained_net_use_infinite_timing_window

Specifies that unconstrained nets will have an infinite timing window.

Type: enum
Enum Values: true false
Default: true
Edit: Yes
Reference: si_unconstrained_net_use_infinite_timing_window

si_use_infinite_timing_window

Type: enum
Enum Values: true false
Default: false
Edit: Yes
Reference: si_use_infinite_timing_window

sites

All the sites defined in LEF or OA.

Type: obj(site)*
Default: ""
Edit: No

skew_groups

list of skew_group
Type: obj(skew_group)*
Default: ""
Edit: No
Reference: skew_groups

soft_stack_size_limit

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Soft stacksize limit in mbytes. When the tool is launched, auto-enlarge the soft stacksize limit
to 0.2%RAM. If 0.2%RAM is larger than hard limit, set to the hard limit.
Type: string
Default: 8
Edit: Yes
Reference: soft_stack_size_limit

source_continue_on_error

Enable/Disable 'source' to continue the script on TCL_ERROR. If true, the source command
will ignore Tcl errors, and continue processing the script files. If false, a Tcl error will halt the
script.
Type: bool
Default: false
Edit: Yes
Reference: source_continue_on_error

source_echo_filename

This will display 'sourcing a.tcl' after a 'source $file' command in the log file. This is useful to
see the actual filename rather than the Tcl variable name. It is ignored if source_verbose is
true, since that will also write out the filename anyway. Type 'man log_file' for more details.
Type: bool
Default: false
Edit: Yes
Reference: source_echo_filename

source_verbose

Writes out each command inside the source script to the log and cmd files. Type 'man log_file'
for more details.
Type: bool
Default: true
Edit: Yes
Reference: source_verbose

source_verbose_line_length_limit

Limits the command printed to stdout and the .log file to the specified number of characters for
verbose script source. This is normally only needed if you log commands "post Tcl expansion"
when long Tcl lists may occur in the command args. Type 'man log_file' for more details.
Type: int
Default: -1
Edit: Yes
Reference: source_verbose_line_length_limit

stack_via_rules

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The stack_via_rules available in this design from the LEF or create_stack_via_rules.

Type: obj(stack_via_rule)*
Default: {}
Edit: No

tcl_partial_cmd_argument_matching

Use this switch to control command argument partial matching as well as enum value partial
matching. When it's turned on, argument '-opt' will match '-option' if no other argument name
begins with -opt. Default is 'quiet', which means to silently allow partial-matching when there's
no ambiguity. 'warn' means allow partial-matching with a warning message. 'error' means to
disable partial-matching, and error out.
Type: enum
Enum Values: quiet warn error
Default: quiet
Edit: Yes
Reference: tcl_partial_cmd_argument_matching

tcl_return_display_length_limit

Limits the number of characters displayed to stdout and the .log file. The Tcl return value itself
is not affected--only the display is truncated. A value of -1 indicates that there is no display
limit. This is useful to limit the output to the display of any command that can return long lists of
objects or values.
Type: int
Default: 10000
Edit: Yes
Reference: tcl_return_display_length_limit

tech_db_units

Database units per micron from LEF or OA techfile, unless init_min_dbu_per_micron is larger.
Type: int
Default: ""
Edit: No
Reference: tech_db_units

tech_finfet_grid_direction

An enum value indicating the direction of the finfet grid from the LEF FINFET statement or OA.
Type: enum
Enum Values: vertical horizontal
Default: vertical
Edit: Yes
Reference: tech_finfet_grid_direction

tech_finfet_grid_offset

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The finfet grid offset from 0 in microns from the LEF FINFET statement or OA.
Type: coord
Default: no_value
Edit: Yes
Reference: tech_finfet_grid_offset

tech_finfet_grid_pitch

Returns a single floating point number indicating the pitch of the FINFET grid as described in
LEF.
Type: coord
Default: no_value
Edit: Yes
Reference: tech_finfet_grid_pitch

tech_inst_mask_shift_layers

Ordered list of layer pointers to layers that allow instance mask shifting. This is the list of
layers that will show up in the DEF COMPONENTMASK statement for layers that can have
mask values shifted in standard cells.
Type: obj(layer)*
Default: ""
Edit: No
Reference: tech_inst_mask_shift_layers

tech_mfg_grid

Manufacturing grid from LEF or OA techfile. Note, this is the default value for each layer, but it
can be overridden for specific layers. In some technologies the mfg_grid for higher metal
layers is coarser than for the lower layers.
Type: coord
Default: ""
Edit: No
Reference: tech_mfg_grid

texts

Short-cut to all the text objects in the current_design.

Type: obj(text)
Default: ""
Edit: No

timing_all_registers_include_icg_cells

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Controls whether to include ICG cells as register in all_registers -edge_triggered

Type: bool
Default: true
Edit: Yes
Reference: timing_all_registers_include_icg_cells

timing_allow_input_delay_on_clock_source

When set to true allows you to apply input delay constraints on a pin where a clock was
previously asserted
Type: bool
Default: false
Edit: Yes
Reference: timing_allow_input_delay_on_clock_source

timing_analysis_aocv

AOCV Analysis
Type: bool
Default: false
Edit: Yes
Reference: timing_analysis_aocv

timing_analysis_async_checks

Async checks
Type: enum
Enum Values: async no_async async_only
Default: async
Edit: Yes
Reference: timing_analysis_async_checks

timing_analysis_case_analysis

caseAnalysis
Type: bool
Default: true
Edit: Yes
Reference: timing_analysis_case_analysis

timing_analysis_check_type

Report Violations for hold, setup

Type: enum
Enum Values: setup hold
Default: setup
Edit: Yes
Reference: timing_analysis_check_type

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timing_analysis_clock_gating

clockGatingCheck
Type: bool
Default: true
Edit: Yes
Reference: timing_analysis_clock_gating

timing_analysis_clock_net_marking_mode

clkNetsMarking
Type: enum
Enum Values: before_constant_propagation after_constant_propagation
Default: before_constant_propagation
Edit: Yes
Reference: timing_analysis_clock_net_marking_mode

timing_analysis_clock_propagation_mode

Timing arc attributes effect on timing analysis

Type: enum
Enum Values: sdc_control forced_ideal
Default: sdc_control
Edit: Yes
Reference: timing_analysis_clock_propagation_mode

timing_analysis_clock_source_paths

clkSrcPath
Type: bool
Default: true
Edit: Yes
Reference: timing_analysis_clock_source_paths

timing_analysis_cppr

Removes pessimism from clock paths that have a portion of the clock network in common
between the clock source and clock destination paths
Type: enum
Enum Values: both none setup hold
Default: none
Edit: Yes
Reference: timing_analysis_cppr

timing_analysis_enable_transistor_mode

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If true, ebnables the transistor level timing analysis mode

Type: bool
Default: false
Edit: Yes

timing_analysis_engine

Statistical or Static or Rql

Type: enum
Enum Values: statistical static rql
Default: static
Edit: Yes
Reference: timing_analysis_engine

timing_analysis_honor_active_logic_view

Honor Active Logic View

Type: bool
Default: false
Edit: Yes
Reference: timing_analysis_honor_active_logic_view

timing_analysis_precision_ps

Control delay precision 0.1ps or 0.01ps

Type: double
Default: 0.01
Edit: Yes
Reference: timing_analysis_precision_ps

timing_analysis_self_loops_paths_no_skew

Eliminates clock skew due to clock uncertainty for a path starting and ending at the same
register. If the clock skew is not eliminated, the timing for such paths is pessimistic
Type: bool
Default: false
Edit: Yes
Reference: timing_analysis_self_loops_paths_no_skew

timing_analysis_socv

SOCV Analysis
Type: bool
Default: false
Edit: Yes
Reference: timing_analysis_socv

timing_analysis_type

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Single or BCWC or OCV TimingAnalysis type

Type: enum
Enum Values: single best_case_worst_case ocv
Default: best_case_worst_case
Edit: Yes
Reference: timing_analysis_type

timing_aocv_analysis_mode

Controls handling of AOCV analysis modes

Type: enum
Enum Values: launch_capture clock_only separate_data_clock combine_launch_capture
Default: launch_capture
Edit: Yes
Reference: timing_aocv_analysis_mode

timing_aocv_chip_size

Specifies the diagonal length of the chip, in microns

Type: double
Default: 1e+30
Edit: Yes
Reference: timing_aocv_chip_size

timing_aocv_core_size

Specifies the diagonal length of the core area, in microns

Type: double
Default: 1e+30
Edit: Yes
Reference: timing_aocv_core_size

timing_aocv_derate_mode

Controls the AOCV derating mode

Type: enum
Enum Values: aocv_multiplicative aocv_additive
Default: aocv_multiplicative
Edit: Yes
Reference: timing_aocv_derate_mode

timing_aocv_slack_threshold

Analyze aocv slack based at specified threshold

Type: double
Default: 0.0
Edit: Yes

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timing_aocv_stage_count_update_on_timing_reset

When set to true, the aocv stage counts are recalculated when timing is reset.
Type: bool
Default: false
Edit: Yes
Reference: timing_aocv_stage_count_update_on_timing_reset

timing_apply_check_derate_to_external_output_delay

Applies check derate to output external delay

Type: bool
Default: false
Edit: Yes
Reference: timing_apply_check_derate_to_external_output_delay

timing_apply_default_primary_input_assertion

When set to true, primary input and bidirectional ports that do not have an explicit arrival time
specified are provided a default arrival time
Type: bool
Default: true
Edit: Yes
Reference: timing_apply_default_primary_input_assertion

timing_apply_exceptions_to_data_check_related_pin

When set to true, any false path assertion which blocks the data path to the related (-from) pin
of the data-to-data check also causes the check to be disabled
Type: bool
Default: true
Edit: Yes
Reference: timing_apply_exceptions_to_data_check_related_pin

timing_apply_setup_hold_exceptions_to_data_check_related_pin

When set to false, application of path exception with only -setup/hold on reference path
doesn't affect signal path
Type: bool
Default: true
Edit: Yes
Reference: timing_apply_setup_hold_exceptions_to_data_check_related_pin

timing_cap_unit

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If set, this value is passed to set_library_unit -cap to set the capacitance units used in timing
library and .sdc files and timing reports. Legal values are 1pf and 1ff.
Type: string
Default: ""
Edit: Yes
Reference: timing_cap_unit

timing_case_analysis_for_icg_propagation

Determines whether constant propagation continues through integrated clock gating (ICG)
cells
Type: enum
Enum Values: false require_seq_prop always
Default: false
Edit: Yes
Reference: timing_case_analysis_for_icg_propagation

timing_case_analysis_for_sequential_propagation

When set to true, calculates constants on the outputs of sequential elements

Type: bool
Default: false
Edit: Yes
Reference: timing_case_analysis_for_sequential_propagation

timing_case_analysis_propagation

Overrides sequential and ICG propagation behaviors.

Type: bool
Default: true
Edit: Yes
Reference: timing_case_analysis_propagation

timing_check_timing_report_all_checks

Enables reporting of all checks performed by check_timing

Type: bool
Default: false
Edit: Yes
Reference: timing_check_timing_report_all_checks

timing_check_timing_signal_level_high_to_low_threshold

Threshold for warnig about difference in signal level between hight_drv and low_rcv
Type: double
Default: 0.0
Edit: Yes
Reference: timing_check_timing_signal_level_high_to_low_threshold

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timing_check_timing_signal_level_low_to_high_threshold

Threshold for warnig about difference in signal level between low_drv and high_rcv
Type: double
Default: 0.0
Edit: Yes
Reference: timing_check_timing_signal_level_low_to_high_threshold

timing_clock_phase_propagation

Lets you select appropriate clock phases at register clock pins when both positive and
negative phases of the same clock signal are seen in the clock network
Type: enum
Enum Values: positive negative both
Default: both
Edit: Yes
Reference: timing_clock_phase_propagation

timing_clock_source_paths_unconstrained_mark_clock_used_as_data

global is set to true, is_clock_used_as_data returns true for unconstrained clock source
network
Type: bool
Default: true
Edit: Yes
Reference: timing_clock_source_paths_unconstrained_mark_clock_used_as_data

timing_clock_source_use_driving_cell

When set to false, the create_clock command for output pins of cells uses default slew instead
of the propagated slew from the primary input ports
Type: bool
Default: true
Edit: Yes
Reference: timing_clock_source_use_driving_cell

timing_clock_uncertainty_from_to_precedence

Gives higher precedence to clock-to-clock uncertainty when set to true

Type: bool
Default: false
Edit: Yes
Reference: timing_clock_uncertainty_from_to_precedence

timing_collection_all_fanin_fanout_traversal_mode

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Controls the way software processes netlist for all_fanin/all_fanout command processing
Type: enum
Enum Values: hierarchical flat
Default: flat
Edit: Yes
Reference: timing_collection_all_fanin_fanout_traversal_mode

timing_collection_result_display_limit

Limits the number of objects of a collection to be displayed in the output report

Type: int
Default: 100
Edit: Yes
Reference: timing_collection_result_display_limit

timing_collection_variable_assignment_compatibility

Enables printing names of output of get objects commands when set to false
Type: bool
Default: true
Edit: Yes
Reference: timing_collection_variable_assignment_compatibility

timing_conditions

Returns the information about the timing conditions in the design.

Type: obj(timing_condition)*
Default: ""
Edit: No

timing_constraint_disable_min_max_input_delay_worst_casing

Used for disabling the override of -max value from -min value in set_input_delay.
Type: bool
Default: false
Edit: Yes
Reference: timing_constraint_disable_min_max_input_delay_worst_casing

timing_constraint_enable_detailed_report_invalid_begin_end_points

Enables detailed reporting of invalid begin points/end points specified with

set_false_path/set_multicycle_path constraints else only checks structural end points
Type: bool
Default: false
Edit: Yes
Reference: timing_constraint_enable_detailed_report_invalid_begin_end_points

timing_constraint_enable_drv_limit_override

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Enables support of drv override flow

Type: bool
Default: false
Edit: Yes
Reference: timing_constraint_enable_drv_limit_override

timing_constraint_enable_logging

Enables dumping of constraint command in log file

Type: bool
Default: false
Edit: Yes
Reference: timing_constraint_enable_logging

timing_constraint_enable_report_invalid_begin_end_points

Enables reporting of invalid begin points/end points specified with

set_false_path/set_multicycle_path constraints
Type: bool
Default: false
Edit: Yes
Reference: timing_constraint_enable_report_invalid_begin_end_points

timing_constraint_enable_search_path

Enable searching of constraint files in search_path directory variable

Type: bool
Default: false
Edit: Yes
Reference: timing_constraint_enable_search_path

timing_constraint_enable_separate_multicycle_data_checks

When set to true, disables multicycle path constraint application on data checks
Type: bool
Default: false
Edit: Yes
Reference: timing_constraint_enable_separate_multicycle_data_checks

timing_constraint_path_delay_exclude_check_delay_from_ignore_clock_latency

Excludes check delays from set_max/min_delay -ignore_clock_latency slack computation

Type: bool
Default: false
Edit: Yes
Reference: timing_constraint_path_delay_exclude_check_delay_from_ignore_clock_latency

timing_constraint_path_delay_exclude_io_delay_from_ignore_clock_latency

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Excludes input/output delays from set_max/min_delay -ignore_clock_latency slack

computation
Type: bool
Default: false
Edit: Yes
Reference: timing_constraint_path_delay_exclude_io_delay_from_ignore_clock_latency

timing_constraint_path_delay_exclude_unconstrained_endpoints

When set to true, does not constrain unconstrained path with path delay.
Type: bool
Default: false
Edit: Yes
Reference: timing_constraint_path_delay_exclude_unconstrained_endpoints

timing_constraint_path_delay_include_clock_pin_endpoints

When set to true, considers register clock pins as endpoint's for path delay constraints applied
upstream
Type: bool
Default: false
Edit: Yes
Reference: timing_constraint_path_delay_include_clock_pin_endpoints

timing_constraint_warn_for_timing_derate_exceeding_max_limit

Sets the limit on derate value for giving the warning in case the larger derate is applied
Type: double
Default: 100.0
Edit: Yes
Reference: timing_constraint_warn_for_timing_derate_exceeding_max_limit

timing_constraints_warning_on_partial_search_match

Display Warning in case of partial success/failure while fetching objects in certain constraints
Type: bool
Default: false
Edit: Yes

timing_continue_on_error

When set to true, directs software to skip the error and continue processing when an error
occurs during timing analysis
Type: bool
Default: false
Edit: Yes
Reference: timing_continue_on_error

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timing_cppr_enable_mismatch_transition_mode

Enables CPPR compatibility mode when transitions mismatch at the common pin
Type: bool
Default: false
Edit: Yes

timing_cppr_opposite_edge_mean_scale_factor

Controls mean delay component for CPPR credit for opposite transition edges at common pin
Type: double
Default: 1.0
Edit: Yes
Reference: timing_cppr_opposite_edge_mean_scale_factor

timing_cppr_opposite_edge_sigma_scale_factor

Controls sigma delay component for CPPR credit for opposite transition edges at common pin
Type: double
Default: 1.0
Edit: Yes
Reference: timing_cppr_opposite_edge_sigma_scale_factor

timing_cppr_opposite_edge_sigma_scale_factor_cell

Controls cell sigma delay component for CPPR credit for opposite transition edges at common
pin
Type: double
Default: 1.0
Edit: Yes
Reference: timing_cppr_opposite_edge_sigma_scale_factor_cell

timing_cppr_opposite_edge_sigma_scale_factor_net

Controls net sigma delay component for CPPR credit for opposite transition edges at common
pin
Type: double
Default: 1.0
Edit: Yes
Reference: timing_cppr_opposite_edge_sigma_scale_factor_net

timing_cppr_propagate_thru_latches

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When set to true, the cppr of a timing path crossing a latch (or latches) is calculated using the
common pin of its origin flop and the capture device at the end of the path. Otherwise the usual
segment-based cppr calculation is performed. This cppr setting is considered only when the
latch thru analysis mode is enabled.
Type: bool
Default: false
Edit: Yes
Reference: timing_cppr_propagate_thru_latches

timing_cppr_remove_clock_to_data_pessimism

When set to true, removes clock reconvergence pessimism (CRP) for clock source paths
Type: bool
Default: false
Edit: Yes
Reference: timing_cppr_remove_clock_to_data_pessimism

timing_cppr_self_loop_mode

When set to true in case of self-loop paths, computes CPPR adjustment by taking the
difference between early and late clock arrival time of the common point
Type: bool
Default: true
Edit: Yes
Reference: timing_cppr_self_loop_mode

timing_cppr_skip_clock_reconvergence

Specifies the branch point to use for computing clock path pessimism removal (CPPR)
adjustment when there is reconvergence in the clock tree
Type: bool
Default: false
Edit: Yes
Reference: timing_cppr_skip_clock_reconvergence

timing_cppr_skip_clock_reconvergence_for_unmatched_clocks

When set to true, this enables CPPR branch point search in reconverging clock tree only
when launching and capturing clocks are different.
Type: bool
Default: false
Edit: Yes
Reference: timing_cppr_skip_clock_reconvergence_for_unmatched_clocks

timing_cppr_threshold_ps

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Specifies the maximum amount of pessimism that clock path pessimism removal (CPPR)
analysis is allowed to leave in the path
Type: double
Default: 20.0
Edit: Yes
Reference: timing_cppr_threshold_ps

timing_cppr_transition_sense

Specifies the transition sense of the launching and capturing clocksat the common node, to
calculate clock path pessimism removal (CPPR)
Type: enum
Enum Values: normal same_transition same_transition_expanded
Default: normal
Edit: Yes
Reference: timing_cppr_transition_sense

timing_create_clock_default_propagated

Enables clocks to be created in propagated mode

Type: bool
Default: false
Edit: Yes
Reference: timing_create_clock_default_propagated

timing_default_opcond_per_lib

When set to true, use default operating conditions for each lib
Type: bool
Default: true
Edit: Yes
Reference: timing_default_opcond_per_lib

timing_defer_mmmc_obj_updates

You can set the timing_defer_mmmc_object_updates global to true, so that the software
allows a sequence of MMMC updates to be accumulated before new data is loaded and
analyzed
Type: bool
Default: false
Edit: Yes
Reference: timing_defer_mmmc_obj_updates

timing_derate_aocv_dynamic_delays

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This global controls whether or not AOCV derating factors are applied to the dynamic, SI-
induced delay component or not. With a value of '1', the AOCV derating factor will be applied
to both the static and dynamic components of the delay arc. When set to '0', the AOCV derate
will only apply to the static component of the delay.
Type: bool
Default: true
Edit: Yes
Reference: timing_derate_aocv_dynamic_delays

timing_derate_aocv_reference_point

Allows specification of reference point for AOCV factors

Type: int
Default: 1
Edit: Yes
Reference: timing_derate_aocv_reference_point

timing_derate_dynamic_compatibility

This global controls how the set_timing_derate factors that are not specified using either -
static or -dynamic options are applied to the delay. When this global is set to '1' the behavior
will be compatible with previous releases. In this mode, the static and dynamic components
will be summed before applying derating. With a setting of '0', the static and dynamic
components will be derated separately and then combined. A setting of '0' is equivalent to
using separate derate assertions with the -dynamic and -static options explicitly specified.
Type: bool
Default: true
Edit: Yes
Reference: timing_derate_dynamic_compatibility

timing_derate_incremental_adjust_additive_mode

By default or with a setting of 'false', successive application of incremental derating using the -
increment option (or deprecated -incremental_adjust option) will overwrite any existing derate
value with the new value. When this global is set to 'true', successive application of the
derates will be accumulated into a final derate value.
Type: bool
Default: false
Edit: Yes
Reference: timing_derate_incremental_adjust_additive_mode

timing_derate_negative_delay_backward_compatibility

Type: bool
Default: true
Edit: Yes

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timing_derate_ocv_reference_point

Allows specification of reference point for OCV factors

Type: int
Default: 1
Edit: Yes
Reference: timing_derate_ocv_reference_point

timing_derate_spatial_distance_unit

Set the distance unit.

Type: enum
Enum Values: default 1um 1nm
Default: default
Edit: Yes
Reference: timing_derate_spatial_distance_unit

timing_disable_bus_contention_check

Checks for setup and hold violations in three-state bus designs

Type: bool
Default: false
Edit: Yes
Reference: timing_disable_bus_contention_check

timing_disable_clock_period_checks

When set to true, disables timing model clock period checks during timing analysis
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_clock_period_checks

timing_disable_constant_propagation_for_sequential_cells

When set to true, disables constant prop. across sequential cells if sequential_prop global is
false
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_constant_propagation_for_sequential_cells

timing_disable_drv_report_on_constant_nets

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Disables DRV checks for nets having disabled constant propagation:

Type: bool
Default: false
Edit: Yes
Reference: timing_disable_drv_report_on_constant_nets

timing_disable_floating_bus_check

When set to true, disables propagation of minimum delay through three state disable timing
arcs and maximum delay through three state enable arcs. These checks are only valid during
floating bus conditions
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_floating_bus_check

timing_disable_genclk_combinational_blocking

Disables blocking of generated clocks with '-combinational' option which are downstream of
another generated clock
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_genclk_combinational_blocking

timing_disable_inferred_clock_gating_checks

When set to true, disables clock gating checks that are inferred on combinational elements in
the clock path. Explicit clock gating checks that are described in the timing library are not
affected by this global variable
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_inferred_clock_gating_checks

timing_disable_inout_output_side_timing_checks

When set to false, timing checks on both the input and output sides of the bidirectional pin are
analyzed
Type: bool
Default: true
Edit: Yes
Reference: timing_disable_inout_output_side_timing_checks

timing_disable_internal_inout_cell_paths

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When set to false, enables internal bidirectional feedback paths that are completely contained
in one instance
Type: bool
Default: true
Edit: Yes
Reference: timing_disable_internal_inout_cell_paths

timing_disable_internal_inout_net_arcs

When set to true, this global disables internal bidirectional feedback paths that span multiple
instances
Type: bool
Default: true
Edit: Yes
Reference: timing_disable_internal_inout_net_arcs

timing_disable_lib_pulse_width_checks

When set to true, disables timing model pulse width checks during timing analysis
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_lib_pulse_width_checks

timing_disable_library_data_to_data_checks

When set to true, this global disables data-to-data checks that are coded in the library as non-
sequential timing checks
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_library_data_to_data_checks

timing_disable_library_tieoffs

Disables constant functions in a library

Type: bool
Default: false
Edit: Yes
Reference: timing_disable_library_tieoffs

timing_disable_netlist_constants

When set to true, ignores constants defined in the Verilog netlist

Type: bool
Default: false
Edit: Yes
Reference: timing_disable_netlist_constants

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timing_disable_nochange_checks

When set to true, disables no change timing model checks during timing analysis
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_nochange_checks

timing_disable_non_sequential_checks

When set to true, disables the timing arcs between any data-to-clock or clock-to-clock checks
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_non_sequential_checks

timing_disable_output_as_clock_port

Controls clock to output port to be treated as data or clock irrespective of constraints set on the
port
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_output_as_clock_port

timing_disable_parallel_arcs

to control enabling/disabling both CTE's parallel arc reduction, and the related task
compression on the AAE side. Setting this variable to 'true' should yield AAE task
compression mode '2'. Setting it to 'false' will result in task compression mode '0'
Type: bool
Default: true
Edit: Yes

timing_disable_pulse_width_same_edge_si_cppr_mode

Enables SI CPPR credit up to the last divergent pin for pulse width checks for zero width pulse
clocks
Type: bool
Default: true
Edit: Yes
Reference: timing_disable_pulse_width_same_edge_si_cppr_mode

timing_disable_report_header_info

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Controls whether timing reports are generated using a common report header.
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_report_header_info

timing_disable_retime_clock_path_slew_propagation

Controls whether analysis is performed on data or clock paths

Type: bool
Default: true
Edit: Yes
Reference: timing_disable_retime_clock_path_slew_propagation

timing_disable_sdf_retain_arc_merging

Controls handling of retain arcs in SDF2.1

Type: bool
Default: false
Edit: Yes
Reference: timing_disable_sdf_retain_arc_merging

timing_disable_skew_checks

When set to true, disables library skew checks for timing analysis
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_skew_checks

timing_disable_test_signal_arc

When set to true, timing analysis will not analyze the signal arcs coming from or going to the
test pin
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_test_signal_arc

timing_disable_timing_model_latch_inferencing

Controls whether latch behavior is inferred for cell descriptions tagged with the Liberty
timing_model_type attribute, including all values: abstracted, extracted, or qtm
Type: bool
Default: true
Edit: Yes
Reference: timing_disable_timing_model_latch_inferencing

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timing_disable_tristate_disable_arcs

When set to true, disables all 0/1->Z transitions of tristate arcs during timing analysis
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_tristate_disable_arcs

timing_disable_user_data_to_data_checks

When set to true, disables data-to-data checks that are created by the set_data_check
command
Type: bool
Default: false
Edit: Yes
Reference: timing_disable_user_data_to_data_checks

timing_driving_cell_override_library

Controls the selection of library cells specified using the set_driving_cell command
Type: bool
Default: false
Edit: Yes
Reference: timing_driving_cell_override_library

timing_enable_aocv_slack_based

Enable aocv analysis using slack based method

Type: bool
Default: false
Edit: Yes
Reference: timing_enable_aocv_slack_based

timing_enable_case_analysis_conflict_warning

Controls to report case analysis conflict warnings to CTE_constant_mismatch.rpt file.

Type: bool
Default: true
Edit: Yes
Reference: timing_enable_case_analysis_conflict_warning

timing_enable_clock_phase_based_rise_fall_derating

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Determines the interpretation of edge-specific derating factors for clock paths, specified using
the set_timing_derate -rise/-fall parameters
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_clock_phase_based_rise_fall_derating

timing_enable_clock_to_clock_clock_gating_check

When set to true, performs clock to clock gating checks at gating elements
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_clock_to_clock_clock_gating_check

timing_enable_data_through_clock_gating

When set to false, blocks signals arriving on the enable of the clock-gating check
Type: bool
Default: true
Edit: Yes
Reference: timing_enable_data_through_clock_gating

timing_enable_derating_for_pulse_width_checks

Applies check derating for pulse width checks

Type: bool
Default: false
Edit: Yes
Reference: timing_enable_derating_for_pulse_width_checks

timing_enable_early_late_data_slews_for_setuphold_mode_checks

When set to true, the global variable enables propagation of early and late slews on data
paths. Delay calculation then uses these early and late slews to calculate timing checks. You
can use this global in simultaneous setup and hold mode only.
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_early_late_data_slews_for_setuphold_mode_checks

timing_enable_genclk_divide_by_inherit_parent_duty_cycle

Controls inheritance of duty cycle from master clock for generated clocks with divide by option
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_genclk_divide_by_inherit_parent_duty_cycle

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timing_enable_genclk_source_path_register_limit

Limits generated clock source latency path to traverse across one register only
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_genclk_source_path_register_limit

timing_enable_generated_clock_edge_based_source_latency

Controls how the software chooses generated clock source latency paths
Type: bool
Default: true
Edit: Yes
Reference: timing_enable_generated_clock_edge_based_source_latency

timing_enable_get_obj_escaped_name_backward_compatible

Enables printing of escape characters in the get_object_name command output.

Type: bool
Default: false
Edit: Yes
Reference: timing_enable_get_obj_escaped_name_backward_compatible

timing_enable_get_objects_regexp_compatibility

Enables the -regexp option compatibility for get_* commands

Type: bool
Default: false
Edit: Yes

timing_enable_hierarchical_get_nets_support

Enable the hierarchical segment support for get_nets.

Type: bool
Default: false
Edit: Yes
Reference: timing_enable_hierarchical_get_nets_support

timing_enable_latch_thru_mode

Enable the latch thru analysis mode in which timing paths can propagate across latches,
depending on their arrival time with respect to the latch transparency window.
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_latch_thru_mode

timing_enable_latency_through_clock_gating

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Controls propagation of latency phases across a clock gating element.

Type: bool
Default: true
Edit: Yes
Reference: timing_enable_latency_through_clock_gating

timing_enable_mmmc_loop_breaking

When set to true, loop breaking is handled independently per analysis view
Type: bool
Default: true
Edit: Yes
Reference: timing_enable_mmmc_loop_breaking

timing_enable_multi_drive_net_reduction_with_assertions

Controls whether multi-drive net reduction (if enabled) will attempt to reduce mult-drive nets
that also have only either/both set_annotated_delay or set_annotated_transitions assertions
present. By default, any assertions present on different drivers of multi-drive nets will prevent
reduction of the multi-drive net.
Type: enum
Enum Values: none all delay
Default: none
Edit: Yes
Reference: timing_enable_multi_drive_net_reduction_with_assertions

timing_enable_multi_frequency_latch_analysis

Enables multi-frequency latch timing analysis of the latch time borrowing for when a data
signal coming to a latch is controlled by a clock with a frequency different to a clock of the
latch enabling signal
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_multi_frequency_latch_analysis

timing_enable_multicycle_data_check_compatibility

Enables checking for SDC compatible data checks when set_multicycle_path -start parameter
is specified
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_multicycle_data_check_compatibility

timing_enable_path_delay_to_unconstrained_endpoints_compatibility

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When set to true, does not constrain path with path delay if path ends at unconnected input pin
of combo cell.
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_path_delay_to_unconstrained_endpoints_compatibility

timing_enable_pessimistic_cppr_for_reconvergent_clock_paths

When set to true, enables pessimistic cppr adjustment for re-convergent clock paths
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_pessimistic_cppr_for_reconvergent_clock_paths

timing_enable_power_ground_constants

Controls whether case analysis is inferred from power and ground rail connections.
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_power_ground_constants

timing_enable_preset_clear_arcs

Determines whether timing arcs are created to model the transition to active state (assertion)
of the preset or clear pin, and the subsequent transition of the output to controlled state
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_preset_clear_arcs

timing_enable_pulse_latch

Enables pulse-latch analysis

Type: bool
Default: true
Edit: Yes
Reference: timing_enable_pulse_latch

timing_enable_si_cppr

Enables more accurate CPPR analysis when incremental delays are present and the
timing_remove_clock_reconvergence_pessimism global variable is set to true
Type: bool
Default: true
Edit: Yes
Reference: timing_enable_si_cppr

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timing_enable_simultaneous_setup_hold_mode

Controls whether setup and hold checks are analyzed separately, or together on the same
timing graph
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_simultaneous_setup_hold_mode

timing_enable_spatial_derate_mode

When set to true, enables spatial derate feature.

Type: bool
Default: false
Edit: Yes
Reference: timing_enable_spatial_derate_mode

timing_enable_timing_window_pessimism_removal

When set to true, removes common clock path pessimism between aggressor and victim pins
in the design
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_timing_window_pessimism_removal

timing_enable_tristate_clock_gating

When this global is set to true, inferred gated-clock checks are added when clock and data
signals converge through the tristate enable and data input of tristate buffers
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_tristate_clock_gating

timing_enable_uncertainty_for_clock_checks

Considers clock uncertainty when performing clock checks.

Type: bool
Default: true
Edit: Yes
Reference: timing_enable_uncertainty_for_clock_checks

timing_enable_uncertainty_for_pulse_width_checks

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When set to true, considers clock uncertainty when performing minimum pulse width checks
Type: bool
Default: false
Edit: Yes
Reference: timing_enable_uncertainty_for_pulse_width_checks

timing_extract_model_aocv_mode

This global sets the AOCV mode to be used during model extraction
Type: enum
Enum Values: none graph_based path_based
Default: none
Edit: Yes
Reference: timing_extract_model_aocv_mode

timing_extract_model_case_analysis_in_library

When set to false, specifies that port propagated constants are written to the generated
constraints file
Type: bool
Default: true
Edit: Yes
Reference: timing_extract_model_case_analysis_in_library

timing_extract_model_check_arcs_as_lvf

With this global turned on, check arcs will be modeled as LVF arcs
Type: bool
Default: false
Edit: Yes
Reference: timing_extract_model_check_arcs_as_lvf

timing_extract_model_consider_design_level_drv

When set to false, specifies that user asserted design level DRVs should not be considered
while writing to the extracted timing model
Type: bool
Default: true
Edit: Yes
Reference: timing_extract_model_consider_design_level_drv

timing_extract_model_disable_cycle_adjustment

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When set to true, the cycle adjustment for the multcycle-paths that could not be pushed out, is
disabled
Type: bool
Default: false
Edit: Yes
Reference: timing_extract_model_disable_cycle_adjustment

timing_extract_model_exhaustive_validation_dir

Specifies the output directory where the validation reports will be written
Type: string
Default: ""
Edit: Yes
Reference: timing_extract_model_exhaustive_validation_dir

timing_extract_model_exhaustive_validation_mode

Enables ETM validation at the minimum and maximum indices of the slew / load indices
Type: bool
Default: false
Edit: Yes
Reference: timing_extract_model_exhaustive_validation_mode

timing_extract_model_gating_as_nochange_arc

When set to false, disables conversion of clock gating checks to nochange arcs in the
extracted timing model
Type: bool
Default: true
Edit: Yes
Reference: timing_extract_model_gating_as_nochange_arc

timing_extract_model_ideal_clock_latency_arc

Specifies if latency arc from ideal master clock need to be extracted in timing model
Type: bool
Default: true
Edit: Yes
Reference: timing_extract_model_ideal_clock_latency_arc

timing_extract_model_include_applied_load_in_characterization_range

When set to true, specifies that actual load visible to timer, will be included in the load
characterization range for path endpoints
Type: bool
Default: true
Edit: Yes
Reference: timing_extract_model_include_applied_load_in_characterization_range

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timing_extract_model_include_applied_slew_in_characterization_range

When set to true, specifies that actual timer slew must be included in the characterization
range for timing model.
Type: bool
Default: true
Edit: Yes
Reference: timing_extract_model_include_applied_slew_in_characterization_range

timing_extract_model_max_feedthru_characterization_load

Load specified will be used by model extractor for feed through path characterization.
Type: double
Default: 0.0
Edit: Yes

timing_extract_model_non_borrowing_latch_path_as_setup

If turned ON, models the non borrowing interface latch paths as setup check.
Type: bool
Default: false
Edit: Yes
Reference: timing_extract_model_non_borrowing_latch_path_as_setup

timing_extract_model_slew_propagation_mode

Specifies the type of slew propagation to use for generating extracted timing model
Type: enum
Enum Values: worst_slew path_based_slew
Default: worst_slew
Edit: Yes
Reference: timing_extract_model_slew_propagation_mode

timing_extract_model_write_clock_checks_as_arc

Allows timing model to write min pulse width or min period checks as arcs.
Type: bool
Default: false
Edit: Yes
Reference: timing_extract_model_write_clock_checks_as_arc

timing_extract_model_write_clock_checks_as_scalar_tables

Allows timing model to write min pulse width or min period checks as scalar arcs.
Type: bool
Default: false
Edit: Yes
Reference: timing_extract_model_write_clock_checks_as_scalar_tables

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timing_extract_model_write_lvf

When set to true, generated ETM contains LVF model.

Type: bool
Default: false
Edit: Yes
Reference: timing_extract_model_write_lvf

timing_extract_model_write_min_max_clock_tree_path

When set to true, writes the min max worst latency for each clock source.
Type: bool
Default: true
Edit: Yes
Reference: timing_extract_model_write_min_max_clock_tree_path

timing_generate_normalized_driver_waveform

To generate ndw if it is not defined in the library.

Type: bool
Default: true
Edit: Yes
Reference: timing_generate_normalized_driver_waveform

timing_generated_clocks_allow_nested_assertions

Enables clock latency handling for nested generated clocks created on the same timing pin as
their master clocks
Type: bool
Default: false
Edit: Yes
Reference: timing_generated_clocks_allow_nested_assertions

timing_generated_clocks_inherit_ideal_latency

When set to true, makes generated clocks to inherit parent's ideal network latency
Type: bool
Default: false
Edit: Yes
Reference: timing_generated_clocks_inherit_ideal_latency

timing_get_of_objects_hier_compatibility

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When set to true, the get_pins -of_objects parameter will return hierarchical leaf pins
connected to the specified objects
Type: bool
Default: false
Edit: Yes
Reference: timing_get_of_objects_hier_compatibility

timing_hier_obj_name_compatibility

Controls how hierarchical delimiters are interpreted in the search pattern, when the -hier
parameter is used with the get_* collection command
Type: bool
Default: true
Edit: Yes
Reference: timing_hier_obj_name_compatibility

timing_ignore_lumped_rc_assertions

When set to false, the set_load and set_resistance values override the actual extracted
representation
Type: bool
Default: false
Edit: Yes
Reference: timing_ignore_lumped_rc_assertions

timing_inter_power_domain_derate_flow_use_path_segment_delay_difference

When set to true, aocv-pba calculation with launch/capture path segment delay difference
based computation using interface power domain (ipd) derate offsets is enabled
Type: bool
Default: false
Edit: Yes
Reference: timing_inter_power_domain_derate_flow_use_path_segment_delay_difference

timing_io_use_clock_network_latency

Controls whether network latency of a reference clock is added or not to the data arrival time
on the port
Type: enum
Enum Values: always ideal
Default: ideal
Edit: Yes
Reference: timing_io_use_clock_network_latency

timing_library_build_async_deassert_arc

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Controls whether input to output arcs from the preset or clear pins transitioning to inactivestate
are included when the timing system is initialized
Type: bool
Default: true
Edit: Yes
Reference: timing_library_build_async_deassert_arc

timing_library_ccs_receiver_weight_factor

Specifies the weight factor to calculate the rise/fall capacitance range values from ccs receiver
capacitance model
Type: double
Default: 1.0
Edit: Yes
Reference: timing_library_ccs_receiver_weight_factor

timing_library_convert_async_setuphold_to_recrem

Controls whether single-edged setup and hold checks on asynchronous pins in the Liberty
library are inferred as recovery and removal checks. This is mainly to support older modeling
styles in legacy libraries.
Type: int
Default: 1
Edit: Yes
Reference: timing_library_convert_async_setuphold_to_recrem

timing_library_enable_advanced_capacitance_support

Enables support for N-piece CCS receiver capacitance and ecsm_capacitance_set groups in
libraries
Type: bool
Default: true
Edit: Yes

timing_library_generated_clock_use_group_name

When set to true, the software uses the generated_clock group name when creating a
generated clock from a library-generated clock group
Type: bool
Default: false
Edit: Yes
Reference: timing_library_generated_clock_use_group_name

timing_library_hold_constraint_corner_sigma_multiplier

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User control multiplier to generate constraint table applied for hold arc.
Type: double
Default: 0.0
Edit: Yes
Reference: timing_library_hold_constraint_corner_sigma_multiplier

timing_library_hold_sigma_multiplier

User control multiplier to generate constraint table applied for hold arc.
Type: double
Default: 0.0
Edit: Yes
Reference: timing_library_hold_sigma_multiplier

timing_library_infer_async_pins_from_timing_arcs

This global marks the pins as async pins based on the timing arcs associated with the pin.
Type: bool
Default: false
Edit: Yes
Reference: timing_library_infer_async_pins_from_timing_arcs

timing_library_infer_cap_range_from_ccs_receiver_model

When true infer the rise/fall capacitance range values from ccs receiver capacitance model
Type: bool
Default: false
Edit: Yes
Reference: timing_library_infer_cap_range_from_ccs_receiver_model

timing_library_infer_cap_range_from_ecsm_receiver_model

When this global is enabled would infer cap range from ecsm capacitance group of library.
Type: bool
Default: false
Edit: Yes
Reference: timing_library_infer_cap_range_from_ecsm_receiver_model

timing_library_infer_socv_from_aocv

Infer sensitivity data from AOCV libraries

Type: bool
Default: false
Edit: Yes
Reference: timing_library_infer_socv_from_aocv

timing_library_interpolate_drv_values

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Allows the software to use a range of trilib DRV values for performing delay calculations
Type: bool
Default: false
Edit: Yes
Reference: timing_library_interpolate_drv_values

timing_library_read_ccs_noise_data

can read ccs noise construct from library when enabled.

Type: bool
Default: true
Edit: Yes
Reference: timing_library_read_ccs_noise_data

timing_library_read_without_ecsm

Switch off loading of ECSM data

Type: bool
Default: false
Edit: Yes
Reference: timing_library_read_without_ecsm

timing_library_read_without_power

can read library without power by setting this global to true

Type: bool
Default: false
Edit: Yes
Reference: timing_library_read_without_power

timing_library_read_without_sensitivity

Switch off loading of ECSM timing sensitivity data

Type: bool
Default: false
Edit: Yes
Reference: timing_library_read_without_sensitivity

timing_library_scale_aocv_to_socv_to_n_sigma

AOCV derates are expected to be derived based on 3-sigma variation

Type: double
Default: 3.0
Edit: Yes
Reference: timing_library_scale_aocv_to_socv_to_n_sigma

timing_library_setup_constraint_corner_sigma_multiplier

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User control multiplier to generate constraint table using sigma values applied for setup arc.
Type: double
Default: 0.0
Edit: Yes
Reference: timing_library_setup_constraint_corner_sigma_multiplier

timing_library_setup_sigma_multiplier

User control multiplier to generate constraint table using sigma values applied for setup arc.
Type: double
Default: 0.0
Edit: Yes
Reference: timing_library_setup_sigma_multiplier

timing_library_term_voltage_from_lib_pin

Use Library pin voltage for reporting the term voltage.

Type: int
Default: 0
Edit: Yes
Reference: timing_library_term_voltage_from_lib_pin

timing_library_use_two_piece_receiver_cap

When libraries have both 2 piece and multi piece pin caps, give priority to two piece models.
Type: bool
Default: false
Edit: Yes
Reference: timing_library_use_two_piece_receiver_cap

timing_library_zero_negative_timing_check_arcs

When true check for negative values in timing arcs

Type: bool
Default: false
Edit: Yes
Reference: timing_library_zero_negative_timing_check_arcs

timing_multi_frequency_clock_rounding_factor

Rounds off irrational numbers so that they can be read appropriately

Type: double
Default: 1e-05
Edit: Yes
Reference: timing_multi_frequency_clock_rounding_factor

timing_normalized_driver_waveform_clip_linear_part

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To control the clipping of the generated ndw which is generated by the global
timing_generate_normalized_driver_waveform.
Type: bool
Default: false
Edit: Yes
Reference: timing_normalized_driver_waveform_clip_linear_part

timing_normalized_driver_waveform_weight_factor

Decides the weight factor for the exponential and the linear part in the waveform generated by
the global timing_generate_normalized_driver_waveform.
Type: double
Default: 0.5
Edit: Yes
Reference: timing_normalized_driver_waveform_weight_factor

timing_nsigma_multiplier

Controls sigma multiplier to be used in SOCV mode

Type: double
Default: 3.0
Edit: Yes
Reference: timing_nsigma_multiplier

timing_null_collection_return_compatibility

Allows you to migrate previous release scripts to the new use model
Type: bool
Default: false
Edit: Yes
Reference: timing_null_collection_return_compatibility

timing_path_based_enable_exhaustive_depth_bounded_by_gba

Enable the tool to bound the PBA exhaustive analysis by next worst GBA slack incase the
depth is exhausted for any given endpoint
Type: bool
Default: true
Edit: Yes
Reference: timing_path_based_enable_exhaustive_depth_bounded_by_gba

timing_path_based_enable_report_launch_clock_path

set it to false to skip reporting launch clock path in pba path_type full report
Type: bool
Default: true
Edit: Yes
Reference: timing_path_based_enable_report_launch_clock_path

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timing_path_based_enable_verbose_mode

controls the verbosity of path based analysis messages printed during and at the end of the
analysis
Type: enum
Enum Values: 0 1 2 true false
Default: 1
Edit: Yes
Reference: timing_path_based_enable_verbose_mode

timing_path_based_exhaustive_enable_design_coverage

Enables the exhaustive path based analysis to evaluate all violating endpoints
Type: bool
Default: false
Edit: Yes
Reference: timing_path_based_exhaustive_enable_design_coverage

timing_path_based_exhaustive_max_paths_limit

Set the maximum number of paths which can be retimed during exhaustive path based
analysis
Type: int
Default: 2000000
Edit: Yes
Reference: timing_path_based_exhaustive_max_paths_limit

timing_path_based_exhaustive_pba_bounded_mode

Turn on EPBA Bounded mode

Type: bool
Default: false
Edit: Yes

timing_path_based_low_memory_mode

A lower value for this variable will reduce the peak memory footprint of path based analysis
(PBA) at the cost of some addition runtime.
Type: double
Default: 10.0
Edit: Yes

timing_pba_exhaustive_path_nworst_limit

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Specify the nworst exhaustive limit to be honored by tool during PBA exhaustive limit
Type: int
Default: 10000
Edit: Yes
Reference: timing_pba_exhaustive_path_nworst_limit

timing_prefix_module_name_with_library_generated_clock

When set to true, the software appends the instance name to the clock pin name when
creating a generated clock
Type: bool
Default: true
Edit: Yes
Reference: timing_prefix_module_name_with_library_generated_clock

timing_propagate_latch_data_uncertainty

When set to true, uses the clock phase associated with a flush latch's data pin as the from
clock phase for downstream uncertainty timing calculations
Type: bool
Default: false
Edit: Yes
Reference: timing_propagate_latch_data_uncertainty

timing_property_arrival_window_enable_tcl_dict_format

When set to TRUE, new format for the arrival_windows property will be used to print.
Type: bool
Default: false
Edit: Yes
Reference: timing_property_arrival_window_enable_tcl_dict_format

timing_property_return_null_collection_with_quiet

Enables returning properties values for all objects when -quiet option is used in get_property
Type: bool
Default: false
Edit: Yes
Reference: timing_property_return_null_collection_with_quiet

timing_rail_swing_checks_high_voltage_threshold

user to specify voltage thresholds for high rail swing checks

Type: double
Default: 0.95
Edit: Yes
Reference: timing_rail_swing_checks_high_voltage_threshold

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timing_rail_swing_checks_low_voltage_threshold

user to specify voltage thresholds for low rail swing checks

Type: double
Default: 0.05
Edit: Yes
Reference: timing_rail_swing_checks_low_voltage_threshold

timing_recompute_sdf_in_setuphold_mode

Controls the recomputing of SDF delays when the software is in simultaneous setup and hold
analysis mode
Type: bool
Default: false
Edit: Yes
Reference: timing_recompute_sdf_in_setuphold_mode

timing_reduce_multi_drive_net_arcs

Controls the reduction of the number of net arcs created for timing analysis for nets driven by
parallel buffers
Type: bool
Default: true
Edit: Yes
Reference: timing_reduce_multi_drive_net_arcs

timing_reduce_multi_drive_net_arcs_threshold

Sets a threshold number used by the tool to trigger the reduction of timing arcs of nets driven
by parallel buffers
Type: int
Default: 10000
Edit: Yes
Reference: timing_reduce_multi_drive_net_arcs_threshold

timing_report_clock_pin_as_begin_point

Enable whether to show CLK as start point

Type: bool
Default: false
Edit: Yes
Reference: timing_report_clock_pin_as_begin_point

timing_report_constraint_enable_extended_drv_format

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Enables reporting of report_constraint as per clock/data phases and rise/fall

Type: bool
Default: false
Edit: Yes
Reference: timing_report_constraint_enable_extended_drv_format

timing_report_constraint_rise_fall_clock_period_check

Enables rise-fall check for clock_period check type in report_constraint

Type: bool
Default: false
Edit: Yes
Reference: timing_report_constraint_rise_fall_clock_period_check

timing_report_disable_max_paths_per_group

This global controls whether or not group-based mode semantics are used when -group and -
max_paths are used with report_timing.
Type: bool
Default: false
Edit: Yes
Reference: timing_report_disable_max_paths_per_group

timing_report_drv_enable_clock_source_as_clock

Enables clock drv for pure clock source path in place of data drv
Type: bool
Default: false
Edit: Yes
Reference: timing_report_drv_enable_clock_source_as_clock

timing_report_drv_enable_frequency_per_view

Enables view based frequency drv flow

Type: bool
Default: false
Edit: Yes
Reference: timing_report_drv_enable_frequency_per_view

timing_report_drv_enable_slew_threshold_scaling

Enables transition constraints scaling as per slew threshold

Type: bool
Default: false
Edit: Yes
Reference: timing_report_drv_enable_slew_threshold_scaling

timing_report_enable_cppr_point

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Enable Cppr Point reporting in report timing command

Type: bool
Default: false
Edit: Yes
Reference: timing_report_enable_cppr_point

timing_report_enable_flag_field_symbols

Enables reporting of Instance/Net related bits in report_timing Flags column

Type: bool
Default: false
Edit: Yes
Reference: timing_report_enable_flag_field_symbols

timing_report_enable_markers

Enables marker for report_timing for Pin/timing points columns

Type: bool
Default: true
Edit: Yes
Reference: timing_report_enable_markers

timing_report_enable_max_capacitance_drv_for_constant_nets

Enables max capactiance DRV checks for nets having disabled constant propagation
Type: bool
Default: false
Edit: Yes
Reference: timing_report_enable_max_capacitance_drv_for_constant_nets

timing_report_enable_max_path_limit_warning

warning message if max_paths option specified is not enough for coverage

Type: bool
Default: false
Edit: Yes
Reference: timing_report_enable_max_path_limit_warning

timing_report_enable_report_clock_timing_across_clock_pin

Enables fanout tracing across clock pins if any combinational arc is present
Type: bool
Default: false
Edit: Yes
Reference: timing_report_enable_report_clock_timing_across_clock_pin

timing_report_enable_si_debug

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For decision regarding SI attribute debugging through path collection objects

Type: bool
Default: false
Edit: Yes
Reference: timing_report_enable_si_debug

timing_report_enable_unique_pins_multiple_capture_clock_paths

enables reporting different paths w.r.t ref clocks in unique_pins

Type: bool
Default: false
Edit: Yes
Reference: timing_report_enable_unique_pins_multiple_capture_clock_paths

timing_report_enable_verbose_ssta_mode

Enables new format for header in report_timing SOCV mode

Type: bool
Default: false
Edit: Yes
Reference: timing_report_enable_verbose_ssta_mode

timing_report_fields

Specifies a report_timing format

Type: string
Default: instance arc cell delay arrival required
Edit: Yes
Reference: timing_report_fields

timing_report_generated_clock_info

When set to true (the default), generated clock information is automatically added to the report
if generated clocks are encountered in either the launching or latching clock paths
Type: bool
Default: true
Edit: Yes
Reference: timing_report_generated_clock_info

timing_report_group_based_mode

Groups paths by clock domain

Type: bool
Default: false
Edit: Yes
Reference: timing_report_group_based_mode

timing_report_max_transition_check_using_nsigma_slew

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Enables report_constraint drv checking to use mean+nsigma slew values in socv flow
Type: bool
Default: false
Edit: Yes
Reference: timing_report_max_transition_check_using_nsigma_slew

timing_report_property_fastest_clock_consider_data_phase

When on, it will consider data phase also while finding the fastest clock.
Type: bool
Default: false
Edit: Yes
Reference: timing_report_property_fastest_clock_consider_data_phase

timing_report_pulse_width_matching_launch_capture_paths

Reports only those pulse_width paths that have same pins on launch and capture path
Type: bool
Default: false
Edit: Yes
Reference: timing_report_pulse_width_matching_launch_capture_paths

timing_report_redirect_message_types

Redirect reporting messages to report file

Type: enum
Enum Values: info warning error all none
Default: none
Edit: Yes
Reference: timing_report_redirect_message_types

timing_report_retime_formatting_mode

This variable can be used to manage the retiming fields in reporting format. Based upon given
setting it would automatically replaces (or add) the default columns with respective retiming
columns. For example in case of delay column it will add(or replace) the 'Retime Delay'
automatically.
Type: enum
Enum Values: manual retime_compare retime_replace
Default: manual
Edit: Yes
Reference: timing_report_retime_formatting_mode

timing_report_skip_constraint_loop_check

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skip reporting of loop in case timing graph inside loop is broken due to create_clock,
set_input_delay, set_output_delay defined inside the loop
Type: bool
Default: false
Edit: Yes
Reference: timing_report_skip_constraint_loop_check

timing_report_timing_header_detail_info

Controls whether the report_timing reports are generated using the default orextended report
header
Type: enum
Enum Values: default extended
Default: default
Edit: Yes
Reference: timing_report_timing_header_detail_info

timing_report_unconstrained_path_early_late_header

When set to true, prints late and early type for unconstrained path
Type: bool
Default: false
Edit: Yes
Reference: timing_report_unconstrained_path_early_late_header

timing_report_unconstrained_paths

When set to true, the report_timing command reports unconstrained paths if it cannot find a
constrained path to report
Type: bool
Default: false
Edit: Yes
Reference: timing_report_unconstrained_paths

timing_report_use_receiver_model_capacitance

Uses ECSM pin capacitance values for load or DRV calculation

Type: bool
Default: false
Edit: Yes
Reference: timing_report_use_receiver_model_capacitance

timing_report_use_worst_parallel_cell_arc

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When set to false, setting the -nworst parameter reports several paths by selecting parallel
arcs in the library cell between two pins
Type: bool
Default: false
Edit: Yes
Reference: timing_report_use_worst_parallel_cell_arc

timing_resolve_driver_conflicts

Resolves values of nets having multiple drivers

Type: enum
Enum Values: conservative aggressive
Default: aggressive
Edit: Yes
Reference: timing_resolve_driver_conflicts

timing_scaling_for_negative_checks

Modifies the scaling of the negative timing analysis check value

Type: enum
Enum Values: default divider multiplier
Default: default
Edit: Yes
Reference: timing_scaling_for_negative_checks

timing_scaling_for_negative_delays

Modifies the scaling of the negative delay value to be used during timing analysis
Type: enum
Enum Values: default divider multiplier
Default: default
Edit: Yes
Reference: timing_scaling_for_negative_delays

timing_sdf_adjust_negative_setuphold

Controls how Setup and Hold check values are adjusted when both are initially negative.
Type: bool
Default: false
Edit: Yes
Reference: timing_sdf_adjust_negative_setuphold

timing_sdf_enable_setuphold_scond_ccond

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To enable proper generation of SDF (Standard Delay Format) with scond and ccond qualifiers
on SETUPHOLD and RECREM timing checks
Type: bool
Default: false
Edit: Yes
Reference: timing_sdf_enable_setuphold_scond_ccond

timing_self_loop_paths_no_skew_max_depth

Identifies self-loop paths at the specified depth.

Type: int
Default: 10
Edit: Yes
Reference: timing_self_loop_paths_no_skew_max_depth

timing_self_loop_paths_no_skew_max_slack

Identifies self-loop paths at the specified threshold

Type: double
Default: 0.0
Edit: Yes
Reference: timing_self_loop_paths_no_skew_max_slack

timing_set_clock_source_to_output_as_data

When set to true, causes a clock source path leading to an output or bidi port to be treated as a
data path if there is a set_output_delay or set_data_check assertion on the port
Type: bool
Default: false
Edit: Yes
Reference: timing_set_clock_source_to_output_as_data

timing_socv_rc_variation_mode

Enable interconnect variation mode in SOCV mode

Type: bool
Default: true
Edit: Yes
Reference: timing_socv_rc_variation_mode

timing_socv_statistical_min_max_mode

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Controls worstcasing mode to be used for SOCV

Type: enum
Enum Values: statistical three_sigma_bounded mean_and_sigma_bounded
mean_and_three_sigma_bounded max_mean_and_sigma
Default: mean_and_three_sigma_bounded
Edit: Yes
Reference: timing_socv_statistical_min_max_mode

timing_socv_view_based_nsigma_multiplier_mode

Enables setting of view-based separate setup and hold sigma multipliers

Type: bool
Default: true
Edit: Yes
Reference: timing_socv_view_based_nsigma_multiplier_mode

timing_spatial_derate_chip_size

Type: double
Default: 1e+30
Edit: Yes
Reference: timing_spatial_derate_chip_size

timing_spatial_derate_distance_mode

Type: enum
Enum Values: bounding_box chip_size
Default: bounding_box
Edit: Yes
Reference: timing_spatial_derate_distance_mode

timing_suppress_escape_characters

Suppresses the reporting of escape characters in timing object names

Type: bool
Default: true
Edit: Yes
Reference: timing_suppress_escape_characters

timing_suppress_ilm_constraint_mismatches

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When set to true, the software suppresses all error and warning messages related to objects
not found when loading SDC constraint files for the ILM flow
Type: bool
Default: false
Edit: Yes
Reference: timing_suppress_ilm_constraint_mismatches

timing_time_unit

This value is passed to set_library_unit -time to set the time units used in timing library and
.sdc files and timing reports. Legal values are none, 1ns, 1ps, 10ps, 100ps.
Type: string
Default: none
Edit: Yes
Reference: timing_time_unit

timing_use_clock_pin_attribute_for_clock_net_marking

To allow the propagation of clocks to pins with clock attributes regardless of the presence of
check arcs or trigger arcs at the pins
Type: bool
Default: false
Edit: Yes
Reference: timing_use_clock_pin_attribute_for_clock_net_marking

timing_use_incremental_si_transition

When set to true, enables usage of incremental slew during DRV violation reporting
Type: bool
Default: false
Edit: Yes
Reference: timing_use_incremental_si_transition

timing_use_latch_early_launch_edge

Enables the latch use early launch edge feature.

Type: bool
Default: true
Edit: Yes
Reference: timing_use_latch_early_launch_edge

timing_use_latch_time_borrow

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When set to false, does not consider time borrowing during timing analysis. Time borrowing is
the amount of time borrowed by a previous logic
Type: bool
Default: true
Edit: Yes
Reference: timing_use_latch_time_borrow

timing_waveform_aware_pulse_width_checks_high_voltage_level

User to specify high voltage level to be used for waveform aware pulse-width checks
Type: double
Default: 0.95
Edit: Yes
Reference: timing_waveform_aware_pulse_width_checks_high_voltage_level

timing_waveform_aware_pulse_width_checks_low_voltage_level

User to specify low voltage level to be used for waveform aware pulse-width checks
Type: double
Default: 0.05
Edit: Yes
Reference: timing_waveform_aware_pulse_width_checks_low_voltage_level

timing_write_sdf_no_escape_backslash

Supports various patterns of the escape character.

Type: bool
Default: false
Edit: Yes
Reference: timing_write_sdf_no_escape_backslash

top_sdps

Short-cut to all top level structured data path (sdp) objects.

Type: obj(sdp)*
Default: ""
Edit: No

trace_obj_macro_pins

specify macro pin name patterns in regular expression

Type: string
Default: ""
Edit: Yes
Reference: trace_obj_macro_pins

trace_obj_max_fanin_fanout

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Specify the maximum number of a pin's fanin/fanout,a pin will be ignored in tracing
connectivity if its fanin/fanout larger than the specified number
Type: int
Default: 1000
Edit: Yes
Reference: trace_obj_max_fanin_fanout

trace_obj_register_inputs

Specify register input pin names

Type: string
Default: ""
Edit: Yes
Reference: trace_obj_register_inputs

trace_obj_register_outputs

Specify register output pin names

Type: string
Default: ""
Edit: Yes
Reference: trace_obj_register_outputs

track_patterns

Short-cut to all the track_pattern objects in the design.

Type: obj(track_pattern)*
Default: ""
Edit: No

trim_grids

Short-cut to all the trim_grid objects in the design from the LEF TRIMMETALTRACK
statement.
Type: obj(trim_grid)*
Default: ""
Edit: No

ui_precision

Specifies the number of significant digits to be displayed in timing reports for data with no
specific type.
Type: int
Default: 3
Edit: Yes
Reference: ui_precision

ui_precision_capacitance

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Specifies the number of significant digits to be displayed in timing reports for data of type
capacitance.
Type: int
Default: 3
Edit: Yes
Reference: ui_precision_capacitance

ui_precision_derating

Specifies the number of significant digits to be displayed in timing reports for derating factors
such as those specified via set_timing_derate constraints or AOCV derating libraries.
Type: int
Default: 3
Edit: Yes
Reference: ui_precision_derating

ui_precision_power

Specifies the number of significant digits to be displayed in timing reports for data of type
power.
Type: int
Default: 3
Edit: Yes
Reference: ui_precision_power

ui_precision_sensitivities

Specifies the number of significant digits to be displayed in timing reports for statistical
sensitivity values and SOCV sigma values.
Type: int
Default: 3
Edit: Yes
Reference: ui_precision_sensitivities

ui_precision_timing

Specifies the number of significant digits to be displayed for timing reports for delay type
values including cell and net delays, transitions, arrival and required times, and slacks.
Type: int
Default: 3
Edit: Yes
Reference: ui_precision_timing

via_def_rules

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All the via_def_rules defined in the LEF or OpenAccess techfile.

Type: obj(via_def_rule)*
Default: ""
Edit: No

via_defs

All the via_defs (via master definitions).

Type: obj(via_def)*
Default: ""
Edit: No

write_db_auto_save_user_globals

If true, write_db automatically saves user created Tcl global variables. User globals are
defined as any "info globals" names that do not exist at startup (e.g. created by user executed
code). See the define_variables command to add or delete specific Tcl variables from the
automatic save list.
Type: bool
Default: false
Edit: Yes
Reference: write_db_auto_save_user_globals

write_db_binary_timing_constraints

If true, write_db will save timing constraints in binary format. The value of the global should be
persistent in subsequent write_db and read_db operations.
Type: bool
Default: true
Edit: Yes
Reference: write_db_binary_timing_constraints

write_db_cmd_file_limit

write_db saves the complete .cmd history across multiple sessions in the inn.cmd.gz file
inside the save directory up to this file length limit in units of Mb. If it is set to 0, no history is
saved at all
Type: int
Default: 10
Edit: Yes
Reference: write_db_cmd_file_limit

write_db_copy_timing_constraints_always

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Specifies whether SDC files are always copied to the DB directory rather than links to external
SDC files. By default they are only copied if the constraints were modified.
Type: bool
Default: false
Edit: Yes
Reference: write_db_copy_timing_constraints_always

write_db_create_read_file

If true, 'write_db my_db' will also create a 'my_db.read' file with a 'read_db my_db' command
inside it. This is a Tcl file that can be passed to the Linux executable to make it easy to load
the DB at startup like this: 'innovus -files my_db.read'. For OA usage, it would have the
appropriate 'read_db -oa_lib_cell_view {<lib> <cell> <view>}' command inside it.
Type: bool
Default: false
Edit: Yes
Reference: write_db_create_read_file

write_db_include_metal_fill_rules

specify whether to save metalfill settings

Type: int
Default: 0
Edit: Yes
Reference: write_db_include_metal_fill_rules

write_db_save_unused_lef_block_names

Specifies whether to remember a list of unused macros during saving

Type: bool
Default: false
Edit: Yes
Reference: write_db_save_unused_lef_block_names

write_def_compress_vias

Compress the via statement in SPECIALNETS section. This variable controls write_def to sort
vias with two dimension array, so it can use 'DO numX BY numY STEP stepX stepY'
statement.
Type: int
Default: 0
Edit: Yes
Reference: write_def_compress_vias

write_def_hierarchy_delimiter

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Specify the write_def hierarchy delimiter.

Type: string
Default: ""
Edit: Yes
Reference: write_def_hierarchy_delimiter

write_def_include_lef_ndr

Output LEF NONDEFAULTRULES in DEF. This variable controls write_def to output LEF
nondefault rule information. By default, write_def does not write out nondefaultrules defined in
LEF. Set this variable to true to output nondefault rules defined in LEF .
Type: bool
Default: false
Edit: Yes
Reference: write_def_include_lef_ndr

write_def_include_lef_vias

Output LEF vias in DEF. This variable controls write_def to output LEF via information. By
default, write_def does not write out via defined in LEF. Set this variable to true to output LEF
via.
Type: bool
Default: false
Edit: Yes
Reference: write_def_include_lef_vias

write_def_lef_out_version

Specify LEF/DEF output version. Possible string value are 5.5, 5.6, 5.7, 5.8 and 6.0. The
default is 5.8.
Type: enum
Enum Values: 5.5 5.6 5.7 5.8 6.0
Default: 5.8
Edit: Yes
Reference: write_def_lef_out_version

write_def_polygon_die_area

By default write_def writes out polygon DIEAREA if the design is rectilinear. To write out
rectangular DIEAERA along with blockages in cut-out area for a rectilinear design, set this
variable to false.
Type: bool
Default: true
Edit: Yes
Reference: write_def_polygon_die_area

write_def_stream_check_uncolored

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Specify how to check and ignore uncolored shapes on DPT layers during DEF out and stream
out. If true or 1, checks uncolored shapes on all DPT layers; if false or 0, doesn't do check; if
metal_only, only checks uncolored shapes on metal layers, uncolored shapes on cut layers
are ignored. It’s automatically set to metal_only for TSMC N5 and below nodes.
Type: enum
Enum Values: true 1 false 0 metal_only
Default: false
Edit: Yes
Reference: write_def_stream_check_uncolored

write_lec_dft_constraints

write_lec_directory_naming_style

write_lec_files

Specifies whether 'write_do_lec' should write intermediate files to the verification directory
specified by the 'write_lec_directory_naming_style' attribute. If false, no files are written.
Type: bool
Default: true
Edit: Yes
Reference: write_lec_files

write_lef_abstract_customer_header

Write lef abstract files with customer specified header information.

Type: string
Default: ""
Edit: Yes
Reference: write_lef_abstract_customer_header

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write_netlist_full_pin_out

Output all pins.

Type: bool
Default: false
Edit: Yes
Reference: write_netlist_full_pin_out

write_netlist_port_association_style

Do implicit port mapping.

Type: bool
Default: false
Edit: Yes
Reference: write_netlist_port_association_style

write_stream_allow_path_type4

If false, converts PATHTYPE4 to PATHTYPE0.

Type: bool
Default: true
Edit: Yes
Reference: write_stream_allow_path_type4

write_stream_cell_instance_color

stream out the instance based color. The instance mask shift is honored in write_stream.
When the option is on and -merge option is used, the merged gds files with mask shift suffix
must be provided through option -merge.
Type: bool
Default: false
Edit: Yes
Reference: write_stream_cell_instance_color

write_stream_cell_master_color

stream out the cell based color from innovus color engine.
Type: bool
Default: true
Edit: Yes
Reference: write_stream_cell_master_color

write_stream_cell_name_prefix

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Add a prefix to ALL cell names being written out, use user specified prefix can avoid potential
conflict when integrating different macros, which potentially 2 different cells (in 2 different
libraries) with the same name.
Type: string
Default: ""
Edit: Yes
Reference: write_stream_cell_name_prefix

write_stream_cell_name_suffix

Instead of appending color pattern to normal cell names, use user specified suffix. This
applies to fixed color shift (flip) pattern only. i.e., only single shift (flip) pattern applied to the
design.
Type: string
Default: ""
Edit: Yes
Reference: write_stream_cell_name_suffix

write_stream_check_map_file

Check the specified map file. If the objects existed in innovus, but the objects have no objects
mapping in map file, print the missed objects mapping and missed objects in log file, only the
main objects mapping are checked by the option.
Type: bool
Default: false
Edit: Yes
Reference: write_stream_check_map_file

write_stream_compatible

Output instance only is FOREIGN is specified.

Type: bool
Default: false
Edit: Yes
Reference: write_stream_compatible

write_stream_define_via_name

Specifies the naming convention that the write_stream command uses for via cells declared in
the DEF file.
Type: string
Default: default
Edit: Yes
Reference: write_stream_define_via_name

write_stream_ignore_fixed_mask

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Ignore macro FIXEDMASK keywords, enable color flip function.

Type: bool
Default: false
Edit: Yes
Reference: write_stream_ignore_fixed_mask

write_stream_label_all_pin_shape

If true, label pin name to its all shapes.

Type: bool
Default: false
Edit: Yes
Reference: write_stream_label_all_pin_shape

write_stream_merge_append

Append cell color information in current design to cell geometries that are from merging files.
This option is for TSMC 10nm fixed-mask design. It is exclusive with
write_stream_ignore_inst_color attribute and write_stream_ignore_inst_cce_color attribute, it
will set those two attributes to false automatically when it is set to true.
Type: bool
Default: false
Edit: Yes
Reference: write_stream_merge_append

write_stream_merge_trim_shapes

Specify the setting for trim shapes merge. layers, specify the layer list which need merge trim
shapes. gap merge, the trim shapes when end to end gap is less the value. max_trim_num,
specify the max trim shapes number are merged. masks, specify the trim shapes color need to
be merged.
Type: string
Default: ""
Edit: Yes
Reference: write_stream_merge_trim_shapes

write_stream_oasis_cell_offset

Include cell offset table to declare the byte offset from the beginning of the file (byte 0) to where
the corresponding CELL record appears in the file.
Type: bool
Default: false
Edit: Yes
Reference: write_stream_oasis_cell_offset

write_stream_oasis_compression

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CBLOCK compression is partial-selective encryption technology uses OASIS CBLOCK

records to encrypt arbitrarily encapsulated sets of data records within an OASIS layout file.
REPETITION compression supports an 'array' of cell placements, geometries, or text
elements, instead of write each the element separate only different in position, this can save
duplicate information for an OASIS layout file size.
Type: bool
Default: true
Edit: Yes
Reference: write_stream_oasis_compression

write_stream_oasis_layer_name

Support LAYERNAME in OASIS file.

Type: bool
Default: false
Edit: Yes
Reference: write_stream_oasis_layer_name

write_stream_pin_text_orientation

Output pin name on the boundary of design to improve readability.

Type: string
Default: ""
Edit: Yes
Reference: write_stream_pin_text_orientation

write_stream_remove_nets

Don't output nets in the list.

Type: string
Default: ""
Edit: Yes
Reference: write_stream_remove_nets

write_stream_snap_to_mfg

Snap net's wire to manufacture grid if it is not.

Type: bool
Default: false
Edit: Yes
Reference: write_stream_snap_to_mfg

write_stream_stream_convert_rect_to_path

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When enabled, DEF SPECIALNETS path/rect and FILLS shapes are converted to
GDSII/stream PATH data instead of BOUNDARY data. Conversion to path data can result in
significantly smaller output database when there are many rectangle shapes (example: after
metal fill is included).
Type: bool
Default: false
Edit: Yes
Reference: write_stream_stream_convert_rect_to_path

write_stream_stream_version

Specify GDSII version to output.

Type: int
Default: 3
Edit: Yes
Reference: write_stream_stream_version

write_stream_text_size

Changes the size of the text used in the text labels.

Type: double
Default: 1.0
Edit: Yes
Reference: write_stream_text_size

write_stream_uniquify_cell_names_prefix

Adds a prefix, instead of a suffix, to uniquified cell names.

Type: bool
Default: false
Edit: Yes
Reference: write_stream_uniquify_cell_names_prefix

write_stream_via_names

Determines the naming convention used for vias declared in the LEF file.
Type: bool
Default: false
Edit: Yes
Reference: write_stream_via_names

write_stream_virtual_connection

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Specifies whether a colon (:) label is appended to pin names for DEF pins with the .extraN
syntax and to LEF pins with multiple ports (if -output_macros is specified for LEF pin ports that
have disjoint shapes).
Type: bool
Default: true
Edit: Yes
Reference: write_stream_virtual_connection

route_blockage

Parent Objects
design, root

Definition
Routing blockage

Attribute Description

density

The density percentage allowed for a partial routing blockage. It causes the global router to
only use up to this percent of the routing resource on the layer in the blockage area, so the
global router will see higher congestion and put fewer routes on that layer in the area.
Type: int
Default: ""
Edit: Yes

design_rule_width

Specifies that the blockage has an effective width for the purposes of spacing calculations to
other shapes on the same layer. A value of 0 indicates that there is no specified
design_rule_width value. The design_rule_width and spacing attributes are not allowed to
have non-default values at the same time, so the design_rule_width value cannot be changed
when the spacing attribute's value is not the default.
Type: coord
Default: no_value
Edit: Yes

inst

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The instance that the routing blockage is associated with (equivalent to DEF BLOCKAGES +
COMPONENT)
Type: obj(inst)
Default: ""
Edit: No

is_except_pg_net

Indicates that Power/Ground routing is ignored when checking for DRC violations (including
shorts) involving the current shape (equivalent to DEF BLOCKAGES + EXCEPTPGNET)
Type: bool
Default: false
Edit: Yes

is_no_wrong_way

Block wrong way routing. Only real routing wires are honored to not have jogs in this region.
Type: bool
Default: ""
Edit: No

is_pushdown

Indicates that routing blockage has been pushed down from a higher level in the design
hierarchy. The idea is that the routing blockage is owned by a higher level(equivalent to DEF
BLOCKAGES + PUSHDOWN)
Type: bool
Default: false
Edit: Yes

layer

layer of blockage
Type: obj(layer)
Default: ""
Edit: Yes

name

name of blockage
Type: string
Default: ""
Edit: Yes

obj_type

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The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (route_blockage)
Default: ""
Edit: No

rects

List of non-overlapping rectangles that defines the shape of the route_blockage. If the
blockage was defined with a polygon, it is broken up into non-overlapping rectangles
Type: rect*
Default: ""
Edit: No

shapes

List of shapes that define the blockage area

Type: obj(shape)*
Default: ""
Edit: No

spacing

Specifies the minimum spacing allowed between the blockage and any other shape on the
same layer (e.g. DEF BLOCKAGES with +SPACING). If there is no spacing value defined, the
default is -1 in DB units, which will appear like a small value < 0 (e.g.-0.0005 if the get_db
db_units is 2000). The design_rule_width and spacing attributes are not allowed to have non-
default values at the same time, so the spacing value cannot be changed when the
design_rule_width attribute's value is also set. To reset the spacing value use [set_db -dbu
route_blockages .spacing -1].
Type: coord
Default: no_value
Edit: Yes

type

The routing blockage type. default: means the blockage is completely blocked and check_drc
will treat it like min-width routing for spacing checks. partial: means a percentage of the routing
resource is available on the layer (see density attribute). fills: means do not add any metal fill
in the area. slots: means don't add slots to the area. slots is not used in Innovus but is allowed
to match DEF. The type corresponds to the DEF BLOCKAGES + FILLS or + SLOTS value.
There is no DEF syntax for 'partial', so partial blockages are currently lost when written to
DEF.
Type: enum
Enum Values: default slots fills partial
Default: ""
Edit: Yes

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Database Objects--route_rule

route_rule

Parent Objects
patch_wire, track_pattern, wire, pg_base_pin, via, route_type, root, base_pin

Definition
Rule information

Attribute Description

is_from_lib

Indicates whether the rule came from the library technology (true: from LEF or OA tech) or from
the design (false: from DEF, OA database, or create_route_rule).
Type: bool
Default: ""
Edit: No

is_hard_spacing

Indicates that any spacing values that exceed the LEF LAYER spacing requirements are
'hard' rules instead of 'soft' rules.
Type: bool
Default: ""
Edit: No

layer_rules

List of layers rules

Type: obj(layer_rule)*
Default: ""
Edit: No

min_cuts

List of cut layer and minimum number of cuts allowed for any via using the specified cut layer
Type: string*
Default: ""
Edit: No

name

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Database Objects--route_type

Name of non-default rule.

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (route_rule)
Default: ""
Edit: No

via_defs

List of via, default or USEVIA or derived from mincut.

Type: obj(via_def)*
Default: ""
Edit: No

route_type

Parent Objects
root

Definition
route type

Attribute Description

bottom_mask_layer_num

Specify the bottom layer number that the mask constraint should be applied.
Type: int
Default: 0
Edit: Yes

bottom_one_side_layer_num

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Database Objects--route_type

Specify the bottom layer number that one side spacing constrain should be applied on. By
default, NDR spacing is applied to both sides of an NDR net or wire. Use this to specify the
layer range for wires that have only one neighboring wire with minimum spacing, which
means only one side needs to follow larger NDR spacing.
Type: int
Default: 0
Edit: Yes

bottom_preferred_layer

driver_use_multi_cut_via

If true, then driver pins will use multi-cut vias.

Type: bool
Default: false
Edit: Yes

em_route_rule

Specifies the EM route_rule to associate with this route type. When routing within the distance
specified in route_em_rule_distance from the output pin, the router will use this route_rule to
route. By default no route_em_rule is used.
Type: string
Default: ""
Edit: Yes

em_route_rule_distance

Specifies the distance from the output pin, when the route_em_rule is applied to the net. This
allows a larger width route_rule for a short distance to avoid EM violations near the output pin.
When routing outside this distance from the output pin, the router uses the normal net
route_rule.
Type: double
Default: no_value
Edit: Yes

is_table

Indicates that whether the route type is table based.

Type: bool
Default: ""
Edit: No

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Database Objects--route_type

mask

Indicates mask number for multiple mask layer usage. Refer to layers .numMask attribute for
valid range, 0 indicates unconstrained. Layers that do not support the specified value will be
treated as unconstrained. (Legal range: 0-3).
Type: int
Default: 0
Edit: Yes

min_stack_layer

The net should use a stacked via from output pins up to the given layer before starting normal
routing. This is normally used to force the routing to higher layers with wider widths to reduce
wiring resistance or avoid EM current limits for high-drive outputs. If output_stack_via_rule or
input_stack_via_rule is also specified, the specified stack via rule is used for the input or
output pins accordingly. If both output_stack_via_rule/input_stack_via_rule are not specified, a
single-cut stacked-via will be used for the output pins only.
Type: obj(layer)
Default: ""
Edit: Yes

name

Name of route_type object.

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (route_type)
Default: ""
Edit: No

route_effort

route effort
Type: enum
Enum Values: low medium high
Default: ""
Edit: Yes

route_rule

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Database Objects--route_type

The non-default rule corresponding to the net, nets with the default routing rule will return
NULL (0x0).
Type: obj(route_rule)
Default: ""
Edit: No

shield_net

shield net
Type: obj(net)
Default: ""
Edit: No

shield_side

Specifies whether to perform one sided or two sided shielding for the route type specified.
Type: enum
Enum Values: one_side both_side
Default: ""
Edit: Yes

shield_tap_instance_insertion_effort

stack_distance

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Database Objects--row

Specifies that the cut distance of cuts on adjacent layers in the stacked vias are defined in
min_stack_layer.
Type: enum
Enum Values: double
Default: no_value
Edit: Yes

top_mask_layer_num

Specify the top layer number that the mask constraint should be applied.
Type: int
Default: 0
Edit: Yes

top_one_side_layer_num

Specify the top layer number that one side spacing constrain should be applied on. By default,
NDR spacing is applied to both sides of an NDR net or wire. Use this to specify the layer
range for wires that have only one neighboring wire with minimum spacing, which means only
one side needs to follow larger NDR spacing.
Type: int
Default: 0
Edit: Yes

top_preferred_layer

The preferred highest routing layer. This attribute is a soft limit; that is, NanoRoute might use a
layer above the specified layer if necessary to complete routing.
Type: obj(layer)
Default: ""
Edit: No

row

Parent Objects
design, root

Definition
Row (core), constructed from sites (equivalent to DEF ROWS)

Attribute Description

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Database Objects--row

name

Name of row (generated name)

Type: string
Default: ""
Edit: No

num_x

Number of sites in X direction (refer to DEF ROW syntax)

Type: int
Default: ""
Edit: Yes

num_y

Number of sites in Y direction (refer to DEF ROW syntax)

Type: int
Default: ""
Edit: Yes

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (row)
Default: ""
Edit: No

orient

Orientation of the sites in the row

Type: enum
Enum Values: r0 r90 r180 r270 mx mx90 my my90
Default: ""
Edit: Yes

rect

Rectangle that defines the row shape

Type: rect
Default: ""
Edit: No

site

The site used in the row

Type: obj(site)
Default: ""
Edit: Yes

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Database Objects--sdp

step_x

Step in the X direction (refer to DEF ROW syntax)

Type: coord
Default: no_value
Edit: Yes

step_y

Step in the Y direction (refer to DEF ROW syntax)

Type: coord
Default: no_value
Edit: Yes

sdp

Parent Objects
inst, design, root

Definition
A structured datapath object. Each sdp is formed hierarchically from a list of sdps below it. Each sdp can be a
row, column, space or inst (see .type). At the leaf-level, an sdp can only be a space or inst. See the
create_sdp_group command for more help.

Attribute Description

bbox

Bounding box of the data path.

Type: rect
Default: ""
Edit: No

flip

Specifies if an sdp group or an sdp element is flipped in vertical, horizontal, or both directions.
If an sdp group is flipped, its members will also be flipped.
Type: enum
Enum Values: none flip_x flip_y flip_xy
Default: ""
Edit: Yes

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Database Objects--sdp

hier_name

Specifies the hierarchical path name prepended to inst names inside the sdp file. This
attribute is only available when .is_top = 1.
Type: string
Default: ""
Edit: Yes

insts

All the insts from a hierarchical descent below this sdp to the bottom of the tree.
Type: obj(inst)*
Default: ""
Edit: No

is_placed

Specifies if the data path is placed. This attribute is only available when .is_top = 1.
Type: bool
Default: ""
Edit: No

is_top

Indicates that the data path is a top data path group.

Type: bool
Default: ""
Edit: No

justify_by

Specifies the anchor point that will be used for aligning an sdp group or an sdp element. If the
justify_by constraint is not specified at current level, it will be inherited from its parent level.
Type: enum
Enum Values: sw se nw ne mid
Default: ""
Edit: Yes

local_list

An ordered list of sdp objects and inst objects contained by this sdp (e.g. just one-level of the
sdp hierarchy).
Type: obj(sdp)* obj(inst)*
Default: ""
Edit: No

location

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Database Objects--sdp

Lower left location of the data path.

Type: point
Default: ""
Edit: Yes

name

Name of Data Path.

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (sdp)
Default: ""
Edit: No

orient

The orientation of an sdp group or an sdp element. If the orientation is specified at sdp group
level, it will be applied to instances that belong to this sdp group.
Type: enum
Enum Values: r0 r180 mx my none
Default: ""
Edit: Yes

parent

Return parent sdp group that the sdp belongs to.

Type: obj(sdp)
Default: ""
Edit: No

pin_alignment

The sdp edge to use for pin alignment. The w, e, mid values are only available for sdp objects
in a column sdp group (.type = column), that have .pin_names set. All others will have a value
of unknown.
Type: enum
Enum Values: unknown w e mid
Default: ""
Edit: Yes

pin_names

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Database Objects--shape

The pin names by which sdps are aligned using the .pin_alignment setting.
Type: string*
Default: ""
Edit: Yes

sdps

List of all the sdps from a hierarchical descent inside and below this sdp.
Type: obj(sdp)*
Default: ""
Edit: No

snap_row_site_index

Specifies the single row site that SDP bbox should snap to.
Type: int
Default: -1
Edit: Yes

space

Specifies a space value to be skipped. If the space value is defined in a column, then this
value is for row skipping and represents the number of skipped rows. If the space value is
defined in a row, then this value is for column skipping and represents the number of M2
tracks (pitch of first vertical routing layer). This attribute is only valid when .type = space.
Type: string
Default: ""
Edit: Yes

type

Type of data path object. A row or column sdp has a .local_list with an ordered list of sdp and
inst objects, while a space type only has a .space value.
Type: enum
Enum Values: row column space
Default: ""
Edit: No

shape

Parent Objects
route_blockage, place_blockage, layer_shape

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Database Objects--shape

Definition
A LEF PIN or OBS single-layer shape (RECT, POLYGON or PATH statement). Note that PATH statements
are converted to one or more equivalent rect shapes. See shape_vias for a LEF VIA used in a PIN or OBS
statement.

Attribute Description

mask

Indicates mask number for multiple mask layer usage. Refer to layer's .num_masks attribute
for legal range, 0 indicates uncolored.
Type: int
Default: 0
Edit: Yes

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (shape)
Default: ""
Edit: No

polygon

Points of the polygon for either rect or polygon shapes.

Type: polygon
Default: ""
Edit: No

rect

Bounding box for either rect or polygon shapes.

Type: rect
Default: ""
Edit: No

type

The shape type (rect or polygon). A LEF PATH statement is converted to one or more rect
shapes.
Type: enum
Enum Values: rect polygon
Default: ""
Edit: Yes

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Database Objects--shape_via

shape_via

Parent Objects
base_cell, physical_pin

Definition
layer shape via

Attribute Description

bottom_mask

Indicates mask number for bottom layer for multiple mask layer usage. Refer to layer's
.numMask attribute for legal range, 0 indicates uncolored
Type: int
Default: 0
Edit: Yes

bottom_rects

List of rectangles (typically only one) on bottom routing layer in terms of design coordinates
(equivalent attribute on the via master is in coordinates local to the via master)
Type: rect
Default: ""
Edit: No

cut_mask

Indicates mask number for cut layer for multiple mask layer usage. Applies to lower left cut of
the via, other cuts are rotated from the reference cut in the lower left corner. Refer to layer's
.numMask attribute for legal range, 0 indicates uncolored},cutMask,,
Type: int
Default: 0
Edit: Yes

cut_rects

List of rectangles on cut layer in terms of design coordinates (equivalent attribute on the via
master is in coordinates local to the via master).
Type: rect*
Default: ""
Edit: No

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Database Objects--site

location

Via location
Type: point
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (shape_via)
Default: ""
Edit: No

top_mask

Indicates mask number for top layer for multiple mask layer usage. Refer to layer's .numMask
attribute for legal range, 0 indicates uncolored
Type: int
Default: 0
Edit: Yes

top_rects

List of rectangles (typically only one) on top routing layer in terms of design coordinates
(equivalent attribute on the via master is in coordinates local to the via master)
Type: rect
Default: ""
Edit: No

via_def

The via master of this via

Type: obj(via_def)
Default: ""
Edit: No

site

Parent Objects
base_cell, design, row, power_domain, root

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Database Objects--site

Definition
LEF SITE

Attribute Description

class

Site class (equivalent to LEF SITE CLASS)

Type: enum
Enum Values: pad core
Default: ""
Edit: No

name

Name of site (equivalent to LEF SITE NAME)

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (site)
Default: ""
Edit: No

size

Size of the site (equivalent to LEF SITE SIZE)

Type: point
Default: ""
Edit: No

symmetry

site symmetry.
Type: enum
Enum Values: none x y xy any
Default: ""
Edit: Yes

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Database Objects--skew_group

skew_group

Parent Objects
pin, root, port

Definition
skew group

Attribute Description

cts_skew_group_constrains

Specifies how this skew group constrains the balancing of sinks during CCOpt.
If set to "default", this skew group will constrain sinks during "clock_design" and during the
initial global balancing step of a regular "ccopt_design" run.
If set to "all", this skew group will constrain both "clock_design" and the whole of
"ccopt_design" - not just the initial solution.
If set to "none" this specifies that the skew group will only be used for reporting purposes.
Valid values: none default all
Type: string
Default: default
Edit: Yes

cts_skew_group_created_from_clock

This contains the name of the SDC clock that this skew group has been created
to represent the balancing constraints in CCOpt.
Valid values: string
Type: string
Default: ""
Edit: Yes

cts_skew_group_created_from_constraint_mode

This contains the name of the constraint mode that this skew_group has been
created to represent the balancing constraints in CCOpt.
Valid values: string
Type: string
Default: ""
Edit: Yes

cts_skew_group_created_from_delay_corners

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Database Objects--skew_group

This contains the delay corners associated with this

skew_group that has been created to represent the balancing constraints in CTS.
Valid values: string
Type: string
Default: ""
Edit: Yes

cts_skew_group_include_source_latency

Specifies whether clock tree source latency should be included when timing the skew group.
Valid values: true false
Type: bool
Default: false
Edit: Yes

cts_skew_group_target_insertion_delay

The target insertion delay used for clock tree synthesis. This may be set to
the following values:
auto - Allow the minimum clustered insertion delay to be pushed up a
little (around 5%) to facilitate clock tree power reduction.
A numeric value - Attempt to balance the clock tree to the specified
insertion delay (specified in library units). CTS will attempt
to have a longest clock path delay of no more than this value
plus half of the skew target, and a shortest path delay of no
less than this value minus half the skew target.
The value must be positive and real valued.
Valid values: auto | double
Type: string
Default: auto
Edit: Yes

cts_target_skew

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Database Objects--skew_group

ignore_pins

ignored pins within the skew group

Type: obj(pin)* obj(port)*
Default: ""
Edit: No

name

name of skew_group
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (skew_group)
Default: ""
Edit: No

sinks

sinks (pins or ports) of the skew group

Type: obj(pin)* obj(port)*
Default: ""
Edit: No

sinks_active

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Database Objects--special_via

active sinks (pins or ports) of the skew group

Type: obj(pin)* obj(port)*
Default: ""
Edit: No

sources

source(s) (pins or ports) of the skew group

Type: obj(pin)* obj(port)*
Default: ""
Edit: No

special_via

Parent Objects
net

Definition
A special_via is normally used for power-vias, flip-chip routing, and sometimes pre-routed nets. special_vias
(along with special_wires) are not changed during signal routing. They appear in the DEF SPECIALNETS
section.

Attribute Description

bottom_mask

Is the mask number for the lower, left shape on the bottom layer of the via. Normally there is
only one shape on the bottom layer of a via, but if there are two or more bottom layer shapes,
then the mask for the other shapes on the bottom layer are derived from the corresponding
via_def mask values by "shifting" the via_def's mask values to match. See the DEF manual
section on 'Multi-Mask Layers with Special Wiring' for figures and examples. A value of 0
indicates the bottom layer is uncolored, or the layer is not a multi-mask layer.
Type: int
Default: 0
Edit: Yes

bottom_rects

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Database Objects--special_via

bottom_rects_mask

List of mask values for each rect in bottom_rects in the same order as bottom_rects. A value of
0 means it is uncolored, or this layer is not a multi-mask layer.
Type: int*
Default: ""
Edit: No

cut_mask

Is the mask number for the lower, left cut of the via. The mask for the other cuts of the
special_via are derived from the via_def by "shifting" the via_def's cut masks to match. So, if
the via_def lower, left cut is mask 1, and the special_via cut_mask is set to 3, then all the
via_def cuts on mask 1 become mask 3 for this special_via, and similarly cuts on 2 shift to 1,
and cuts on 3 shift to 2. See the layer .num_masks attribute for the max mask value allowed.
See the DEF manual section on 'Multi-Mask Layers with Special Wiring' for figures and
examples. A value of 0 indicates the cut layer is uncolored, or the layer is not a multi-mask
layer.
Type: int
Default: 0
Edit: Yes

cut_rects

List of rectangles on cut layer in terms of design coordinates (equivalent attribute on the via
master is in coordinates local to the via master)
Type: rect*
Default: ""
Edit: No

cut_rects_mask

List of mask values for each rect in cut_rects in the same order as cut_rects. A value of 0
means it is uncolored, or this layer is not a multi-mask layer.
Type: int*
Default: ""
Edit: No

net

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Database Objects--special_via

The net that the special_via belongs to

Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (special_via)
Default: ""
Edit: No

point

Location of Via
Type: point
Default: ""
Edit: No

shape

DEF SPECIALNETS + SHAPE equivalents (ring, stripe, etc.)

Type: enum
Enum Values: notype ring stripe followpin iowire corewire blockwire fillwire blockagewire
padring blockring drcfill fillwireopc
Default: ""
Edit: Yes

shield_net

The net that is shielded if status is shield

Type: obj(net)
Default: ""
Edit: No

status

Wiring status (equivalent to DEF SPECIALNETS special wiring status)

Type: enum
Enum Values: routed fixed cover shield unknown
Default: ""
Edit: Yes

top_mask

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Database Objects--special_wire

Is the mask number for the lower, left shape on the top layer of the via. Normally there is only
one shape on the top layer of a via, but if there are two or more top layer shapes, then the
mask for the other shapes on the top layer are derived from the corresponding via_def mask
values by "shifting" the via_def's mask values to match. See the DEF manual section on
'Multi-Mask Layers with Special Wiring' for figures and examples. A value of 0 indicates the
top layer is uncolored, or the layer is not a multi-mask layer.
Type: int
Default: 0
Edit: Yes

top_rects

top_rects_mask

List of mask values for each rect in top_rects in the same order as top_rects. A value of 0
means it is uncolored, or this layer is not a multi-mask layer.
Type: int*
Default: ""
Edit: No

user_class

User_class value (empty string is returned if no user_class is specified)

Type: string
Default: ""
Edit: Yes

via_def

The via master

Type: obj(via_def)
Default: ""
Edit: No

special_wire

Parent Objects
net

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Database Objects--special_wire

Definition
Special wire (equivalent to DEF SPECIALNETS wiring)

Attribute Description

area

Area of the special wire as defined by the LEF MACRO SIZE or OVERLAP information
Type: area
Default: ""
Edit: No

begin_extension

Extension of path at the first point (only on path type)

Type: coord
Default: ""
Edit: No

end_extension

Extension of path at the last point (only on path type)

Type: coord
Default: ""
Edit: No

has_trim_metal

Indicate the special wire has trimm etal or not

Type: bool
Default: ""
Edit: No

layer

The layer of special_wire

Type: obj(layer)
Default: ""
Edit: No

mask

Indicates mask number for multiple mask layer usage. Refer to layer's .numMask attribute for
legal range, 0 indicates uncolored.
Type: int
Default: 0
Edit: Yes

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Database Objects--special_wire

net

The net that the special_wire belongs to

Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (special_wire)
Default: ""
Edit: No

path

2 points for pathSeg center-line, n points for path center-line, n points for polygon, null for rect
Type: point*
Default: ""
Edit: No

polygon

Polygon boundary for the object, the first point is not repeated as the last point in the list
Type: polygon
Default: ""
Edit: No

rect

Rectangle that defines the special_wire shape if type = rect, or if type = path_seg and it is
orthogonal. If type = polygon, or 45-degree path_seg, this is the bounding box of the shape
Type: rect
Default: ""
Edit: Yes

shape

DEF SPECIALNETS + SHAPE equivalents (ring, stripe, etc.)

Type: enum
Enum Values: notype ring stripe followpin iowire corewire blockwire fillwire blockagewire
padring blockring drcfill fillwireopc
Default: ""
Edit: Yes

shield_net

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Database Objects--special_wire

The net that is shielded if status is shieldNet

Type: obj(net)
Default: ""
Edit: No

status

Wiring status (equivalent to DEF SPECIALNETS special wiring status)

Type: enum
Enum Values: routed fixed cover shield unknown
Default: ""
Edit: Yes

trim_metal_color

Color of this special wire trim metal

Type: int
Default: ""
Edit: No

trim_metal_rect

The trim_metal rect if the special_wire has a trim_metal shape attached. This only occurs for
some advanced node layers that use self-aligned patterning. {0 0 0 0} is returned if there is no
trim_metal attached.
Type: rect
Default: ""
Edit: No

type

Type of shape (rect, polygon, etc.)

Type: enum
Enum Values: rect polygon path_seg path
Default: ""
Edit: No

user_class

User_class value (empty string is returned if no user_class is specified)

Type: string
Default: ""
Edit: Yes

width

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Database Objects--stack_via_rule

Width of path/pathSeg type

Type: coord
Default: no_value
Edit: Yes

stack_via_rule

Parent Objects
pin, root, base_pin

Definition
Stack via rule information

Attribute Description

name

Stack Via Rule name.

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (stack_via_rule)
Default: ""
Edit: No

text

Parent Objects
design, root

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Database Objects--stack_via_rule

Definition
Interoperable text labels

Attribute Description

alignment

Horizontal and vertical alignment of the text string

Type: enum
Enum Values: upper_left center_left lower_left upper_center center_center lower_center
upper_right center_right lower_right
Default: ""
Edit: No

drafting

Indicates if the text is always displayed left-to-right or top-to-bottom. Text will remain readable
even if rotated and mirrored if this value is true.
Type: bool
Default: ""
Edit: No

font_name

Font name
Type: enum
Enum Values: euro_style gothic math roman script stick fixed swedish mil_spec
Default: ""
Edit: No

font_number

Font Number
Type: enum
Enum Values: 0 1 2 3 4 5 6 7 8
Default: ""
Edit: No

height

Text height
Type: coord
Default: no_value
Edit: Yes

label

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Database Objects--stack_via_rule

Text string value

Type: string
Default: ""
Edit: Yes

layer

The layer of text

Type: obj(layer)
Default: ""
Edit: Yes

oa_purpose

User specified purpose name for OA text layer purpose pair support. Only values available
that exist in the library's tech graph are allowed. The default value is 'drawing'.
Type: string
Default: ""
Edit: Yes

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (text)
Default: ""
Edit: No

orient

Text Orientation
Type: enum
Enum Values: r0 r90 r180 r270 mx mx90 my my90
Default: ""
Edit: No

point

Text location
Type: point
Default: ""
Edit: No

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Database Objects--timing_condition

timing_condition

Parent Objects
delay_corner, root

Definition
A timing_condition represents a set of libraries at a specific operating condition - effectively defining a device
corner. When assigned to a power domain - the domain uses the library and PVT bindings defined by the
timing_condition. Timing conditions may be assigned to one or several power domains in the design via the
delay_corner object's timing condition attributes. Use the create_timing_condition and
update_timing_condition commands to create and modify timing_conditions.

Attribute Description

library_sets

Specifies the associated library_set object(s). A list of library_sets (a bundle) can be used for
voltage interpolation.
Type: obj(library_set)*
Default: ""
Edit: No

name

Provides the name of this timing_condition object as specified by create_timing_condition.

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (timing_condition)
Default: ""
Edit: No

opcond

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Specifies the associated opcond object. If this is not set, the opcond is derived from timing
library itself. The root attribute timing_default_opcond_per_lib can also affect which opcond is
used if it is not set here.
Type: obj(opcond)
Default: ""
Edit: No

opcond_library

The library of the opcond for this timing condition. Can be empty if this is a virtual opcond.
Type: obj(library)
Default: ""
Edit: No

timing_path

Parent Objects

Definition
cte timing path

Attribute Description

arrival

arrival
Type: double
Default: ""
Edit: No

arrival_mean

Returns the arrival_mean property for a timing_path

Type: double
Default: ""
Edit: No

arrival_sigma

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Returns the arrival_sigma property for a timing_path

Type: double
Default: ""
Edit: No

borrowing_path_q_pin_and_transition

Returns the borrowing_path_q_pin_and_transition property for a timing_path

Type: string
Default: ""
Edit: No

borrowing_path_q_pin_transition

Returns the borrowing_path_q_pin_transition property for a timing_path

Type: string
Default: ""
Edit: No

capture_clock_path

Returns the capture_clock_path property for a timing_path

Type: obj(timing_path)*
Default: ""
Edit: No

capturing_clock

Returns the capturing_clock property for a timing_path

Type: obj(clock)*
Default: ""
Edit: No

capturing_clock_close_edge_time

Returns the capturing_clock_close_edge_time property for a timing_path

Type: double
Default: ""
Edit: No

capturing_clock_close_edge_type

Returns the capturing_clock_close_edge_type property for a timing_path

Type: string
Default: ""
Edit: No

capturing_clock_is_inverted

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Returns the capturing_clock_is_inverted property for a timing_path

Type: bool
Default: ""
Edit: No

capturing_clock_is_propagated

Returns the capturing_clock_is_propagated property for a timing_path

Type: bool
Default: ""
Edit: No

capturing_clock_latency

Returns the capturing_clock_latency property for a timing_path

Type: double
Default: ""
Edit: No

capturing_clock_latency_mean

Returns the capturing_clock_latency_mean property for a timing_path

Type: double
Default: ""
Edit: No

capturing_clock_latency_sigma

Returns the capturing_clock_latency_sigma property for a timing_path

Type: double
Default: ""
Edit: No

capturing_clock_latency_skewness

Returns the capturing_clock_latency_skewness property for a timing_path

Type: double
Default: ""
Edit: No

capturing_clock_latency_stddev

Returns the capturing_clock_latency_stddev property for a timing_path

Type: double
Default: ""
Edit: No

capturing_clock_open_edge_type

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Returns the capturing_clock_open_edge_type property for a timing_path

Type: string
Default: ""
Edit: No

capturing_clock_pin

Returns the capturing_clock_pin property for a timing_path

Type: obj(pin)*
Default: ""
Edit: No

capturing_clock_source_arrival_time

Returns the capturing_clock_source_arrival_time property for a timing_path

Type: double
Default: ""
Edit: No

capturing_clock_source_arrival_time_mean

Returns the capturing_clock_source_arrival_time_mean property for a timing_path

Type: double
Default: ""
Edit: No

capturing_clock_source_arrival_time_sigma

Returns the capturing_clock_source_arrival_time_sigma property for a timing_path

Type: double
Default: ""
Edit: No

capturing_point

Returns a pointer to the end point of the timing path.

Type: obj(port)* obj(pin)*
Default: ""
Edit: No

capturing_point_is_level_sensitive

Returns a value of true if the end point of the data path is level sensitive.
Type: bool
Default: ""
Edit: No

check_delay

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Returns the check_delay property for a timing_path

Type: double
Default: ""
Edit: No

check_delay_mean

Returns the check_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

check_delay_sigma

Returns the check_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

check_type

Returns the check_type property for a timing_path

Type: string
Default: ""
Edit: No

clock_path_end_point

clock_path_end_point
Type: obj(timing_point)*
Default: ""
Edit: No

clock_source_jitter

clock_source_jitter
Type: double
Default: ""
Edit: No

clock_uncertainty

clock_uncertainty
Type: double
Default: ""
Edit: No

cppr_adjustment

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Returns the CPPR adjustment of the timing path.

Type: double
Default: ""
Edit: No

cppr_adjustment_mean

Returns the cppr_adjustment_mean property for a timing_path

Type: double
Default: ""
Edit: No

cppr_adjustment_sigma

Returns the cppr_adjustment_sigma property for a timing_path

Type: double
Default: ""
Edit: No

cppr_branch_point

Returns the CPPR branch point of the given timing path.

Type: obj(port)* obj(pin)*
Default: ""
Edit: No

cumulative_manhattan_length

Returns the cumulative_manhattan_length property for a timing_path.

Type: double
Default: ""
Edit: No

cumulative_manhattan_length_x

Returns the cumulative_manhattan_length_x poperty for a timing_path.

Type: double
Default: ""
Edit: No

cumulative_manhattan_length_y

Returns the cumulative_manhattan_length_y property for a timing_path.

Type: double
Default: ""
Edit: No

cycle_adjustment

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Returns the cycle_adjustment property for a timing_path

Type: double
Default: ""
Edit: No

drive_adjustment

Returns the drive_adjustment property for a timing_path

Type: double
Default: ""
Edit: No

drive_adjustment_mean

Returns the drive_adjustment_mean property for a timing_path

Type: double
Default: ""
Edit: No

drive_adjustment_sigma

Returns the drive_adjustment_sigma property for a timing_path

Type: double
Default: ""
Edit: No

external_delay

external_delay
Type: double
Default: ""
Edit: No

gba_slack

Returns the gba_slack property for a timing_path

Type: double
Default: ""
Edit: No

gba_slack_mean

Returns the gba_slack_mean property for a timing_path

Type: double
Default: ""
Edit: No

gba_slack_sigma

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Returns the gba_slack_sigma property for a timing_path

Type: double
Default: ""
Edit: No

hold

hold
Type: double
Default: ""
Edit: No

is_clock_gating_hold

Returns a value of true if the path is a clock gating hold check.

Type: bool
Default: ""
Edit: No

is_clock_gating_setup

Returns a value of true if the path is a clock gating setup check.

Type: bool
Default: ""
Edit: No

is_invalid

Returns the is_invalid property for a timing_path

Type: bool
Default: ""
Edit: No

is_path_borrowing

Returns the is_path_borrowing property for a timing_path

Type: bool
Default: ""
Edit: No

is_retimed

Returns the is_retimed property for a timing_path

Type: bool
Default: ""
Edit: No

is_time_given

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Returns the is_time_given property for a timing_path

Type: bool
Default: ""
Edit: No

is_transparent_latch

Returns a value of true if the path is a transparent latch path.

Type: bool
Default: ""
Edit: No

launch_clock_path

launch_clock_path
Type: obj(timing_path)*
Default: ""
Edit: No

launching_clock

launching_clock
Type: obj(clock)*
Default: ""
Edit: No

launching_clock_is_inverted

launching_clock_is_inverted
Type: bool
Default: ""
Edit: No

launching_clock_is_propagated

launching_clock_is_propagated
Type: bool
Default: ""
Edit: No

launching_clock_latency

launching_clock_latency
Type: double
Default: ""
Edit: No

launching_clock_open_edge_time

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launching_clock_open_edge_time
Type: double
Default: ""
Edit: No

launching_clock_open_edge_type

launching_clock_open_edge_type
Type: string
Default: ""
Edit: No

launching_clock_source_arrival_time

launching_clock_source_arrival_time
Type: double
Default: ""
Edit: No

launching_clock_source_arrival_time_mean

Returns the launching_clock_source_arrival_time_mean property for a timing_path

Type: double
Default: ""
Edit: No

launching_clock_source_arrival_time_sigma

Returns the launching_clock_source_arrival_time_sigma property for a timing_path

Type: double
Default: ""
Edit: No

launching_input_delay

launching_input_delay
Type: double
Default: ""
Edit: No

launching_point

Returns a pointer to the start point of the timing path.

Type: obj(port)* obj(pin)*
Default: ""
Edit: No

launching_point_is_level_sensitive

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Database Objects--timing_path

Returns a value of true if the begin point of the data path is level sensitive.
Type: bool
Default: ""
Edit: No

lending_path_d_pin

Returns the lending_path_d_pin property for a timing_path

Type: string
Default: ""
Edit: No

lending_path_d_pin_transition

Returns the lending_path_d_pin_transition property for a timing_path

Type: string
Default: ""
Edit: No

nets

Returns a collection of nets of the timing path.

Type: obj(net)*
Default: ""
Edit: No

num_cell_arcs

Returns the num_cell_arcs property for a timing_path

Type: double
Default: ""
Edit: No

num_net_arcs

Returns the num_net_arcs property for a timing_path

Type: double
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (timing_path)
Default: ""
Edit: No

other_end_arrival

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Returns the other_end_arrival property for a timing_path

Type: double
Default: ""
Edit: No

other_end_arrival_mean

Returns the other_end_arrival_mean property for a timing_path

Type: double
Default: ""
Edit: No

other_end_arrival_sigma

Returns the other_end_arrival_sigma property for a timing_path

Type: double
Default: ""
Edit: No

other_end_arrival_skewness

Returns the other_end_arrival_skewness property for a timing_path

Type: double
Default: ""
Edit: No

other_end_arrival_stddev

Returns the other_end_arrival_stddev property for a timing_path

Type: double
Default: ""
Edit: No

path_adjust_value

Returns the path_adjust_value property for a timing_path

Type: double
Default: ""
Edit: No

path_cell_delay

Returns the path_cell_delay property for a timing_path

Type: double
Default: ""
Edit: No

path_cell_delay_mean

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Returns the path_cell_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

path_cell_delay_sigma

Returns the path_cell_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

path_delay

Returns the path_delay property for a timing_path

Type: double
Default: ""
Edit: No

path_delay_adjustment

Returns the path_delay_adjustment property for a timing_path

Type: double
Default: ""
Edit: No

path_delay_mean

Returns the path_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

path_delay_sigma

Returns the path_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

path_group

path_group
Type: obj(path_group)*
Default: ""
Edit: No

path_group_name

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Database Objects--timing_path

Returns the name of the path group for the timing path.
Type: string
Default: ""
Edit: No

path_net_delay

Returns the path_net_delay property for a timing_path

Type: double
Default: ""
Edit: No

path_net_delay_mean

Returns the path_net_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

path_net_delay_sigma

Returns the path_net_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

path_type

Reports max type for late path and min type for early path
Type: string
Default: ""
Edit: No

period

Returns the period property for a timing_path

Type: double
Default: ""
Edit: No

phase_shift

Returns the phase_shift property for a timing_path

Type: double
Default: ""
Edit: No

real_gba_arrival

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Returns the real_gba_arrival property for a timing_path

Type: double
Default: ""
Edit: No

real_gba_arrival_mean

Returns the real_gba_arrival_mean property for a timing_path

Type: double
Default: ""
Edit: No

real_gba_arrival_sigma

Returns the real_gba_arrival_sigma property for a timing_path

Type: double
Default: ""
Edit: No

real_gba_arrival_skewness

Returns the real_gba_arrival_skewness property for a timing_path

Type: double
Default: ""
Edit: No

real_gba_arrival_stddev

Returns the real_gba_arrival_stddev property for a timing_path

Type: double
Default: ""
Edit: No

real_gba_slack

Returns the real_gba_slack property for a timing_path

Type: double
Default: ""
Edit: No

real_gba_slack_mean

Returns the real_gba_slack_mean property for a timing_path

Type: double
Default: ""
Edit: No

real_gba_slack_sigma

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Returns the real_gba_slack_sigma property for a timing_path

Type: double
Default: ""
Edit: No

real_gba_slack_skewness

Returns the real_gba_slack_skewness property for a timing_path

Type: double
Default: ""
Edit: No

real_gba_slack_stddev

Returns the real_gba_slack_stddev property for a timing_path

Type: double
Default: ""
Edit: No

recovery

Returns the recovery time at the end point of the path.

Type: double
Default: ""
Edit: No

removal

removal
Type: double
Default: ""
Edit: No

required_time

Returns the required time for the timing path.

Type: double
Default: ""
Edit: No

required_time_mean

Returns the required_time_mean property for a timing_path

Type: double
Default: ""
Edit: No

required_time_sigma

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Returns the required_time_sigma property for a timing_path

Type: double
Default: ""
Edit: No

setup

The setup time at the end point of the path.

Type: double
Default: ""
Edit: No

skew

Returns the skew property for a timing_path

Type: double
Default: ""
Edit: No

slack

Returns the slack of the timing path.

Type: double
Default: ""
Edit: No

slack_mean

Returns the slack_mean property for a timing_path

Type: double
Default: ""
Edit: No

slack_sigma

Returns the slack_sigma property for a timing_path

Type: double
Default: ""
Edit: No

spatial_distance

Returns the spatial_distance property for a timing_path

Type: double
Default: ""
Edit: No

time_borrowed

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Returns the amount of time borrowed from the timing end point.
Type: double
Default: ""
Edit: No

time_lent

Returns the amount of time lent to the timing start point.

Type: double
Default: ""
Edit: No

timing_points

timing_points
Type: obj(timing_point)*
Default: ""
Edit: No

total_cell_delta_delay

Returns the total_cell_delta_delay property for a timing_path

Type: double
Default: ""
Edit: No

total_cell_delta_delay_mean

Returns the total_cell_delta_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

total_cell_delta_delay_sigma

Returns the total_cell_delta_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

total_delta_delay

Returns the total_delta_delay property for a timing_path

Type: double
Default: ""
Edit: No

total_delta_delay_mean

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Returns the total_delta_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

total_delta_delay_sigma

Returns the total_delta_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

total_net_delta_delay

Returns the total_net_delta_delay property for a timing_path

Type: double
Default: ""
Edit: No

total_net_delta_delay_mean

Returns the total_net_delta_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

total_net_delta_delay_sigma

Returns the total_net_delta_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

underated_slack

Returns the underated slack time for the timing path. The underated slack value is available
with timing path object only if it is generated using the -derate parameter.
Type: double
Default: ""
Edit: No

view_name

The name of the analysis view for the timing_path

Type: string
Default: ""
Edit: No

worst_cell_delay

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Returns the worst_cell_delay property for a timing_path

Type: double
Default: ""
Edit: No

worst_cell_delay_mean

Returns the worst_cell_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

worst_cell_delay_sigma

Returns the worst_cell_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

worst_cell_delta_delay

Returns the worst_cell_delta_delay property for a timing_path

Type: double
Default: ""
Edit: No

worst_cell_delta_delay_mean

Returns the worst_cell_delta_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

worst_cell_delta_delay_sigma

Returns the worst_cell_delta_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

worst_delay

Returns the worst_delay property for a timing_path

Type: double
Default: ""
Edit: No

worst_delay_mean

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Returns the worst_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

worst_delay_sigma

Returns the worst_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

worst_delta_delay

Returns the worst_delta_delay property for a timing_path

Type: double
Default: ""
Edit: No

worst_delta_delay_mean

Returns the worst_delta_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

worst_delta_delay_sigma

Returns the worst_delta_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

worst_manhattan_length

Returns the worst_manhattan_length property for a timing_path

Type: double
Default: ""
Edit: No

worst_manhattan_length_net_name

Returns the worst_manhattan_length_net_name property for a timing_path.

Type: string
Default: ""
Edit: No

worst_net_delay

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Returns the worst_net_delay property for a timing_path

Type: double
Default: ""
Edit: No

worst_net_delay_mean

Returns the worst_net_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

worst_net_delay_sigma

Returns the worst_net_delay_sigma property for a timing_path

Type: double
Default: ""
Edit: No

worst_net_delta_delay

Returns the worst_net_delta_delay property for a timing_path

Type: double
Default: ""
Edit: No

worst_net_delta_delay_mean

Returns the worst_net_delta_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

worst_net_delta_delay_sigma

Returns the worst_net_delta_delay_mean property for a timing_path

Type: double
Default: ""
Edit: No

timing_point

Parent Objects
timing_path

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Database Objects--timing_point

Definition
cte timing point

Attribute Description

arrival

Returns the arrival time at the timing point.

Type: double
Default: ""
Edit: No

arrival_mean

Returns the arrival_mean property for a timing_point

Type: double
Default: ""
Edit: No

arrival_sigma

Returns the arrival_sigma property for a timing_point

Type: double
Default: ""
Edit: No

delay

Returns the delay property for a timing_point.

Type: double
Default: ""
Edit: No

delay_mean

Returns the delay_mean property of a timing_point

Type: double
Default: ""
Edit: No

delay_sigma

Returns the delay_sigma property for a timing_point.

Type: double
Default: ""
Edit: No

delta_delay

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Returns the delta_delay property for a timing_point

Type: double
Default: ""
Edit: No

direction

Returns the direction property for a timing_point

Type: string
Default: ""
Edit: No

hierarchical_name

Returns the hierarchical_name property for a timing_point

Type: string
Default: ""
Edit: No

is_fanin_arc_cell_arc

Returns cell arc in the fanin of the timing point

Type: bool
Default: ""
Edit: No

is_hierarchical

Returns the is_hierarchical property for a timing_point

Type: bool
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (timing_point)
Default: ""
Edit: No

Returns the pin property for a timing_point

Type: obj(port)* obj(pin)*
Default: ""
Edit: No

slack

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Returns the slack property for a timing_point

Type: double
Default: ""
Edit: No

slack_mean

Returns the slack_mean property for a timing_point

Type: double
Default: ""
Edit: No

slack_sigma

Returns the slack_sigma property for a timing_point

Type: double
Default: ""
Edit: No

slew

Returns the path-specific slew of the timing point.

Type: double
Default: ""
Edit: No

slew_mean

Returns the slew_mean property for a timing_point.

Type: double
Default: ""
Edit: No

slew_sigma

Returns the slew_sigma property for a timing_point

Type: double
Default: ""
Edit: No

spatial_derate

Returns the spatial_derate property for a timing_point

Type: double
Default: ""
Edit: No

spatial_derate_sigma

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Database Objects--timing_point

Returns the spatial_derate_sigma property for a timing_point

Type: double
Default: ""
Edit: No

ssi_derate

Returns the path-specific ssi_derate of the timing point.

Type: double
Default: ""
Edit: No

total_derate

Returns the total_derate property for a timing_point

Type: double
Default: ""
Edit: No

total_derate_sigma

Returns the total_derate_sigma property for a timing_point

Type: double
Default: ""
Edit: No

transition_type

Returns the transition type of the timing point: rise or fall .

Type: string
Default: ""
Edit: No

user_derate

Returns the user_derate property for a timing_point

Type: double
Default: ""
Edit: No

user_derate_sigma

Returns the user_derate_sigma property for a timing_point

Type: double
Default: ""
Edit: No

voltage

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Stylus Common UI Database Object Information
Database Objects--track_pattern

Returns the voltage property for a timing_point

Type: double
Default: ""
Edit: No

track_pattern

Parent Objects
design, root

Definition
Floorplan track information (DEF TRACKS equivalent)

Attribute Description

direction

Specifies the location and direction of the first track defined. x indicates vertical lines; y
indicates horizontal lines.
Type: enum
Enum Values: y x
Default: ""
Edit: No

layers

List of layers
Type: obj(layer)*
Default: ""
Edit: No

mask

Specifies the mask number for the first track.

Type: int
Default: ""
Edit: No

num_tracks

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Database Objects--track_pattern

Specifies the number of tracks to create for the grid

Type: int
Default: ""
Edit: Yes

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (track_pattern)
Default: ""
Edit: No

route_rule

Pointer to route_rule object (DEF NONDEFAULTRULE) to be used as a constraint for wiring

that can be created on the track. An empty value indicates that there is no constraint on the
rules of the wires on the track. This value can be set with add_tracks and is intended for
advanced nodes that do not allow different route_rules on the same track for lower routing
layers.
Type: obj(route_rule)
Default: ""
Edit: No

start

Specifies the coordinate of the first line

Type: coord
Default: no_value
Edit: Yes

step

Specifies the spacing between the tracks

Type: coord
Default: no_value
Edit: Yes

width

Width constraint for wiring that can be created on the track. A value of 0 indicates that there is
no constraint on the width of wires on the track. This value can be set with add_tracks and is
intended for advanced nodes that do not allow different widths on the same track for lower
routing layers.
Type: coord
Default: ""
Edit: No

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Stylus Common UI Database Object Information
Database Objects--via

via

Parent Objects
net

Definition
DEF NETS via instance

Attribute Description

bottom_mask

Is the mask number for the lower, left shape on the bottom layer of the via. Normally there is
only one shape on the bottom layer of a via, but if there are two or more bottom layer shapes,
then the mask for the other shapes on the bottom layer are derived from the corresponding
via_def mask values by "shifting" the via_def's mask values to match. See the DEF manual
section on 'Multi-Mask Patterns for Routing Points' for figures and examples. A value of 0
indicates the bottom layer is uncolored, or the layer is not a multi-mask layer.
Type: int
Default: 0
Edit: Yes

bottom_rects

bottom_rects_mask

List of mask values for each rect in bottom_rects in the same order as bottom_rects. A value of
0 means it is uncolored, or this layer is not a multi-mask layer.
Type: int*
Default: ""
Edit: No

cut_mask

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Stylus Common UI Database Object Information
Database Objects--via

Is the mask number for the lower, left cut of the via. The mask for the other cuts of the via are
derived from the via_def by "shifting" the via_def's cut masks to match. So, if the via_def lower,
left cut is mask 1, and the via cut_mask is set to 3, then all the via_def cuts on mask 1 become
mask 3 for this via, and similarly cuts on 2 shift to 1, and cuts on 3 shift to 2. See the layer
.num_masks attribute for the max mask value allowed. See the DEF manual section on 'Multi-
Mask Patterns for Routing Points' for figures and examples. A value of 0 indicates the cut layer
is uncolored, or the layer is not a multi-mask layer.
Type: int
Default: no_value
Edit: Yes

cut_rects

List of rectangles on cut layer in terms of design coordinates (equivalent attribute on the via
master is in coordinates local to the via master)
Type: rect
Default: ""
Edit: No

cut_rects_mask

List of mask values for each rect in cut_rects in the same order as cut_rects. A value of 0
means it is uncolored, or this layer is not a multi-mask layer.
Type: int*
Default: ""
Edit: No

location

Location of Via
Type: point
Default: ""
Edit: No

net

The net that the via belongs to

Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (via)
Default: ""
Edit: No

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Database Objects--via

route_rule

The non-default rule corresponding to the via, vias with the default routing rule will return an
empty string.
Type: obj(route_rule)
Default: ""
Edit: No

status

Wiring status (equivalent to DEF NETS regular wiring status)

Type: enum
Enum Values: unknown routed fixed cover noshield
Default: ""
Edit: Yes

top_mask

Indicates mask number for top layer for multiple mask layer usage. Refer to layer's .numMask
attribute for legal range, 0 indicates uncolored
Type: int
Default: 0
Edit: Yes

top_rects

top_rects_mask

List of mask values for each rect in top_rects in the same order as top_rects. A value of 0
means it is uncolored, or this layer is not a multi-mask layer.
Type: int*
Default: ""
Edit: No

via_def

The via cell

Type: obj(via_def)
Default: ""
Edit: No

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Stylus Common UI Database Object Information
Database Objects--via_def

via_def

Parent Objects
route_rule, shape_via, via, special_via, root

Definition
A via definition. This is equivalent to the LEF/DEF VIA section statements. A via_def can be either a
parameterized via (VIA with VIARULE parameters), or a fixed via (VIA with just RECT statements). See the
LEF/DEF manual VIA section for more details.

Attribute Description

bottom_layer

The bottom routing layer

Type: obj(layer)
Default: ""
Edit: No

bottom_rects

List of rectangles (typically only one) on bottom routing layer.

Type: rect*
Default: ""
Edit: No

bottom_rects_mask

List of mask values for each rect in bottom_rects in the same order as bottom_rects. A value of
0 means it is uncolored, or this layer is not a multi-mask layer.
Type: int*
Default: no_value
Edit: Yes

cut_class

Returns the name of the CUTCLASS definition (from LEF or OA tech) for the cut_rects in this
via_def. It returns an empty string if no CUTCLASS exists for the cut layer, or no CUTCLASS
matches the size of the cut_rects.
Type: string
Default: ""
Edit: No

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Database Objects--via_def

cut_columns

The number of cut columns. It is only set for generated vias created from a via_def_rule. See
the LEF/DEF manual VIA definition with VIARULE and ROWCOL values for more details. It is
0 for fixed vias (e.g. a LEF/DEF VIA definition with only RECT values).
Type: int
Default: 0
Edit: No

cut_layer

The cut layer of via

Type: obj(layer)
Default: ""
Edit: No

cut_rects

List of rectangles on cut layer

Type: rect*
Default: ""
Edit: No

cut_rects_mask

List of mask values for each rect in cut_rects in the same order as cut_rects. A value of 0
means it is uncolored, or this layer is not a multi-mask layer.
Type: int*
Default: no_value
Edit: Yes

cut_rows

The number of cut rows. It is only set for generated vias created from a via_def_rule. See the
LEF/DEF manual VIA definition with VIARULE and ROWCOL values for more details. It is 0
for fixed vias (e.g. a LEF/DEF VIA definition with only RECT values).
Type: int
Default: 0
Edit: No

cut_size

The {width height} of the first rect in cut_rects in microns.

Type: point
Default: ""
Edit: No

from_design

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Stylus Common UI Database Object Information
Database Objects--via_def

Indicates that the via is from design

from_design = true && from_lib = false: The via is generated from DEF or
create_via_definition.
from_design = false && from_lib = true: The via is generated from LEF.
from_design = true && from_lib = true: The via is generated by NanoRoute.
from_design = false && from_lib = false: The via is generated by VIAGEN.
Type: bool
Default: ""
Edit: No

from_lib

Indicates that the via is from library. See the from_design attribute for more details.
Type: bool
Default: ""
Edit: No

is_default

Indicates that the via is a default via (LEF VIA DEFAULT)

Type: bool
Default: ""
Edit: No

is_non_default

Indicates that the via is declared in a LEF NONDEFAULTRULE

Type: bool
Default: ""
Edit: No

name

Via name
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (via_def)
Default: ""
Edit: No

resistance

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Stylus Common UI Database Object Information
Database Objects--via_def

Via resistance in ohms that is derived from LEF or OA data. This may not match the resistance
of RC extraction results derived from extraction coefficient data. If the via is a fixed via with a
resistance value defined in the LEF VIA definition statement or OA via_def, that value is
returned. For vias without a resistance value, the resistance is computed from the cut-layer
resistance_per_cut value and the number of cuts in the via (or equivalent cuts for a LEF
CUTCLASS or OA cut_class via with different cut sizes). If both the via definition, and the cut-
layer has no resistance value, then 0.0 is returned
Type: double
Default: ""
Edit: No

top_layer

The top routing layer of via

Type: obj(layer)
Default: ""
Edit: No

top_rects

List of rectangles (typically only one) on top routing layer.

Type: rect*
Default: ""
Edit: No

top_rects_mask

List of mask values for each rect in top_rects in the same order as top_rects. A value of 0
means it is uncolored, or this layer is not a multi-mask layer.
Type: int*
Default: no_value
Edit: Yes

via_def_rule

The via_def_rule for this via_def. It is only set for generated vias created from via_def_rule
parameters. See the LEF/DEF manual VIA statement with VIARULE for more details. It returns
{} for fixed vias (e.g. a LEF/DEF VIA with only RECT values).
Type: obj(via_def_rule)
Default: ""
Edit: No

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Database Objects--via_def_rule

via_def_rule

Parent Objects
via_def, root

Definition
Equivalent of one LEF VIARULE GENERATE statement that has the rules to create new generated vias (e.g.
LEF/DEF VIA statements with VIARULE parameters). See the LEF manual for more details.

Attribute Description

bottom_enclosure

Two minimum enclosure values for the cuts in the via. The order of the two values does not
matter. The bottom layer shape must enclose all the cuts by one of the enclosure values in
one direction (e.g. either X or Y), and by the other enclosure value in the other direction. If it is
{0 0}, which is recommended for newer technologies, then only the DRC rules are used to
compute the minimum enclosure..
Type: point
Default: ""
Edit: No

bottom_layer

The bottom routing layer for the via.

Type: obj(layer)
Default: ""
Edit: No

bottom_width

Optional min and max width. If given, this rule should only be used if the bottom wire width is
greater than or equal to the first value (min-width), and less than or equal to the second value
(max-width). For example, {1 2} means min-width is >= 1.0, and max_width is <= 2.0). If not
given, the default is {0 0}, which means this rule can be used for any width.
Type: point
Default: ""
Edit: No

cut_layer

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Stylus Common UI Database Object Information
Database Objects--via_def_rule

The cut layer for the via.

Type: obj(layer)
Default: ""
Edit: No

cut_rect

The size of one cut rectangle.

Type: rect
Default: ""
Edit: No

cut_spacing

Minimum center-to-center spacing in the X and Y directions..

Type: point
Default: ""
Edit: No

name

Via rule name.

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (via_def_rule)
Default: ""
Edit: No

resistance_per_cut

Optional via resistance per cut in ohms that is defined in LEF or OA data. This value is useful
for estimation, but will not match the resistance extracted by RC extraction commands that use
more accurate coefficient files. It is 0.0 if not given in the library data.
Type: double
Default: ""
Edit: No

top_enclosure

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Stylus Common UI Database Object Information
Database Objects--virtual_wire

Two minimum enclosure values for the cuts in the via. The order of the two values does not
matter. The top layer shape must enclose all the cuts by one of the enclosure value in one
direction (e.g. either X or Y), and by the other enclosure value in the other direction. If it is {0 0},
which is recommended, then only the DRC rules are used to compute the minimum enclosure.
Type: point
Default: ""
Edit: No

top_layer

The top routing layer for the via.

Type: obj(layer)
Default: ""
Edit: No

top_width

Optional min and max width. If given, this rule should only be used if the top wire width is
greater than or equal to the first value (min-width), and less than or equal to the second value
(max-width). For example,. {1 2} means min-width is >= 1.0, and max_width is <= 2.0). If not
given, the default is {0 0}, which means this rule can be used for any width.
Type: point
Default: ""
Edit: No

virtual_wire

Parent Objects
net

Definition
DEF NETS VIRTUAL wire

Attribute Description

begin_layer

The begin layer for the virtual connection

Type: obj(layer)
Default: ""
Edit: No

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Stylus Common UI Database Object Information
Database Objects--virtual_wire

begin_point

Reference point to the begin symbolic location

Type: point
Default: ""
Edit: No

end_layer

The end layer for the virtual connection

Type: obj(layer)
Default: ""
Edit: No

end_point

Reference point to the end symbolic location

Type: point
Default: ""
Edit: No

net

The net that the virtual connection belongs to

Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (virtual_wire)
Default: ""
Edit: No

status

Wiring status ( equivalent to DEF NET regular wiring status)

Type: enum
Enum Values: unknown routed fixed cover noshield
Default: ""
Edit: No

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Database Objects--wire

wire

Parent Objects
net

Definition
A 2-point wire segment intended for symbolic routing where the end-points normally align with other wire or
via end-points, or end on a pin shape or special_wire. The wire, via, and patch_wire objects correspond to the
DEF NETS symbolic routing data.

Attribute Description

begin_extension

Extension of wire at the first point

Type: coord
Default: no_value
Edit: Yes

direction

Direction of wire, consistent with layer direction from LEF/OpenAccess

Type: enum
Enum Values: vertical other horizontal
Default: ""
Edit: No

end_extension

Extension of wire at the second point

Type: coord
Default: no_value
Edit: Yes

layer

The layer of wire

Type: obj(layer)
Default: ""
Edit: No

length

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Stylus Common UI Database Object Information
Database Objects--wire

The center-line length of the wire between the two end points. It does not include the
extension values
Type: coord
Default: ""
Edit: No

mask

Indicates mask number for multiple mask layer usage. Refer to layer's .numMask attribute for
legal range, 0 indicates uncolored.
Type: int
Default: 0
Edit: Yes

net

The net that the wire belongs to

Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (wire)
Default: ""
Edit: No

points

2 points (center-line) for the wire

Type: point*
Default: ""
Edit: No

rect

Rectangle that defines the wire shape, including any begin extension or end extension.
Type: rect
Default: ""
Edit: No

route_rule

The non-default rule corresponding to the wire, wires with the default routing rule will return
empty string.
Type: obj(route_rule)
Default: ""
Edit: No

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Stylus Common UI Database Object Information
Database Objects--resistor

status

Wiring status (equivalent to DEF NETS regular wiring status)

Type: enum
Enum Values: unknown routed fixed cover noshield
Default: ""
Edit: Yes

width

Width of wire
Type: coord
Default: ""
Edit: No

resistor

Parent Objects

Definition
After loading a Voltus IR-drop analysis result, you can select a resistor in the GUI. The pointer of the object is
the same as its name, like resistor

Attribute Description

capacitance

The capacitance for the two nodes before any effects of set_rail_what_if_capacitance in units
of farads.
Type: double*
Default: ""
Edit: No

current

The current of the resistor in units of A. For static rail_analysis it is the average value, for
dynamic power analysis it is the rms value.
Type: double
Default: ""
Edit: No

current_direction

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Stylus Common UI Database Object Information
Database Objects--resistor

The direction of current. no_value is returned for non-orthogonal resistors or if it is not

available.
Type: enum
Enum Values: no_value left right up down
Default: ""
Edit: No

em_jmax_dc_avg_ratio

The ratio of the current / em_jmax_dc_avg limit in the Quantus ICT file. This is computed
during static rail analysis. The jmax name is used for legacy reasons, but the value is a current
value ratio, not a current density ratio.
Type: double
Default: ""
Edit: No

em_jmax_dc_rms_ratio

The ratio of the current / em_jmax_dc_rms limit in the Quantus ICT file. This is computed
during dynamic rail analysis. The jmax name is used for legacy reasons, but the value is a
current value ratio, not a current density ratio.
Type: double
Default: ""
Edit: No

failure_in_time

The failure in time value of the resistor in units of 1e9 hours (e.g. 1.0 means one failure in 1e9
hours of operation).
Type: double
Default: ""
Edit: No

layer

The layer of the resistor. A via resistor will have a via-layer, and a routing layer resistor will
have a routing layer.
Type: string
Default: ""
Edit: No

length

The length of the resistor in unit of um.

Type: coord
Default: ""
Edit: No

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Stylus Common UI Database Object Information
Database Objects--resistor

location

The x, y location of the two nodes at each end of the resistor.

Type: point*
Default: ""
Edit: No

name

This is an R followed by an integer to identify the resistor.

Type: string
Default: ""
Edit: No

net

The net of the resistor.

Type: obj(net)
Default: ""
Edit: No

node_names

This is an N followed by an integer to identify the two nodes at each end of the resistor.
Type: string
Default: ""
Edit: No

node_reff

The values are in units of ohms and are valid whenever the node reff db is available in the
loaded state directory.
Type: double*
Default: ""
Edit: No

node_voltage_drop

The IR voltage drop of the two nodes in units of mV.

Type: double*
Default: ""
Edit: No

node_voltages

The IR voltage drop of the two nodes in units of mV.

Type: double*
Default: ""
Edit: No

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Database Objects--resistor

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (resistor)
Default: ""
Edit: No

resistance

The resistance before any effects from set_rail_what_if_resistance in units of ohms.

Type: double
Default: ""
Edit: No

switch_net

The switched net of the resistor.

Type: obj(net)
Default: ""
Edit: No

what_if_capacitance

The capacitance after any effects of set_rail_what_if_capacitance. This is the capacitance

actually used in the rail analysis in units of farads.
Type: double*
Default: ""
Edit: No

what_if_resistance

The resistance after any effects of set_rail_what_if_resistance. This is the resistance actually
used in the rail analysis in units of ohms.
Type: double
Default: ""
Edit: No

width

The width of the resistor in unit of um.

Type: coord
Default: ""
Edit: No

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Stylus Common UI Database Object Information
Database Objects--message

message

Parent Objects
root

Definition
Formatted error, warning and info messages (e.g. ERROR

Attribute Description

count

The number of times message has been issued in current session.

Type: int
Default: ""
Edit: No

long_help

Some messages have additional help information. It is also available with 'man ABCDEF-123'
in the DESCRIPTION section.
This is also the "DESCRIPTION" part of get_message -long. If the "DESCRIPTION" of a
message is "There are no further details for this message", get_db doesn't need to return it, but
return an empty string instead.
Type: string
Default: ""
Edit: No

max_print

Specifies the maximum number of times the message will be printed to the log file and screen.
-1 is unlimited. 0 is suppressed.
Type: int
Default: 20
Edit: Yes

message

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Database Objects--message

A brief explanation of the message. It is also available with 'help ABCDEF-123'. It uses printf
syntax with %s, %d, etc. for message specific arguments.
This is the get_message -short string.
Type: string
Default: ""
Edit: No

name

The message name (e.g. ABCDEF-123 for the message "ERROR: (ABCDEF-123):...").
The DPO name would be "message:ABCDEF-123".
Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (message)
Default: ""
Edit: No

on_error

The error action for the specified message. This only applies if the message has severity =
error, and is ignored for messages with severity of warning or info. Valid values are:
msg_only: Write out message, with normal command behavior.
exit: Fatal error. Exit and return to Linux.
stop_script: If message occurs inside 'source <file>', then the source command stops and
returns.
Type: enum
Enum Values: exit stop_script msg_only
Default: msg_only
Edit: Yes

severity

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Stylus Common UI Database Object Information
Database Objects--what_if_wire

The severity of the message. The severity is "default" until some application writes it out and
sets the severity, or the user sets it. Setting it to "default" will undo any previous setting, and
then applications will set it if again the next time they write it out. Valid values are:
default: A default severity is set to all messages until it is issued at least once.
info: An information message. No user action needed.
warning: A possible problem, but the command can continue.
error: A problem causing wrong behavior. In some cases, the command cannot continue and
stops, and sometimes it can continue to enable debugging or prototyping with errors.
Type: enum
Enum Values: default error warning info
Default: default
Edit: Yes

what_if_wire

Parent Objects
net

Definition
After loading a Voltus IR-drop analysis result, you can use add_what_if_shapes to add 'what if' power wires to
see how they would improve the IR-drop results without modifying the real power-mesh.

Attribute Description

layer

The layer for the wire.

Type: obj(layer)
Default: ""
Edit: No

net

The net of the wire.

Type: obj(net)
Default: ""
Edit: No

obj_type

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Database Objects--what_if_via

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (what_if_wire)
Default: ""
Edit: No

rect

The rect for the wire.

Type: rect
Default: ""
Edit: No

width

The width of the wire.

Type: coord
Default: ""
Edit: No

what_if_via

Parent Objects
net

Definition
After loading a Voltus IR-drop analysis result, you can use add_what_if_shapes to add 'what if' power vias to
see how they would improve the IR-drop results without modifying the real power-mesh.

Attribute Description

bottom_layer

The bottom routing layer for this what_if_via.

Type: obj(layer)
Default: ""
Edit: No

cut_layer

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Stylus Common UI Database Object Information
Database Objects--inst_obs

The cut_layer for this what_if_via.

Type: obj(layer)
Default: ""
Edit: No

cut_rect

The rect on the cut_layer for this what_if_via.

Type: rect
Default: ""
Edit: No

net

The net for this what_if_via.

Type: obj(net)
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (what_if_via)
Default: ""
Edit: No

top_layer

The top routing layer for this what_if_via.

Type: obj(layer)
Default: ""
Edit: No

inst_obs

Parent Objects

Definition
obstruction shape on an instance

Attribute Description

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Stylus Common UI Database Object Information
Database Objects--trim_grid

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (inst_obs)
Default: ""
Edit: No

trim_grid

Parent Objects
design, root

Definition
Trim grid pattern. Equivalent to LEF TRIMMETALTRACK statement that defines the grids that trim shapes
must align to. See the LEF manual for more descriptions, figures and examples of how these attributes are
defined.

Attribute Description

group

Specifies the group names of the trim_grid from the LEF TRIMMETALSTACK GROUP value.
Type: string
Default: {}
Edit: No

layer

The trim layer of this trim_grid from the LEF TRIMMETALSTACK trimLayer value
Type: obj(layer)
Default: {}
Edit: No

mask

Specifies the mask number for the trim_grid, from the LEF TRIMMETALSTACK MASK value.
Type: int
Default: {}
Edit: No

obj_type

July 2021 857 Product Version 21.11

Stylus Common UI Database Object Information
Database Objects--trim_grid

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (trim_grid)
Default: ""
Edit: No

offset

Specifies the offset from the lower left point of the core box to the first trim_grid from the LEF
TRIMMETALSTACK COREOFFSET value.
Type: coord
Default: {}
Edit: No

on_track

True if the LEF TRIMMETALSTACK ONTRACK keyword is given for this trim_grid.
Type: bool
Default: false
Edit: No

pitch

Specifies the spacing between each trim_grid from the LEF TRIMMETALSTACK PITCH
value.
Type: coord
Default: {}
Edit: No

track_count

The number of times to repeat the pitch for this track_index from the LEF TRIMMETALSTACK
METALTRACKPITCH value. See the LEF manual for figures and examples of how this is
used.
Type: int
Default: 0
Edit: No

track_index

Specifies the index value of the trim_grid from the LEF TRIMMETALSTACK
METALTRACKOFFSET value. The offset and pitch values apply to this track_index for
track_count times. See the LEF manual for figures and examples of how this is used to overlay
different track_index settings on one layer on top of each other to create non-uniform grid
patterns.
Type: int
Default: 0
Edit: No

July 2021 858 Product Version 21.11

Stylus Common UI Database Object Information
Database Objects--gcell

gcell

Parent Objects
design, root

Definition
A global-routing cell. It only exists after global routing has been run, and includes the number of routing tracks
available (supply), and the tracks used (demand) for each gcell.

Attribute Description

demand

Number of routing tracks used in the preferred routing direction for the layer. If no layer index is
given, the value is not useful, so -1 is returned.
Type: int
Allowed -index values: layer
Default: 0
Edit: No

horizontal_demand

Number of routing tracks used in horizontal direction for all routing layers.
Type: int
Default: 0
Edit: No

horizontal_remaining

Number of routing tracks remaining in horizontal direction for all routing layers.
Type: int
Default: 0
Edit: No

horizontal_supply

Number of routing tracks available in horizontal direction for all routing layers.
Type: int
Default: 0
Edit: No

index

July 2021 859 Product Version 21.11

Stylus Common UI Database Object Information
Database Objects--gcell

The X and Y index values into the gcell array. The bottom, left gcell has index = {0 0}
Type: int*
Default: ""
Edit: No

name

Object name derived from index value

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (gcell)
Default: ""
Edit: No

rect

Physical dimensions {{llx lly} {urx ury}}

Type: rect
Default: ""
Edit: No

remaining

Number of routing tracks remaining in the preferred routing direction for the layer. A negative
value indicates overflow. If no layer index is given, the value is not useful, so -1 is returned.
Type: int
Allowed -index values: layer
Default: 0
Edit: No

supply

Number of routing tracks available in the preferred routing direction for the layer. If no layer
index is given, the value is not useful, so -1 is returned.
Type: int
Allowed -index values: layer
Default: 0
Edit: No

vertical_demand

July 2021 860 Product Version 21.11

Stylus Common UI Database Object Information
Database Objects--inst_obs_shape

Number of routing tracks used in vertical direction for all routing layers.
Type: int
Default: 0
Edit: No

vertical_remaining

Number of routing tracks remaining in vertical direction for all routing layers.
Type: int
Default: 0
Edit: No

vertical_supply

Number of routing tracks available in vertical direction for all routing layers.
Type: int
Default: 0
Edit: No

inst_obs_shape

Parent Objects

Definition
This corresponds to one of the .base_cell.obs_layer_shapes.shapes (LEF OBS shapes) for a given inst. It
carries a link to the 'inst' object, that a 'shape' object does not have. This allows GUI operations that need both
the shape and the inst object together to select, highlight or query the shape. It can only be accessed by
selecting the object with the GUI.

Attribute Description

inst

The inst of this OBS shape

Type: obj(inst)
Default: ""
Edit: No

is_ignore_pg_net

July 2021 861 Product Version 21.11

Stylus Common UI Database Object Information
Database Objects--inst_obs_shape

layer

The layer of the obstruction

Type: obj(layer)
Default: ""
Edit: No

mask

Indicates mask number for multiple mask layer usage. Refer to layer's .num_mask attribute for
legal range, 0 indicates uncolored.
Type: int
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (inst_obs_shape)
Default: ""
Edit: No

polygon

Points of the polygon (if type = polygon) in design coordinates (e.g. base_cell values are
transformed for this inst).
Type: point*
Default: ""
Edit: No

rect

Box of the shape (if type = rect) in design coordinates (e.g. base_cell values are transformed
for this inst).
Type: rect
Default: ""
Edit: No

spacing

July 2021 862 Product Version 21.11

Stylus Common UI Database Object Information
Database Objects--bus_sink_group

LEF OBS SPACING value, no_value if not specified in LEF.

Type: coord
Default: ""
Edit: No

type

Type of shape (rect, polygon)

Type: enum
Enum Values: rect polygon
Default: ""
Edit: No

bus_sink_group

Parent Objects
design, root

Definition
A group of sinks (loads) that some floorplan and routing commands use to control adding buffers and routing
for a bus. See 'help *bus_sink*' for a list of commands related to this object.

Attribute Description

name

The name of the bus_sink_group.

Type: string
Default: {}
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (bus_sink_group)
Default: ""
Edit: No

sinks

July 2021 863 Product Version 21.11

Stylus Common UI Database Object Information
Database Objects--bump_pin

A list of sinks (pins of insts, or ports of the design) for this bus.
Type: obj(pin)* obj(port)*
Default: {}
Edit: No

bump_pin

Parent Objects
bump

Definition
PIN in bump LEF

Attribute Description

base_name

The bump_pin name without bump path.

Type: string
Default: ""
Edit: No

base_pin

The equivalent base_pin.

Type: obj(base_pin)
Default: ""
Edit: No

bump

The bump that the bump_pin belongs to.

Type: obj(bump)
Default: ""
Edit: No

direction

July 2021 864 Product Version 21.11

Stylus Common UI Database Object Information
Database Objects--bump_pin

bump_pin's direction from the corresponding base_pin.

Type: enum
Enum Values: in out inout
Default: ""
Edit: No

escaped_name

The bump_pin name including bump path.

Type: string
Default: ""
Edit: No

layer

The layer of the bump_pin. For bump_pin with more than one shape, it is the layer of the first
shape (which is the same shape used for the .location value).
Type: obj(layer)
Default: ""
Edit: No

location

The location of the bump_pin. For bump_pin with more than one shape, it is the location of the
first shape (which is the same shape used for the .layer value).
Type: point
Default: ""
Edit: No

name

The bump_pin name including bump path.

Type: string
Default: ""
Edit: No

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (bump_pin)
Default: ""
Edit: No

port

The port that the bump_pin connects to.

Type: obj(port)
Default: ""
Edit: No

July 2021 865 Product Version 21.11

Stylus Common UI Database Object Information
Database Objects--lef_set

lef_set

Parent Objects

Definition
A lef set is a group of lef files used by design(s).

Attribute Description

obj_type

The obj_type name for this object. To see all obj_type names, go to Contents
Type: enum (lef_set)
Default: ""
Edit: No

July 2021 866 Product Version 21.11

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