initialize_floorplan -site_def unit -flip_first_row true -core_utilization 0.

7 -use_site_row -core_offset
{10}

Removing existing floorplan objects

Creating core...

Core utilization ratio = 70.07%

Unplacing all cells...

Creating site rows...

Creating routing tracks...

Initializing floorplan completed.

check_boundary_cells

****************************************

Report : check_boundary_cells

Design : PRE_FLOORPLAN_DONE

Version: S-2021.06-SP2

Date : Mon Nov 20 17:30:42 2023

****************************************

Collecting design data...

Continuity report

============================================================

Information: No continuity violation. (CHF-024)

Continuity violations in design PRE_FLOORPLAN_DONE: 0

Redundant extra boundary cells report

============================================================

Information: No redundant extra boundary cells violation. (CHF-024)

Redundant extra boundary cell in design PRE_FLOORPLAN_DONE: 0

Corner and boundary cell report

============================================================

Information: No corner and boundary cell violation. (CHF-024)

 Corner and boundary cell violations in design PRE_FLOORPLAN_DONE: 0

Orientation report

============================================================

Information: No orientation violation. (CHF-024)

Orientation violations in design PRE_FLOORPLAN_DONE: 0

Reading Verilog into new design 'ChipTop' in library 'chiptop'. (VR-012)

Number of modules read: 78

Top level ports: 105

Total ports in all modules: 4738

Total nets in all modules: 12552

Total instances in all modules: 6783

Elapsed = 00:00:00.19, CPU = 00:00:00.19

report_design

****************************************

Report : design

Design : ChipTop

Version: S-2021.06-SP2

Date : Sun Nov 26 16:21:53 2023

****************************************

Total number of std cells in library : 4048

Total number of dont_use lib cells : 4000

Total number of dont_touch lib cells : 0

Total number of buffers : 364

Total number of inverters : 204

Total number of flip-flops : 688

Total number of latches : 180

Total number of ICGs :0

Cell Instance Type Count Area

--------------------------------------

TOTAL LEAF CELLS 6707 29697.622

Standard cells 6703 3025.505

Hard macro cells 4 26672.117

Soft macro cells 0 0.000

Always on cells 0 0.000

Physical only 0 0.000

Fixed cells 0 0.000

Moveable cells 6707 29697.622

Sequential 0 0.000

Buffer/inverter 0 0.000

ICG cells 0 0.000

Logic Hierarchies : 76

Design Masters count : 107

Total Flat nets count : 7909

Total FloatingNets count : 1116

Total no of Ports : 105

Number of Master Clocks in design : 0

Number of Generated Clocks in design : 0

Number of Path Groups in design : 6 (0 of them Non Default)

Number of Scan Chains in design :0

List of Modes : default

List of Corners : default

List of Scenarios : default

Core Area : 0.000

Chip Area : 0.000

Total Site Row Area : 0.000

Number of Blockages :0

Total area of Blockages : 0.000

Number of Power Domains :1

Number of Voltage Areas :1

Number of Group Bounds :0

Number of Exclusive MoveBounds :0

Number of Hard or Soft MoveBounds : 0

Number of Multibit Registers :0

Number of Multibit LS/ISO Cells :0

Number of Top Level RP Groups :0

Number of Tech Layers : 63 (63 of them have unknown routing dir.)

Total wire length : 0.00 micron

Total number of wires :0

Total number of contacts :0

report_ports

****************************************

Report : port

Module : ChipTop

Mode : default

Corner : default

Scenario: default

Version: S-2021.06-SP2

Date : Sun Nov 26 16:24:05 2023

****************************************

Attributes:

I - ideal network

H - HyperScale context override

Pin Cap Wire Cap

Min Max Min Max

Port Dir rise/fall rise/fall rise/fall rise/fall Attributes

--------------------------------------------------------------------------------

MemOverflow

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[0]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[10]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[11]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[12]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[13]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[14]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[15]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[16]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[17]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[18]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[19]
 in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[1]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[20]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[21]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[22]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[23]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[24]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[25]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[26]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[27]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[28]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[29]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[2]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[30]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[31]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[3]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[4]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[5]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[6]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[7]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[8]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemReadBus[9]

in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[0]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[10]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[11]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[12]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[13]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[14]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[15]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[16]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[17]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[18]
 out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[19]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[1]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[20]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[21]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[22]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[23]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[24]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[25]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[26]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[27]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[28]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[29]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[2]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[30]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[31]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[32]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[33]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[34]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[35]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[36]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[37]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[38]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[39]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[3]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[40]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[41]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[42]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[43]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[44]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[45]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[46]
 out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[47]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[48]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[49]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[4]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[50]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[51]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[52]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[53]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[54]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[55]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[56]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[57]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[58]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[59]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[5]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[60]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[61]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[62]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[63]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[6]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[7]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[8]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteBus[9]

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

MemWriteValid

out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

VDD in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

VDD_1 inout 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

VSS in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

VSS_1 inout 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

clock in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

power_ack out 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

reset in 0.00/0.00 0.00/0.00 0.00/0.00 0.00/0.00

icc2_shell> sizeof_collection [all_inputs ]

38

icc2_shell> sizeof_collection [all_outputs ]

69

icc2_shell> sizeof_collection [get_po

get_port_antenna_property get_power_budget get_power_domains get_power_strategies

get_port_buses get_power_clock_scaling get_power_group

get_power_switch_patterns

get_ports get_power_derate get_power_group_objects

icc2_shell> sizeof_collection [get_ports]

105

icc2_shell> sizeof_collection [all_inputs ]

38

icc2_shell> sizeof_collection [all_outputs ]

69

check_pg_connectivity

Loading cell instances...

Number of Standard Cells: 10799

Number of Macro Cells: 4

Number of IO Pad Cells: 0

Number of Blocks: 0

Loading P/G wires and vias...

Number of VSS Wires: 740

Number of VSS Vias: 16

Number of VSS Terminals: 1

**************Verify net VSS connectivity*****************

Number of floating wires: 739

Number of floating vias: 16

Number of floating std cells: 10771

Number of floating hard macros: 4

Number of floating I/O pads: 0

Number of floating terminals: 1

Number of floating hierarchical blocks: 0

************************************************************

Loading cell instances...

Loading P/G wires and vias...

Number of VDD Wires: 744

Number of VDD Vias: 16

Number of VDD Terminals: 1

**************Verify net VDD connectivity*****************

Number of floating wires: 743

Number of floating vias: 16

Number of floating std cells: 10771

Number of floating hard macros: 4

Number of floating I/O pads: 0

Number of floating terminals: 1

Number of floating hierarchical blocks: 0

************************************************************
Overall runtime: 0 seconds.

{PATH_19_680 PATH_19_681 PATH_19_682 PATH_19_683 PATH_19_684 PATH_19_685 PATH_19_686

PATH_19_687 PATH_19_688 PATH_19_689 PATH_19_690 PATH_19_691 PATH_19_692 PATH_19_693
PATH_19_694 PATH_19_695 PATH_19_696 PATH_19_697 PATH_19_698 PATH_19_699 PATH_19_700
PATH_19_701 PATH_19_702 PATH_19_703 PATH_19_704 PATH_19_705 PATH_19_706 PATH_19_707
PATH_19_708 PATH_19_709 PATH_19_710 PATH_19_711 PATH_19_712 PATH_19_713 PATH_19_714
PATH_19_715 PATH_19_716 PATH_19_717 PATH_19_718 PATH_19_719 PATH_19_720 PATH_19_722
PATH_19_723 PATH_19_724 PATH_19_725 PATH_19_726 PATH_19_727 PATH_19_728 PATH_19_729
PATH_19_730 PATH_19_731 PATH_19_732 PATH_19_733 PATH_19_734 PATH_19_735 PATH_19_736
PATH_19_737 PATH_19_738 PATH_19_739 PATH_19_740 PATH_19_741 PATH_19_742 PATH_19_743
PATH_19_744 PATH_19_745 PATH_19_746 PATH_19_747 PATH_19_748 PATH_19_749 PATH_19_750
PATH_19_751 PATH_19_753 PATH_19_754 PATH_19_755 PATH_19_756 PATH_19_757 PATH_19_758
PATH_19_759 PATH_19_760 PATH_19_761 PATH_19_762 PATH_19_763 PATH_19_764 PATH_19_765
PATH_19_766 PATH_19_767 PATH_19_768 PATH_19_769 PATH_19_770 PATH_19_771 PATH_19_772
PATH_19_773 PATH_19_774 PATH_19_775 PATH_19_776 PATH_19_777 PATH_19_778 PATH_19_779
PATH_19_780 PATH_19_781 ...}

icc2_shell>check_pg_drc

Command check_pg_drc started at Mon Nov 20 17:43:05 2023

Command check_pg_drc finished at Mon Nov 20 17:43:05 2023

CPU usage for check_pg_drc: 0.35 seconds ( 0.00 hours)

Elapsed time for check_pg_drc: 0.35 seconds ( 0.00 hours)

Total number of errors found: 4

4 insufficient spacings on M5

------------

Description of the errors can be seen in gui error set "DRC_report_by_check_pg_drc"

check_design -checks pre_placement_stage

****************************************

Report : check_design

Options: { pre_placement_stage }

Design : ChipTop

Version: S-2021.06-SP2

Date : Mon Nov 20 17:59:11 2023

****************************************

Running mega-check 'pre_placement_stage':

Running atomic-check 'design_mismatch'

 Running atomic-check 'scan_chain'

Running atomic-check 'mv_design'

Running atomic-check 'rp_constraints'

Running atomic-check 'timing'

Running atomic-check 'hier_pre_placement'

*** EMS Message summary ***

----------------------------------------------------------------------------------------------------

Rule Type Count Message

----------------------------------------------------------------------------------------------------

DFT-011 Info 1 The design has no scan chain defined in the scandef.

MV-050 Error 24362 %type related supply net(s) of signal pin '%signalPin' cannot be...

TCK-001 Warn 67 The reported endpoint '%endpoint' is unconstrained. Reason: '%re...

----------------------------------------------------------------------------------------------------

Total 24430 EMS messages : 24362 errors, 67 warnings, 1 info.

----------------------------------------------------------------------------------------------------

*** Non-EMS message summary ***

----------------------------------------------------------------------------------------------------

Rule Type Count Message

----------------------------------------------------------------------------------------------------

NDMUI-173 1 There are no relative placement groups in the design.

PVT-032 2 Corner %s: no PVT mismatches.

----------------------------------------------------------------------------------------------------

Total 3 non-EMS messages : 0 errors, 0 warnings, 3 info.

----------------------------------------------------------------------------------------------------

Information: EMS database is saved to file 'check_design.ems'.

Information: Non-EMS messages are saved into file 'check_design2023Nov20175911.log'.

1
group_path -from [all_registers] -to [all_registers] -name reg2reg

Warning: Path group 'reg2reg' has no paths; it will not affect optimization. (CSTR-010)

icc2_shell>group_path -from [all_inputs] -to [all_registers] -name in2reg

icc2_shell>group_path -from [all_registers] -to [all_outputs] -name reg2out

icc2_shell>group_path -from [all_inputs] -to [all_outputs] -name in2out