IEEE PEDS 2011, Singapore, 5 - 8 December 2011

A Space Vector Based Pulse Width Modulation

Scheme for a 5-Level Induction Motor Drive
Shiny G., M.R.Baiju
Power Electronics Research Laboratory
Dept. of Electronics & Communication Engineering
College of Engineering Trivandrum, Kerala, India
mrbaiju@cet.ac.in

Abstract- A Space Vector based Pulse Width Modulation proposed in [10] uses an approach based on fractal concept to
(SVPWM) scheme for a 5-level inverter is presented. Sector find the sector of operation. Identification of sector by fractal
identification is carried out using an approach based on fractal approach involves progressively dividing the basic sector to
concept. To represent the space vectors, 60° coordinate system is locate the instantaneous reference space vector. The fractal
used. The use of 60° coordinate system avoids fractal arithmetic
compared to Cartesian coordinate system, and increases speed of based scheme discussed in [10] uses the Cartesian coordinate
computation. No look up tables are used to generate sectors and system to represent the space vectors. Representation of space
switching vectors. The scheme also works in over modulation vectors in Cartesian coordinate system build up large number
region. Experimental results for a 5-level inverter using induction of fractional values and this will increase the computational
motor in open-end winding configuration are presented to validate complexity of the scheme. In this paper a low computation
the scheme.
PWM scheme based on fractal concept is presented. Instead
I. INTRODUCTION of the Cartesian coordinate system, 60° coordinate frame
work is used to represent the space vectors [11-13]. In 60°
Multilevel inverters found wide application in the field of coordinate system the switching vectors will have integer
industrial drives. Typical applications include pumps, fans, values and hence this scheme reduces the computation time
compressors, grinding mills, wind energy conversion and significantly [11]. The switching vectors needed to realize the
railway traction [1-3]. Advantages of multilevel inverters reference space vector are automatically generated, with out
such as reduced dv / dt stresses, low electromagnetic using look up tables.
compatibility problems, low switching losses and smaller
common mode voltage have been reported in literature [1-4].
II. POWER CIRCUIT OF FIVE - LEVEL INVERTER USING
Different multilevel inverter topologies like Neutral Point INDUCTION MOTOR IN OPEN-END WINDING CONFIGURATION
Clamped multilevel inverter, diode clamped multilevel
inverter, flying capacitor multilevel inverter and cascaded Fig. 1 shows the power circuit configuration of the 5-level
multilevel inverters with separate DC sources are proposed in inverter structure. The 5-level inverter is realized by feeding
[5]. Realization of a 3-level inverter structure by feeding an an open-end winding induction motor from both ends by a
open-end winding induction motor from both ends by two 3-level inverter at one side and a 2-level inverter at the other
2-level inverters with symmetric DC link voltage is proposed side. The 3-level inverter uses a cascaded connection of two
in [6]. If the 2-level inverters in open-end winding 2-level inverters (Inverter-1 and Inverter-2). Inverter-3 is a
configuration are fed with asymmetric DC link voltages, it 2-level inverter. The phase winding of the open-end induction
will result in a 4-level inverter configuration [7]. Higher motor is connected across the poles of Inverter-2 and
multilevel inverter structures can also be realized if an open- Inverter-3. The inverters are fed with asymmetric DC link
end winding induction motor is fed with a 3-level inverter at voltages. Inverter-1 and Inverter-3 are fed with DC link
one end and a 2-level inverter at the other end [8]. The 3-level voltages of VDC 4 . The DC link voltage of Inverter-2 is
inverter structure in the above topology is realized by VDC 2 , where VDC is the DC link voltage of a conventional
cascaded connection of two 2-level inverters. The modulation 2-level inverter. The pole voltage of a given phase of
and control strategies used for multilevel inverters like carrier Inverter-2 can assume three possible values : 0, VDC 2 and
based PWM, space vector PWM and selective harmonic 3VDC 4 , which is the characteristics of a 3-level inverter.
elimination PWM are also discussed [3]. This paper proposes The pole voltage of Inverter-3 assumes two values viz. 0 and
a Space Vector based Pulse Width Modulation (SVPWM) VDC 4 , depending on whether the top switch or the bottom
scheme for a 5-level inverter. Sector identification is one of switch of a given phase leg is turned ON. When these
the steps in the implementation of SVPWM, even though inverters drive the induction motor from both ends, each
schemes with out sector identification are also been proposed phase of the induction motor can achieve five different
[9]. In SVPWM, as the number of levels of the inverter voltage levels. The voltage levels realized for the proposed
increases, identification of the sector to locate the 5-level inverter are −VDC 4 , 0 , VDC 4 , VDC 2 and
instantaneous reference space vector will become a tedious 3VDC 4 . These five voltage levels can be represented by
process. The space vector pulse width modulation scheme vectors 0,1,2,3 and 4 respectively.

978-1-4577-0001-9/11/$26.00 ©2011 IEEE 292

Fig. 1. 5-Level Inverter structure realized by feeding an open-end winding
induction motor from both ends by a 3-Level inverter
and a 2-Level inverter. Fig. 2. Space Vector Representation of a 5-Level Inverter. The redundant
switching vector combinations not shown.
Table-I shows pole voltage of the individual inverters and
the corresponding motor phase voltage. Since isolated power
supplies are used to feed the individual inverters, the
harmonic components of triplen order will be dropped across
the points O and O’ (Fig. 1). Therefore triplen harmonics will
be absent in the motor phase voltage.
Fig. 2 shows the space vector representation of a 5-level
inverter. The space vector diagram of multilevel inverters can
be viewed as a hexagonal structure with one inner hexagon
and several outer sub hexagons as shown in Fig. 2. Each
hexagon is identified with a center referred as Sub Hexagon
Center (SHC). The sub hexagon center of the inner hexagon
is named as ' O ' . The centers of the outer sub hexagons are
designated as A1 − A6 , B1 − B12 and C1 − C18 . Each
hexagon is also divided into small triangular region called
sectors. There are 96 such sectors in the space vector diagram
of a 5-level inverter. Fig. 3 shows the space vector Fig. 3. Space Vector Representation of a 5-level Inverter in
representation of the 5-level inverter in 60° coordinate 60° Coordinate System
system. Computational efficiency can be increased by
III. MODULATION SCHEME FOR THE FIVE-LEVEL INVERTER
representing the space vectors in 60° coordinate framework
[11] . The proposed Space Vector based pulse width modulation
TABLE I scheme involves the following steps to realize the reference
POLE VOLTAGE OF INDIVIDUAL INVERTERS AND CORRESPONDING MOTOR space vector OX shown in Fig. 2.
PHASE VOLTAGE IN A-PHASE WINDING a. Determine the small sector which encloses the tip
of the reference space vector OX and to find the
Pole voltage of Pole voltage of
Motor Phase Voltage
Realized sub hexagon center which is nearest to the tip of
in
3-Level Inverter 2-Level Inverter switching the reference space phasor.
A-phase winding
(VA2O) (VA3O’) level b. Mapping to determine the duration of switching
VA2A3= VA2O -VA3O’
vectors. This is done by shifting the sub hexagon
0 VDC / 4 −VDC / 4 0
enclosing the tip of reference space vector to
0 0 0 1
coincide with the inner sub hexagon with
VDC / 2 VDC / 4 VDC / 4 2 center ' O ' . The reference space vector OX gets
VDC / 2 0 VDC / 2 3 mapped to OX' as shown in Fig. 2.
c. Generation of actual switching vectors which
3VDC / 4 VDC / 4 VDC / 2 3
forms the vertices of the sector enclosing the tip of
3VDC / 4 0 3VDC / 4 4
reference space phasor.

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A. Identification of Sector and Sub Hexagon Center
In the proposed work an approach based on fractals is used Let the instantaneous amplitudes of the three phase
to find the sector which encloses the tip of the reference reference sinusoid are denoted as Va , Vb and Vc . The
vector. Since the space vector representation of multilevel
inverters has an inherent fractal structure, the sectors of corresponding ' m' and ' n' coordinates of reference space
higher level inverter can be generated by a technique called vector OX are calculated as
triangularization [10]. Fig. 4 shows the space vector Vm = Va − Vb (1)
representation of a 5-level inverter ( only the vectors in the
periphery are shown) and a reference space vector
Vn = Vb − Vc (2)
OX situated in basic sector 3. Here the term basic sector is The (m, n) coordinates of the sub hexagon center are
used to represent the sector which is equivalent to the sector represented as (Vms , Vns ) . For sub hexagon center C7 , the
of a conventional 2-level inverter. The 60° coordinates
corresponding to basic sector 3 are (0,0), (-4,4) and (-4,0). In values of (Vms , Vns ) are (-3,3). Then the coordinates of the
triangularization, each basic sector is divided into similar mapped reference vector OX' are found out by using the
small triangular regions. This is achieved by finding the following equations.
midpoints of the lines joining the vertices of the basic sector. Vm _ map = Vm − Vms (3)
Applying triangularization to basic sector 3 generates four
similar sectors as shown in Fig. 5. The new switching vectors Vn _ map = V n − V ns (4)
formed by the process of triangularization are (-2,2), (-2,0)
and (-4,2). Further triangularization will generate sixteen The new phase values of the mapped reference vector
small sectors as shown in Fig. 6. The centroid of each sector OX' are denoted as Vas , Vbs and Vcs and are also found out.
is also calculated as the average value of the vertices
enclosing the sector. The sector with its centroid closest to the Vas = ( 2Vm _ map +Vn _ map ) 3 (5)
tip of the reference space vector is taken as the sector of
Vbs = (Vn _ map −Vm _ map ) 3 (6)
operation. As shown in Fig. 6, the sector of operation
identified for reference space vector OX is sector with Vcs = ( −Vm _ map −2Vn _ map ) 3 (7)
number 14.
Once the sector of operation is found out by applying
triangularization, the sub hexagon which is closest to the tip The phase voltage timings Tga , Tgb and Tgc for the three
of the reference space vector is also identified. For the phases are calculated as given in [15].
reference space phasor OX , the sub hexagon center
identified is C7 , with coordinate (-3,3). C. Actual Switching Vector Generation
B. Mapping to 2-level and determination of duration of switching
vectors To find out the actual switching vectors for realizing the
The time duration of the switching vectors is determined by reference space vector, the (m, n) coordinates corresponding
mapping the reference space vector to 2-level [14]. In to the sub hexagon center (Vms , Vns ) are converted to
mapping, the identified sub hexagon is shifted to coincide
with the center of the inner sub hexagon ' O ' . The mapped switching vectors S a , Sb and Sc as given in Table-II
reference space vector is shown in Fig. 2 as OX' .

Fig. 4. Space Vector Representation of a Fig. 5. First triangularization of the basic sector Fig. 6. Second triangularization generates sixteen sectors,
5-level Inverter with reference space vector generates four small sectors, numbered 1 to 16. The tip of the reference space vector is
OX situated in basic sector number 3. numbered 1 to 4. located in small sector with number 14.

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 TABLE II
IV. EXPERIMENTAL VERIFICATION
CONVERSION OF (m, n) COORDINATES OF SUB HEXAGON CENTER INTO The proposed SVPWM scheme is experimentally verified
CORRESPONDING SWITCHING VECTORS by implementing the scheme on a 2 HP, 3 - phase induction
Basic Switching Vectors motor drive in open loop with v / f control for different
Sector modulation indices. The gating pulses for the three inverters
(2-Level) Sa Sb Sc
are generated using the dSPACE DS 1104 RTI platform and
1 and 2 Vms + Vns Vns 0
FPGA Xilinx Virtex. The gating signals used to drive the
3 and 4 0 −Vms −Vms − Vns inverters in 3-level (modulation index, m = 0.4) , 4-level
(m = 0.53) , 5-level ( m = 0.85) and over modulation
5 and 6 Vms 0 −Vns operation (m = 1.1) are shown in Fig. 8, Fig. 9, Fig. 10 and
Fig. 11 respectively.
For the sub hexagon center C7 , the (m, n) coordinates are The experimental results of pole voltage, phase voltage and
(-3,3). Since the sub hexagon center is situated in basic sector motor current for all regions of operation including over
number 3, the switching vectors calculated are modulation are shown from Fig. 12 to Fig. 23.
Sa = 0
Sb = −Vms = 3
Sc = −Vms − Vns = 0
Thus the switching vector corresponding to the sub
hexagon center C7 is (030). This vector is then added with
the vectors corresponding to the mapped reference space
vector OX' to generate the actual switching vectors for
reference space phasor OX [16], as shown in Fig. 7. Fig. 8. Gating Signal for Inverters for 3 - level Operation.
Upper Three Traces for Inverter-1, Middle Three Traces for Inverter-2
Lower Three Traces for Inverter-3 (m = 0.4)
D. Generation of switching signals for over modulation region

The proposed scheme also works in over modulation

region. If the tip of the reference space vector OX lies outside
the hexagon, it will be considered as over modulation region
of operation. During over modulation, the vector representing
sub hexagon center is not switched. The two other active
vectors will switch for the entire sample period.
Fig. 9. Gating Signal for Inverters for 4 - level Operation.
Upper Three Traces for Inverter-1, Middle Three Traces for Inverter-2
Lower Three Traces for Inverter-3 (m = 0.53)

Fig. 10. Gating Signal for Inverters for 5 - level Operation.

Upper Three Traces for Inverter-1, Middle Three Traces for Inverter-2
Lower Three Traces for Inverter-3 (m = 0.85)

Fig. 7. Adding Sub hexagon center vector with Mapped 2- level

PWM signal generates actual switching vectors
Fig. 11. Gating Signal for Inverters for Over modulation Operation.
Upper Three Traces for Inverter-1, Middle Three Traces for Inverter-2
Lower Three Traces for Inverter-3 (m =1.1)

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Fig. 12. Experimental waveforms of Pole
Voltage for 3 - level operation (m=0.4) Fig. 13. Experimental waveform of Phase voltage Fig. 14. Experimental waveform of motor
Upper Trace Pole Voltage of Inverter-2 for 3 - level operation (m=0.4) current for 3 - level operation (m=0.4)
Middle Trace Pole Voltage of Inverter-3 Scale: X-axis: 20ms/div; Y-axis: 25V/div Scale: X-axis: 20ms/div; Y-axis: 2A/div
Lower Trace Effective Pole Voltage

Fig. 15. Experimental waveforms of Pole

Voltage for 4-level operation (m=0.53) Fig. 16. Experimental waveform of Phase voltage Fig. 17. Experimental waveform of motor
Upper Trace Pole Voltage of Inverter-2 for 4 - level operation (m=0.53) current for 4 - level operation (m=0.53)
Middle Trace Pole Voltage of Inverter-3 Scale: X-axis: 20ms/div; Y-axis: 50V/div Scale: X-axis: 20ms/div; Y-axis: 2A/div
Lower Trace Effective Pole Voltage

Fig. 18. Experimental waveforms of Pole

Voltage for 5-level operation (m=0.85) Fig. 19. Experimental waveform of Phase voltage Fig. 20. Experimental waveform of motor
Upper Trace Pole Voltage of Inverter-2 for 5 - level operation (m=0.85) current for 5 - level operation (m=0.85)
Middle Trace Pole Voltage of Inverter-3 Scale: X-axis: 10ms/div; Y-axis: 50V/div Scale: X-axis: 10ms/div; Y-axis: 2A/div
Lower Trace Effective Pole Voltage

Fig. 21. Experimental waveforms of Pole

Voltage for over modulation operation (m=1.1) Fig. 22. Experimental waveform of Phase voltage Fig. 23. Experimental waveform of motor
Upper Trace Pole Voltage of Inverter-2 for over modulation operation (m=1.1) current for over modulation operation (m=1.1)
Middle Trace Pole Voltage of Inverter-3 Scale: X-axis: 10ms/div; Y-axis: 50V/div Scale: X-axis: 10ms/div; Y-axis: 2A/div
Lower Trace Effective Pole Voltage

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