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Design and analysis of 8 bit fully segmented digital to analog converter

Conference Paper · December 2015

DOI: 10.1109/RAECS.2015.7453307

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 Proceedings of 2015 RAECS UIET Panjab University Chandigarh 21-22nd December 2015

Design and Analysis of 8 Bit Fully Segmented Digital

to Analog Converter
Arpit Kumar Baranwal Anurag Balwinder Singh
ACSD, Centre for Development of ACSD, Centre for Development of ACSD, Centre for Development of
Advanced Computing Advanced Computing Advanced Computing
Mohali, Punjab 160071 Mohali, Punjab 160071 Mohali, Punjab 160071
baranwal.arpit@gmail.com anurag@cdac.in balwinder@cdac.in

Abstract— This paper presents design of an 8-bit 1.8V fully thermometer row and column decoder, D latch and Current cell
segmented digital to analog converter (DAC) using 180nm CMOS array. Current cell array consist of similar current cell which is
technology. DAC is an essential part of digital signal processor. combination of current Source and current switches. The
Digital to analog converter is employed in processing of digital schematic has been designed using cadence virtuoso tool at
signals and providing analog output in the form of current or 180nm technology. Simulation of all the schematic has been
voltage for corresponding binary input. The differential non achieved using Spectre simulator.
linearity of a DAC shows variation in output corresponding to
1LSB change at input that is accuracy of data conversion. To II. DESIGN OF FULLY SEGMENTED DAC
achieve low non linearity or more accurate data conversion a
DAC is designed with unary coding or a fully segmented digital An 8-bit fully segmented current steering DAC has been
to analog converter with current steering technique. The INL and designed at 180nm technology and the block diagram is shown
DNL achieved in this research work are 0.145LSB and 0.013LSB in Fig 1. As shown in figure overall design is implemented
respectively. The power consumption is simulated as 99.67mW. with thermometer decoder for better linearity.
A. Block Diagram
Keywords— fully Segmented; current steering dac;

I. INTRODUCTION
Digital-to-Analog converter (DAC) is a device which takes MSB
digital (usually binary) data as input and provides analog 4-bit Column
signals as output. Analog signal is always continuous in time binary Decoder
domain while discrete signal is discontinuous in time domain. Input
In digital processing system DAC is used as a bridge between
analog and digital part. In modern communication system and
in wireless telecommunication high speed segmented current
steering DAC is widely used. The other application of DAC is
in medical instrument for converting pulses from discrete
sample to continuous analog wave form. There are several
different types of DAC on the basis of their speed and accuracy LSB Current
but in this article fully segmented current steering DAC is 4-bit Row Cell Output
binary Decoder Array Voltage
described. Current steering architecture have array of similar
current source. Segmentation is combination of unary coding Input
and binary weighted current steering DAC. Percentage of
segmentation depends on number of bits used in unary coding
in DAC [1]. In many research paper segmentation has done
Fig. 1: Block Diagram of Fully Segmented DAC
with the combination of binary weighted and unary coding,
only changing the percentage of segmentation according to The basic block diagram of fully segmented digital to
need of speed, power and bandwidth. Segmentation with analog converter is shown in Fig. 1. It includes binary data
combination of unary and binary weighted coding has inputs, row and column thermometer decoder and array of
advantage of both. Binary weighted DAC provide higher non current cells. In fully segmented the first four digital binary
linearity with low power consumption, lower area and higher input used for column decoder and the next four lower or LSB
speed of conversion, while thermometer coded DAC provide bit are applied to row decoder. The advantage of using row and
less non linearity with higher power consumption, more area column decoder is reducing area of DAC by arranging current
occupation and increased delay. The performance of DAC cell array in matrix structure. The each decoder has 16 outputs
depends on accuracy in data conversion. In this research paper corresponding to 4 binary inputs. Total 255 current cells are
DAC is designed only with thermometer coding to achieve needed in design of 8-bit unary segmented current steering
good linearity. The basic component of designed DAC is DAC. Proper matching of current sources in current cell array

978-1-4673-8253-3/15/$31.00 ©2015 IEEE

 Proceedings of 2015 RAECS UIET Panjab University Chandigarh 21-22nd December 2015

provides lower glitches [6]. The value of output current or C. Thermometer Decoder
voltage across output load resistor depends on the applied
digital input data which steered in the form of current from TABLE 1: BINARY-TO-THERMOMETER TRUTH TABLE
current source to output. Binary Thermometer
B. Current Cell 0000 000 0000 0000 0000
0001 000 0000 0000 0001
0010 000 0000 0000 0011
0011 000 0000 0000 0111
0100 000 0000 0000 1111
0101 000 0000 0001 1111
0110 000 0000 0011 1111
0111 000 0000 0111 1111
1000 000 0000 1111 1111
1001 000 0001 1111 1111
1010 000 0011 1111 1111
1011 000 0111 1111 1111
Fig. 2: Schematic Design of Current Cell
1100 000 1111 1111 1111
Current cell is formed with the combination of analog and 1101 001 1111 1111 1111
digital part as shown in Fig.2. The digital part have D latch,
1110 011 1111 1111 1111
and basic logic gates (AND, OR) connected to latch [1]. The
input given to logic gate AND is combination of row and 1111 111 1111 1111 1111
column decoder output with cascading inverter, which provide
synchronization by delaying the input. The OR gate has one
input from output of AND gate and another input is
(Column+1). The output of OR gate is given to D latch. The
two outputs of D latch, Q and Qbar, control the operation of
current switch, which is generated with the combination of row
and column decoder output passing through basic logic gates
(AND, OR). The clock is given to latch for proper operation.
The decoding logic used in design of unary coded segmented
DAC requires three signal, these are Row, Column and an extra
redundant column signal (Column+1). The controlling signal Q
is given as [5],
Q = (Column + 1) + (Row × Column) (1)
The analog part has current source and current switch. For
high output impedance either current mirror technique is used
or transistor arranged in cascoded form in current cell circuit
design. In this research work cascoded arrangement of
transistor is used. PMOS transistor implemented for current
source because hole has lower mobility than electron so PMOS
is less affected by noise. The Vg1 and Vg2 are the applied gate Fig. 3: Schematic Diagram of Fully Segmented DAC
voltage at PMOS transistor. As the size of transistor increases
transconductance increases due to which output impedance Here 8-bit DAC is designed so a thermometer decoder with
increases [3]. The parasitic capacitance depends on transistor 8 binary inputs and 255 thermometer coded output is required.
size. Larger size of current source transistor results in large For more optimize design thermometer decoder is divide in
parasitic capacitance at the output node which combined with row and column decoder [2]. Thermometer decoder provide
large output resistance and causes lower bandwidth with higher good linearity because change in binary input value from one
delay. To maintain a trade-off between output impedance, to another, at a time, results in transition of more than one
bandwidth and delay, optimized transistor size is chosen [7]. places which leads non linearity, while in thermometer
Current switches made up of NMOS transistor. There are two decoding only one bit transition occur. For N-bit thermometer
extra NMOS transistor in current switch which connected to coded DAC, 2 1 equal current cells are required which
Vdd, provide protection from CFT effect and minimize glitches causes more power and area consumption. Row and column
[4]. Current cell is connected to the output of binary to decoder both have 4 inputs and 16 outputs. Let an example of
thermometer decoder. 4-bit thermometer-coded DAC, for that decoder as shown in

978-1-4673-8253-3/15/$31.00 ©2015 IEEE

 Proceedings of 2015 RAECS UIET Panjab University Chandigarh 21-22nd December 2015

the Table I, 16 outputs. The schematic of fully segmented DAC

is shown in Fig.3, where current cell array and decoder output
connection is displayed. By providing similar voltage pulses at
the gate of PMOS transistor of current source in current cell
array and a common clock pulse to the latch of current cell
array, output of designed DAC is obtained by combining the
output of current cells together.
III. SIGNIFICANCE OF DESIGNED DAC
The unary coded segmented DAC are used for accurate
digital to analog conversion with linear output. For higher
resolution fully segmented DAC, complexity increases because
of more number of current cells, this also increases area and
power consumption. The advantage of fully segmented DAC is
in minimizing the non linearity. In defense for highly security
purpose efficient and correct data conversion are required and
it may be possible with a DAC having linear output so the need
of designing a fully segmented DAC occur. Fig.5: Simulation Waveform of 8-Bit Fully Segmented DAC

IV. SIMULATION RESULT V. CONCLUSION

Simulations of fully segmented DAC have been performed This paper presents design of 8-bit fully segmented digital
with spectre simulator in Cadence Virtuoso tool at 180nm to analog converter in brief with simulation results. The fully
technology. Simulated output waveform of fully segmented segmented DAC has been designed at 180nm technology. The
DAC has shown in fig.4 and fig.5. The circuit is operated at concept of current steering technique with thermometer coding
supply voltage of 1.8V. The 8-bit binary inputs of segmented and cascoded arrangement of transistor in current source are
DAC are r0, r1, r2, r3, d0, d1, d2, d3, d4 from least significant used in the design of DAC to minimize noise and non linearity
bit (LSB) to most significant bit (MSB). The input voltage with high output impedance. The power dissipation of DAC is
pulse with period of 2ns is applied at r0 and voltage pulse of depends on reference current value and resolution of DAC. If
period 256ns applied to d3 with 50 percent duty cycle. The reference current value increases power dissipation increases.
input waveform from r0 to d1 has been shown in fig.4 and So there must be tradeoff between power, accuracy, area and
input waveform from d0 to d3 with output v1 and v2 has been speed.
shown in fig.5. The output of designed DAC has 256 different
output levels corresponding to 256 combinations of 8 bit binary TABLE II : PERFORMANCE OF FULLY SEGMENTED DAC
inputs. The differential and integral non linearity and power
Parameters Performance
has been calculated from simulation result.
. Resolution 8-bits

Technology 180nm

Supply Voltage 1.8V

DNL 0.013LSB

INL 0.145LSB

Power 99.67mW

REFERENCES
[1] Sarkar, S.Banerjee, "An 8-bit 1.8 V 500 MSPS CMOS Segmented
Current Steering DAC," IEEE Computer Society Annual Symposium
on VLSI, pp.268-273, May 2009.
[2] M. Gustavsson, J. J. Wickner and N. N. Tan, CMOS Data Converters
for Communications, Kluwer Academic Pblishers, 2002.
[3] B. Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw-
Hill, 2002.
Fig.4: Simulation Waveform of 8-Bit Fully Segmented DAC
[4] M. Song, H. Lee, M. K. Song andW. Song , “A Fully Integrated Current-
Steering 10-bit CMOS D/A Converter with a Self CalibratedCurrent
Bias Circuit ,” Analog Integrated Circuits and Signal Processing, vol.
44, pp.251–259, Sept 2005.
[5] C. Y. Huang, T. T. Hou and H. Y. Wang, “A 12-bit 250-MHz Current
Steering DAC,” in 6th International Conference on ASIC
(ASICON),vol. 1, pp. 411– 414, Oct 2005.

978-1-4673-8253-3/15/$31.00 ©2015 IEEE

 Proceedings of 2015 RAECS UIET Panjab University Chandigarh 21-22nd December 2015

[6] Irfansyah, A.N, Lehmann, T., Jenkins, J., Hamilton, T.J., "Analysis and
design considerations of systematic nonlinearity for sigma-delta current-
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[7] Xueqing Li, Qi Wei, Huazhong Yang,"Code-independent output
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[8] B. Razavi, Design of Analog CMOS Integrated Circuits, Tata
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[9] A. Hastings, Art of Analog Layout, Prentice Hall, 2005.

978-1-4673-8253-3/15/$31.00 ©2015 IEEE

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