EXPERIMENT-3

AIM: To Write a Verilog code to design 8-to-1 multiplexer and 1-to-8

SOFTWARE REQUIRED :

1. Vivado

2. Windows OS (latest version)

THEORY:

8-to-1 Multiplexer

1-to-8 Demultiplexer
CODE:

8 to 1 Multiplexer

1.Gatelevel Model:

module mux (a, b, c, i0, i1, i2, i3, i4, i5, i6, i7,o);

input a, b, c, i0, i1, i2, i3, i4, i5, i6, i7;

output o;

wire an, bn, cn;

wire p, q, r, s, t, u, v, w;

not x1 (an, a);

not x2 (bn, b);

not x3 (cn, c);

and x4 (p, an, bn, cn, i0);

and x5 (q, an, bn, c, i1);

and x6 (r, an, b, cn, i2);

and x7 (s, an, b, c, i3);

and x8 (t, a, bn, cn, i4);

and x9 (u, a, bn, c, i5);

and x10 (v, a, b, cn, i6);

and x11 (w, a, b, c, i7);

or x12 (o, p, q, r, s, t, u, v, w);

endmodule

2.Behavioural model:
 module mux_behave (a, b, c, i0, i1, i2, i3, i4, i5, i6, i7,o);

input a,b,c, 10, 11, 12, 13, 14, 15, 16, 17;

output reg o;

reg an, bn, cn;

reg p, q, r, s, t, u, v, w;

always @(a or b or c or 10 or il or i2 or i3 or i4 or i5 or i6 or i7 )

begin

an=-a;

bn=-b;

cn=-c;

p=an&bn&cn&i0;

q=an&bn&c&i1;

r=an&b&cn&i2;

s=an&b&c&i3;

t=a&bn&cn&i4;

u=a&bn&c&i5;

v=a&b&cn&i6;

w=a&b&c&i7;

o=p|q|r|s|t|u|v|w;

end

endmodule

3.Dataflow model:

module mux_dataflow (a, b, c, i0, i1, i2, i3, i4, i5, i6, i7,o);
input a, b, c, i0, i1, i2, i3, i4, i5, i6, i7

output o;

wire an, bn, cn;

wire p, q, r, s, t, u, v, w;

assign an =~a;

assign bn=~b;

assign cn=~c;

assign p=an&bn&cn&i0;

assign q=an&bn&c&i1;

assign r=an&b&cn&i2;

assign s=an&b&c&i3;

assign t=a&bn&cn&i4;

assign u=a&bn&c&i5;

assign v=a&b&cn&i6;

assign w-=a&b&c&i7;

assign o=p|q|r|st|u|v|w;

endmodule

Testbench:

module mux81_tb;
reg a, b, c, i0, i1, i2, i3, i4, i5, i6, i7;

wire o;

mux xa (a, b, c, i0, i1, i2, i3, i4, i5, i6, i7, 0);

initial begin

a = 0; b = 0; c = 0;i0 = 1; i1 = 0; i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 0; #100

a = 0; b = 0; c = 1;i0 = 0; i1 = 1; i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 0; #100

a = 0; b = 1; c = 0;i0 = 0; i1 = 0; i2 = 1;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 0; #100

a = 0; b = 1; c = 1;i0 = 0; i1 = 0; i2 = 0;i3 = 1;i4 = 0;i5 = 0;i6 = 0;i7 = 0; #100

a = 1; b = 0; c = 0;i0 = 0; i1 = 0; i2 = 0;i3 = 0;i4 = 1;i5 = 0;i6 = 0;i7 = 0; #100

a = 1; b = 0; c = 1;i0 = 0; i1 = 0; i2 = 0;i3 = 0;i4 = 0;i5 = 1;i6 = 0;i7 = 0; #100

a = 1; b = 1; c = 0;i0 = 0; i1 = 0; i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 1;i7 = 0; #100

a = 1; b = 1; c = 1;i0 = 0; i1 = 0; i2 = 0;i3 = 0;i4 = 0;i5 = 0;i6 = 0;i7 = 1; #100

end

endmodule

1 to 8 demultiplexer

Gate level:

module demux (i, a, b, c, i0, i1, i2, i3, i4, i5, i6, i7);

input i, a, b, c;

output i0, i1, i2, i3, i4, i5, i6, i7;

wire an, bn, cn;

not x1 (an, a);

not x2 (bn, b);

not x3 (cn, c);

and x4 (i0, an, bn, cn, i);

and x6 (i2, an, b, cn, i);

and x7 (i3, an, b, c, i);

and x8 (i4, a, bn, cn, i);

and x9 (i5, a, bn, c, i);

and x10 (i6, a, b, cn, i);

and x11 (i7, a, b, c, i);

or x12 (0, p, q, r, s, t, u, v, w);

endmodule

2.Behavourial code:

module demux_behav(i, a, b, c, i0, i1, i2, i3, i4, i5, i6, i7);

input i, a,b,c;

output reg i0, i1, i2, i3, i4, i5, i6, i7;

reg an, bn, cn;

always @(i or a or b or c)

begin

an=~a;

bn=~b;

cn=~c;

i0=an&bn&cn&i;

i1=an&bn&c&i;

i2=an&b&cn&i;

i3=an&b&c&i;

i4=a&bn&cn&i;
i5=a&bn&c&i;

i6=a&b&cn&i;

i7=a&b&c&i;

end

endmodule

3.Dataflow model:

module demux_dataflow(i, a, b, c, i0, i1, i2, i3, i4, i5, i6, i7);

input i,a,b,c;

output i0, i1, i2, i3, i4, i5, i6, i7;

wire an, bn, cn;

assign an=~a;

assign bn=~b;

assign cn=~c;

assign i0=an&bn&cn&i;

assign i1=an&bn&c&i;

assign i2=an&b&cn&i;

assign i3=an&b&c&i;

assign i4=a&bn&cn&i;

assign i5=a&bn&c&i;

assign i6=a&b&cn&i;

assign i7=a&b&c&i;

endmodule

Test bench:

module demux81_tb;

reg i, a, b, c;

wire i0, i1, i2, i3, i4, i5, i6, i7;

initial

begin

a = 0; b = 0; c =0; i = 1;#100;

a = 0; b =0; c =1; i = 1;#100;

a = 0; b =1; c =0; i = 1;#100;

a = 0; b = 1; c =1; i = 0;#100;

a = 1; b = 0; c =0; i = 1;#100;

a = 1; b = 0; c =1; i = 1;#100;

a = 1; b = 1; c = 0;1 = 0;#100;

a = 1; b = 1; c = 1; i = 1;#100;

end

endmodule

OUTPUT:

1. 8-to-1 Multiplexer
2.1 to 8 demultiplexer:
RESULT : Hence, 8 to 1 multiplexer and 1 to 8 demultiplexer are designed.
 EXPERIMENT-4
AIM: To Write a Verilog code to design of 4 bit binary to gray code converter.

SOFTWARE REQUIRED :
1. Vivado

2. Windows OS (latest version)

THEORY:
 CODE:

1.Gate Level:

module gray (b3,b2, b1, b0, g3, g2, g1, g0);

input b3,b2, b1, b0;

output g3, g2, g1, g0;

xor xl (g0, b0, b1);

xor x2 (g1,b2, b1);

xor x3 (g2, b2, b3);

or x4 (g3, b3, 0);

endmodule

2.Behavioural model:

module bin_gray_behave (b3, b2, b1,b0, g3, g2, g1, g0);

input b3, b2, b1,b0;

output reg g3, g2, g1, go;

always @(b3 or b2 or b1 or b0)

begin

g3-b3;

g2=b3^b2;

g1=b1^b2;

g0=b1^b0;

end

endmodule

3.Dataflow model:
module bin_gray_dataflow (b3, b2, b1, b0, g3, g2, g1, g0);

input b3, b2, b1,b0;

output g3, g2, g1, g0;

assign g3=b3;

assign g2-b3b2;

assign g1=b1^b2;

assign g0=b1^b0;

endmodule

Testbench:

module gray_tb();

reg b3,b2, b1, b0;

wire g3,g2, g1, g0;

gray xa (b3,b2, b1, b0, g3, g2, g1, g0);

initial

begin

b3 = 1; b2 = 1; b1 = 0; b0 =1; # 200;

b3 = 0; b2 = 0;b1 = 1;b0 =1; # 200;

b3 = 0; b2 = 1;b1 = 0;b0 =1; # 200;

b3= 0; b2 = 1; b1 = 1;b0 = 0; #200;

end

endmodule

OUTPUT:
RESULT: Hence, a 4 bit binary to gray code converter is designed and their
characteristics are observed.