Unit 4.

Flip Flops

Prepared by, Dr S C Tamane

UNIT IV
 Flip Flops:
 Introduction,
 A 1 Bit Memory Cell,
 Clocked S-R FLIP FLOP,
 J-K FLIP FLOP,
 D and T FLIP FLOP,
 Excitation table of FLIP FLOP,
 Conversion from one type of FLIP FLOP to Another Type
Books

 Text Books:
1. R.P. Jain, “Modern Digital Electronics”, Tata McGraw Hill Publication, 4th Edition, 2010.
2. M. M. Mano, “Digital Logic and Computer Design”, Prentice Hall of India Publication, 4 th
Edition, 2006.

 Reference Books:
1. D. P. Leach, A. P. Malvino, G. Saha, “Digital Principles and Applications”,Tata McGraw Hill
Publication, 8th Edition, 1993.
2. Comer, “Digital Logic & State Machine Design”, Oxford Universities Press, 3rd Edition,
2014

 E-Sources:
 NPTEL videos
 Introduction
• So far we have studied the analysis and design of combinational
digital circuits.
• The other major aspect of digital systems is analysis and design of
sequential circuits and this depends on the combinational circuit
design.
• There are many applications in which digital outputs are required
to be generated in accordance with the sequence in which the
input signals are received.
• This requirement can not be satisfied using a combinational logic
systems.
• These applications require outputs to be generated that are not
only dependent on the present input conditions but also depend
upon the past history of these inputs.
• The past history is provided by feedback from the output back to
the input.
 Introduction
• The block diagram of the sequential circuit is shown in following fig. 7.1
• It consists of combinational circuits which accept digital signals from
external inputs and from outputs of memory elements and generates
signals for external outputs and for inputs to memory elements
referenced to a excitation.
 A 1-Bit Memory Cell
• The basic digital memory circuit is known as FLIP-FLOP.
• It has two stable states which are known as the 1 state and the 0 state.
• It can be obtained using NAND or NOR gates.
• Fig. 7.3 consists of two inverters G1 and G2 (NAND gates used as inverters).

• The output of G1 is connected to the

input of G2(A2) and the output of G2 is
connected to the input of G1(A1).
• Let us assume that the output of G1 to be
Q=1, which is also the input of G2(A2=1).
• Therefore the output of G2 will be Q’=0,
which makes A1=0 and Q=1.
• If Q=0 then Q’=1 and this is also
consistent with the circuit connections.
 A 1-Bit Memory Cell
1. The outputs Q and Q’ are always complementary.
2. The circuit has two stable states.
i. Q=1 or 1 state
ii. Q=0 or 0 state
3. If the circuit is in 1 state, it continues to remain in this state and if it is in 0 state,
it continues to remain in this state. This property is called as Memory/Latch.
 A 1-Bit Memory Cell
• In the latch of fig. 7.3 there is no way of entering the desired digital information
to be stored in it.
• When the power is switched on, the circuit switches to one of the stable states
(Q=1 or 0).
• If G1 and G2 are replaced with NAND gates, the other input terminals of the
NAND gates can be used to enter the desired digital information.
• The modified circuit is shown in the fig. 7.4.
 B A NAND

0 0 1

A 1-Bit Memory Cell 0

1
1
0
1
1
1 1 0

• If S=R=0, the circuit is same as fig. 7.3.

• If S=1 and R=0, the output of G3 will be 0 and the output of G4 will be 1.
• Since one of the inputs of G1 is 0, its output will be 1.
• Both the inputs of G2 will be 1 and Q’=0. Therefore, for this input condition,
Q=1 and Q’=0.
• If S=0 and R=1, then the outputs
will be Q=0 and Q’=1.
• The first of these two input
conditions S=1, R=0 makes Q=1:
set state.
• The second input condition S=0
and R=1 makes Q=0: reset state
or clear state.
7.1 Show that the circuit of fig. 7.4 with S=R=0 is
the same as that of fig. 7.3

Solution:
When S=R=0, the outputs of the gates G 3 and G4
will be 1.
Therefore, G1 and G2 will act as inverters .
Hence, the circuit of fig. 7.4 is the same as that of
fig. 7.3.
 Clocked S-R Flip-Flop
• It is often required to set or reset the memory cell (fig. 7.4) in synchronism.
• Such a circuit is shown in fig 7.5 and is referred to as a Clocked set-reset S-R Flip-
Flop.
• In this circuit, if a clock pulse is present (CK=1), its operation is same as fig. 7.4.
• If a clock pulse is not present (CK=0), the gates G3 and G4 are inhibited, i.e. there
outputs are 1 irrespective of the values of S and R.
• Truth table of S-R flip-flop is shown below for CK=1.
 Clocked S-R Flip-Flop
• It is often required to set or reset the memory cell (fig. 7.4) in synchronism.
• Such a circuit is shown in fig 7.5 and is referred to as a Clocked set-reset S-R Flip-
Flop.
• In this circuit, if a clock pulse is present (CK=1), its operation is same as fig. 7.4.
• If a clock pulse is not present (CK=0), the gates G3 and G4 are inhibited, i.e. there
outputs are 1 irrespective of the values of S and R.
• Truth table of S-R flip-flop is shown below for CK=1.

Inputs Output
Sn Rn Qn+1
0 0 Qn
1 0 1
0 1 0
1 1 ?
 Clocked S-R Flip-Flop
• Sn=Rn=1 condition is not allowed. Let us see what happens for this condition in S-R
Flip-flop.
• When Ck=1, the outputs of gates G3=G4=0, making one of the inputs of G 1 and G2
NAND gates 0
• Q=Q’=1, which is inconsistent.
• When Ck=0, the outputs of gates G3 = G4 =1, making Qn+1=1 (or Q’n+1=0) or Qn+1=0 (or
Q’n+1=1), will result. That means the state of the circuit is
undefined/indeterminate/ambiguous.
• Therefore the condition Sn=Rn=1 is forbidden.
• The logic symbol of clocked S-R Flip-flop is given in the fig. 7.6.
7.2 In a circuit of fig. 7.4 if the
inputs change from
a) S=1, R=0 to S=R=0 and
b) S=0, R=1 to S=R=0
Show that the outputs do not
change.

• Solution: a)
• When S=1 and R=0, the outputs of G3 and G4 are 0 and 1
resp.
• Since G1=0, Q=1, this makes inputs of G2 as 1, Q’=0.

• When S=R=0, the inputs and output of G2 remain

unaffected, which makes the lower input of G1 as 0,
while the upper one becomes one giving again Q=1.
• This means output do not change.
7.2 In a circuit of fig. 7.4 if the
inputs change from
a) S=1, R=0 to S=R=0 and
b) S=0, R=1 to S=R=0
Show that the outputs do not
change.

• Solution: b)
• With S=0 and R=1, Q’=1 and Q=0 in a manner similar to
part a) and also Q and Q’ will remain unchanged when S
and R both are made 0.
 Preset and Clear
• In the Flip-flop of fig 7.5, when the power is switched on, the state of the
circuit is uncertain.
• It may come to set Q=1 or reset Q=0 state.
• In many applications it is desired to initially set or reset the flip-flop.
• This is done by using the direct or asynchronous inputs, referred to as preset
(Pr) and Clear (Cr) inputs.
• This is shown in the fig. 7.7.
 Preset and Clear
• In the Flip-flop of fig 7.5, when the power is switched on, the state of the
circuit is uncertain.
• It may come to set Q=1 or reset Q=0 state.
• In many applications it is desired to initially set or reset the flip-flop.
• This is done by using the direct or asynchronous inputs, referred to as preset
(Pr) and Clear (Cr) inputs.
• This is shown in the fig. 7.7.
 Preset and Clear
• If Pr=Cr=1 the circuit operates in accordance with the truth table of S-R Flip-
flop given in Table 7.1.
• If Pr=0 and Cr=1, the output of G1(Q) will certainly be 1.
• All the three inputs to G2 will be 1 which will make Q’=0. hence, making Pr=0
sets the Flip-flop.
• If Pr=1 and Cr=0, the Flip-flop is reset. Once the state of the Flip-flop is
established asynchronously, the asynchronous inputs Pr and Cr must be
connected to logic 1 before the next clock is applied.
7.3 Design an S-R latch using 2 input NOR gates.
7.4 In the FF circuit of fig. 7.28 show that if
a) Pr=0 and Cr=1 then Q=1 (independent of S, R and CK)
b) Pr=1 and Cr=0 then Q=0 (independent of S, R and CK)
c) Pr=Cr=1 then it functions as a clocked S-R FF.
7.4 In the FF circuit of fig. 7.28 show that if
a) Pr=0 and Cr=1 then Q=1 (independent of S, R and CK)

(a) With Pr = 0, Q’ will be 0 which makes one of the inputs of G3 0.

Therefore, whatever may be the other input of G3, its output will be 1.
• This results in both the inputs of AND gate G5 to be 1 giving Q = 1.
• That is, the FLIP-FLOP is set irrespective of the S, R, and CK inputs.
7.4 In the FF circuit of fig. 7.28 show that if
b) Pr=1 and Cr=0 then Q=0 (independent of S, R and CK)

(b) If Cr = 0, then the FLIP-FLOP is reset following the same logic as

discussed in part (a)
7.4 In the FF circuit of fig. 7.28 show that if
c) Pr=Cr=1 then it functions as a clocked S-R FF.

Inputs Output
Sn Rn Qn+1
0 0 Qn
1 0 1
0 1 0
1 1 ?

(c) If Pr = Cr = 1, the AND gates G5 and G6 are enabled, making this

circuit identical to a normal clocked S – R FLIP-FLOP as shown in Fig.
7.5.
 J-K Flip-Flop
• The uncertainty in the state of an S-R Flip-flop when Sn=Rn=1 can be
eliminated by converting it into a J-K Flip Flop.
• The data inputs are J and K which are ANDed with Q’ and Q resp. to obtain S
and R inputs, i.e.
• S=J.Q’ and R=K.Q
• A J-K Flip-flop thus obtained is shown in fig. 7.8
 J-K Flip-Flop
• Verify Table 7.3a)
• (i) When Jn = Kn = 0, the AND gates are disabled resulting in Sn = Rn = 0.
• Therefore, when a clock pulse is applied, the outputs Q and Q’ will not
change, i.e., Qn+1 = Qn.
 J-K Flip-Flop
• (ii) When Jn = 1 and Kn = 0, then Sn = Q’n and Rn = 0.
• Now, if Qn = 1 then Sn = 0, i.e., Sn = Rn = 0 and the output Qn+1 = Qn = 1.
• On the other hand if Qn = 0 then Sn = 1 which will make Qn+1 = 1.
• Therefore, whatever may be the state of the FLIP-FLOP, it will go to set state
in this condition when a clock pulse is applied.
 J-K Flip-Flop
• (iii) If Jn = 0 and Kn = 1 then Sn = 0 and Rn = Qn.
• Following the above discussion, we find that the FLIP-FLOP will go to the
reset state when a clock pulse is applied.
 J-K Flip-Flop
• (iv) If Jn = Kn = 1, then Sn = Q’n and Rn = Qn.
• Now, if Qn = 1, then Sn = 0 and Rn = 1 which will make Qn+1 = 0.
• Similarly, if Qn = 0, then Sn = 1 and Rn = 0 which makes Qn+1 = 1.
• Therefore, Qn+1 = Q’n.
 J-K Flip-Flop
• Truth table is reduced to table 7.3b for convenience.
 J-K Flip-Flop
• It is not necessary to use the AND gates of fig. 7.8, since the same function
can be performed by adding an extra input terminal to each NAND gate G3
and G4 of fig. 7.7.
• The new circuit is shown in the fig. 7.9.
• The logic symbol of J-K Flip-flop is shown in the fig.7.10.
 J-K Flip-Flop
• It is not necessary to use the AND gates of fig. 7.8, since the same function
can be performed by adding an extra input terminal to each NAND gate G3
and G4 of fig. 7.7.
• The new circuit is shown in the fig. 7.9.
• The logic symbol of J-K Flip-flop is shown in the fig.7.10.
• 7.6 Determine the output Y1 of fig. 7.29a and Y2 of fig. 7.29b
and show that Y1=Y2.

• Y1 = ((J.Q’).CK)’
= (J.Q’.CK)’
• Y2 = (J.Q’.CK)’
• Hence, Y1 = Y2
 D Type Flip-Flop
• If we use only the middle two rows of the truth table of the S-R
or J-K Flip-Flop, we obtain a D-Type Flip-Flop as shown in the fig.
7.14.
• It has only one input referred to as D-input or data input.
• Its truth table is given in the table 7.4.

Truth Table of a D
Type Flip-Flop
Input Output
Dn Qn+1
0 0
1 1
 D Type Flip-Flop
• The input data appears at the output at the end of the clock pulse.
• Thus the transfer of data from the input to the output is delayed and
hence the name delay (D) Flip-flop.
• It is either used as a delay device or as a latch to store 1-bit of binary
information.

Truth Table of a D
Type Flip-Flop
Input Output
Dn Qn+1
0 0
1 1
 T Type Flip-Flop
• In a J-K Flip-Flop, if J=K, the resulting Flip-flop is referred to as a T-type
Flip-Flop and is shown in fig. 7.15.
• It has only one input, referred to as T-input.
• Its truth table is shown below.
• If T=1 it acts as a toggle switch, for every clock pulse, the output Q
changes.

Truth Table of a T
Type Flip-Flop
Input Output
Tn Qn+1
0 Qn
1 Q’n
 T Type Flip-Flop
• An S-R Flip-Flop cannot be converted into a T-type Flip-Flop
since S=R=1 is not allowed.
• However, the circuit of fig.7.16 acts as a toggle switch, i.e. the
output Q changes with every clock pulse.

Truth Table of a T
Type Flip-Flop
Input Output
Tn Qn+1
0 Qn
1 Q’n
7.11 Verify that the circuit of fig. 7.16 acts as a toggle
switch.

•Let Q = 1 and Q’ = 0.
•This makes R = Q = 1 and S = Q’ = 0.
•When a clock pulse is applied, Q and Q’ will become 0 and 1 resp.
•Now, R = Q = 0 and S = Q’ = 1 and on application of a clock pulse,
Q and Q’ become 1 and 0 resp.
•This shows that Q and Q’ change with every clock pulse, and
hence the circuit behaves as a toggle switch.
7.12 Prepare the truth table for the circuit of fig. 7.34
and show that it acts as a T-type Flip-flop.

Tn Qn Sn Rn Qn+1
0 0 0 1 0
0 1 1 0 1
1 0 1 0 1
1 1 0 1 0

From truth table,

when Tn = 0, Qn+1 = Qn, whereas,
when Tn = 1, Qn+1 = Q’n.
7.13 If Q’ output of a D type Flip-flop is connected to D
input, it acts as a toggle switch. Verify.

Truth Table of a D
Type Flip-Flop
Input Output
Dn Qn+1
0 0
1 1

•When Q’ = D = 0, a clock pulse will make Q and Q’ 0 and 1 resp.

•Now Q’ = D = 1 and the next clock pulse will change the Q output
o 1.
•Thus, the outputs change with every clock pulse.
 Excitation Table of Flip-Flop
• The truth table of a Flip Flop is also referred to
as the characteristics table and specifies the
operational characteristic of the Flip-Flop.
• Present state-next state: the state of the
circuit prior to and after the clock pulse resp.
• Ex. S-R FF:
– Before the clock pulse: Qn=0
– After the clock pulse: (output does not change)
Qn=0
 Excitation Table of Flip-Flop
• A tabulation of input conditions of all FFs for all possible
situations can be found in the excitation table.
• Following table gives this information for S-R, J-K, T and D
FFs.
• This is derived from the characteristic table of the FF.

Present Next S-R FF J-K FF T-FF D-FF

State State Sn Rn Jn Kn Tn Dn
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
 Excitation Table of Flip-Flop
Inputs Output (S-R)

Sn Rn Qn+1
0 0 Qn
1 0 1
0 1 0
1 1 ?

Present Next S-R FF J-K FF T-FF D-FF

State State Sn Rn Jn Kn Tn Dn
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
 Excitation Table of Flip-Flop

Present Next S-R FF J-K FF T-FF D-FF

State State Sn Rn Jn Kn Tn Dn
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
 Excitation Table of Flip-Flop
Truth Table of a T
Type Flip-Flop
Input Output
Tn Qn+1
0 Qn
1 Q’n

Present Next S-R FF J-K FF T-FF D-FF

State State Sn Rn Jn Kn Tn Dn
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
 Excitation Table of Flip-Flop
Truth Table of a D
Type Flip-Flop
Input Output
Dn Qn+1
0 0
1 1

Present Next S-R FF J-K FF T-FF D-FF

State State Sn Rn Jn Kn Tn Dn
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
Conversion from One Type of Flip Flop
to Another Type
• Consider the general model for conversion from one type of
Flip-Flop to another type.
• This model requires to design the combinational logic decoder
(conversion logic) for converting new input definitions into
input codes which will cause the given Flip-Flop to perform as
desired.
Conversion from One Type of Flip Flop
to Another Type
• To design the conversion logic we need to combine the
excitation tables for both Flip-Flops and make a truth table
with data input(s) and Q as the inputs and the input(s) of the
given FLIP-FLOP as the output(s).
• Example 7.2 Convert an S-R Flip-Flop to a J-K Flip-Flop.
• Solution:
Row FF data inputs Output SR FF Inputs
J K Q S R

Truth Table 1 0 0 0 0 X
of 2 0 1 0 0 X
Conversion 3 1 0 0 1 0
Logic → 4 1 1 0 1 0
5 0 1 1 0 1
6 1 1 1 0 1
7 0 0 1 X 0
8 1 0 1 X 0

Excitation Present Next S-R FF J-K FF T-FF D-FF

Table → State State Sn Rn Jn Kn Tn Dn
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
• Example 7.2 Convert an S-R Flip-Flop to a J-K Flip-Flop.
• Solution:
Row FF data inputs Output SR FF Inputs
J K Q S R

Truth Table 1 0 0 0 0 X
of 2 0 1 0 0 X
Conversion 3 1 0 0 1 0
Logic → 4 1 1 0 1 0
5 0 1 1 0 1
6 1 1 1 0 1
7 0 0 1 X 0
8 1 0 1 X 0
• 7.15 Using the conversion method, carry out the following conversions:
• 7.15 Using the conversion method, carry out the following conversions.
• Solution: a) S-R to D

Excitation Present Next S-R FF J-K FF T-FF D-FF

Table → State State Sn Rn Jn Kn Tn Dn
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
• 7.15 Using the conversion method, carry out the following conversions.
• Solution: b) J-K to D

Excitation Present Next S-R FF J-K FF T-FF D-FF

Table → State State Sn Rn Jn Kn Tn Dn
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
• 7.15 Using the conversion method, carry out the following conversions.
• Solution: c) D to J-K

Excitation Present Next S-R FF J-K FF T-FF D-FF

Table → State State Sn Rn Jn Kn Tn Dn
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
• 7.15 Using the conversion method, carry out the following conversions.
• Solution: d) S-R to T

Excitation Present Next S-R FF J-K FF T-FF D-FF

Table → State State Sn Rn Jn Kn Tn Dn
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 1 0
1 1 X 0 X 0 0 1
• 7.15 Using the conversion method, carry out the following conversions.
• Solution: e) to k)