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Mid Term Exam Sp20 Solutions

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26 views8 pages

Mid Term Exam Sp20 Solutions

Uploaded by

Sirish Oruganti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE382M: VLSI-II EXAM 1 March 11, 2020

EE382M - VLSI II
MID SEMESTER EXAM
SPRING 2020

Print Name Here ___Solutions_________________________


UT – EID ___________________________________
Signature ___________________________________

This is a closed book, closed notes and closed electronic devices exam. The exam
is to be completed in ninety (90) minutes.

_______Please check here to indicate that you have received all parts of the
exam. (8 Pages including this one)

Problem 1 ________________ (20 Points)

Problem 2 ________________ (25 Points)

Problem 3 ________________ (30 Points)

Problem 4 ________________ (25 Points)

Total for exam ________________ (100 Points)

1
EE382M: VLSI-II EXAM 1 March 11, 2020

Qualitative Questions (2 points each) (20 Points

Problem 1: Answer the following questions using these symbols ONLY:


 Value goes up

➔ Value stays the same

 Value goes down

2
EE382M: VLSI-II EXAM 1 March 11, 2020

Problem 2: Nano-scale Transistors 25 Points

a) For a FinFET technology, with Fin_height=50nm, Fin_width=25nm, and Fin_spacing = 25nm, quantify
the ON current improvement compared to the planar transistor. Assume that top of the fin also
contributes in the FinFET behavior. Assume all other device parameters (oxide thickness, stress/strain
effects) are same in both transistors (15 points)

3
EE382M: VLSI-II EXAM 1 March 11, 2020

b) Write at least two variants of Gate All Around (GAA) transistor structures ( 5 points)

c) Write at least two non-ideal effects for ON current reduction and Vt degradation? ( 5 points)

On current reduction:

Vt degradation:

4
EE382M: VLSI-II EXAM 1 March 11, 2020

Problem 3: Flip-Flop characterization 30 Points

* UNIT delays on all INVERTERS, NAND gates, and transmission gates. Both transistors on the
transmission gate must be on before it transmits a signal.

* Assume perfect rise/fall times on all signals.

a) Given Clk and Din in the timing diagram below, draw PCLK, A, B and Dout waveforms. Each “tick” on
the graph represents one gate delay. ( 15 points)

5
EE382M: VLSI-II EXAM 1 March 11, 2020

b) What limits the maximum frequency of this type of flip-flop? ( 5 points)

c) What is storing the state of this sequential when the pass-gate is OFF? Is it susceptible to NOISE?
( 5 points)

d) What would you do to make sure that node B is stable at all times or reduce/mitigate attacker
NOISE? Will this affect the Fmax of this design? Will dynamic power increase? ( 5 points)

6
EE382M: VLSI-II EXAM 1 March 11, 2020

Problem 4: Power Gating 25 Points

a) Derive and quantify the breakeven time required to justify this power gating scenario ( 15 points)

CL= 1nF, CPower_Gate = 10% of CL, VDD= 1V, VDD_OFF=0.1V, Ileak2/ILeak1 = 1/1000;

7
EE382M: VLSI-II EXAM 1 March 11, 2020

b) What are implications of power gate sizing on the design? ( 5 points)

Increasing power gate size:

Decreasing power gate size:

c) How the rush current can be managed during the wake-up event? ( 5points)

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