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LNA Design Report

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39 views57 pages

LNA Design Report

Uploaded by

intissar abbes
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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AVM 864 - RF Integrated Circuits

Course Project

Design of Low-Power Noise cancelling


LNA for LoRa IoT application
Index
1. Introduction (LoRa)
2. Literature review
3. CS with Inductive degeneration LNA
4. Main Topology (CG with noise cancelling)
a. DC operating point
b. Without noise cancellation design & results
c. With noise cancellation design & results
d. Number of Fingers - Introduction & effects
e. Number of Fingers : Special Case
i. Without noise cancellation design and results
ii. With noise cancellation design and results
5. Conclusion table
6. Dual band CG-LNA (preliminary work)
7. Conclusion & References
Introduction
LoRa :
● Used for long range communication majorly between the sensor
nodes of a Wireless Sensor Network
● This forces some major requirements on the receiver design
architecture i.e
○ Low Power Consumption
○ High range and thus forcing higher sensitivity
LoRa :
● LoRa (short for long range) is a spread
spectrum modulation technique
derived from chirp spread spectrum
(CSS) technology.
● The resulting bit rate will vary between
300 bps and 37.5kbps.
● Here we are using Frequency range
with minimum and maximum
frequency defined and in between
frequency defines different Symbols.
● We are using 860MHz band for our
Chirp Spectrum
project.
Literature Review
Noise cancellation :CG topology
● The CG stage realizes wideband input
impedance matching and gain, while the CS
stage realizes an anti-phase output signal
which is responsible for noise cancelling.
● It cancels the noise of the CG transistor in
order to obtain a noise figure (NF) close to
or lower than 3 dB.

Gain matching :
Noise cancellation :CS topology
● Here we can see the same
concept of noise
cancellation in CS LNA also.
● Z1 and Z2, matched at the
input resonant frequency to
cancel noise contributed by
the cascoding transistor, M2.

Gain matching :
CS with Inductive
degeneration LNA
Governing Equations:
Transition frequency
DC operating point
Circuit with Noise Cancellation

CS circuit with
Inductive degeneration

Here we used
impedance matching
for proper noise
cancellation
Gain Matching for
Noise Cancelling
Stage
Gain matching for noise cancelling
stage is done so as to cancel noise as
much as possible on all frequency
range.
Results
Issues
★ Power Consumption -- too high
★ Lg = 86.7 nH -- Off chip
★ Noise figure = 2.608 dB -- High value for CS topology
CG LNA design (without
noise cancellation)
DC operating point : circuit
● Made biasing circuit with
○ Vds = 0.6 V
○ W = 6 um
● Sweeping Vgs and plotting gm vs Id
and gm vs Vgs curve to choose
operating point along with table.

Gm Id Vgs Vth Vds

1.935 0.162 0.438 0.427 0.597

2.092 0.182 0.448 0.428 0.596

2.251 0.203 0.458 0.428 0.596


DC Operating Point: Point Selection

Point is to be chosen at a lower side to obtain less power consumption.


CG LNA Circuit Design
● Started with CG topology
and made a model with
focus on less power
consumption and least
amount of noise possible
with a constrain of all the
inductors being on chip

● First scale the width and


then tune the width to get
gm as 20 ms.
● Tune the inductor and
capacitor to get proper
matching and gain.
DC Parameter and Power
S-Parameter
Noise Figure
CG LNA : Noise
Cancellation
With Noise Cancellation:
Circuit diagram
Used same
width and
load along
with an
extra
resistance
in parallel
to control
gain
With Noise Cancellation:
Gain matching
● Tuned the widths and
resistance to match the gain
of main stage and noise
cancelling stage
● Same profile because of same
load with same Q
With Noise cancellation: DC
parameters and power

Power consumption excludes buffer stage and biasing circuit.


With Noise Cancellation:
S-parameter

Operating point is
near to the Sopt point
With Noise Cancellation: Noise
Figure
● We can see Noise Cancelling
stage had a great impact on
NF which created a dip
around the desired frequency.

● As expected, NF is closer to
the NFmin
Number of Fingers’ Effect
Introduction

Increasing NoF
○ Decreases Parasitic
Capacitance
○ Decreases Gate resistance of
MOSFET
○ NF decreases
○ IIP3 Increases
S11 changing Non-uniformly

Bandwidth decreasing exponentially (Low Drop)


Noise-Figure decreasing exponentially

Small increment in IIP3


Number of Fingers : Special Case
Used in the scale of half of the width

● Value of Nof in our design:


○ MOSFET5 (W=49 um) : 25
○ MOSFET9 (W=49 um) : 25
○ MOSFET10 (W=51 um) : 25
○ MOSFET11 (W=73.5 um) : 35

Used only for main transistors, not for biasing and buffer stage.
Without Noise cancelling
design with number of fingers
DC parameters and Power

Power consumption decrease..


S-parameter and Noise figure
Circuit for Nonlinearity Analysis
1-dB Compression Point
Circuit for Two-Tone Test
IIP3 Analysis

As expected, IIP3 ~ P1dB + 9.6 dB


Noise cancelling design
with number of fingers
Gain Matching
● Already matched, no change.

● No effect of Number of
fingers.
DC Parameters and Power

Power consumption decrease..


S-Parameter

Again Operating point is


near to the Sopt point
Noise Figure

As expected, NF is closer to
the NFmin
NF value decrease due to
added fingers.
Circuit for Nonlinearity Analysis
1-dB Compression Point
Circuit for Two-Tone Test
IIP3 Analysis

As expected, IIP3 ~ P1dB + 9.6 dB


Conclusion Table
Noise Power P1dB IIP3
(S(1,1)) (S(2,1))
Sl.No LNA Design Figure Consumption (dBm) (dBm)
dB dB
(Nf) (mW)

CG LNA(without noise
1 -35.485 13.574 4.317 2.413
cancellation)

-7.8 0.6
CG LNA (without noise
2 -35.596 13.436 2.966 2.278
cancellation with Nof)

CG LNA(with Noise
3 -38.248 18.216 3.585 5.312
cancellation)

-6 1.85

CG LNA(with noise
4 -42.931 18.073 2.172 5.006
cancellation with Nof)
Dual Band LNA design : Circuit

Used extra
capacitor
(C13,C14 and
C15) with
ideal switch
to get
another band
at 433 MHz.
Here we added capacitor bank
which can be used in conjunction
with the mosfet switches to get to
the desired band.
This is a preliminary work and
need some optimizations.
Dual Band LNA design : Results
CONCLUSION
We successfully designed LNA with following specifications:
● Differential output
● All components are on-chip
● Lower noise figure with use of number of fingers
● High linearity

Demerit:
● Slightly higher power consumption

Future work of this could be to optimize dual band LNA design using MOSFET
as switch.
REFERENCES
● Navaratne, D., Beaulieu, A., & Belostotski, L. (2010, June). Noise figure optimization
of a noise-cancelling wide-band CMOS LNA. In Proceedings of the 8th IEEE
International NEWCAS Conference 2010 (pp. 125-128). IEEE.
● Thakur, A., Agarwal, S., & Chatterjee, S. (2019, June). A 900-MHz 1.25-dB
Noise-Figure Differential-Output LNA with 12.5 dB/mW FoM. In 2019 17th IEEE
International New Circuits and Systems Conference (NEWCAS) (pp. 1-4). IEEE.
● Blaakmeer, S. C., Klumperink, E. A., Leenaerts, D. M., & Nauta, B. (2008). The BLIXER,
a wideband balun-LNA-I/Q-mixer topology. IEEE Journal of Solid-State Circuits,
43(12), 2706-2715.
● Behzad Razavi. - RF microelectronics _-Prentice Hall, (c2012.)
● Analog Layout & Design, “MULTIPLIER & FINGER”, https://youtu.be/gthnxp9P6uU
Thank You
Submitted By:
Group B
Akash Ganguly - SC18B072
Kothadiya Princekumar - SC18B078
Kshitij Singh - SC18B079
Aditya Amrit - SC18B087
Vivek Garg- SC18B093
Divyansh Sagar - SC18B101

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