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VHDL Lab

This document contains a VHDL practical file submitted by a student named Himanshu Kataria. It includes 8 experiments involving VHDL code for common digital logic circuits like a 3:8 decoder, 1:8 demultiplexer, 8:1 multiplexer, 4-bit adder/subtractor, and 4-bit comparator. Each experiment lists the aim, software used, VHDL code, and simulation results.

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123 views14 pages

VHDL Lab

This document contains a VHDL practical file submitted by a student named Himanshu Kataria. It includes 8 experiments involving VHDL code for common digital logic circuits like a 3:8 decoder, 1:8 demultiplexer, 8:1 multiplexer, 4-bit adder/subtractor, and 4-bit comparator. Each experiment lists the aim, software used, VHDL code, and simulation results.

Uploaded by

himanshukataria
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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PRACTICAL FILE VHDL

SUBMITTED TOEr.DEEPAK MALIK (ece department)

SUBMITTED BYHIMANSHU KATARIA ROLL NO.- 11080359 ECE-A3 , 6th sem

INDEX
S.NO . . 1. EXPERIMENT DATE SIGN

Write a VHDL program to implement 3:8 decoder Write a VHDL program to implement 1:8 demultiplexer. Write a VHDL program to implement 8:1 multiplexer. Write a VHDL program to implement 4 bit Addtion and Subtraction. Write a VHDL program to implement 4 bit Addtion and Subtraction.

2.

3.

4.

5.

6.

Write a VHDL program to perform 3 arithmetic and 4 logical operations. Write a VHDL program to perform serial to parallel transfer of 4 bit binary number. Write a VHDL program to perform 8:3 priority encoder. Write a VHDL program to generate MOD-10 upcounter.

7.

8.

9.

EXPERIMENT NO. 1
AIM:- Write a VHDL program to implement 3:8 decoder. SOFTWARE USED :- Xilinx ISE 8.1i. PROGRAM :-

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity decoder is Port ( a : in STD_LOGIC_VECTOR (2 downto 0); z : out STD_LOGIC_VECTOR (7 downto 0)); end decoder; architecture Behavioral of decoder is begin z<="00000001" when a="000" else "00000010" when a="001" else "00000100" when a="010" else "00001000" when a="011" else "00010000" when a="100" else "00100000" when a="101" else "01000000" when a="110" else "10000000" when a="111" ; end Behavioral; `

SIMULATION RESULT:-

EXPERIMENT NO. 2
AIM:- Write a VHDL program to implement 1:8 demultiplexer. SOFTWARE USED:- Xilinx ISE 8.1i. PROGRAM:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity m is Port ( a : in STD_LOGIC; z : out STD_LOGIC_VECTOR (7 downto 0); s : in STD_LOGIC_VECTOR (2 downto 0)); end m; architecture Behavioral of m is begin process(s,a) begin if s <= "000" then z(0) <= a ; elsif s <= "001" then z(1) <= a ; elsif s <= "010" then z(2) <= a ; elsif s <= "011" then z(3) <= a ; elsif s <= "100" then z(4) <= a ; elsif s <= "101" then z(5) <= a ; elsif s <= "110" then z(6) <= a ; elsif s <= "111" then z(7) <= a ; end if ; end process ; end Behavioral;

SIMULATION RESULT:-

EXPERIMENT NO. 3
AIM:- Write a VHDL program to implement 8:1 multiplexer. SOFTWARE USED:- Xilinx ISE 8.1i. PROGRAM:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mux is Port ( s : in STD_LOGIC_VECTOR (2 downto 0); i : in STD_LOGIC_VECTOR (7 downto 0); z : out STD_LOGIC); end mux; architecture Behavioral of mux is begin process(s) begin if s="000" then z<=i(0); elsif s="001" then z<=i(1); elsif s="010" then z<=i(2); elsif s="011" then z<=i(3); elsif s="100" then z<=i(4); elsif s="101" then z<=i(5); elsif s="110" then z<=i(6); elsif s="111" then z<=i(7); end if; end process; end Behavioral;

SIMULATION RESULT:-

EXPERIMENT NO. 4
AIM:- Write a VHDL program to implement 4 bit Addtion and Subtraction. SOFTWARE USED:- Xilinx ISE 8.1i. PROGRAM:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity addsub is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); x : in STD_LOGIC; y : out STD_LOGIC_VECTOR (3 downto 0)); end addsub; architecture Behavioral of addsub is begin process(x,a,b) begin if x='0' then y<=a+b; else y<=a-b; end if; end process; end Behavioral;

SIMULATION RESULT:SUBTRACTION

ADDITION

EXPERIMENT NO. 5
AIM:- Write a VHDL program to implement 4 bit Compartor. SOFTWARE USED:- Xilinx ISE 8.1i. PROGRAM:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity comp is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); x : out STD_LOGIC; y : out STD_LOGIC; z : out STD_LOGIC); end comp; architecture Behavioral of comp is begin process(a,b) begin if a<b then x<='1';y<='0';z<='0'; elsif a>b then x<='0';y<='1';z<='0'; elsif a=b then x<='0';y<='0';z<='1'; end if; end process; end Behavioral;

SIMULATION RESULT:WHEN a<b

WHEN a>b

WHEN a=b

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