EE5320: Analog Integrated Circuit Design; Nagendra Krishnapura (nagendra@ee.iitm.ac.

in) 1

Assignment 8

CMFB1 Bias Differential opamp CMFB2 Acm2

Vdd Vdd
M00 M14 M0 M12
M0x Mc3 Mc4
out
Ccm op Ccmx
im M1 M2 ip
Acm2
M5 M6
(a) I00 VB56
o1p o1m
om op
Cc M7 M8 Cc Mc1 Mc2
VB78 om Vcm
Rcm
M3x M4x
M3 M4
o1p o1m M01 M13 M11 Ccm From M01 Mc0
Vss Vss

CMFB1 Bias Differential opamp CMFB2 Acm2

Vdd Vdd
Mc0
o1p o1m M01 M13 M11 From M01
M3 M4
M3x M4x
VB78 Ccm op Ccmx
M7 M8 Mc1 Mc2
om op
o1p o1m
Cc Cc Acm2
(b) I00 VB56
M5 M6

M1 M2
om Vcm
Rcm out
M00 M0 Mc3 Mc4
M0x M14 M12
Vss Vss

Rf = kRi Rf = kRi
RL
Ri Ri L C
Vcm+Vi /2
Ri Vo CL Vcm Vcm Ri Vreturn L Vtest
Vcm-Vi /2
C
(c) RL (d)
Rf = kRi Rf = kRi

Figure 8.1: Problem 8.1. (a) Fully differential opamp with a pMOS input pair, (b) Fully differential opamp with a
nMOS input pair, (c) Test circuit, (d) Loop gain test circuit.

8.1. Fig. 8.1 shows fully-differential two-stage opamps. It is a modification of the single-ended opamp from the
previous assignment. Use the same bias current in the first and second stages as in the previous assignment.

• In the differential opamp, use the same transistors as in the single-ended opamp. 𝑀13 and 𝑀14 are the same
as 𝑀11 and 𝑀12 respectively. 𝑉𝐵56 and 𝑉𝐵78 can be same as in the single-ended opamp.
• Add another transistor 𝑀01 to the bias branch to derive the gate bias.2.
2This works fine with an ideal current source as shown here. In practice, two separate branches are required for 𝑀00 and 𝑀01
2 EE5320: Analog Integrated Circuit Design; Nagendra Krishnapura (nagendra@ee.iitm.ac.in)

• 𝑀0𝑥,3𝑥,4𝑥 form the common-mode feedback for the first stage. 𝑀3𝑥,4𝑥 must be replicas (⇒ same unit
transistor and current density, different number of fingers) of 𝑀11,13 . Make the current through 𝑀0𝑥 the
same as that through 𝑀0 . Adjust the sizes of 𝑀3𝑥,4𝑥 accordingly.
• The second stage uses a linear common-mode detector using 𝑅𝑐𝑚 = 100 kΩ. For 𝐴𝑐𝑚2 use the same
tail current as the first stage. 𝑉𝑐𝑚 = 𝑉𝑑𝑑 /2 V. Initially omit 𝐶𝑐𝑚 and 𝐶𝑐𝑚𝑥 . Step 𝑉𝑐𝑚 from 𝑉𝑑𝑑 /2 V to
𝑉𝑑𝑑 /2 + 50 mV. The output nodes op and om should settle without ringing. If there is ringing, introduce a
small 𝐶𝑐𝑚 ( 10 fF) and increase it until the overshoot reduces to 5%.

Realize the inverting amplifier (Fig. 8.1(c)), differential version of the opamp that you designed in assignment 4
using the opamp in Fig. 8.1(a) or (b). Use the same transistor sizes as in assignment 5 in corresponding stages.
You will also need the results of MOS characterization to determine the current density.
Do the circuit design in steps. Verify proper operation (bias voltages and currents) and move to the next step.

• Construct the first stage fully differential amplifier. Bias its outputs with an ideal dc voltage source such
that all transistors are in saturation. Verify the bias currents and voltages. Some residual current could be
flowing through the dc voltage source, but should be small. Make sure that the tail source 𝑀0 is in the
saturation region. If it is not, use a wider (increase 𝑚) transistor to get a lower 𝑉𝐷𝑆 𝐴𝑇 . You will also have
to change 𝑀00 and 𝑀0𝑥 appropriately.
• Construct CMFB1, connect it to the first stage outputs instead of the ideal voltage source in the above step.
Verify the bias currents and voltages. The output voltage should be such that it biases the second stage at
the right current.
• Add the second stage to the first. Bias the outputs op, om, with an ideal dc voltage source such that all
transistors are in saturation. Verify the bias currents and voltages. Some residual current could be flowing
through the dc voltage source, but should be small.
• Construct CMFB2 (without 𝐶𝑐𝑚 and 𝐶𝑐𝑚𝑥 ), connect it to the first stage outputs instead of the ideal voltage
source in the above step. Verify the bias currents and voltages. The output common-mode voltage should
be 𝑉𝑑𝑑 /2.
• Adjust 𝐶𝑐𝑚 for 5% overshoot with a common mode step as described above. Add 𝐶𝑐𝑚𝑥 if you are unable
to stabilize the loop. Use the minimum value required.
• Realize the inverting amplifier and run the required simulations.

(The transistor sizes in the first and second stages should be same as in the previous assignment. Others can be
found from the current densities mentioned in the above instructions.)

• 𝑉𝑑𝑑 = 1.8 V, 𝑉𝑠𝑠 = 0 V, 𝑉𝑐𝑚 = 0.9 V.

• Simulation temperature: 100◦ C.
• Odd roll numbers: pMOS input pair; Even roll numbers: nMOS input pair.
• 𝐿 = 0.3 µm for all transistors.
• Use3 𝑉DSAT = 0.15 V for the first stage transistors except 𝑀0 . Use 𝑉DSAT = 0.25 V for the second stage
transistors, 𝑀0 , and 𝑀00 .
• Choosing the 𝑉DSAT value fixes the 𝑔𝑚 and 𝐼 𝐷 per 1 µm/0.3 µm finger. Choose the multiplier 𝑚 for each
transistor to set its 𝑔𝑚 or 𝐼 𝐷 as required.
3Choose the current density that sets the 𝑉DSAT to within 10 mV of the specified values. Do not aim for microvolt precision.
EE5320: Analog Integrated Circuit Design; Nagendra Krishnapura (nagendra@ee.iitm.ac.in) 3

• For 𝑀00 , use 𝑚 = 2 and choose 𝐼00 (integer µA) that sets the desired bias in the first and the second stages.
• All nMOS bulk terminals should be connected to 𝑉𝑠𝑠 . All pMOS bulk terminals should be connected to
𝑉𝑑𝑑 .
• Adjust 𝑉𝐵56 such that the 𝑉𝐷𝑆 of 𝑀1,2 is 50 mV above their 𝑉DSAT . Similarly, Adjust 𝑉𝐵78 such that the
𝑉𝐷𝑆 of 𝑀3,4 is 50 mV above their 𝑉DSAT . i.e., 𝑀1−4 must be in saturation region with 50 mV margin.

Present the following results.

Tables: (Gain, transfer function etc. below refer to the differential quantities unless otherwise mentioned.)

(a) Specification table with your specific values and all the component values.
(b) Table showing simulation results: closed loop dc gain, closed loop 3-dB bandwidth, unity loop gain
frequency, phase margin, rms output noise (integrated from 10 kHz to 100 MHz), fraction of noise vari-
ance (integrated from 10 kHz to 100 MHz) contributed by 𝑅𝑖 , 𝑅 𝑓 , first stage, second stage, and 𝑅 𝐿 , Opamp
open loop dc gain, positive and negative slew rates, positive and negative swing limits, HD3 , supply voltage,
current consumption. Unity loop gain frequency and phase margin of the second stage CMFB loop. To
find the opamp slew rates apply a large input step (from 𝑉𝑐𝑚 to 𝑉𝑐𝑚 ± 𝑉step ) such that the first stage current
is completely switched to one side.

To find HD3 , apply a sinusoidal input that results in a 1 V peak-peak output at a frequency that is 1/4th the
bandwidth. Report HD3 , the ratio of the third harmonic to the fundamental (in dB).
Plots:

(a) Differential loop gain magnitude (dB) and phase (degrees). The unity loop gain frequency and phase margin
must be marked. Break the loop as shown in Fig. 8.1(d) to simulate the loop gain. Use large 𝐿, 𝐶, e.g.,
𝐿 = 106 H, 𝐶 = 1 F. The frequency range should be from ∼ 0.1× dominant pole to where the loop gain is
∼ −20 dB.
(b) Closed loop transfer function magnitude on a log-y scale showing the dc gain and the 3-dB bandwidth.
(c) Closed loop dc transfer curve. Vary 𝑉𝑖 from −1 V to 1 V
(d) Small-signal step response: Output should step from 0 V to 0.1 V and back. Use a short rise time ∼ 100 ps.
(e) Large-signal step response: Output should step from 0 V to 1 V and back. Use a short rise time ∼ 100 ps.
Get the slew rate from this. Check to see that the current is completely switched to one side in the first
stage. Find the rising and falling slew rate from op and om.
(f) Output noise PSD and the input referred noise PSD of the closed loop amplifier from 10 kHz to 100 MHz.
(g) Input referred noise PSD of the opamp from 10 kHz to 100 MHz.
(h) Second stage CMFB loop gain. You can “break” the loop at the positive input of 𝐴𝑐𝑚2 . The unity loop
gain frequency and phase margin must be marked.

(Not for submission):

• Remove the cascodes from the first stage, run the simulations and find out the differences
• Connect 𝐶𝑐 to the drain of 𝑀2 or 𝑀4 instead of the drains of 𝑀6,8 . See if there is a difference in phase
margin. You can also try connecting 𝐶𝑐 /2 each to the drains of 𝑀2 and 𝑀4 .
4 EE5320: Analog Integrated Circuit Design; Nagendra Krishnapura (nagendra@ee.iitm.ac.in)

• What is pole frequency of the feedback network. This is due to the resistive divider with 𝑅 𝑓 and 𝑅𝑖 in
combination with the input capacitance of the opamp. You can take 𝐶𝑔𝑠 /2 to be the differential input
capacitance. Does it matter in this design? If so, how would you mitigate its effect?