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Module 10:
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Analysis and Debug

Lab 10-1 Using Global Timing Debug Interface to Debug Timing

Results

Objective: To run the timing analysis and fix a couple of timing violations.

Tempus Timing Signoff Solution is a timing signoff tool used to verify that the design meets your
timing goals. In this lab, you will first rerun the previous session of Place & Route and continue it
with running Tempus timing analysis inside of Innovus .

This lab uses the following software:

INNOVUS221 (22.10-p001_1)

SSV221 (22.10-p001_1)

You will then run Tempus in the Timing Signoff mode.

You can start the Tempus tool using the command tempus -stylus.

You can start the Tempus TSO software using the command tempus -stylus -eco.

The following files are from the physical design lab and will serve as inputs to Tempus:

counter_netlist.v Gate-level netlist output after synthesis.

counter_sdc.sdc Constraint file generated during synthesis.

counter.view The implementation view definitions listed in this MMMC file.

gsclib045_tech.lef, gsclib045_macro.lef LEF files used in physical design.

slow_vdd1v0_basicCells.lib and fast_vdd1v0_basicCells.lib Timing libraries.

There are a few additional files in the directory that are not listed above.

Running Timing Analysis and Debugging in the Innovus Session

Innovus is a cockpit for a lot of implementation and verification tools front-to-back.

In this section, you will be running a Tempus-style timing analysis inside of Innovus.

1. Let us rerun the previous session of Place & Route inside the STA directory instead of
using a saved session:
LINUX# cd STA
LINUX# innovus -stylus files runPnR.tcl

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Timing Analysis and Debug

At the end of this session, the design is routed and timing analyzed.
A screenshot of runPnR.tcl is shown here.

2. Set the timing analysis mode by running the following commands:

set_db timing_analysis_type ocv

3. Run setup-and-hold timing analysis by running the following commands:

time_design post_route

Are there any setup violations?

Answer: _________________

As you can see in the following timing summary,

violating paths in setup mode.

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Analysis and Debug

Let's run the hold check using the command:

time_design post_route -hold

Note: There are a lot of hold violations in the design. Let us see how to fix all of
them in Tempus.

4. If the graphical interface is not open, start it using the following command:
gui_show

5. Run timing analysis using the Timing Debug Timing menu.

a. Select hold in the Check Type field.

b. Click OK.

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Timing Analysis and Debug

The Timing Debug window opens.

c. Right-click on path #1 in the Path List and select Show Timing Path Analyzer.

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Analysis and Debug

You will see the Timing Path Analyzer window.

Note: From the Timing Path Analyzer, if you want to debug violating paths, you
can right-click on any of the signals, and you will get additional options
like interactive ECO, etc.

6. Save the design including the SPEF, DEF, and the libraries, by entering:
write_db -rc_extract -def postRoute

7. Keep this session open if you would like for debugging purposes. You can close it
later.

Running an Independent Timing Analysis in Tempus

1. Start Tempus independently:

tempus -stylus

2. Load the Innovus database into Tempus using the following command:
read_db physical_data postRoute

This loads the entire design along with the physical layout.
Open the Layout tab (click the sign to see other available tabs) to confirm that the
same layout from Innovus is also shown here in Tempus.

Once the design is loaded successfully, then generate the following reports.

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Timing Analysis and Debug

3. Check the analysis coverage using the following command:

report_analysis_coverage

4. View the list of all constraint violations using the following command:
report_constraint -all_violators

5. Report the worst slack time for setup and hold, respectively, using the following
commands:
report_timing late
report_timing early

6. Generate timing histograms using the following commands:

report_timing early max_paths 100 output_format gtd > early.mtarpt
read_timing_debug_report early.mtarpt

7. Open the Analysis tab (click the sign to see other available tabs).

After the timing analysis is done, you can see the histogram for the hold analysis.

a. Browse through the Path List with Startpoint Pin as rst, right-click on the path,
and select Show Timing Path Analyzer.

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Analysis and Debug

You will see the Timing Path Analyzer window.

8. In the Timing Path Analyzer window, select the rst pin and right-click and select
Interactive ECO/WhatIf Add Repeater.

The Interactive ECO window opens, which will allow you to add repeaters.

9. In the Interactive ECO window:

a. Click Get Selected to populate the net information, or just enter rst.

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Timing Analysis and Debug

b. In the New Cell field, select BUFX2.

c. Choose early from the Evaluation Type.

d. Click Eval All to choose which buffer is suitable for the path that adds more
delay and reduces the hold slack.

Notice the list of buffer suggestions appears at the Tempus terminal.

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Analysis and Debug

From the evaluation list, we can observe that Slack can be reduced to a maximum extent
to -0.0956 with the cell BUFX2.
Note: Add only BUFX* cells to fix the timing violation, do not add any CLKBUFX*
cells in the design.

e. Now, select the BUFX2 cell in the Interactive ECO.

f. Click Eval Only.

g. View the messages by the <tempus> prompt.

Note: Ensure that there is a change in the Slack (it is negative). The result should
be an improvement in Slack -0.0956 when you Apply the repeater
addition.

10. Click Apply.

The slack improvement is clearly observable. Let us see now analyze the results using
the Timing Path Analyzer window.

Note: Ignore the ERROR: (IMPSP-365) if any.

11. Rerun the timing report using the below icon from the Analysis window and compare
the WNS.

a. Click the load icon from the Report Files(s) field

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Timing Analysis and Debug

The Display/Generate Timing Report window appears.

b. Choose the Timing Report File early.mtarpt.

c. Select hold from Check Type.

d. Click OK.

12. Notice the improvement in timing using the below screenshots.

Notice the improvement in the WNS in the Analysis window.

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Timing
ing Analysis and Debug

Notice the improvement in Hold Slack for the rst pin in the Timinig Path Analyzer
window.

13. As we can see, the Slack is still negative (-0.096), and we need to add a buffer on the
same net of the pin rst, until we get the Zero/Positive Slack for the pin rst.

14. So, In the Analysis window, select the rst pin and right-click again on the path, and
select Show Timing Path Analyzer.

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Timing Analysis and Debug

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Analysis and Debug

15. Repeat Steps 8, 9, and 10 again by selecting the first path of the rst pin and choosing
Add Repeater from the Timing Path Analyzer window.

Click Eval all and choose the buffer cell (BUFX*).

Observe the BUFX20 cell is the best delay cell to add to the path to reduce the Hold
Timing Slack to -0.0705.
Note: If you have an area constraint or less area in your design, then choose a cell
that adds moderate delay and less area according to the design requirement.

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Timing Analysis and Debug

16. After adding the BUFX20 cell, rerun the Timing Debug report as shown in Step 11.

Note: As we can see, the Slack is still negative (-0.070), and we need to add buffers
on the same net of the pin rst, until we get the Zero/Positive Slack for the pin
rst.

17. Repeat Steps 7, 8, 9 and 10 again by selecting the first path of the rst pin from the
Analysis window and choosing Add Repeater from the Timing Path Analyzer
window.

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Analysis and Debug

Click Eval all and choose the buffer cell (BUFX*).

Note: Observe that BUFX20 cell is the best delay cell to add on the path to reduce
the timing slack but has the highest area penalty. So, ensure that if you have
the area constraint or less area is present in your design, then go for the cell,
which adds moderate delay with a lesser area overhead.

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Timing Analysis and Debug

So, choose the BUFX2 cell in this scenario because the area of BUFX2 is less than the
BUFX20 cell, and also Timing-Slack reduction is not much different between those two
cells.

18. After adding the BUFX2 cell, rerun the Timing Debug report and analyze the Hold
Slack as shown in Step 11

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Analysis and Debug

19. Likewise, add more buffers on the same path, analyze the Hold slack for the pin rst,
and notice the reduction in WNS.

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Timing Analysis and Debug

20. Now, check the analysis coverage using the following command to ensure the Setup
Slack is not affected by the changes made in the Hold Violated Paths.
report_analysis_coverage

21. Now. Try a similar exercise by buffering the SE pin to fix the Hold Slack Violations
and compare the results.
Earlier:

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Analysis and Debug

Later:

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Timing Analysis and Debug

22. Similarly, fix the remaining timing violations. As a result, it will show zero failing
paths in the final timing report, as shown in the figure below.

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Analysis and Debug
Analysis

Summary

1. You can run timing analysis from within Innovus. You can also evaluate and create
timing-fixing ECOs interactively from within Tempus.

2. You can run independent timing analysis from within Tempus. Independent analysis
frees up Innovus to do other things.

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