SONY CXD2545Q CD Digital Signal Processor with Built-in Digital Serv Description ‘The CXD2545Q is a digital signal processor IC wit ‘a buil-in digital servo for CD players. This IC is broadly divided into a digital signal processor bloc and a digital servo block, and these blocks possess ‘the following functions. Digital Signal Processor Block + Wide frame jittor margin (228 frames) due to a builtin 32K RAM ‘The bit clock, which strobes the EFM signal, is {generated by the digital PLL. + Enhanced EFM frame sync signal protection * Refined super strategy-based powerful correction C1: double correction, C2: quadruple correction * Quadruple-speed, double-speed and variable pitch yyback error play + Noise reduction during track jumps. * Auto zero-cross mute *Subcode demodulation and Sub Q data error detection il spindle servo (with oversampling fiter) ‘+ Asymmetry compensation circuit * Error correction monitor signal, ete. output from a. new CPU interface + Servo auto sequencer search performs track jumps with high ‘accuracy Digital level meter, peak meter * Bilingual compatible Digital Servo Block ‘Microcomputer software-based control + Servo error signal, offset cancel function * Servo loop, auto gain control function + E:F balance, focus bias adjustment function flexible servo igtal signals produced during playback processed with a single chip * Allows highly integrated chip mounting by incorporating the RAM and digital servo on-chip ‘Absolute Maximum Ratings * Supply voltage Voo Input voltage Vs 03070 Vv 0310470 Vv (Vss-0.3V to Voo +0.3V) + Output voltage Vo 0310470 V + Storage temperature Tstg 4000125 °C + Supply voltage difference: Ves~AVss -0:910403 Vv Voo-AVoo 0310403 V 100 pin GFP (Plastic) Recommended Operating Conditions ‘Supply voltage Voo* 4.50105.50 V * Operating temperature Topr -20t0475 °C. *The Voo (min.) for the CXD2545Q varies according to the playback speed and builtin VCO selection. The Voo (min. is 4.50V when high-speed. VCO and quadruple-speed playback are selected Watiable pitch off. The Voo (min) for the ‘CXD2545Q under various conditions are as shown in the following table. Playback Voo (min) IV] speed [VCO high speed [VCO normal speed xa 450 = xa 4.00 = x2 340 4.00 x 340 340 xt 340 340 Dashes indicate that there is no assurance of the processor operating. Al values are for variable pte oft * When the internal operation of the LSI is set to normalspeed playback and the operating clock of the signal processor is doubled, double-speed playback results. 2 When the intemal operation of the LS! is set to double-speed mode and the crystal oscilating frequency is halved in low power consumption mode, normal-speed playback results WO Capacitance “Input capacitance =» G12 (max) pF *Outputcapacitance Co 12 (max) pF When at high impedance Note) Measurement conditions Voo = V1= OV f= 1MHZ Sony reserves the right fo change products and specteations without por noi, This femation does not convey any eens by any impcaton or aherwis under ary patonts or other gt. Appleton creuts shown, any, ae piel examples iusvating th operation ofthe devoes. Sony cannot assume responsibly for any problems arising oul of the use ofthese ores = Ess 194A5K-PS WM 8382363 0015318 256 mmSONY exoesisa, Block Diagram ‘SeRMUPARALLEL Processor c anon connecron| owRatNEE coenennton2 se Sa Prose Back SRO Ow Pin GENERATOR FoCusSeAVO ee ‘TaaganG Eun | ‘Rack senvo—-—_} «Taga an s:e0 SeAVvO ceieaien TO = WM 8382383 0025319 194 mm IrSONY coxoestsa Pin Configuration Pin Description Fe Symes] vo Deetoton 7 [BRON] ©” Sled ive sup 2 [SROR| 0 | Sed ave ouput 3 SFON [| Sle ave oa 77 [Teor | 0” [ Tracking dive uot 3 [RON | 0 | Tekin eve ouput 3 [TADA | 0 Tracking ve pa 7 [TON | 0 | Tracking ave ouput 2 [FOR | 0 Foes dive opt 2 [FRON] 0 | Foes ave ouput 70” [FROA | 0” | Fos ave oupa iL FFON | 0” Foaus dive oupu *2[Voo0| © | Analog ERA eSaon crt oui #8 [COT |__| Analog ERMPLLosclton ceutinpu hoat= BSBA va [FEST [1 Testi Nomatr NO i [vis [= Bia ono a W@™@ 6362383 0015320 90b mm aSONY coxo2sssa. Rit |symbot} vo Description 16 | TES2 | 1 | Testpin, Normally GND. W7_[ TESS [|_| Testpin. Normally GND. 18 [PDO_| | Analog EFM PLL charge pump output 19 | VPGO | © | Variable poh PLL charge pump output 20__[ VCKT_| 1 | Variable plch clock input rom the external VCO. feenter = 16 SG4aNz 21_[AVoo_| — | Analog power supply. 22_[IGEN | 1 _| Reference resistance connection for dgial sew operational ampilierGarent source | 23_[ Aves | — | Analog GND. 24 | ADIO | © | AD converter input monitor. 25_[ RFC _| |_| RFDG Input low-pass fiter capacitor connection, 26_[ RFOC |_| | RF signal input. Input range: 2.15 to 5.0V (when Voo = AVeo = 5 0V) 27_ [TE [1 | Tracking error signal input. Input range: 25 21.0V (when Voo = AVoo = 5 OV). 28 [SE__| |_| Sled-eor signal input Input range: 2.5 =1.0V (when Voo = AVoo = 8.0V)- 29_[FE__|_1_| Focus enor signal input Input range: 2.5 =1.OV (when Voo = AVoo 30 [ve | 1 | Center votage input 31_[ FILO_| 0 | Master PLL fiter output 32_[FIL_| |_| Master PLL er input 33_[POO_| 0 | Master PLL charge pump output 34 [ CLTV |__| Master PLL VCO control voltage input 35. [Aves | — | Analog GND. 36 [ RFAG | 1 | EFWeignal input 37_[BIAS_|_1_| Constant currentinput of asymmetry Grout 38_[ ASY_|_1 | Comparator voltage input of asymmetry creut '39_[ ASYO | 0 _| EFM ful-swing output (ow = Ves, high = Voo. 40__[Avoo | — | Analog power supply. 4_| Vo _| — | Diatal power suppy. 42_[ ASVE |__| Asyrnmety creuit on/off (ow = of high = on. 43_| PSSL | 1_| Audio data ouput mode switching input Low: Serial ouput igh parallel Supa 44 [WOOK] 0 | Dininterace and word clock for 48-bit slot. f= OF 45 [LRGK | 0 | DiAinterace and LA clock for 48-0 slot. = Fs 46 [DATS | 0 | DAT6 output when PSSL = 1, 48-bit slot serial data when PSEL =O. 47 [DAIS | 0 | DATS output when PSSL =, 48‘il slot bit lock when PSSL =O, 4% [Data | 0 | DAT4 output when PSSL = 1, 64-bit aot serial data when PSSL =. 4 [DAIS | 0 | DATS autput when PSS = 1, 64-bit slot Bit clock when PSSL = 6, 30 | DAI2 | 0 | DAT2 output when PSSL = 1. 64bilalot LR clock when PSSI 51_[ ATT | 0 | DATT output when PSSL = 1. GTOP ouiput when PSSL = 0. 52 [DATO | 0 | DATO output when PSSL = 1, XUGF output when PSSL= 0, M@™ 8382383 0015321 842 mmSONY ‘exnesssa Fe Jsymba] vo Desrpten BAGS | 0” BREN cpa when PEL = XPLOK apt when PSSL=O 4 [oa0e | ©” [BA08 cut won PSSL=T. FS ouburwion PSSL=O 5 [Bn07 | 0” | Bao? ea ven PESL=".RFOK oapu when PSBL = 2 [bn08 | 0” |0f08 ep hon PSL =". CEPO aap when PESL =O. 7 [BROS |_O” | BA0S cut whon PSL =". AGF enpat when PS [noe | 0” | BA0% eat won PSL =. WNT ouput when FSSL =O a Baa | ©” | BA08 cpt whon PSC =". NT aaput when PSBL =O 89” [Brae | 0” OAGE ei ven PSSL= WNT aapul when PSSL=0 Bi_[Bn01 | 0” BABY aut when PESL = - WNT opal when PESL=0 a2 [RTA [| Gta cele itp put 6 S4aeeo 93 —a06N [TAO | © | Gta eciaon set onpu ve era | 1 | Sealetcornpt Low won ie cys To STAIR gh wn re Syms 33.8688MHz (during normal-speed playback). [Ws | — | Ba eno ae [FETT | 1 | Da sono tio ioc dean NO we |raor © | iene Sir aaa Ps an Ta ST « [even | © | SSSR a Tn caren dam aS ENG 72 [NEE|T”[ Dita Out nt ent ow a Wah =) 71 [BOUT [0 Bear ow ouput 72 [ura | o | Bavbec ae enphass mode cup Gupus ahigh Sal wn a pabaa se hat emphase,ardalow gna nfon rts ergs} WER | 0 WFEK oun ve [econ 0 | Siig re om Supa ah pawn eis ee 75 | 3850 | | Sib Po Woonal samt 78 [EXOK | | 5850 readout socks 7 [S260 | 0” Bub GEO ouput POM pak anion daa TER Bap 7a | 800K | 1 | $0850 readout cook roa 7 [ MOTE [1 [ me vcig pin rm) 20 SENS [0 SENS opti SPU a1 [xRST | 1 | Sito est Goat when ow @ TRE [1 [ Used ack ups pt Vs ova who ata) aa [ S0uk | 1 | SENS sora data eadoutcok aa BFSW| 1 DFCT swing pin ink OFCT somone roa ah 3 [ATER [1 Anshook in WH 8382383 0015322 739 amSONY ‘oxo2sis0 Ro. [Symbol] vo Description 86 [DATA | 1 | Serial data input from CPU. 87 | XLAT | |_| Latch input rom CPU. @8 | CLOK | 1 | Serial data transfer clock input from CPU, 89 | CouT | O | Track count signal input. 90 |Voo | — | Digital power supply. 91 [MIRR | 0 | Mirror signal output. ‘92 [FCT | © | Defect signal output 93 [FOK | 0 | Focus OK output. ‘94 [FSW | | Spindle motor output filter switching output ‘95 [MON | O | Spindle motor on/off control output. 96 | MDP | © | Spindle motor servo control. 97 [MDS | © | Spindie motor serve control 98 | Lock | © | GFSIs sampled at 460H2; when GFS is high, this pin outputs a high signal. I GFS is low eight consecutive samples, this pin outputs low. 99 [SSTP |__| Disc innermost track detective signal pin 100 | SFOR | © | Sied drive output, Notes) + The 64-bit slot is an LSB first, two's complement output. The 48-bit slot is an MSB first, two's ‘complement output. ‘+ GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) ‘+ XUGF is the negative pulse for the frame sync obtained from the EFM signal. Itis the signal before sync protection. = XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the faling edge and the EFM signal transition point coincide. + The GFS signal goes high when the frame sync and the insertion protection timing match, ‘ RFCK is derived from the crystal accuracy, and has a cycle of 136ps. + C2PO represents the data error status. ‘+ XRAOF is generated when the 32K RAM exceeds the 428 F jitter margin. WM 5382383 0015323 b15 mmSONY cxoeseso Electrical Characteristics 1. DC Characteristics (Woo -2010 475°C) Tem Conditions| Min. [Typ.] Max. | Unit [ppoate ped reavotage cn [aren vetage [Ve 0.7V00 vi, Lowlevelinputvotiage | Vu (1) (0.3Vb0] V rouvotag [THR EEMHN RADE [Vy | O8NED vt Lowlevelinputvoliage | Vu (@) (02V00] V input votage (@)| Input votage Vin(3) [Analog input | Ves Vo |v [an (Outputvottage [High evel oxiputvotage | Von(t) [iow =—amA _|Voo-08 vo [Vv | ) Lowlevel output votiage | Vet) oa fv [Outputvotage | High evel output votage | Vow(2) vo [vy 2) Low level output voltage | Vou(2) o4 [Vv [Cupatvotage @)| Low level output wottage | Vox (3) oa [vie [Ouputvotage | High level output volage | Vou(4) veo [vl (4) Low level output voltage | Vox (4) o4 | Vv Input leak current (1) way wossv | 10 70 [pA Input leak current (2) W@ [Viatst0s6v| 20 20 [wa |e Input leak current (8) u@) |Visdtwsov | 40 600 | wa | Upsets ho |vo=owssv | 6 5 | us| +o ‘Applicable pins " XTSL, DATA, XLAT, MD2, PSSL, TEST, TES2, TESS, DFSW, DIRC, SSTP, ATSK * CLOK, XRST, EXCK, SQCK, MUTE, VCKI, ASYE, FSTI, SCLK *3 CLTV, FILI, RFAC, ASYI, RFDC, TE, SE, FE, VC ** MDP, PDO, PCO, VPCO “5 ASYO, DOUT, FSTO, FSOF, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, SENS, MDS, DAO! to DA16, LACK, WFCK, FOK, COUT, MIRR, DFCT, FON, FROR, FRON, FFOR, TFON, TROR, ‘TRON, TFDR, SFON, SRDR, SRON, SFOR 5 FSW 7 FILO *8 TE, SE,FE,VC "* FDC “19 SENS, MDS, MDP, FSW, PDO, PCO, VPCO “1 RFC. @™@ 5362383 0035324 55) mm waSONY oxoes4sa 2. AC Characteristics (1) XTAI pin, VCOI pin (a) When using self-excited oscillation (Topr = ~20 to +75°C, Voo = AVoo = 6.0V 10%) Rem | Symbol | Min. | Typ. | Max] Unit Oscillation frequency fax 7 34 | MHz (b) When inputting pulses to XTAI and VCO! (Topr = -20 10 +75°C, Voo = AVoo = 5.0V 210%) tem [Symbol Min. | Typ. | Max | Unit igh level pose ia tmx | 19 500 | ns Low level pulse Me tmx | 13 500 Pusecyctle | tox 6 1000 | ns Inputhightevel | Vix |Voo-1.0 v Inputiow tevet | vax os | v Rise ime, 1s fall time oe w (¢) When inputting sine waves to the XTAI and VCO! pins via a capacitor (Topr = ~20 to +75°C, Voo = AVoo = 5.0V 210%) Tem ‘Symbol Min. | Typ. | Max. | Unit Input amplitude | vi 2.0 \Voo + 0.3| Vp-p WH 6382383 0015325 495 mmSONY ‘oxoasss0, (2) CLOK, DATA, XLAT, SQCK and EXCK pins (Vo0 = AVoo = 5.0V 210%, Vss = AVss = OV, Topr = -20 to +75°C) Ttem Symbol] Win | Typ] Max | Unt Clock frequency tee 065 _| Miz Clock pulse width twee | 750 15 ‘Setup time tu 300 ns Hold time & 300 nS Delay time Cy 300 ns Latch pulse width te 750 ns EXCK SOCK frequency _[ fr 06s [wiz EXCKSQGK pulse width | twr 750 m8 Mo» Soros ace! owe ara xa > rc exck sack =| l J ee or ca @™@ 5382383 OO1S326 324 mmSONY oxp2ssa (6) SCLK in ur meee sexx . Tax a) (ws XX XCF fem ‘Symbol | Min. Typ. Max. | Unit ‘SCLK frequency fscux 1 MHz ‘SCLK pulse width ‘tspw 500 ns aay tine ms [18 = (4) COUT, MIRR and DFCT pins ‘Operating frequency (Voo = AVo0 = 5 0V 10%, Vas = AVss = OV, Topr =-2010 475°C), Tem ‘Symbol | Min. | Typ._|_Max_| Unit | Conditions ‘COUT maximum operating frequency | feour | 40 we | MIRA maximum operating frequency | fuan | 40 whe | DFCT maximum operating frequency | forom | 5 iz [9 ** When using a high-speed traverse TZC. When the RF signal continuously satisfies the following conditions during the above traverse. +A=06101.9V + BL = less than 25% A+B *3 During complete RF signal omission. ‘When settings related to DFCT signal generation are Typ. -10- MH 8382363 0015327 260 mmSONY ‘oxpesssa, Contents [1] CPU Interface §1-1. CPU Interface Timing «nen §1-2. CPU Interface Command Table... §1-3. CPU Command Presets §1-4. Description of SENS Signals SRBS [2] Description of CD Signal Processing-System Commands and Functions {§2-1. Description of Commands and Data Sets. §2-2. Subcode interface. §2-3. Digital PLL... §2-4. EFM Frame Sync Protecton.. §25, Error Correction. se §2-6. DA Interface... §27. Digital Out §2-8. Servo Auto Sequencer. §2-9. Digital CLV... : §2-10. Asymmetry Compensation. §2-11. Playback Speed. eepeeessars [5] Description of Servo Signal Processing-System Functions and Commands $20. General Designo ne Ser Signa Processing ye... §3-1. Servo Master Clock (MCK). §82. AVRG Measurement and Compensation §93. _E:F Balance Adjustment Function §9-4. FOS Bias Adjustment Function. §85. AGONTL Function . §3-6, FCS Servo and FCS Search, §37. RK and SLD Servo Control... §38. MIRA and DFCT Signal Generation. §39. DFCT Countermeasure Circut. §9-10._AntShock Circuit. $9411. Brake Circuit... §9412. COUT Signal... §3-13. Serial Readout Circuit... §8-14. Writing the Cootfcient RAM... $3415. PWM Outp... . §2416._DIRC Input Fi §3417. Servo Status Changes Produced by the LOCK Signal §3-48. Description of Commands and Data Sots. §3-19. List of Servo Fite Coefficients. §3-20. FILTER Composition §921. TRACKING and FOCUS Frequency Response [4] Application Circuit §4-1. Application Circut 104 Explanation of abbreviations AVRG: Average AGCNTL: Automatic gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect att MH 6362363 0015326 177SONY coxasasa [1] CPU Interface §1-1. CPU Interface Timing * CPU interface ‘This interface uses DATA, CLOK and XLAT to set the modes. ‘The interface timing chart is shown below. 750n8 o¢ more the “UWL TUL eg 78m or more nur Registers waa + The internal registers are initialized by a reset when XRST = 0. §1-2. CPU Interface Command Table Total bit length for each register Register | _ Totalbit length 0102 abit 3 to 24bit 4106 16bit 7 2obit BIOA bit B 2obit | EC tee eee OO -12- mm 8382363 0015329 033 mm‘exozs4s0 SONY 70 00 — ziosas wa eNNIVD ONDOWEL FaoaTas YaLts nine ONDOWEL en NIVO ONDIOWELL “WHRaON Ivo ONDIOWiL suo ava No aivea 340.0086 UNY No¥00HS UN ouLN0o $000 lopinovill ‘aN 3OWLION Havas sno04 Natoa 30¥4710" HOWYaS SNOOS 10 30¥L10A wouvas sno04 "430 ONS S1!003 -4n0 70) ‘440 OnMaS SOS ‘wtoa vo snaod) No onuas soos Cynon ve snood) NO ORAS S004 OULNoD 000 | TuLNOS a za[eia|ra|sia 310 110 [10 [ora ozaieza preuwog zen 8a) oto ~13- WM 6362383 0015330 855 mmcoxasasa SONY vw yuo — (eapnoaeas =) TBAT ONGTS (Goenoneg +69) BATON GTS clo caries) sEATDONGTS oo reoq (oneNomea F=) “EAT OMOTS o}o 1100 403138) aia 6a jocanieza) = pueuwog eons aromas stan AON aS GEVMEO Noonwasans suo Onwasa716 Janne yoru asuara anne xove aus NOOnS ONDIOML, {HO ONS ONDIOMEL o100 300” lonmiove | za [ea] na] sa -14- M@™ 6382383 0015331 791 acoxo2s4sa. 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SONY ‘re 00 — -|-|]-]- =[-]-]o}ofo}o]o]o} o | o Jomo} mo | ano | eno soon mo | 3 ‘smo joni] -|-]-]- -|-]-]e}ofofofo]}o| o | o |S} a | a fmm) rors | momo] a Bins lonr00| | osavt| isaw|oaaw | tae -|-]-|- -J|-|-J]ojoleofofofo 0 [OSQM| ssa) caw} '3ONT 944 | wxosseo | 9 e8 reo | usp | ue | uwo coe fons sno -|-|-]- z |r |e | a | ze | v0 | oat | ose | zis | seo | ar0z | oer | cove |rae'orfeoree] s 108 seweu!| 9 wmog yan | on aso ory -j-|{-|- -—]-]=]afo]}o]}o} o | o Jzous}soua| sy | erm |i] oh | ors 2 v —-|-T-|- -|-l- ‘ans | Nivii [HONO|zONO|zzCNO!CNO] , 54 , | vowDAd eo fe [2 |e | © [974 } ron | ona | Tia [ossy|edsa|aroa| +9? vworpung | & 735 [sani] oer | nou -|-|-]- = ]-]-] 0] 0] oJ o | o Jic0s|susw} 235 jrasm|zorm svt | MOH) coos 8 -|-|- - z |v [a | a | ze | v0 | oat | osz | ais | veo | aro | ooo | cove lrocrtoorze| sero ‘ -|-|-]- =]=] =] of o |] o | o | os} am | eax | ean | ocs | tas | cas | eas | 0110 ° -|-|-|- -]-=]-]e}ofofol}ofo}o} o jou | mu | cu | eu] toro s -|-|-]- =] =] =} 6 | © | 0 Jrssi} oun | say | zum | eum | osy | ssv | zsv | esv | oo10 , oa | ta | za | ca sa | sa | zo | 0 | 0 | oa | na | aia] era | na | sia | aia | 1a | aia | era [ocamezal pueunrog fase $0 rea erro zea rea 505009 (xa 04 xp) a1gey puewwi0g -21~ WM 6362383 0015338 O4b mmoxo2s4s0, SONY ‘e0 1u00 — ‘Douwves 01 xx00FeS) 7 =e ‘viva WVet ge Soren seid waEYECD eu 805, ofofofs]o] soo ea [oa] za [ea] ra] so [oo [ za] ea ca [a[nalealsa|ra]sio|nalaalealsajocaceza| e zea reed fd 2 eeey sso hreeayionenoseas 1] _—]—]-|-]-]-]-|-]-]-|-|-|-|— _ BART HONOTS o}ofolo| tr00 0a | 0a | 2a | 2a | v0 | sa | 90 | za | 00 | 6a fora] tia|z1a|era| na] sia] ora 210 | #10] 610 [ocasree0 puruswog parsfou| Fama ve ene. zea ree ss00py woomasans|—]—]-]-|-]|-]-]-|-]-|-]-|-]-|- — 300” 140 ONH3S ONDOVEL oe Tee | eee fonwiomn | @ tomaseants{—|_]|—|—|-|—-|-|-]-|-]|-[-|-[-|- — OuLNOD A. NIVO ONDIOVEL, HL te fe] £9? ono | TSS SSeS SSS2S4SSBee 7 e000 | 7uNCO| 5 “430 onteas sn904 oyeyeye ‘snooa 00 | 1 | za | ea | 20 | sa | 00 | za | 00 | 6a [ora] tia] za fea] ria] sta | 91a | 210 | 10 [610 [oza ezal pueunsog |ssseu ‘sua rere ema zero. vera Sey (xpe 01 X08) e192 yese1g puewwi0D ‘sias0id PUBUIWIOD dd “E-18 ~22- mm 6362383 0015339 Té2 mmcoxo2sis SONY co [a [20 [ea [ra [oo [eo [a [oa [ea [ova |vna|aia eva [ova [aia ava] a [wa [eva ova een vee 00 zg Ta = oz -]-]-]-|_]-J-]- |-]-T-]-|-]-]-]- 100 4978 10040) 921. ofoytlet ca [va [ea [sa [va [oa [ea [ ‘exo2s4sa ‘ADDRESS| DATA CONTENTS 00) £0 | SLED INPUT GAIN Ko1 81 | SLEDLOWBOOST FILTER AH Ko2 23 | SLED LOW BOOST FILTER AL Koa, 7F _ | SLED LOW BOOST FILTER B-H Ko4 6A | SLED LOW BOOST FILTER B-L KOS, 10 | SLED OUTPUT GAIN, 06 14 | FOCUS INPUT GAIN Ko7 30 | SLED AUTO GAIN Kos 7F | FOCUS HIGH CUTFILTERA Koo 46 | FOCUS HIGH CUT FILTER B KOA @1 | FOCUS LOW BOOST FILTER AH KOB 1G | FOCUS LOW BOOST FILTER A-L Koc 7F | FOCUS LOW BOOST FILTER BH Koo 58 | FOCUS LOW BOOST FILTER B-L KOE 82 | FOCUS PHASE COMPENSATE FILTER A KOF 7F _ | FOCUS DEFECT HOLD GAIN Ki0 4 | FOCUS PHASE COMPENSATE FILTER B Ki 32 | FOCUS OUTPUT GAIN Ki2 20 | ANTI SHOCK INPUT GAIN K13, 80 | FOCUS AUTO GAIN Kia 80 | HPTZC/ Auto Gain HIGH PASS FILTER A K15, 77 | HPTZC / Auto Gain HIGH PASS FILTER B K16 80 | ANTI SHOCK HIGH PASS FILTER A KI7, 77 | HPTZC/ Auto Gain LOW PASS FILTER B KB, 00 | Fix* Kia F1___ | TRACKING INPUT GAIN KIA 7F | TRACKING HIGH CUT FILTER A KIB 3B | TRACKING HIGH CUT FILTER B Kic 81 | TRACKING LOW BOOST FILTER AH KID. 44 _ | TRACKING LOW BOOST FILTER AL. KIE 7F _ | TRACKING LOW BOOST FILTER B-+H KF SE _| TRACKING LOW BOOST FILTER BL K20 82 | TRACKING PHASE COMPENSATE FILTER A kar 44 | TRACKING PHASE COMPENSATE FILTER B kaa 18 | TRACKING OUTPUT GAIN kaa, 30 | TRACKING AUTO GAIN koa 7F | FOCUS GAIN DOWN HIGH CUT FILTER A kas, 46 | FOCUS GAIN DOWN HIGH CUT FILTER B k26 81 | FOCUS GAIN DOWN LOW BOOST FILTER AH kar 3A | FOCUS GAIN DOWN LOW BOOST FILTER A-L k2B 7F | FOCUS GAIN DOWN LOW BOOST FILTER 8-H 29 66 | FOCUS GAIN DOWN LOW BOOST FILTER B-L Kea 82 _| FOCUS GAIN DOWN PHASE COMPENSATE FILTER A, KB 44 _ | FOCUS GAIN DOWN DEFECT HOLD GAIN kao 4E | FOCUS GAIN DOWN PHASE COMPENSATE FILTER B kD 18 _ | FOCUS GAIN DOWN OUTPUT GAIN KE 00 | NOTUSED. kor 00 | NOTUSED -25- mm 8382383 0015342 577 mmSONY ‘oxo25450 ‘ADDRESS | DATA CONTENTS 30 80 | Fie kat 68 | ANTI SHOCK LOW PASS FILTERB ka2 00 | NOTUSED kaa 7F | ANTI SHOCK HIGH PASS FILTER B-H ka4 6E | ANTI SHOCK HIGH PASS FILTER B-L Ka5 20 _ | ANTI SHOCK FILTER COMPARATE GAIN k36 7F | TRACKING GAIN UP2 HIGH CUT FILTER A Ka7 3B _ | TRACKING GAIN UP? HIGH CUT FILTER B kaa 80 | TRACKING GAIN UP2 LOW BOOST FILTER AH ka9 44 | TRACKING GAIN UP2 LOW BOOST FILTER A-L KoA 7F _ | TRACKING GAIN UP2 LOW BOOST FILTER 8-H KB 77 _ | TRACKING GAIN UP2 LOW BOOST FILTER B-L kc 86 | TRACKING GAIN UP PHASE COMPENSATE FILTER A kad 0D _| TRACKING GAIN UP PHASE COMPENSATE FILTER B. KE 87 | TRACKING GAIN UP OUTPUT GAIN kar 00 _| NOTUSED Kao (04 | TRACKING HOLD FILTER INPUT GAIN kat 7F | TRACKING HOLD FILTER A-H Kaz 7F | TRACKING HOLD FILTER A-L. a3 79 | TRACKING HOLD FILTER B-H kag 17 _ | TRACKING HOLD FILTER BL Kas 6D | TRACKING HOLD FILTER OUTPUT GAIN kas 00 | NOTUSED Kaz 00 | NOT USED kas 02 | FOCUS HOLD FILTER INPUT GAIN kag 7F | FOCUS HOLD FILTER A-H Kaa 7F | FOCUS HOLD FILTER A-L Kap 79 | FOCUS HOLD FILTER BH kac 17 _ | FOCUS HOLD FILTER B-L kad 84 | FOCUS HOLD FILTER OUTPUT GAIN Kae 00 | NOT USED Kar oo _| NOTUSED * Fix indicates that normal preset values should be used. ~26- WH 4382383 0015343 403 mm aSONY cxoestsa §1-4, Description of SENS Signals SENS output Microcomputer sera register . (latching not required) | ASEQ=0 ca ese 50x Z FzC = ux Z aS = BX z TZ = $36 Z GOK = 336 z XAVEBSY™ = $201097, S2Ato.3F : ay = $2008 Z TE Avrg Reg. obi $3908 z FE Avg Reg oR $3900 z Vo Avg Rog. obit S910 z TAVSC Reg. obit $3910 z FB Reg. obi S001F z FDC Avrg Reg. abi aK z XBUSY = 3X z FOK = 36x z ° = SAX GFS oS = 38x ‘COMP ‘COMP = 50x ‘cour cour = 3ex Ovea Ove = $7%, BX, OX, DX, FX : o = '$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVAG measurement, ‘STP is output in all other cases. -27- @™ 6362383 OOL5344 34T mmSONY ‘oxoes4s0 Description of SENS Signals SENS output Zz ‘The SENS pin is high impedance. XBUSY Low while the auto sequencers in operation, high when operation terminates. ee ‘Outputs the same signal as the FOK pin High for “focus OK". GFS High when the regenerated frame sync is obtained with the correct timing. aoe ‘Counts the number of tracks set with Reg B. High when Reg B is latched, low when the initial Reg B number is input by CNIN. Counts the number of tracks set with Reg B. cour High when Reg B is latched, toggies each time the Reg B number is input by CNIN. While $44 and $46 are being executed, toggles with cach CNIN 8-count instead of the Reg B number. over ‘Low when the EFM signal, after passing through the sync detection fier, is lengthened by 64 channel clock pulses or more. ~28- MH 8382383 OOLS34S 286 mmSONY ‘exnasts0 [2] Description of CD Signal Processing-System Commands and Functions ‘§2+1. Description of Commands and Data Sets. $4X commands Register name Data t Data Data 3 a Command MAX timer value Timer range ‘asa | as2 | ast | aso | MT3| mt2[ m1 | mTo [ussL| o | 0 | 0 ‘Command ‘ASS. AS2. AST ‘ASO Cancel 0 0 °O o Fine Search ° 1 ° RXF Focus-On ° 1 7 1 1 Track Jump 1 0 0 AXF 10 Track Jump 1 ° 1 AXF 2N Track Jump 1 1 0 BXF M Track Move 1 1 1 BX ‘= When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. ‘When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence AXF=0 Forward RXF=1 Reverse is interrupted, ‘Cancel timer value Timer range Mra Mia MT MTO ist 232ms_| items | 58me | 29ms 0 1.495 O74 0.378 0.185 7 * To invalidate the MAX timer, set $4X0 and the timer value to 0. $5X commands Timer TRS TRA TRI TRO Biind (A, E), Overflow (G, G) O.18ms (0.08ms 0.045ms ‘O.0zams Brake (8) 0:36ms ‘O18ms ‘O.09rs ‘0.045ms ~29- ME 8382383 OOLS34b 112 mmSONY ‘x0a5460 $6X commands Register name Data Data 2 6 KICK (0) KICK (F) soa | sb2 | sot | sbo | KF3 | KF2 | KFI | KFO Timer ‘S03 ‘S02 ‘S01 ‘S00 When executing KICK (0) $44 or $45, 23.2ms Theme ‘5.oms 2.9ms When executing KICK (0) $4C or $4D 11.6ms Bams 2ams 145ms Timer KFS KF2, KFI KFO KICK (FY 0-72ms ‘036ms O.18ms (0.09ms $7X commands ‘Auto sequence track jump count setting Datat Data2 Data 3 Data + ‘Command D19[018]017]D16[015|D14]D13]D12/011]D10] 09 | 8 | D7 | D6 | O5 | 04 ‘Auto sequence trackjump | 545! 24] o18| a12| a1 | a10 7 | 28 2 | 2 eoaneane 285] 214] 219] ata] att | a10| 28 | 28 | a7 | 26 | 2s | 24 | 29 | 22 | 21 | 20 ‘This command is used to set N when a 2N-track jump is executed, M when an M track move is executed and the jump count when a fine search is executed for auto sequence. + The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count is determined by the mechanical limitations ofthe optical system. ‘= When the track jump count is from 0 to 15, the COUT signal is used to count tracks for 2N-track jump/M track ‘move; when the count is 16 or over, the MIRR signal is used. For fine search, the COUT signal is used 10 ‘count tracks. ‘$8X commands Data Data 2 Command bia | p18 | Di7 | Die | DIS | Dia | DIS | DIA MODE DouT | Doout Speccation [COROM| SANT | ewe | wseL |vcoset| ass | soct | 0 ‘Command bit C2PO timing Processing - [CDROM mode; average value interpolation and pre-value hold COROM=1 | Soothe Timing Chant21. Ero - ; [Ausio mode; average value interpolation and pre-value hold are| COROM=0 | See the Timing Chant 2-1, RAGE ‘Command bit Processing DOUT Mute = 1_ | When Digital Out is on (M2 pin = 1), DOUT output is muted, BOUT Mute = 0 | When Digital Out is on, DOUT output is not muted. ‘Command Bit Processing D. out Mute F= 1 | When Digital Out is on (MD2 pin = 1), DA output is muted, . out Mute F = 0 | DA output mute is not affected when Digital Out is either on or of =30> WM 5382383 0015347 059 mmSONY Timing Chart 2-11.) coxoa54s0 MO2 | Other mute conditions® | DOUT Mute [.out Mute F] DOUT output [DA output ° 0 ° 0 0 1 ry 0 @ 7 0 0 0 T 1 off ° 1 0 0 0 1 0 1 dB ° 1 7 0 0 1 7 1 7 0 ° 0 008, 008 i 0 ° 1 = 1 @ 7 o 008 i 0 1 1 1 1 @ 0 8 1 1 o 1 dB 7 1 7 ° 1 7 1 1 * See mute concitions (1), (2) and (4) to (6) under SAX commands for other mute conditions. ‘Syne protection window width "Application 228 channel clook™ ‘Anivvoling is enhanced 36 channel lock Syne window protection is enhanced. * tn normal-speed playback, the channel clock=4,3218MHz Command bit Processing Use ; Used for nommal-speed and double-speed VooseL.=0 | The builtin VCOis set to normal speed. | Uses etnomarepend and moe Used for quadruple-speed and double-speed VOOSEL= 1 | ThebultinVcO 'ssetto ign speed. | quacruple correction) playback. (Command bit Function Use : ‘The command transfer rato to SSP is set_| Used for normal-speed and double-speed ASHS=0 | tonormal speed. (double correction) playback. ae “The command transfer ratoto SSP is set | Used for quadruple-speed and double-speed ASHS=1 | to half speed. (quadruple correction) playback. (Command bit Function SOCT=0 _ | Sub Gis output rom the S080 pin, oct a1 | Each signalis output from the SOSO pin. Input the readout lock to SOCK. (See the ~31— MH 8382383 0015348 735SONY ‘exoesssa $9X commands Data t Data2 Command, bia | pie | di7 | pie | DS | Dia | Dis | Di2 Function | OcLv | spa | Asea | Dru | ewaL [eiar | eo |G ‘specification | ON-OFF |ON-OFF |ON-OFF |ON-OFF| MAIN | SUB Camara [elmo Gaon During OLS | FSW =fow MON Tigh MDS «MOP = evo conta rose camer regency of 00heatTo=Dandaebreal The BOL onto : DuiogGLVP | FW =, WON-= ig NOS = speeder ia ar earl mode Tae MOP phase clog carer Woqaroyot Si TAOS = PWM party sgal winonDouv, care reuecyo ite ccwvonst=1 | owingcuvs | Piitandi 1] MOP = PUM abscute sve sup ina), ow non fa |ocl came femecy of TS reaues) | mes wosez Winon Dou | MP = ear PYM out jan carrier frequency of 132kKHz When DCLY onvoft = 1 for the Digital CLV servo, the sampling frequency of the internal digital fiter switches simultaneously with the CLVPICLVS switching. Therefore, the cut-off frequency for the CLVS is fc = 70Hz at Ta = 0, and fe = 140Hz at Ts = 1 ‘Command bit Processing DSPB=0 | Normal-speed playback, C2 error quadruple correction, variable pitch possible. DSP! Double-speed playback, C2 error double correction, variable pitch prohibited, Normally, FLFC is 0. Command bit Meaning DPLL= 0° _ | AFPLL is analog. PDO, VGOI and V60O are used DPLL=1 | RFPLL is digital. PDO is high impedance, * Extemal parts for Pins 18 to 20 are required even when analog PLL is selected. ‘Command bit | BiIGL MAIN = 0 BIIGLSUB=0 | STEREO iL SUB =1 SUB Definition of bilingual capable MAIN, SUB and STEREO. ‘The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output tothe left and right channels for STEREO. 22- @™@ 6382383 0015349 92) mmSONY oxoesisa ‘SAX commands Data 4 Data2 Command pis | oie | ot” | Die | 015 | DIM | Dia | Die Vai | van audocraL| Ya | Qa" | mute | arr | ect: | pcre | 0 ° Vari Van Down ee acy «210% VOOO% 40.1% !40.2% 409% 402%! +010 som [orm 02%! Xtal Ow NT CO SO gO 0 TH Command bit Meaning ‘Command bit Meaning Mate off if other mute ‘Attenuation off Mute =0 me conditions are not set. Er Mute on. Peak register Muto=1 | Mute Mute conditions (1) When register A mute = 1 (2) When Mute pin = 1 (8) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin = 1). (4) When GES stays low for over 36ms (during normal-speed). (8) When register 9 BIIGL MAIN = Sub = 1 (6) When register A PCT1 = 1 and PCT: (1) t0 (4) perform zero-cross muting with 2 1 me time limit ‘Command bit PoM Meaning ECC error correction ability Pott | PoT2 Gain 0 0 | Normal mode x0dB | C1: double; C2: quadruple o Level meter mode | x0d8 | C1: double: C2: quadruple 1 0 | Peakmetermode | Mute | C1: double; G2: double 1 Normal mode x0dB_| C1: double; C2: double Description of level meter mode (see the Timing Chart 2-2.) * When the LSI is set to this mode, it can possess digital level meter functions. * When the 96-bit clock is input to SACK, 96 bits of data are output to SASO. ‘The inital 80 bits of data are Sub Q data (see §2-2. Subcode Interface). The last 16 bits are LSB first, 15-bit PCM data (absolute values). ‘The final bit is POM data. However, itis high when generated by the left channel and low when generated by the right channel * PCM data is reset and the LIR flag is reversed after one readout. ‘The maximum value for this status is then measured until the next readout. ~33- M™ 6362383 0015350 b43 mmSONY ‘oxo2sis0 Description of peak meter mode (see the Timing Chart 2-3.) ‘= When the LSI is set to this mode, the maximum PCM data value is detected regardless of iit comes from the left or right channel ‘The 96-bit clock must be input to SQCK to read out this data, ‘+ When the 96-bit clock is input, 96 bits of data are output to SASO and the LSI internal register is reset, In other words, the PCM maximum value detection register is not reset by the readout ‘To reset the PCM maximum value detection register, set PCT1 = PCT2 =0 or set the SAX mute. ‘= The Sub Q absolute time is automatically controled in this mode, In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. The normal operation is conducted for the relative time. + The final bit (UR fag) of the 96-bit data is normally 0 * The pre-value hold and average value interpolation data are fixed to level (~~) for this mode, $BX commands This command sets the traverse monitor count. Datat Data2 Data 3 Data 4 b19]518[17[D16[D15|014]019]012|011]D10] 09 | Ds | D7 | Ds | 05 | D4: 218| are! 219 a2] a1| a10| 29 | 28 | 27 | 26] as | 2 | 22 | 22 | or | 0 Command “Traverse monitor count setting ‘+ When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off * The traverse monitor count is set when the traverse status is monitored by the SENS output COMP and cour. $CX commands E Command ata | Data 2 Explanation Dis | ove | 07 [bie | OWS [Om | DIe | Ow Serve eoetcent | Gain | Gain | Gan | Gain Gain setting MoP1|MDPo|mos1|mpso| ° |ocvo| ° Oe eerie DCL uv cTAL Dx) en Valid when DOLV = 1 oo ‘The spindle servo gains externally set when DCL * CLVS mode gain setting: GCLVS Gain] Gain | Gain wosi | moso | civs | SCLVS Note) When DCLV = 0, the CLVS gain is as follows: 0 0 neal When Gain CLVS = 0, GCLVS =~124B. When Gain CLVS = 1, GCLVS = OdB. 0 0 1 608 0 1 0 | 608 0 1 008 1 0 Co 1 1 +608 =34— M@™ 6382383 001535) Sot mmSONY * CLVP mode gain setting: GMDP: GMDS Gain] Gain moP1 | mopo | CMDP Gain] Gain mpsi | mpso | GMOS 0 0 | 6B ° 1 | 008 1 0 | +608 * DCLV overall gain setting: GDCLV Gain petvo | @DcLv 0 | ode 1 | +608 ‘$DX commands Command Dia | 018 DIT, 016 CLV CTAL ana Pwa mo} TS wr Gain cuvs See the $CX commands. ‘Command bit Explanation (See the Timing Chart 2-4,) CLV PWM MD =1 Digital CLV PWM mode specified, Both MOS and MDP are used. DOLV PWM MD =0 Digital CLV PWM mode specified. Temary MOP values are output, ‘Command bit Explanation Botiom hold in CLVS and CLVH modes at a eycle of RFCKIS2, Bottom hold in CLVS and GLVH modes at a cycle of RECKI16. Peak hold in CLVS mode at a cycle of RFCKI4, Peak hold in CLVS mode at a oycle of RFCKI2. Note) Peak hold is performed at 34kHz in CLVH mode, -35- W™@ 6382383 0015352 41L mm coxo2s4saSONY ox0es450, SEX commands ‘Command Dis_| 018 | bi” | Die CLV mode cus [Gwe | oma | cMo ms | ome] OMT | OMO | Mode Explanation 0 0 0 0 | stop See the Timing Chart 2-5. 1 0 0 0 KICK See the Timing Chan 2-6. 1 0 al 0 | BRAKE See the Timing Chart 27. 1 1 1 o | ows 1 1 0 0 | clWH 1 1 1 7 CLvP 0 1 q o | GWA STOP: Spindle motor stop mode KICK: Spindle motor forward rotation mode BRAKE: Spindle motor reverse rotation mode CLVS: Rough servo mode. When the RF-PLL circuit lock is disengaged, this mode is used to pull the disc rotations within the FF-PLL capture range. CLVP: PLL servo mode CLVA: Automatic CLVSICLVP switching mode. This mode is normally used during playback. —36- @™ 5382383 0015353 352 mmcxoessa, SONY sewed 20191 sensed 20 WOH pe ~~ a Si . een mina aan nea (mcr mnse Kem marmiumar Xa snow users aes opus X sewed 20 ¥991 42 Od 20 HOD HORS oso owes von ne l | von \ be wey Buy, mm 6382383 0015354 299 mmexo2s4sa, SONY Buyuans 109071 10407 -— l vet vee og a 04 mee T mem wo wi TEE os0s 1 yo0s sere aad 8 oan ee beh "tins Esco ee ence [ree .2omp01u 900 an8, 098 EGOS wi Xa (oo \--\va Koa Kove Xv X oa Xe Xoo X X~ “XK be J a ee wey Su -38- Wm 8362383 0015355 125 mmox02s450, SONY Buys s010W Heed woweunsToN uowenseay =e = md oes eer oe i MH 4382383 0015356 Ob) aSONY coxoesis0 ming Chart 2-4 DCLY PWM MO-=0 wr I] ie M_l U aes 4 Perec tes (Output Waveforms with DOL = 1 Timing Chart 2-5 vew=0 mos Mop Fw t Mon L DOLW =1 Dow PWM MO =0 MOP X a FSW and MON are the same as for DCLV = 0 ~40- Wm 8382383 0015357 TTS mmSONY ‘oxozs4s0 Doty = FOCLY PHM MD =1 Mop FSW and MON are the same as for DCL! Timing Chart 26 pow =o = > Fsw MON DOCLV =1 DoLY Pw MD «0 DeLv= 1 OCLY Punt MD. Mos Mor Kick : To FSW and MON are the same as for DCLV = 0 KICK L FSW and MON are the same as for DCL\ aa mm 8382383 0015353 934 mmSONY ‘Timing Chart 2-7 vawv=0 Few OLY =1 DCLY Pw Mk Mos : Mo? boty = 1 poLy Pw MO. Mos Mo? BRAKE BRAKE FSW and MON are the same as for DCLV = 0 u FSW and MON are the same as for DCLV 5 mM 8382383 0025359 870 a coxoasasaSONY exoes46a, §2-2. Subcode Interface This section explains the subcode interface. ‘There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from ‘SBSO by inputting EXCK. ‘Sub Q can be read out aftr the CRC check ofthe 80 bits of information in the subcode frame. This is accomplished, after checking SCOR and CRCF, by inputing 60 clock pulses to SOCK and reading data from the S80 pin, P to W Subcode Read Data can be read out by inputting EXCK immediately after WFCK falls. (See the Timing Chart 2-8.) 80-bit Sub Q Read Fig. 2-9 shows the peripheral block of the 80-bit Sub Q register. * First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/paralle register and the CRC check circuit. ‘+ 96-bit Sub Q is input, and if the CRC is OK, itis output to SQSO with CRCF = 1. In addition, the 80 bits are loaded into the paralleVserial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded. * In the CXD2545Q, when 80-bit data is loaded, the order of the MSB and LSB is inverted for each byte. As a resul, although the sequence of the byles is the same, the bits within the bytes are now ordered LSB first. * Once the fact that the 80-bit data has been loaded is confirmed, SQCK is input so that the data can be read. In this LSI, the SQCK input is detected, and the retriggerable monostable muttvibrator for low is reset. * The retriggerable monostable multivibrator has a time constant from 270 to 40036, When the duration when. ‘SQCK is high is less than this time constant, the monostable muttivibrator is kept reset; during this interval, the S/P register is not loaded into the P/S register. “While the monostable multivibrator is being reset, data cannot be loaded into the peak detection Parallel/serial register or the 80-bit paralleVseral register. In other words, while reading out with a clock cycle shorter than the monostable mulivibrator time constant, the registor will not be rewritten by CRCOK and others. * In this LSI, the previously mentioned peak detection register can be connected to the shitin ofthe 80-bit P/S. register. Input and output for ring control 1 are shorted in peak meter or level meter mode. ‘Those for ring 2 are shorted in peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. ‘As a result, the 96-bit clock must be input in peak meter mode. + In addition, as previously mentioned, the absolute time after peak is generated is stored in the memory in peak meter mode. (See the Timing Chart 2-10.) * Although a clock is input from the SQCK pin to actually perform these operations, the high and low intervals {or this clock should be between 750ns and 1203s. —43— WM 4382383 OO153L0 592 mmSONY ‘Timing Chart 2-8 coxoas4sa. UUUU ULL poe ULM Lies TARR Xe > ‘Sane ‘Same ‘Subcode P.O.R.S.T.UV.W Read Timing ~44— WMH 8382383 002536) 429 mm‘oxo2sis0 SONY —— “| | coos --——| 2 rs on | : paso ony | — Bh | | cvmman [a] mmtrcume = + mo | _t Tico — t ff : i yoce —f*[ [+ ass sang —| sense 20H eat g fo I ° {fd nd ws anon game . i i vapoason 5 x 1 . : \e LD mS . . ° ‘ ‘ + | HT | T HOosaa0ayv someone ws b— one “uo suaySS—~—SsSSSSS eee (nee) (o38v) (wey) 6-7 wesbelg yo0Ig ~45- WH 8382383 0015362 3b5 mmcoxoasasa, SONY seu suo —| I. eaav XK _teav ouay XT B= yODS voUN eMogy 01012 —) wooo wan YX 1089) 10H 1-2 weyo Bur, MH 4382383 0015363 27)coxo2ssa SONY yes 1eyIod Zo ‘ejqissodwy uonseu09 29 | t 1 yes 20 UIOd 19 ‘[qyssodwy| uoneH09 19 | IL 1 1 ‘doo 100d 19 ‘eqssoduy voyoeu09 20 | 0 | + | + yesq ued 1g ‘paweuoosouergom | o | + |b = o fof wsi0ujod 19 ‘pepeucoioueroeuo| + | o | + yese1sejuod 29 ‘parseuco siouezoinoa| o | o | + es 216d 19) sioueroon | o | o | + reser sewed z9 ‘peysenoo sioue zoean | 4 | + | 0 = 1 [+o jesersei4edz9 ‘peiseuoo sioue zoom | o | + | 0 = o{+fo yesaseujod 29 _‘peyeuoo 10020 euD | 0 0 yesorsoquiod 19 ‘peyeuoo10Ne 19 eUD |b 0 0 19891 101010 20 souozoon| 0 | 0 | 0 e801 ‘sue igen|o | 0 | 0 uondioeed 0320 | ¥a20 | e420 wonda8eG ato | aio | eat ‘seseeicep Jequinu epoo Areulg ey) FYI YONS $1 UO}E|ELI09 et ‘yous s1 1unowe sony 444 eur UaYM ‘@pC0 AzBUIQ UL ANdino @Le ZHI OF OHA WNOWE L8H IH Ju syseudue ee aap yeeafeld oun VOU TUBS YBN w sindiNO Hawa} “mor eindno uid en “sues enanoasuoo wie NOL a 1 $40 J TRUBS YoY ® sindino uid stn “UB s1 S19 UEKI :2HOBH 1 Pardes si S45 prow Gurun voqoeyord voqvasui ow ue aUAS ew OM VOY HEIR 330 30 B00 Od ‘esw= dua ‘8S = Oud UI BIE Are: 1q S109} 81g ysnipe 01 pasn) yunowe soy sy | *+¥3d 1 OUAd ue oS Tas ana GY vs cn aro ns fon soe YUU ea ane [ams tino wa aKa om OSS a 2s SOUT bee weug 6uru, ~47— WH 8382383 0015364 138 mmSONY cexoesasa, $23. Digital PLL ‘+ The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. ‘Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, PLL is necessary to regenerate the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. ‘The block diagram of this PLLiis shown in Fig. 2-12, The CXD2545Q has a builn three-stage PLL. * The first-stage PLL regenerates the variable pitch. LPF and VCO are necessary as external parts. ‘The minimum variable amount of pitch is 0.1%, The output of this fist-stage PLL is used as a reference for all clocks within the LSI. Input the XTAO output to the VCKI pin when variable pitch is not used. + The second-stage PLL regenerates a high-frequency clock needed by the third-stage digital PLL. ‘The third-stage PLL is a digital PLL that regenerates the actual channel clock, and has a +150kHz (normal- speed playback) or more capture range. ~48— WM 8382383 OOLS365 O74 mmSONY cxoessa Block Diagram 212 d seootnate anal ™ 100 r Le Ti teen i wes ; veo iL ""G 1 mw LL incon Lf © ee : | 76 raze AMOS TVaapich | Up down counter T pe ar Mocerpusr crit Vata Phase comparator 3 8 mw Ld 1 a0) W™ 8382363 OO353bb TOO mmSONY coxoasisa §2-4. EFM Frame Sync Protection ‘+ Ina CD player operating at normal speed, a frame sync is recorded approximately every 196ps (7.35kH2). ‘This signal is used as a reference to know which data is the data within a frame. Conversely, if the frame ‘sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync property is extremely important for improving playability. ‘In the CXD2545Q, window protection and forward protectionbackward protection have been adopted for frame sync protection. The adoption of these functions achieves very powerful frame sync protection. Tnere are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. In other words, when the frame syne is being regenerated normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. the frame syne cannot be detected for 13 frames or more, the window Is released and the frame sync is, resynchronized. In addition, immediately after the window is released and the resynchronization is executed, i a proper frame ‘sync cannot be detected within 3 frames, the window is released immediately. §26. Error Correction * In the CD format, one &-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte C2 parity. Both C1 and C2 are Reed Solomon codes with 2 minimum distance of 5 + The CXD25450 uses refined super strategy to achieve double correction for C1 and quadruple correction for ce, + In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status, the generation status of the EFM signal, and the operating status of the player. * The correction status can be monitored outside the LSI. See the Table 2-13, * When the C2 pointer is high, the data in question was uncorrectable, Either the pre-value was held or an average value interpolation was made for the data, MNTS | MNT2 | MNT? | MNTO Description o [0 [ 0 | 0 | NoCterors, Ct pointer reset o [oo 1_| One Gt error corrected: Ct pointer reset ove | econ | ec 0 = o,of a = o [1 [0 | 0 | Nocteror Cf pointer set ofa 0 | 1 | OneCtemorcorrected, C1 pointer set o | 7 7 0 | TwoCt errors corrected: C1 pointer set o [4 1 1__ | Ct correction impossible; C1 pointer set 1 0 [0 | 0 | NoC2erors; C2 pointer reset 1 0 [0 | 1 | OneC2erorconected, 62 pointer reset 1 o [4 0 _| Two? errors corrected, C2 pointer reset 1 0.4 1__| Three C2 errors corrected; C2 pointer reset 1 7 0 | 0 | FourC2erors corrected; G2 pointer reset 1 1 ota = 1 1 1 (0 _| C2 correction impossible; 1 pointer copy 1 1 1 1 [2 correction impossible, C2 pointer set Table 2-13. —50- Wm 8382383 0015367 947 mmSONY Timing Chart 2-14 Nomalspeed PB —4 | 400 t0 So0ne RFCK "= Dependent on enor — ‘conaiton Ts 1 correction (62 correction wane wnt MnTo tobe ‘strobe. §246. DA Interface + The CXD25450 has two modes as DA interfaces. a) 48-bit slot interface This interface includes 48 cycles ofthe bit clock within one LACK cycle, and is MSB fist When LACK is high, the data is for the left channel. ) 64-bit slot interface ‘This interface includes 64 cycles of the bit clock within one LACK cycle, and is LSB first, When LACK is low, the data is for the left channel aie WM 8382383 0015368 883 mmSONY ‘exne5ts0 TULL. siva ve t 2 [7 ee yout rovateig peeds-onog 18 HaRy em KAYA KAKA KAKA Ka Ka Ka Ka Kn yenyen yng ra Yer sve TL. cc SUL se % aoe ee TPT e ET al ow Sour T= 7984 *PepKeg pads eULON 10 140% siz wey BULL =52- wm 8382383 0015369 727 acoxoesisa SONY =o) PPEEEEEEEEE EEL (1957 wu nva TUT ae” zee 2 e a = o bee) ane fd poods 9FFeG PIF Ha ¥9 ake e ana a Cran) na 6 Xo 0 wes) a J ser “TsTgsd 94 peods WON 8 a 49 91 MeyD Bui, MH 8382363 0015370 43) mmSONY oxn2s4sa, §2-7. Digital Out ‘There are three digital output formats; the type 1 format for broadcasting stations, the type 2 form 4 format for home use, and the type 2 form 2 format for the manufacture of software, ‘The CXD2545Q supports Type 2 form 1. Regarding the clock accuracy of the channel status, level II is set automatically when the crystal clock is used ‘and level It is variable pitch. In addition, Sub Q data which are matched twice in succession after a CRC check are input tothe frst four bits (bits 0 to 3). OUT is output when the crystal is 34 MHz, the variable pitch is reset, and DSPB. and turn DOUT off. |. Therefore, set MD2 to 0 Digtal ou we Fomabo ope eet ofojolofs}ololo|olololo Too | 101 [coPyem wlo}o}ojo}ojojofololojolo| oja|o|o 2 « ° 1% 01098. Sub Q corr bis tha malched ce wth CRCOK bez .Varpach: 1 xtat 0 Table 2-17. $28. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps, When the auto sequence ‘command is received from the CPU, auto focus, 1 track jump, 2N track jumps, fine search, and M track move are executed automatically. ‘The servo block is used in an exclusive manner during the auto sequence execution (when XBUSY = low), 50 that commands from the CPU are not transferred to the servo block, but can be sent to the signal processor block. In addition, when using the auto sequencer, tum the A. SEQ of register 9 on. When the clock goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100ps afler that point. This is designed to prevent the transfer of erroneous data to the servo block when XBUSY changes from low to high by the monostable mutvibrator, which is reset by CLOK being low (When XBUSY is low). Wm 8382383 0015371 378 mmSONY coxoes4sa In addition, a MAX timer is buitin as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifas the command and Y sets the MAX timer value and timer range. Ifthe executed Auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (ike $40). See 2-1, $4X commands conceming the timer value and range. Also, the MAX timer is invalidated by inputing $4xo. Atthough this command is explained in the format of $4X in the following command descriptions, the timer value and timer range should be actualy sent together from the CPU. (@) Auto focus ($47) Focus searct-up is performed, FOK and FZC are checked, and the focus servo is turned on, 't $47 is received from the CPU, the focus servo is tumed on according to Fig. 2-18. The auto focus is executed after focus search-up, and the pickup should be lowered beforehand (focus search-down). In addition, bind E of register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned (on at the falling edge of FZC after FZC has been continuously high for a longer time than E. MH 8382383 0015372 204 mmSONY oxo2s45a. high forthe parod atime E st with nO _(Shsck whatrer FZC is contuousty register 5. Focus ser ON Fig. 2-18 (a). Auto Focus Flow Chart 47 Latch SEIN (FZ0) aur Commane forse ee Bind E $00, Fig. 2-18 (b). Auto Focus Timing Chart ~56- mm 8362383 0035373 140 aSONY coxo2sasa. (©) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use them when focus, tracking, and sled servo fre on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not performed. ‘+ 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 2-19. Set blind A and brake B with register 8, *10-track jump When $4A ($48 for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 2-20. The principal diference between the 10-track jump and the 1-track jump is whether to kick the Sled or not. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake {is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set in register 5), the tracking and sled servos are tured on. * 2Ndrack jump When $4C ($40 for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 2-21. The track jump count "N" is set in register 7. Although N can be set to 2%° tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when Nis less than 16, and MIRR is used with N is 16 or higher. ‘Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is tured on, the sled continues to move only for *D", set in register 6. + Fine search ‘When $44 ($45 for REV) Is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in ‘accordance with Fig. 2-22. The differences from a 2N-track jump are that a higher precision is achieved by ‘controlling the traverse speed, and long jumps are possible by controling the sled. The track jump count is, ‘set in register 7. N can be set to 2 tracks. Alter kicking the actuator and sled, the traverse speed is Controlled based on the overflow G. Set kick D and F in register 6. In addition, sled speed contro! during traverse can be turned off by causing COMP to fall. Set the number of tracks during which COMP falls in register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is pertormed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set in register 6.) Then, the tracking and sled servos are turned on. ‘Set overflow G to the speed required to slow up just before the track jump terminates, (The speed should be ‘such that it will come on-track when the tracking servo tums on at the termination of the track jump.) For ‘example, set the target track count N — a for the traverse monitor counter which ie set in register B, and COMP will be monitored. When the falling edge of this COMP is detected, overtlow G can be reset. * M track move When $4E (S4F for REV) is received from the CPU, a FWD (REV) M track move Is performed in accordance with Fig. 2-23. M can be set to 216 tracks. COUT is used for counting the number of moves when M is less than 16, and MIRR is used when M is 16 or higher. The M track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. In addition, the tack and sled servo are turned off after M tracks have been counted through COUT or MIRR unlike for the ‘ther jumps. Transfer $25 after the actuator is stabled. -s7- mM 8382383 0015374 087 mmSONY ‘oxpas4sa Track ak (BEV Wek tor REV Sea sone (Jump Tacpey] (Pwo kektornev)) ‘ioe (re Walt (rakes) Track deg owe ON Fig. 2-19 (a). 1-Track Jump Flow Chart ‘$40 (REV = $49) Latch xT i cour | aay i Bing Brake 8 ‘Command (orssP 28 (620) $20 ($28) 5 ig. 2-19 (b). 1-Track Jump Timing Chart 58- mm 8382383 0015375 TL3 mmSONY coxo2sasa (creck wise COUT oc (Comparten cretion 7 Fig. 2-20 (a). 10-Track Jump Flow Chart [4A (REV = $48) Laten st : | cout [] 7] ausv | aay eee aes ‘ovestonc commana eae season see 28 ses Fig. 2-20 (b). 10-Track Jump Timing Chart 50- WH 8382383 001537b 9ST mmSONY ‘oxpes4sa, 2N Track Tack, de FWD ele 1 WAT ine 8) mur | cour Tl eee ell Ja i | ausv / ‘Bing A” COUT MRA Over-tiow C Kick D Command uaa SSE soncsen 2 20) sze.sen ss Fig. 2-21 (b). 2N-Track Jump Timing Chart ~60- Wm 8382383 0015377 896 mmSONY xT 3 Fine Search 8 BI a. WAT (eek) Tia Sie EO Kise WAT (hoe) “Tack Senv9 ON ‘Sed REV Ket | WATT hee) Track Soa ‘Seno ON Fig. 2-22 (a). Fine Search Flow Chart S44 (REV = $45) Latch ‘eek WoexF” Traverse Speed Canto Overow 2)" Wek $26 627) $27 (826) cour fi count Sea (9) 2s Fig. 2-22 (b). Fine Search Timing Chart ~61- WH 5382383 0015378 722 mm ‘oxo2ses0SONY ‘x026460 re Mow [ack Seno. OFF ‘Sed FWD Keck a Wart (Gling 6) ‘Couns COUT tN < 18. Keon 3 Courts MIAR tN 216, [ves "Tack, Sled ‘Servo ON Fig. 2-28 (a). M-Track Move Flow Chart SSE (REV = S4F) Latch a Or my Bind A ‘cour qu) ‘Command Mosun forseno $22 823) 20 Fig. 2-23 (b). M-Track Move Timing Chart ~62- Wm 6362383 0015379 669 aSONY ‘oxpesésa, §2-9. Digital CLV Fig. 2-24 shows the block diagram. Digital CLV makes PWM output in CLVS, CLVP and other modes with the MDS error or MDP error signal sampling frequency increased to 130kHz during normal-speed operation. In addition, the digital spindle servo can set the gain. Dg cav cusp wos ere woe ene oan Y cis eames Measure l T Oise exes of _ ee a \/ sain V/ sain Y wos cuve] MOP | 42 i aiv6 an cw | ‘Over Sampling | CLY-PIS raat Noe Shape wacx.srace sto» —e[ _ Woaaion 1 +| Mode Select MOP DCLVMD al CLVS U/D: Up/down signal from the CLV-S servo MDS error: Frequency error for the CLV-P servo MOP error: Phase error for the CLV-P servo Fig. 2-24. Block Diagram 63- W™ 8362363 0015380 380 aSONY coxoasasa, ‘§2-10. Asymmetry Compensation Fig, 225 shows the block diagram and circuit example. t oxoasesa —— sve t Fe asvo Rt | —_) >—® =a AeA, Ly ogy} ts _ Te 1 ft » |) |g be asm mi + | G noel ons Be mS Fig. 2-25. Example of an Asymmetry Compensation Application Circuit §2-11, Playback Speed In the CXD2545Q, the following playback modes can be selected through different combinations of the crystal, XTSL pin, double-speed playback command (DSPB), VCO selection command (VCOSEL) and command transfer rate selector (ASHS). Also, the minimum operating voltage changes according to the playback mode. (See the Recommended Operating Conditions.) Playback modes Mode | Xtal [ xTSt_[ DSPB [VCOSEL] ASHS [Playback speed] Error correction 1 | 76ers [1 0 a 0 x Ci: double: C2: quadruple 2 | vers | 1 7 on 0 x2 (C1: double; C2: double 3 | 7ears | 0 ° 1 1 x2 Ci: double; C2: quadruple 4 | vers [0 1 1 1 x4 C1: double; ©2: double 5 | sears [0 0 on 0 xt C1: double: C2; quadruple 6 | sears [0 1 on 0 x2 C1: double; C2: double 7 | sears | 1 1 on ° x4 C1: double, C2: double However, Fs = 44.1kHz. 4 mH 8382363 0015381 217 mmSONY oxoasssa. [3] Description of Servo Signal Processing-System Functions and Commands '§2-0. General Description of the Servo Signal Processing System (Voltages are the values for a 5V power supply.) Focus servo ‘Sampling ra 88.2KHz 2.5V center #1.0V 7-bit PWM Offset cancel Focus bias adjustment Focus search Gain-down function Detect countermeasure ‘Automatic gain control Tracking servo Sampling rate: 8a.2ktHz Input range: 25V center #1.0V Output format: 7-bit PWM Others: Offset cancel EF balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel ‘Automatic gain control Vibration countermeasure ‘Sled servo Sampling rate: S4sHz Input range: 2.5V center 21.0V Output format: 7-bit PWM Other Sled move FOK, MIRR, OFCT signals generation FF signal sampling rate: 1.4MHz Input range: 2.18V 10 5.0V Others: AF zero level automatic measurement ‘The signal input from the RFDC pin is mutiplied by a factor of 07 and loaded into the A/D converter. 65 MH 8382383 0025382 153 mmSONY coxoesasa, §9-1. Digital Servo Block Master Clock (MCK) ‘The FST! pin (Pin 66) is the reference clock input pin. The internal master clock (MCK) is generated by dividing the frequency of the signal input to FSTI. the frequency division ratio is 1/2 oF 1/4, Table 3-1 below shows the hypothetical case where the crystal clock generated from the digital signal processor block is 2/S frequency divided and input to the FSTI pin (Pin 66) by externally connecting the FSTI pin (Pin 66) and the FSTO pin (Pin 67). ‘The XTAD and XT2D command settings can be made with D13 and D12 of $3F. (Default = 0) ‘The digital servo block is designed with an MCK frequency of 5.6448MHz. Mode] Xtal | FSTO | FSTI | XTSL | XT4D | xT2D | Frequency division ratio | _MCK frequency 1 [sears | 25ers [asers{ + | o | 1 12 128F5 2 _| sears | asers | 2sers[ 0 | o | 0 2 128Fs 3 | veers | siaFs[stars[ = | 1 0 wa 128Fs, 4 | 7e8Fs | 512Fs | st2Fs| 1 of 0 14 128F 5 Fo.= 44.1kHz, +: Don't care Table 3-1. ‘89-2. AVRG (Average) Measurement and Compensation ‘The ©XD2545Q has a compensation circuit which performs compensation using the RFDC, VC, FE and TE AVRG measurement circuits and their measurement results in order to perform reliable servo control. ‘AVRG measurement and compensation is necessary to initialize the CXD2545Q, and can cancel the offset by performing each AVAG measurement before playback operation and using these results for compensation. The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VLCM), D13 (FLM), D11 (RFLM) and D4 (TCLM) of $38 respectively to 1 AVAG measurement consists of digitally measuring the level applied to each analog input pin by taking the ‘average of 256 samples, and then loading these values into the AVAG register. AVRG measurement requires approximately 2.9ms to 5.8ms after the command is received. During AVAG measurement, if the upper 8 bits of the serial data are 38 (Hex), the termination of AVAG ‘measurement operation can be confirmed by monitoring the SENS pin (Pin 80). (See the Timing Chart 3-2.) xuaT 2910 5.6me sens. Cxavensy) Max. tps Termination of AVAG measurement Timing Chart 3-2, Wm 8382383 0015383 O97 mmSONY coxasssa, *VCAVRG. ‘The offset can be canceled by measuring the VC level which is the center potential forthe system and using that value to apply compensation to each input error signal + FEAVRG ‘This measures the FE signal DC level. In addition, compensation is applied to the FZC comparator level output from the SENS pin during FCS SEARCH (locus search) using these measurement results. TE AVRG ‘This measures the TE signal DC level. + RF AVRG ‘The CXD2545Q generates the MIAR, DFCT and FOK signals from the RF signal. However, the FOK signal is generated by comparing the RF signal at a certain level, so that it is necessary to establish a zero level which becomes the comparator level reference. Therefore, the RF signal is measured before playback ‘operation, and compensation applied to bring this level to the zero level ‘An example of sending AVG measurement and compensation commands is shown below. (Example) $380800 (RF Avrg. measurement on) '$382000 (FE Avrg. measurement on) '$380010 (TE Avrg. measurement on) '$988000 (VC Avrg. measurement on) (Finish each AVRG measurement before starting the next.) $38140A (RFLC, FLCO, FLC1 and TLC1 commands on) (The required compensation tum on together; see Fig. 3-3.) ‘An interval of 5.8ms or more must be maintained between each command, or the SENS pin must be monitored ‘and the next AVRG command sent after confirming that the previous command has been finished. ‘See Fig. 3-3 for the contents of each compensation below, ‘+ RFLC ‘The difference by which the AF signal exceeds the RF AVRG value is input to the RF In register. (00 is input when the RF signal is lower than the RF AVAG value.) *TCLo ‘The value obtained by subtracting the VC AVRG value from the TE signal is input to the TAK In register. TOL ‘The value obtained by subtracting the TE AVRG value from the TE signal is input to the TRK In register. Voie ‘The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register. sFLCt ‘The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register. + FLCO ‘The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register. ~67- W™ 8362383 0015384 T2b MmSONY oxoasssa, §9-3. E:F Balance Adjustment Function When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity, In this condition, the low-band component can be extracted from the TE signal using the buil-in TRK hold fiter by setting D5 (TBLM) of $38 to 1 The extracted low-band component is loaded into the TRVSC register as a digital value, and the TRVSC. register value is established when TBLM retums to 0. Next, setting D2 (TLC2) of $38 to 1 applies only the amount of compensation (subtraction) equal to the TRVSC register value to the values obtained from the TE and SE input pins, enabling the E:F balance offset to be adjusted. (See Fig. 3-3.) ‘89-4. FCS Bias (Focus Bias) Adjustment Function ‘The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 33) ‘When the FBIAS register value is set to D11 = 0 and D10 = vvalue of D9 to D1 (09: MSB). Im addition, the RF jitter can be monitored by setting the SOCT command of $8 to 1. (See the CD Signal Processing-System Block Timing Chart 2-4.) by $34F, data can be written using the 9-bit ~68- Wm 8382383 0015385 ibe mmeoxoesasa, SONY M™ 8382383 0015385 875SONY ‘oxpas4sa §8-5. AGCNTL (Automatic Gain Control) Function ‘The AGCNTL function automatically adjusts the fiter internal gain in order to obtain the appropriate gain with the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, ete., but also obtains the optimal gain for each disc. ‘The AGCNTL command is sent when each servo is tumed on. During AGCNTL operation, ifthe upper 8 bits of the input serial data are 98 (Hex), the termination of AGCNTL operation can be confirmed by monitoring the ‘SENS pin (Pin 80). (See the Timing Chart 3-4 and the Description of SENS Signals.) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation Note) When performing AGCNTL operation, each servo filter must be in the gain normal status, and the anti shock circult (described hereatter) must be disabled, Max. 11.418 sens A¢on \ —____/ t [AGCNTL termination ‘Timing Chart 3-4. Costficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and KO7 for AGT (tracking AGCNTL) due to AGCNTL. ‘These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. ‘After AGCNTL operation has terminated, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related settings The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex) ‘TG6 to TGO; AGT convergence gain soting, effective setting range: 00 to 67 (Hex) AGS; Seltstop on/off ‘AGJ; Convergence completion judgment time AGGF; —_Intemally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; _AGCNTL sensitivity 1 (during high sensiivity adjustment) AGV2; _AGCNTL sensitivity 2 (during low sensitivity ajustment) AGHS; High sensitivity adjustment on/ot AGHT; High sensitivity adjustment time Note) Converging servo loop gain values can be changed with the FGS to 0 and TG6 to 0 setting values. In ‘addition, these setting values must be within the effective setting range. The default settings aim for dB at 1kHz. However, since convergence values vary according to the characteristics of each ‘constituent element of the servo loop, FG and TG values should be set as necessary. -70- Mm 8382363 0015387 735 mmSONY ‘oxbesssa, AGCNTL and default operation have two stages. In the first stage, high sensitivity adjustment is performed for a certain period of time (select 256/128ms with AGHT), and the AGCNTL coafficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is led reliably towards the appropriate value at a relatively low. ‘sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage ‘of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the ‘©XD2545Q confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ), and then terminates AGCNTL operation. (Sell-stop mode) ‘This self-stop mode can be canceled by rewriting AGS to 0. |i addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. ‘An example of AGCNTL coefficient transitions during AGCNTL operation and the relationship between the various settings are shown in Fig. 3-5, ‘nal value ‘Stops AGVT AGONT. Coefcent vale Convergence vale sont Laan, oo condita sexs | Fig. 35, -71- WH 8382383 0015385 67] mmSONY oxnes4s0, §9-6. FCS Servo and FCS Search (Focus Search) ‘The FCS servo is controlled by the 8:bit serial command $0X. (See Table 3-6.) Resistor | Command |023 to 020] 19 to D1 1.0 + + | FOGUS SERVO ON (FOCUS GAIN NORMAL) 111 = + | FOGUS SERVO ON (FOCUS GAIN DOWN) 9 [FOCUS | 5 4 gq | 220 | FOCUSSERVO OFF. VOUT CONTROL (0+ 1 + | FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT 0+ 1-0 | FOCUS SEARCH VOLTAGE DOWN 0 = 1-1 | FOGUS SEARCH VOLTAGE UP =: Don't care Table 36. FCS Search FCS search is required in the course of turing on the FCS servo. Figs. 3-7 and 3-8 show the signals for sending commands $00 -> $02 + $03 and performing only FCS search ‘operation, and for moving from $03 to FCS on ($08), $00 $02. $03, $08 Fesprv FosorV FOK. Fe re a rs 1 |) Fig. 2-7, Fig. 38. -7- WH 8382383 0015389 Sos mmSONY ex02s450, 88-7. TRK (Tracking) and SLD (Sled) Servo Control ‘TRI and SLO servo control is performed by the 8-bit command $2X. (See Table 3-9.) ‘When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin. Register name Command |D23 to 020] D19 to D16| 0 + + | TRACKING SERVO OFF 1 + + | TRACKING SERVO ON 0» | FORWARD TRACK JUMP 1 REVERSE TRACK JUMP ‘SLED SERVO OFF ‘SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE TRACKING RODE! oo10 a] oe} slo *:Don't care Table 3-9. TRK Servo ‘The TRK JUMP ({rack jump) height can be set with the 6 bits D13 to D8 of $36. In addition, when the TAK servo is on, the TRK servo filter assumes gain-up status when D17 of $1 is set to 1. ‘The TRK servo iter also assumes gain-up status when vibration detection Is performed with the LOCK signal (Pin 98) iow and the anti-shock circuit (described hereafter) enabled. ‘The gain-up fiter used when TRK has assumed gain up status has two types of structures which can be selected by setting D16 of $1. (See Table 3-17.) SLD Servo ‘The SLD MOV (sled move) output, composed of a basic value from the 6 bits D13 to D8 of $37, is determined by multiplying this value by the x 1, x 2, x3 or x 4 magnification set using D17 and D16 when Dt ‘set with $3. (See Table 3-10.) SLD MOV must be performed continuously for 50ys or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo tums off. Note) When the LOCK signal is low, the operations which set the TAK servo to gain up status and tum off the ‘SLO servo can be canceled by setting D6 (LKSW) of $38 to 1 Register eae | Command |D28 to D20|019 to D16 0.000 | SLEDKICK LEVEL (basic value x21) 0.00 1 | SLEDKICK LEVEL (basic value x 22) 0-0 1 0 | SLEDKICK LEVEL (basic value x23) 0.011 | SLEDKICK LEVEL (basic value x4) 3 | SELECT Joo11 Table 3-10. -723- mm 8382383 0015390 227 mmSONY exnesssa, §3-8. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin (Pin 26) is sampled at approximately 1.4MHz and loaded, ‘The MIRR and DFCT signals are generated from this RF signal MIRR Signal Generation ‘The loaded RF signal is applied to peak hold and bottom hold circuits. ‘An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is {generated from the average of these envelope waveforms. ‘The MIRA signal is generated by comparing this MIRR comparator level with the waveform generated by ‘subtracting the bottom hold value from the peak hold value. (See Fig. 3-11.) poromiia YY YL ay fae “ — Fig. 311. DFCT Signal Generation The loaded AF signal is input to two peak hold circuits with diferent time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 3-12) ‘The DFCT comparator level can be selected from four values using D13 and D12 of $38. « yw (ny “1 a Pook Holga Peak Hotta = Peak Holst Bee son [AA (ostect comparator lve 4 rer fl Fig. 3-12. -74- mm 8382383 0015391 bb mm