System Integrated

Logic Analyzer v1.1

LogiCORE IP Product Guide

Vivado Design Suite

PG261 February 4, 2021
Table of Contents
IP Facts

Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 2: Product Specification

Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 3: Designing with the Core

Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 4: Design Flow Steps

Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Appendix A: Upgrading

Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Appendix C: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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 IP Facts

• User-selectable AXI4-MM channel debug

Introduction and AXI Data/Address width selection.

The customizable System Integrated Logic • Data and Trigger probe and interface type
Analyzer (System ILA) IP core is a logic analyzer selection.
which can be used to monitor the internal
• BRAM estimation.
signals and interfaces of a design. The System
ILA core includes many advanced features of • AXI4-MM and AXI4-Stream Protocol
modern logic analyzers, including boolean Checking.
trigger equations and edge transition triggers.
• IPI Support.
The core also offers interface debug and
monitoring capability along with AXI4-MM and LogiCORE™ IP Facts Table
AXI4-Stream protocol checking(1). Because the
System ILA core is synchronous to the design Core Specifics
being monitored, all design clock constraints Supported UltraScale+™, UltraScale™,
Device Family(1) Zynq®-7000 SoC, 7 Series
that are applied to your design are also applied
Supported User
to the components of the System ILA core. Interfaces
IEEE Standard 1149.1 - JTAG

Resources
The IP is functionally equivalent to an ILA but
offers additional benefits in debugging Provided with Core
interfaces in both IPI and the Hardware Design Files N/A
Manager. It is recommended to use the System Example Design Not Provided
ILA IP in IPI for debugging interfaces and nets. Test Bench Not Provided
For more information on how to view AXI Constraints File Not Provided
interface transactions and channel events in the Simulation
Not Provided
Vivado Hardware Manager waveform viewer, Model
see [Ref 6]. Supported
S/W Driver (2) N/A
1. AXI4/AXI4-Stream protocol violations can be displayed in Tested Design Flows(3)
waveform view by enabling protocol checker. The
pc_asserted signal assertion indicates protocol Design Entry Vivado® Design Suite
violation while the pc_status signal indicates the nature
Simulation Not Provided
of protocol violation. For more details on the description
of pc_status signal, see [Ref 9] and [Ref 10]. Synthesis Vivado Synthesis

Support
All Vivado IP
Features Change Logs
Master Vivado IP Change Logs 72775

Xilinx Support web page

• User-selectable number of probe ports and
Notes:
probe width. 1. For a complete list of supported devices, see the Vivado IP
catalog.
• Multiple probe ports, which can be 2. Standalone driver details can be found in the Vitis
combined into a single trigger condition. directory(<install_directory>/Vitis/<release>/data/
embeddedsw/doc/xilinx_drivers.htm). Linux OS and driver
• Debugging of any debuggable interface support information is available from the
Xilinx Wiki page.
including AXI4-MM and Stream in a system
3. For the supported versions of the tools, see the
created in IP Integrator. Xilinx Design Tools: Release Notes Guide.

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 Chapter 1

Overview

Feature Summary
Signals and interfaces in the FPGA design are connected to the System ILA probe and slot
inputs (see Figure 1-1). These signals and interfaces, attached to the probe and slot inputs
respectively, are sampled at design speeds and stored using on-chip block RAM (BRAM).

The core parameters specify:

• The number of probes and interface slots.

• Interface types, trace sample depth.
• Data and trigger property of probes and interfaces.
• Number of comparators and the width for each probe and individual ports within
interfaces.

Communication with the System ILA core is conducted using an auto-instantiated debug
core hub which connects to the JTAG interface of the FPGA.
X-Ref Target - Figure 1-1

clk
trig_out
trig_in trig_in_ack
trig_out_ack
probe0
probe1

probe1023
slot0
slot1

slot15

Figure 1-1: System ILA Symbol

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 Chapter 1: Overview

After the design is loaded into the FPGA, you can use the Vivado® logic analyzer software
to set up a trigger event for the System ILA measurement. After the trigger occurs, the
sample buffer is filled and uploaded into the Vivado logic analyzer. You can view this data
using the waveform window. Regular FPGA logic is used to implement the probe sample
and trigger functionality. On-chip block RAM memory stores the data until it is uploaded by
the software. No user input or output is required to trigger events, capture data, or to
communicate with the System ILA core.

As System ILA is capable of monitoring interface level signals, it can convey transaction
level information such as outstanding transaction for AXI4 interfaces.

System ILA Probe Trigger Comparator

Each probe input is connected to trigger comparators which can perform various
operations. After the design has been programmed into the device, in the Vivado Hardware
Manager the comparator can be set to perform = or != comparisons. This includes
matching level patterns, such as X0XX101. It also includes detecting edge transitions such
as rising edge (R), falling edge (F), either edge (B), or no transition (N). The trigger
comparator can also perform more complex comparisons, including >, <, >=, <=.

IMPORTANT: The number of comparators used by the System ILA is set during
customization of the System ILA IP.

System ILA Trigger Condition

The trigger condition is the result of a Boolean AND or OR calculation of each of the System
ILA probe trigger comparator results. Using the Vivado logic analyzer, you can select
whether to AND or OR probe trigger comparators.

The AND setting causes a trigger event when all of the System ILA probe comparisons are
satisfied.

The OR setting causes a trigger event when any of the System ILA probe comparisons are
satisfied. The trigger condition is the trigger event used for the System ILA trace
measurement.

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 Chapter 1: Overview

Applications
The System ILA IP core is designed to be used in any application which requires verification
or debugging using the Vivado logic analyzer. Figure 1-2 shows MicroBlaze™ processor
writes and read from AXI BRAM controller through M_AXI_DP interface. The System ILA core
is connected to the interface net between the MicroBlaze™ processor and AXI Bram
controller to monitor the AXI4 transaction between MicroBlaze™ processor and AXI BRAM
controller in hardware manager.
X-Ref Target - Figure 1-2

Figure 1-2: AXI Interface Debugging use case

Licensing and Ordering

This Xilinx LogiCORE™ IP module is provided at no additional cost with the Xilinx®
Vivado® Design Suite under the terms of the Xilinx End User License.

Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual
Property page. For information on pricing and availability of other Xilinx LogiCORE IP
modules and tools, contact your local Xilinx sales representative.

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 Chapter 2

Product Specification
The customizable System Integrated Logic Analyzer (System ILA) IP core is a logic analyzer
which can be used to monitor the internal signals and interfaces of a design. The System ILA
core includes many advanced features of modern logic analyzers, including boolean trigger
equations and edge transition triggers. The core also offers interface debug and monitoring
capability along with AXI4-MM and AXI4-Stream protocol checking. Because the System ILA
core is synchronous to the design being monitored, all design clock constraints that are
applied to your design are also applied to the components of the System ILA core.

Port Descriptions
The port descriptions for the System ILA IP Core Ports and Parameters are described in the
following sections.

Table 2-1: ILA Ports

Port Name I/O Description
clk I Design clock that clocks all trigger and storage logic.
Probe port input.
The probe port <n> number is in the range from 0 to 1,023.
Probe<n>[<m> - 1:0] I The probe port width (denoted by <m>) is in the range of 1 to 4,096.
You must declare this port as a vector.
For a 1-bit port, use probe<n>[0:0]
Slot interface.
The type of the interface <intf_name> is created dynamically based
Slot_<p>_<intf_name> O on the slot_<p>_<intf_name> interface type parameter.
The individual ports within the interfaces are available for
monitoring in the hardware manager.
The trig_out can be generated either from trigger condition or from
an external trig_in port. There is a Vivado Hardware Manager control
trig_out O
from the Logic Analyzer to switch between trigger condition and
trig_in to drive trig_out. See Figure 1-1.
Input trigger port used in process based system such as Zynq-7000
SoC for Embedded Cross Trigger.
trig_in I
This port can be connected to another ILA to create a cascading
Trigger.

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 Chapter 2: Product Specification

Table 2-1: ILA Ports

Port Name I/O Description
trig_out_ack I An acknowledgment to trig_out.
trig_in_ack O An acknowledgment to trig_in.

Table 2-2: ILA Parameters

Allowable
Parameter Name Values Default Description

String with A-Z, Name of instantiated

Component_Name System_ila_0
0-9, and ‘_’ component.
System ILA monitor type:
NATIVE: Monitor Individual
NATIVE probes
C_MON_TYPE INTERFACE INTERFACE INTERFACE: Monitor
MIX interfaces
MIX: Monitor Individual
probes and interfaces
Number of System ILA Probe
C_NUM_OF_PROBES 1-1,024 1
ports.
C_NUM_MONITOR_SLOTS 1-16 1 Number of Interface Slots.
Probe storage buffer depth.
1,024, 2,048,
This number represents the
4,096, 8,192,
C_DATA_DEPTH 1,024 maximum number of
16,384, 32,768,
samples that can be stored
65,536, 131,072
for each probe input.
Width of probe port <n>.
C_PROBE<n>_WIDTH 1-4,096 1 Where <n> has a value of 0
to 1,023.
The width of individual
native probes can only be set
when the native probe width
propagation is set to manual.
Otherwise, the individual
C_PROBE_WIDTH_PROPAGATION AUTO, MANUAL AUTO
probe width parameters are
not editable.
The value is automatically set
post propagation in IPI
design.
Add extra flops to the probe
C_INPUT_PIPE_STAGES 0-6 0 ports. One parameter applies
to all of the probe ports.

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 Chapter 2: Product Specification

Table 2-2: ILA Parameters

Parameter Name Allowable Default Description

Values
Enables the Capture
(Storage) Qualifier.
By enabling this you can
specify the capture condition
in Vivado Logic Analyzer thus
capture the probes
selectively. This takes one
C_EN_STRG_QUAL 0,1 0
extra compare values (match)
unit. This means if advance
trigger (C_ADV_TRIGGER)
option is enabled, the
maximum number of match
units per probes reduces
from four to three.
Enables the advance trigger
option.
This enables trigger state
C_ADV_TRIGGER True/False False
machine so you can write
your own trigger sequence in
Vivado Logic Analyzer.
Forces the same compare
ALL_PROBE_SAME_MU True/False True value units (match units) to
all of the probes.
Number of Compare Value
(Match) units per probe.
C_PROBE<n>_MU_CNT 1-16 1 This is valid only if
ALL_PROBE_SAME_MU is
FALSE.
Data and/or Trigger property
Data, Trigger, of probe port <n>.
C_PROBE<n>_TYPE Data & Trigger
Data & Trigger Where <n> is the probe port
with a value of 0 to 1,023
Enable the AXI transaction
tracking capability for slot
C_SLOT_<p>_TXN_CNTR_EN 0,1 1 <p> (when the slot is
configured as an AXI
interface).
Configure the number of
C_SLOT_<p>_MAX_WR_BURSTS 2,4,8,16,32,64 2 outstanding write
transactions.
Configure the number of
C_SLOT_<p>_MAX_RD_BURSTS 2,4,8,16,32,64 2 outstanding read
transactions.

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Table 2-2: ILA Parameters

Parameter Name Allowable Default Description

Values
All VLNV[Ref 11]
of debuggable xilinx.com:inter Interface type is the VLNV of
C_SLOT_<p>_INTF_TYPE interfaces face:aximm_rtl: interface connected to
available in 1.0 slot_<p>_<intf_name>
Vivado.
Enable AXI protocol checker
IP for slot <p> (when the slot
C_SLOT_<p>_APC_EN 0,1 0
type is configured as an AXI
interface).
To choose a selected
Data, Trigger, slot_<p> for specifying
C_SLOT_<p>_TYPE Data & Trigger
Data & Trigger trigger conditions, data
storage, or both.
Configure Write Address
channel signals as Data when
C_SLOT_<p>_AXI_AW_SEL_DATA 0,1 0 slot_<p> is configured as
AXI interface and slot_<p>
has a value of 0 to 15.
Configure Write Data
channel signals as Data when
C_SLOT_<p>_AXI_W_SEL_DATA 0,1 0 slot_<p> is configured as
AXI interface where slot <p>
has a value of 0 to 15.
Configure Write Response
channel signals as Data when
C_SLOT_<p>_AXI_B_SEL_DATA 0,1 0 slot_<p> is configured as
AXI interface where slot <p>
has a value of 0 to 15.
Configure Read Address
channel signals as Data when
C_SLOT_<p>_AXI_AR_SEL_DATA 0,1 0 slot_<p> is configured as
AXI interface where slot <p>
has a value of 0 to 15.
Configure Read Data channel
signals as Data when
C_SLOT_<p>_AXI_R_SEL_DATA 0,1 0 slot_<p> is configured as
AXI interface where slot <p>
has a value of 0 to 15.
Configure Write Address
channel signals as Trigger
C_SLOT_<p>_AXI_AW_SEL_TRIG 0,1 0 when slot_<p> is configured
as AXI interface where slot
<p> has a value of 0 to 15.

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 Chapter 2: Product Specification

Table 2-2: ILA Parameters

Parameter Name Allowable Default Description

Values
Configure Write Data
channel signals as Trigger
C_SLOT_<p>_AXI_W_SEL_ TRIG 0,1 0 when slot_<p> is configured
as AXI interface where slot
<p> has a value of 0 to 15.
Configure Write Response
channel signals as Trigger
C_SLOT_<p>_AXI_B_SEL_TRIG 0,1 0 when slot_<p> is configured
as AXI interface where slot
<p> has a value of 0 to 15.
Configure Read Address
channel signals as Trigger
C_SLOT_<p>_AXI_AR_SEL_TRIG 0,1 0 when slot_<p> is configured
as AXI interface where slot
<p> has a value of 0 to 15.
Configure Read Data channel
signals as Trigger when
C_SLOT_<p>_AXI_R_SEL_TRIG 0,1 0 slot_<p> is configured as
AXI interface where slot <p>
has a value of 0 to 15.
Configure AXI4-Stream
signals as Data when
slot_<p> is configured as
C_SLOT_<p>_AXI_DATA_SEL 0,1 0
AXI-Stream interface where
slot <p> has a value of 0 to
15.
Configure AXI4-Stream
signals as Trigger when
slot_<p> is configured as
C_SLOT_<p>_AXI_TRIG_SEL 0,1 0
AXI-Stream interface where
slot <p> has a value of 0 to
15.
AXI4 protocol when
slot_<p> is configured as
AXI interface where slot <p>
AXI3, AXI4LITE,
C_SLOT_<p>_AXI_PROTOCOL AXI4 has a value of 0 to 15.
AXI4
The value is automatically set
post propagation in IPI
design.
AXI-MM data width when
slot_<p> is configured as
AXI interface where slot <p>
32, 64, 128, 256,
C_SLOT_<p>_AXI_DATA_WIDTH 32 has a value of 0 to 15.
512, 1024
The value is automatically set
post propagation in IPI
design.

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 Chapter 2: Product Specification

Table 2-2: ILA Parameters

Parameter Name Allowable Default Description

Values
AXI-MM address width when
slot_<p> is configured as
AXI interface where slot <p>
C_SLOT_<p>_AXI_ADDR_WIDTH 1-32 32 has a value of 0 to 15.
The value is automatically set
post propagation in IPI
design.
AXI-MM ID width when
slot_<p> is configured as
AXI interface where slot <p>
C_SLOT_<p>_AXI_ID_WIDTH 0-32 0 has a value of 0 to 15.
The value is automatically set
post propagation in IPI
design.
AXI-MM AWUSER width
when slot_<p> is configured
as AXI interface where slot
C_SLOT_<p>_AXI_AWUSER_WIDTH 0-1,024 0 <p> has a value of 0 to 15.
The value is automatically set
post propagation in IPI
design.
AXI-MM WUSER width when
slot_<p> is configured as
AXI interface where slot <p>
C_SLOT_<p>_AXI_WUSER_WIDTH 0-1,024 0 has a value of 0 to 15.
The value is automatically set
post propagation in IPI
design.
AXI-MM BUSER width when
slot_<p> is configured as
AXI interface where slot <p>
C_SLOT_<p>_AXI_BUSER_WIDTH 0-1,024 0 has a value of 0 to 15.
The value is automatically set
post propagation in IPI
design.
AXI-MM ARUSER width when
slot_<p> is configured as
AXI interface where slot <p>
C_SLOT_<p>_AXI_ARUSER_WIDTH 0-1,024 0 has a value of 0 to 15.
The value is automatically set
post propagation in IPI
design.

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Table 2-2: ILA Parameters

Parameter Name Allowable Default Description

Values
AXI-MM RUSER width when
slot_<p> is configured as
AXI interface where slot <p>
C_SLOT_<p>_AXI_RUSER_WIDTH 0-1,024 0 has a value of 0 to 15.
The value is automatically set
post propagation in IPI
design.
AXI-Stream tdata width when
slot_<p> is configured as
8, 16, 24, 32, 64, AXIS interface where slot
C_SLOT_<p>_AXIS_TDATA_WIDTH 128, 256, 512, 32 <p> has a value of 0 to 15.
1024 The value is automatically set
post propagation in IPI
design.
AXI-Stream tid width when
slot_<p> is configured as
AXIS interface where slot
C_SLOT_<p>_AXIS_TID_WIDTH 0-32 0 <p> has a value of 0 to 15.
The value is automatically set
post propagation in IPI
design.
AXI-Stream TUSER width
when slot_<p> is configured
as AXIS interface where slot
C_SLOT_<p>_AXIS_TUSER_WIDTH 0-32 0 <p> has a value of 0 to 15.
The value is automatically set
post propagation in IPI
design.
AXI-Stream TDEST width
when slot_<p> is configured
as AXIS interface where slot
C_SLOT_<p>_AXIS_TDEST_WIDTH 0-32 0 <p> has a value of 0 to 15.
The value is automatically set
post propagation in IPI
design.
Enables the trig out
functionality.
C_TRIGOUT_EN True/False False
Ports trig_out and
trig_out_ack are used.
Enables the trig in
functionality.
C_TRIGIN_EN True/False False
Ports trig_in and trig_in_ack
are used.

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 Chapter 3

Designing with the Core

This chapter includes guidelines and additional information to facilitate designing with the
core.

Clocking
The clk input port is the clock used by the System ILA core to register the probe values. For
best results, it should be the same clock signal that is synchronous to the design logic that
is attached to the probe ports of the System ILA core.

Resets
System ILA can only be reset using the Vivado® logic analyzer.

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 Chapter 4

Design Flow Steps

This chapter describes customizing and generating the core, constraining the core, and the
simulation, synthesis and implementation steps that are specific to this IP core. More
detailed information about the standard Vivado® design flows and the IP integrator can be
found in the following Vivado Design Suite user guides:

• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
[Ref 1]
• Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 2]
• Vivado Design Suite User Guide: Getting Started (UG910) [Ref 3]
• Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 4]

Customizing and Generating the Core

This section includes information about using Xilinx tools to customize and generate the
core in the Vivado Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado
Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 1] for
detailed information. IP integrator may auto-compute certain configuration values when
validating or generating the design. To check whether the values do change, see the
description of the parameter in this chapter. To view the parameter value, run the
validate_bd_design command in the Tcl console.

You can customize the IP for use in your design by specifying values for the various
parameters associated with the IP core using the following steps:

1. Select the Add IP option from the Vivado IPI right click menu.
2. Add the System ILA IP from Vivado IPI catalog. (See Figure 4-1.)
3. Double-click the selected IP or select the Customize Block command from the toolbar
or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 2] and
the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 3].

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 Chapter 4: Design Flow Steps

Note: Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE).
The layout depicted here might vary from the current version.
X-Ref Target - Figure 4-1

Figure 4-1: System ILA Core in Vivado IP Catalog

General Options
Figure 4-2 shows the General Options tab (Interface Monitor Type selected). This allows
you to specify general configuration options.
X-Ref Target - Figure 4-2

Figure 4-2: General Options Tab (interface Monitor Type)

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 Chapter 4: Design Flow Steps

Figure 4-3 shows the General Options tab (Mix Monitor Type selected). This allows you to
specify general configuration options.
X-Ref Target - Figure 4-3

Figure 4-3: General Options Tab (Mix Monitor Type)

Component Name - Use this field to provide a unique module name for the System ILA
core.

Monitor Type - This option specifies which type of interface that System ILA should be
debugging. Values for this parameter are INTERFACE, NATIVE and MIX.

° Select INTERFACE to monitor interface level signals.

° Select NATIVE to monitor scaler signals.

° Select MIX to monitor both signal types.

Number of Probes - Use this field to configure the number of probe ports required on the
System ILA core. The valid range used in the Vivado IDE is 1 to 64. If more than 64 probe
ports are required, use the Tcl command flow to generate the System ILA core.

Native Probe Width propagation - Update the Native probe width propagation to
MANUAL in order set the individual probe width parameters.

Number of Interface Slots - Select the number of interface slots on the System ILA core.
The valid range in the Vivado IDE is 1-16.

Sample Data Depth - Select the required sample depth from the drop-down menu.

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Same Number of Comparators for all Probes - Check to enable the same number of
comparators for all the enabled ports and interfaces. This option is available in both Basic
and Advanced Trigger modes.

Number of Comparators - Select to enable the number of comparators that applies to all
enabled probes. The maximum number of comparators is 16 per probe. The number of
comparators can be set from 1 to 16 in both Basic and Advanced Trigger modes.

Trigger Out Port - Check to enable the optional trigger out port.

Trigger In Port - Check to enable the optional trigger in port.

Input Pipe Stages - Select the number of registers you want to add for the probe. This
parameter applies to all of the probes.

Capture Control - Check to enable the qualifier for the trace capture.

Advanced Trigger - Check to enable the state machine-based trigger sequencing.

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Probe Ports
Figure 4-4 shows the Probe Ports tab in the Native/MIX monitor type. This tab allows you
to configure Probe Port options.

Probe Port Width can be configured in this tab. The width of the individual probes are
editable only when the Native Probe Width Propagation parameter value is set to
MANUAL (see Figure 4-3). Otherwise, the width of each individual probe is set
automatically based on IP Integrator parameter propagation. Each Probe Port Panel has up
to eight ports.

The number of comparators per probe can be configured on this tab. This option is
available only when the Advanced Trigger option is selected and the Same Number of
Comparator for all Probes option is cleared on the first page of Vivado IDE (see
Figure 4-3).
X-Ref Target - Figure 4-4

Figure 4-4: Probe Ports Tab

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Interface Options
Figure 4-5 shows the Interface Options tab in the Interface/MIX monitor type with the
AXI4-MM Interface type selected (highlighted).
X-Ref Target - Figure 4-5

Figure 4-5: Interface Options Tab (AXI4-MM)

Figure 4-6 shows the Interface Options tab in the Interface/MIX monitor type with the
AXI4-Stream Interface type selected (highlighted).
X-Ref Target - Figure 4-6

Figure 4-6: Interface Options Tab (AXI4-Stream)

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 Chapter 4: Design Flow Steps

Figure 4-7 shows the Interface Options tab in the Interface/MIX monitor type with a Non
AXI Interface type selected (highlighted).
X-Ref Target - Figure 4-7

Figure 4-7: Interface Options Tab (Non AXI)

Configuration for Slot - Selects the parameters corresponding to slot_<p> (where <p> is
the slot number).

Interface Type - VLNV [Ref 11] of the interface to be monitored by the System ILA core.

AXI-MM Protocol - Selects the protocol of AXI interface when the slot_<p> interface type
is configured as AXI-MM, where <p> is the slot number.

AXI-MM ID Width - Selects the ID width of the AXI interface when the slot_<p> interface
type is configured as AXI-MM, where <p> is the slot number.

AXI-MM Data Width - Selects the Data width of the AXI interface when the slot_<p>
interface type is configured as AXI-MM, where <p> is the slot number.

AXI-MM Address Width - Selects the Address width of the AXI interface when the
slot_<p> interface type is configured as AXI-MM, where <p> is the slot number.

Enable AXI-MM/Stream Protocol Checker - Enables AXI4-MM or AXI4-Stream protocol

checker for slot <p> when the slot_<p> interface type is configured as AXI-MM, where <p>
is the slot number.

Enable Transaction Tracking Counters - Enables AXI4-MM transaction tracking capability.

Number of Outstanding Read Transactions - Specifies the number of outstanding Read

transactions per ID. The value should be equal to or greater than the number of outstanding
Read transactions for that connection.

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Number of Outstanding Write Transactions - Specifies the number of outstanding Write

transactions per ID. The value should be equal to or greater than the number of outstanding
Write transactions for that connection.

Monitor APC Status signals - Enable monitoring of APC status signals for slot <p> when
the slot_<p> interface type is configured as AXI-MM, where <p> is the slot number.

Configure AXI read address channel as Data - Select read address channel signals for
data storage purpose for slot <p> when the slot_<p> interface type is configured as
AXI-MM, where <p> is the slot number.

Configure AXI read address channel as Trigger - Select read address channel signals for
specifying trigger condition for slot <p> when the slot_<p> interface type is configured as
AXI-MM, where <p> is the slot number.

Configure AXI read data channel as Data - Select read data channel signals for data
storage purposes for slot <p> when the slot_<p> interface type is configured as AXI-MM,
where <p> is the slot number.

Configure AXI read data channel as Trigger - Select read data channel signals for
specifying trigger conditions for slot <p> when the slot_<p> interface type is configured as
AXI-MM, where <p> is the slot number.

Configure AXI write address channel as Data - Select write address channel signals for
data storage purpose for slot <p> when the slot_<p> interface type is configured as
AXI-MM, where <p> is the slot number.

Configure AXI write address channel as Trigger - Select write address channel signals for
specifying trigger conditions for slot <p> when the slot_<p> interface type is configured as
AXI-MM, where <p> is the slot number.

Configure AXI write data channel as Data - Select write data channel signals for data
storage purpose for slot <p> when the slot_<p> interface type is configured as AXI-MM,
where <p> is the slot number.

Configure AXI write data channel as Trigger - Select write data channel signals for
specifying trigger condition for slot <p> when the slot_<p> interface type is configured as
AXI-MM, where <p> is the slot number.

Configure AXI write response channel as Data - Select write response channel signals for
data storage purposes for slot <p> when the slot_<p> interface type is configured as
AXI-MM, where <p> is the slot number.

Configure AXI write response channel as Trigger - Select write response channel signals
for specifying trigger condition for slot <p> when the slot_<p> interface type is configured
as AXI-MM, where <p> is the slot number.

AXI-Stream Tdata Width - Selects the Tdata width of the AXI-Stream interface when the
slot_<p> interface type is configured as AXI-Stream>, where <p> is the slot number.

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AXI-Stream TID Width - Selects the TID width of the AXI-Stream interface when the
slot_<p> interface type is configured as AXI-Stream>, where <p> is the slot number.

AXI-Stream TUSER Width - Selects the TUSER width of the AXI-Stream interface when the
slot_<p> interface type is configured as AXI-Stream>, where <p> is the slot number.

AXI-Stream TDEST Width - Selects the TDEST width of the AXI-Stream interface when the
slot_<p> interface type is configured as AXI-Stream>, where <p> is the slot number.

Configure AXIS signals as Data - Select AXI4-Stream signals for data storage purpose for
slot <p> when the slot_<p> interface type is configured as AXI-Stream where <p> is the
slot number.

Configure AXIS signals as Trigger - Select AXI4-Stream signals for specifying trigger
condition for slot <p> when the slot_<p> interface type is configured as AXI-Stream, where
<p> is the slot number.

Configure Slot as Data and/or Trigger - Selects non-AXI slot signals for specifying trigger
condition or for data storage purpose or for both for slot <p> when the slot_<p> interface
type is configured as non-AXI, where <p> is the slot number.

BRAM Resources estimation graph - The bar graph gives an estimates percentage
consumption of BRAM slices for the device part being used.

Output Generation
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 2].

Constraining the Core

This section contains information about constraining the core in the Vivado Design Suite.

Required Constraints
The ILA core includes an XDC file that contains appropriate false path constraints to prevent
the over-constraining of clock domain crossing synchronization paths. It is also expected
that the clock signal connected to the clk input port of the ILA core is properly constrained
in your design.

Device, Package, and Speed Grade Selections

This section is not applicable for this IP core.

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 Chapter 4: Design Flow Steps

Clock Frequencies
This section is not applicable for this IP core.

Clock Management
This section is not applicable for this IP core.

Clock Placement
This section is not applicable for this IP core.

Banking
This section is not applicable for this IP core.

Transceiver Placement
This section is not applicable for this IP core.

I/O Standard and Placement

This section is not applicable for this IP core.

Simulation
This core does not support simulation.

Synthesis and Implementation

For details about synthesis and implementation, see the Vivado Design Suite User Guide:
Designing with IP (UG896) [Ref 2].

IMPORTANT: Synthesis with Synopsys Synplify is not supported for the core.

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 Appendix A

Upgrading
This appendix is not applicable for the first release of the core.

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 Appendix B

Debugging
This appendix includes details about resources available on the Xilinx Support website and
debugging tools.

TIP: If the IP generation halts with an error, there might be a license issue. See Licensing and Ordering
for more details.

Finding Help on Xilinx.com

To help in the design and debug process when using the System ILA, the Xilinx Support web
page contains key resources such as product documentation, release notes, answer records,
information about known issues, and links for obtaining further product support.

Documentation
This product guide is the main document associated with the System ILA. This guide, along
with documentation related to all products that aid in the design process, can be found on
the Xilinx Support web page or by using the Xilinx Documentation Navigator.

Download the Xilinx Documentation Navigator from the Downloads page. For more
information about this tool and the features available, open the online help after
installation.

Answer Records
Answer Records include information about commonly encountered problems, helpful
information on how to resolve these problems, and any known issues with a Xilinx product.
Answer Records are created and maintained daily ensuring that users have access to the
most accurate information available.

Answer Records for this core can be located by using the Search Support box on the main
Xilinx support web page. To maximize your search results, use proper keywords such as:

• Product name
• Tool message(s)

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 Appendix B: Debugging

• Summary of the issue encountered

A filter search is available after results are returned to further target the results.

Technical Support
Xilinx provides technical support at the Xilinx Support web page for this LogiCORE™ IP
product when used as described in the product documentation. Xilinx cannot guarantee
timing, functionality, or support if you do any of the following:

• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.

To contact Xilinx Technical Support, navigate to the Xilinx Support web page.

Debug Tools
There are many tools available to address System ILA design issues. It is important to know
which tools are useful for debugging various situations.

Vivado Design Suite Debug Feature

The Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly
into your design. The debug feature also allows you to set trigger conditions to capture
application and integrated block port signals in hardware. Captured signals can then be
analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a
design running in Xilinx devices.

The Vivado logic analyzer is used with the logic debug IP cores, including:

• ILA 2.0 (and later versions)

• VIO 2.0 (and later versions)

See the Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 6].

For more information on the ability to interact with the ILA core using Tcl Console
commands, see Chapter 5 in the Vivado Design Suite User Guide: Programming and
Debugging (UG908) [Ref 6].

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Hardware Debug
Hardware issues can range from link bring-up to problems seen after hours of testing. This
section provides debug steps for common issues. The Vivado debug feature is a valuable
resource to use in hardware debug. The signal names mentioned in the following individual
sections can be probed using the debug feature for debugging the specific problems.

General Checks
Ensure that all the timing constraints for the core were properly incorporated from the
example design and that all constraints were met during implementation. If using MMCMs
in the design, ensure that all MMCMs have obtained lock by monitoring the locked port.

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 Appendix C

Additional Resources and Legal Notices

Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.

Documentation Navigator and Design Hubs

Xilinx® Documentation Navigator provides access to Xilinx documents, videos, and support
resources, which you can filter and search to find information. To open the Xilinx
Documentation Navigator (DocNav):

• From the Vivado® IDE, select Help > Documentation and Tutorials.
• On Windows, select Start > All Programs > Xilinx Design Tools > DocNav.
• At the Linux command prompt, enter docnav.

Xilinx Design Hubs provide links to documentation organized by design tasks and other
topics, which you can use to learn key concepts and address frequently asked questions. To
access the Design Hubs:

• In the Xilinx Documentation Navigator, click the Design Hubs View tab.
• On the Xilinx website, see the Design Hubs page.
Note: For more information on Documentation Navigator, see the Documentation Navigator page
on the Xilinx website.

References
These documents provide supplemental material useful with this product guide:

1. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
2. Vivado Design Suite User Guide: Designing with IP (UG896)

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 Appendix C: Additional Resources and Legal Notices

3. Vivado Design Suite User Guide: Getting Started (UG910)

4. Vivado Design Suite User Guide: Logic Simulation (UG900)
5. ISE to Vivado Design Suite Migration Guide (UG911)
6. Vivado Design Suite User Guide: Programming and Debugging (UG908)
7. Vivado Design Suite User Guide: Implementation (UG904)
8. LogiCORE IP AXI Interconnect Product Guide (PG059)
9. LogiCORE IP AXI4-Stream Protocol Checker (PG145)
10. LogiCORE IP AXI Protocol Checker (PG101)
11. VLNV ( AR# 50478)

Training Resources
1. Designing FPGAs Using the Vivado Design Suite 1 Training Course
2. Vivado Design Suite QuickTake Video Tutorials

Revision History
The following table shows the revision history for this document.

Section Revision Summary

02/04/2021 Version 1.0
General Updates Version update.
10/05/2016 Version 1.0
IP Facts Updated IP Facts Introduction text.
04/05/2017 Version 1.0
Design Flow Steps Added interface parameters.
11/30/2016 Version 1.0
Debugging Updated the core name.
10/05/2016 Version 1.0
Initial Xilinx release N/A

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 Appendix C: Additional Resources and Legal Notices

Please Read: Important Legal Notices

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maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS
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