VLSI Physical Design with Timing Analysis

Lecture – 31: Min-cut placement

Bishnu Prasad Das

Department of Electronics and Communication Engineering

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 Contents
• Routing congestion
• Min-cut placement - Algorithm
• Min-cut placement – Examples
– Min-Cut Placement Using the KL Algorithm
– Min-Cut Placement Using the FM Algorithm

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 Routing congestion
• The ratio of demand for routing tracks to the supply of available routing
tracks.

SB CH SB CH

Wire capacities
• CH ⇒ horizontal routing tracks
• SB ⇒ horizontal and vertical routing tracks

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 Routing Congestion
• Estimated by the number of nets that pass through the boundaries of
individual routing regions.
• Formally, the local wire density φP(e) of an edge e between two
neighboring grid cells is
ηP(e)
φP(e) =
𝜎P(e)

ηP(e) = estimated number of nets that cross e

𝜎P(e) = maximum number of nets that can cross e
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 Routing congestion
• The wire density of P

ϕ P = max(φP(e))
e∈E
where E is the set of all edges.
• 𝛟 𝐏 ≤ 1 ⟹ design is estimated to be fully routable.
• 𝛟 𝐏 > 1 ⟹ routing will need to detour some nets
through less-congested edges.
Congestion-driven placement seeks to minimize ϕ P .

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 Example: Wire Density of a Placement
v3 v6
• Given: c
a
h5
– placement P of blocks a-f and their pins, h4 h6
v2 d v5 f

– nets N1-N3, h1
b
h2
h3

e
– local vertical cutlines v1-v6, v1 v4

– local horizontal cutlines h1-h6, and

– σP(e) = 3 for all local cutlines e ϵ E.
– N1 = (a1,b1,d2); N2 = (c1,d1,f1); N3 = (e1,f2).
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 Example: Wire Density of a Placement
• Task: find the wire density ϕ P and determine the routability of
P based on the RMST model.

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 Example: Wire Density of a Placement
v3 v6
• Horizontal edges: Vertical Edges: c
a
h5
– ηP(h1) = 1 ηP(v1) = 1 h4 h6
v2 d v5 f

– ηP(h2) = 2 ηP(v2) = 0 h1
b
h2
h3

e
– ηP(h3) = 0 ηP(v3) = 0 v1 v4

– ηP(h4) = 1 ηP(v4) = 0
– ηP(h5) = 1 ηP(v5) = 2
– ηP(h6) = 0 ηP(v6) = 0
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 Example: Wire Density of a Placement
v3 v6
• Maximum ηP(e) = 2. a
c
h5
h4
• ϕ P = ηP(e) / σP(e) = 2/3.
h6
v2 d v5 f
h1 h3
b
• Since ϕ P ≤ 1, P is estimated to be routable. h2
e
v1 v4

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 Min-cut placement
• Min-cut placement uses partitioning algorithms to divide

1. The netlist

2. The layout region into smaller, sub-netlists and sub-regions.

• This process is carried out till each subcircuit consists of a single

gate and has a unique place on the layout area.

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 Min-cut placement
• Each cut heuristically minimizes the number of cut nets.

• Standard algorithms used to minimize the number of cut nets are

– The Kernighan-Lin (KL) algorithm and

– The Fiduccia-Mattheyses (FM) algorithm.

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 Min-cut placement - Algorithm
• Input:

– netlist Netlist,

– layout area LA,

– minimum number of cells per region cells_min

• Output:

– placement P
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 Min-cut placement - Algorithm
1. P=Ø

2. regions = ASSIGN(Netlist,LA) // assign netlist to layout area

3. while (regions != Ø) // while regions still not placed

4. region = FIRST_ELEMENT(regions) // first element in regions

5. REMOVE(regions, region) // remove first element

of regions

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 Min-cut placement - Algorithm
6. if (region contains more than cell_min cells)
7. (sr1,sr2) = BISECT(region) // divide region into two sub-regions sr1 and sr2 ,
obtaining the sub-netlists and sub-areas
8. ADD_TO_END(regions,sr1) // add sr1 to the end of regions
9. ADD_TO_END(regions,sr2) // add sr2 to the end of regions
10. else
11. PLACE(region) // place region
12. ADD(P,region) // add region to P

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 Min-cut placement - Algorithm
• Min-cut optimization is performed iteratively, one cutline at a time

• Heuristic minimum cuts are found for the current sub-netlist, based on
the current sub-regions.

minimize(ψP(cut1)) → minimize(ψP(cut2)) → … → minimize(ψP(cut|Cuts|))

• Cuts denote the set of all cutlines made in the

layout region.

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 Min-cut placement
• Possible approaches to dividing the layout include

– Alternating cutline directions

– Repeating cutline directions

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 Alternating cutline directions
• The algorithm divides the layout by switching between sets of
vertical and horizontal cutlines.

• Suitable for standard-cell designs with high wire density in the

center of the layout region.

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 Alternating cutline directions
• Partitioning a region using alternating cutline directions
2a
4a 4c
3a 3b
4b 4d
1
4e 4g
3c 3d
4f 4h

2b

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 Repeating cutline directions
• The layout is divided using only vertical (horizontal) cutlines until
each column (row) is the width (height) of a standard cell.

• Then, the layout is divided using the orthogonal set of cutlines.

• Often results in greater wirelength because the aspect ratios of

the sub-regions can be very far from one.

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 Repeating cutline directions
• Partitioning a region using repeating cutline directions

4a 3a 4e
2a
4b 3b 4f
1
4c 3c 4g
2b
4d 3d 4h

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 Min-Cut Placement Using the KL Algorithm
cut1
• Given: 1
4
– circuit with gates 1-6 2
5 6
– 2 × 4 layout
3

– initial vertical cut cut1.

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Min-Cut Placement Using the KL Algorithm
• Task: find a 4 × 2 placement with minimum wirelength using
alternating cutline directions and the KL algorithm.

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Min-Cut Placement Using the KL Algorithm
• Converting the circuit netlist into a graph:
cut1 cut1
1
1 4
4
2
2 5
5 6
3 6
3

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Min-Cut Placement Using the KL Algorithm
• Since we need to find a 4 × 2 placement, let’s add two dummy
nodes to the graph.
cut1 cut1
1
1 4
4
2
2 5
5 6
3 6
3
0 0

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Min-Cut Placement Using the KL Algorithm
• After vertical cut cut1, L = {a,b,c} and R = {d,e,f }. Partition using
the KL algorithm.
cut1
Costs D(v) of each node:
1 4
D(1) = 1 D(4) = 1
D(2) = 1 D(5) = -1
2 5
D(3) = 1 D(6) = -1
D(0) = 0 D(0) = 0
3 6
g1 = D(3)+D(4)-2c(3,4)
0 0 = 1 + 1 – 2(0) = 2

Swap nodes 3 and 4.

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Min-Cut Placement Using the KL Algorithm
• Swap nodes 3 and 4.

cut1 cut1
1 4 1 4 5

2 5 2 3 6

3 6 0 0

0 0

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Min-Cut Placement Using the KL Algorithm
cut1
1 4 5

2 3 6

0 0

Horizontal cut cut2L, Horizontal cut cut2R,

T = {1,4}, B = {2,0} T = {3,5}, B = {6,0}.

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Min-Cut Placement Using the KL Algorithm
• After horizontal cut cut2L, T = {1,4}, B = {2,0}

Costs D(v) of each node:

1 4
cut2L D(1) = -1 D(4) = 0
D(2) = 1 D(0) = 0
2 0

No swapping because no g > 0.

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 Min-Cut Placement Using the KL Algorithm
• After horizontal cut cut2r, T = {3,5}, B = {0,6}

Costs D(v) of each node:

3 5
cut2R D(3) = -1 D(5) = 0
D(0) = 1 D(6) = 0
0 6

No swapping because no g > 0.

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Min-Cut Placement Using the KL Algorithm
• Make four vertical cuts cut3TL, cut3TR, cut3BL and cut3BR.

cut3TL cut3TR
1 4 5 3

0 2 6 0
cut3BL cut3BR

• Each region has only one node

– so terminate the algorithm.
Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Min-Cut Placement Using the KL Algorithm
• The final placement is:

cut3TL cut3TR 1 4 5 3
1 4 5 3

0 2 6 0
cut3BL cut3BR 2 6

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Min-Cut Placement Using the FM Algorithm
• Given: A cut1 B
a d
– circuit with gates a-g e
f

– ratio factor r = 0.5 b

g

– gate areas c

• area(INV) = 1, area(NAND) = 2, area(NOR) = 2

– initial partitioning with vertical cut cut1
– a 2 × 4 layout.
Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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 Min-Cut Placement Using the FM Algorithm
• Task: find a placement with minimum wirelength using
alternating cutline directions and using the FM algorithm.

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 Min-Cut Placement Using the FM Algorithm
• Initial vertical cut cut1: L = {a,b,c}, R = {d,e,f,g}.

• Balance criterion:

– 0.5×11 - 2 ≤ area(A) ≤ 0.5×11 + 2 = 3.5 ≤ area(A) ≤ 7.5

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 Min-Cut Placement Using the FM Algorithm
• Iteration 1: cut1
a d
Cell a: FS(a) = 1 TE(a) = 0 g(a) = 1 f
e
Cell b: FS(b) = 1 TE(b) = 0 g(b) = 1
Cell c: FS(c) = 1 TE(c) = 0 g(c) = 1 b
g
Cell d: FS(d) = 1 TE(d) = 1 g(d) = 0
Cell e: FS(e) = 0 TE(e) = 2 g(e) = -2 c
Cell f: FS(f) = 0 TE(f) = 2 g(f) = -2
Cell g: FS(g) = 1 TE(g) = 0 g(g) = 1

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 Min-Cut Placement Using the FM Algorithm
• Iteration 1: cut1
a d
Cell a: FS(a) = 1 TE(a) = 0 g1(a) = 1 f
e
Cell b: FS(b) = 1 TE(b) = 0 g1(b) = 1
Cell c: FS(c) = 1 TE(c) = 0 g1(c) = 1 b
g
Cell d: FS(d) = 1 TE(d) = 1 g1(d) = 0
Cell e: FS(e) = 0 TE(e) = 2 g1(e) = -2 c
Cell f: FS(f) = 0 TE(f) = 2 g1(f) = -2
Cell g: FS(g) = 1 TE(g) = 0 g1(g) = 1

• Cells a, b, c and g have maximum gain.

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 Min-Cut Placement Using the FM Algorithm
• Balance criterion for a:

– area(A) = area(b) + area(c) = 1+1 = 2

– 3.5 ≤ area(A) ≤ 7.5 → Violated

• Balance criterion for b:

– area(A) = area(a) + area(c) = 2+1 = 3

– 3.5 ≤ area(A) ≤ 7.5 → Violated

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 Min-Cut Placement Using the FM Algorithm
• Balance criterion for c:
– area(A) = area(a) + area(b) = 2+1 = 2
– 3.5 ≤ area(A) ≤ 7.5 → Violated
• Balance criterion for g:
– area(A) = area(a) + area(b) + area(c) + area(g)
= 2+1+1+2 = 6
– 3.5 ≤ area(A) ≤ 7.5 → Not violated

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 Min-Cut Placement Using the FM Algorithm
• Move gate g
cut1 cut1
a d a d
f f
e e

b b
g g

c c

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 Min-Cut Placement Using the FM Algorithm
• Iteration 2: cut1
a d
f
Cell a: FS(a) = 1 TE(a) = 0 g2(a) = 1 e
Cell b: FS(b) = 0 TE(b) = 0 g2(b) = 0
Cell c: FS(c) = 0 TE(c) = 1 g2(c) = -1 b
g
Cell d: FS(d) = 1 TE(d) = 1 g2(d) = 0
c
Cell e: FS(e) = 0 TE(e) = 2 g2(e) = -2
Cell f: FS(f) = 0 TE(f) = 2 g2(f) = -2

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 Min-Cut Placement Using the FM Algorithm
• Iteration 2: cut1
a d
f
Cell a: FS(a) = 1 TE(a) = 0 g(a) = 1 e
Cell b: FS(b) = 0 TE(b) = 0 g(b) = 0
Cell c: FS(c) = 0 TE(c) = 1 g(c) = -1 b
g
Cell d: FS(d) = 1 TE(d) = 1 g(d) = 0
c
Cell e: FS(e) = 0 TE(e) = 2 g(e) = -2
Cell f: FS(f) = 0 TE(f) = 2 g(f) = -2

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 Min-Cut Placement Using the FM Algorithm
• Balance criterion for a:

– area(A) = area(b) + area(c) + area(g)

= 1+1+2 = 4

– 3.5 ≤ area(A) ≤ 7.5 → Not violated

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 Min-Cut Placement Using the FM Algorithm
• Move gate a
cut1
a d a d
f f
e e
cut1
b b
g g

c c

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 Min-Cut Placement Using the FM Algorithm
• Further selection steps result in negative Δg and are omitted.

• Maximum positive gain G2 = Δg1 + Δg2 = 2

• After cut cut1, L = {a,d,e,f }, R = {b,c,g}, cut cost = 1

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 Min-Cut Placement Using the FM Algorithm
• After cut cut2T, T = {a,d}, B = {e,f }, cut cost = 1
cut2T cut2T
a d a d
f f
e e
cut1 cut1
b b
g g

c c

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 Min-Cut Placement Using the FM Algorithm
• After cut cut2B, T = {c}, B = {b,g}, cut cost = 1
cut2T cut2T
a d a d
f f
e e
cut1 cut1
b b
g g

c c

cut2B

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 Min-Cut Placement Using the FM Algorithm
• Make three more cuts cut3TL, cut3TR and cut3BR such that every
sub-region has one gate.
cut3TL cut
2T

a d
f
e
cut1
b
cut3BR g

cut2B

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 Min-Cut Placement Using the FM Algorithm

Source: A. B. Kahng et al., VLSI Physical Design: From Graph Partitioning to Timing Closure

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Thank You

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