COMPUTER ARCHITECTURE 1.1 1.

2 Arithmetic Unit

CHAPTER III From the 4 basic operations it is possible to formulate other

arithmetic functions and solve scientific problem by means of
ARITHMETIC UNIT numerical analysis methods.
3.1 THE ARITHMETIC AND LOGIC UNIT An arithmetic processor is the part of a processor unit that
The ALU performs arithmetic and logical operations on data. executes arithmetic operation. The data type assumed to reside
All other components of computer system brings data into ALU in processor register during the execution of an arithmetic
for processing. The information handled in a computer is instruction, is specified in the definition of the instruction. An
generally divided into “words”, each consisting of fixed number arithmetic instruction is specified in the definition of the
of bits for eg., if the words handled by a microcomputer is 32 instruction. An arithmetic instruction may specify binary or
bits in length, the ALU would have to be capable of performing decimal data and in each case the data may be fixed point or
arithmetic operations on 32 bits words. Data are presented to floating point form. Fixed-point number may represent integers
the ALU in registers and the results of an operation are stored or fractions. Negative number may be in signed-magnitude or
in registers. The control unit coordinates the operations of the signed-complement form.
ALU and the movement of the data in and out of the ALU. A step-by-step procedure involved in solving any problem is
Most computers have one or more registers called accumulator, called an algorithm. In this chapter we develop the various
or general purpose registers. The accumulator is the basic register arithmetic algorithms and show the procedure for implementing
containing one of the operands during operations in ALU. If the them with digital hardware. We consider the addition, subtraction,
computer is instructed to add, the number stored in the multiplication and division for the following types of data.
accumulator is augend and the addend will be located and these
1. Fixed-point (data) binary data in signed-magnitude
operands (addend & augend) are added up and the result is
representation.
stored back in the accumulator. The original augend will be lost
in accumulator after addition. 2. Fixed-point binary data in signed 2’s complement
representation.
Arithmetic operations
3. Floating-point binary data
Arithmetic instruction in digital computers manipulates data
to produce result necessary for the solution of computational 4. Binary-coded decimal (BCD) data
problem. These instructions perform arithmetic calculation and Fixed point ALU
are responsible for bulk of activity in processing data in a
computer. The 4 basic arithmetic operations are The following fig shows the most widely used ALU design.
It is intended to implement multiplication and division using one
1) Addition of the sequential digit by digit shift and add/ subtract algorithms.
2) Subtraction Three one word registers are used for operand storage:
3) Multiplication Accumulator AC, the Multiplier Quotient register MQ and the
4) Division data register DR. AC and MQ are organized as a single register

Chap–III 1
COMPUTER ARCHITECTURE Arithmetic Unit

AC.MQ capable of left and right shifting. The main additional Bit -sliced ALU
data processing capability is provided by the parallel adder that
It is possible to construct an entire fixed point ALU on a
receives inputs from AC and DR and places its results in AC.
The MQ register is so called because it stores the multiplier single IC chip especially if the word size m is kept fairly
during the multiplication operation, and quotient during the small ex: 4 or 8 bits. Such an m-bit ALU can be designed to
division operation. DR stores the multiplicand or the divisor be expandable in that k copies of the ALU chip can be
while the result is stored in AC.MQ. connected to form a single ALU capable of processing km-bit
In many instances DR serves as a memory buffer register to operands directly. The resulting array like circuit is called bit
store data addressed by the instruction address field ADR. sliced because each component chip processes an independent
System Bus slice of m bits from each km bit operand. Bit sliced ALU’ s
have advantage that any desired word size or even several
different word sizes can be handled by selecting the appropriate
A ccu m u lato r (A C ) M u ltiplier – Q u o tient D ata R egister (D R ) number of components (bit slices) to use.
R egister M Q

The following fig shows a 16-bit ALU can be constructed

from 4-bit ALU slices. The data buses and registers of the
P arallel A d d er individual slices are placed to increase their sizes from 4 to 16
A n d L o gic C on tro l
circu its u nit bits. The control lines that select and sequence the operation
F lags to be performed are connected to every slice. .so that all slices
Fig: Block diagram of fixed point ALU execute the same operation in step with one another. Each
slice performs the same operation on a different 4-bit part
Addition → AC ← AC + DR
(slice) of the input operands ,and produces only the
Subtraction → AC ← AC - DR corresponding part of the results. The required control lines
Multiplication → AC. MQ ← DR * MQ are derived from an external control unit which is usually micro

{
programmed. Certain operations require information to be
Division → AC. MQ ← MQ / DR MQ – Quotient
exchanged between slices. For ex if a shift operation is to be
AND → AC ← AC ^ DR AC – Reminder implemented then each slice must send a bit to and receive a
OR → AC ← AC V DR bit from left or right neighbors .Similarly when performing
addition the carry bits may have to be transmitted between the
XOR → AC ← AC .XOR. DR neighboring slices.
NOT → AC ← AC *

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COMPUTER ARCHITECTURE Arithmetic Unit

Data in (16 bits) Data out (16 bits) 3.2.1 Signed-Magnitude Representation
The positive and negative numbers are differentiated by
treating the most significant bit in the word as a sign bit.
If the sign bit is 0, the number is positive
If the sign bit is 1, the number is negative
+18 = 0 0 0 1 0 0 1 0
R(0:3) R(4:7) R(8:11) R(12:1
5) ↓ ↓
one sign bit seven bit magnitude
ALU ALU ALU ALU
Range : − ( 2 − 1) to + ( 2 − 1)
Circuits Circuits Circuits Circuits n −1 n −1
Cout cin

Control Control Control Control Eg. A 7 bit register can store numbers from –63 to +63
circuits circuits circuits circuits
Drawbacks
1. Addition and subtraction requires both the sign bit and
magnitude bits to be considered.
External control signals
2. Two representation for zero (0)
Fig: Bit Sliced ALU
+0 → 00000000
3.2 INTEGER REPRESENTATION FIXED POINT –0 → 10000000
The numbers used in digital machines are represented using 3.2.2 Two’s Complement Representation
binary digits 0 and 1. The storage element called flipflops can
In two’s complement system, forming the 2’s complement
hold this digits. Group of flip flops forms a register in computer
of a number is done by subtracting that number from 2N.
systems.
Eg. Representation of –4
Eg. The number 41 can be represented as
In Sign-magnitude 1100
00101001 [8 bit representation]
In 1’s complement 1011
Thus if a register contains 8 bits, a signed binary number
In 2’s complement 1100
in the system will have 7 magnitude bits or integer and a single
sign bit and the system is called signed magnitude binary integer Advantages
system. i. Only one arithmetic operation is required while subtracting
Eg. +18 = 00010010 using 2’s complement notation.
–18 = 10010010 ii. Used in arithmetic applications.

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COMPUTER ARCHITECTURE Arithmetic Unit

Sign Extensions 3.3.1 Full Adder

It is sometimes desirable to take an n-bit integer and store A full adder is a combinational circuit that forms the
it in m bits, where m > n. arithmetic sum of three input bits. It consists of three inputs and
two outputs. Two of the input variables denoted by x and y,
To do this,
represent the two significant bits to be added. The third input,
In sign-magnitude notation, z represents the carry from the previous lower significant position.
• simply move the sign bit to the new leftmost position The two outputs are designated by symbols S for sum and C for
and fill in with zeros. carry. The binary variable S gives the value of the least
significant bit of the sum. The binary variable C gives the output
In 2’s complement notation
carry.
• Move the sign bit to the new leftmost position and fill
it with copies of the sign bit. x
Full C
y
• For +ve no’s fill it with zeros. Adder S
z
• For –ve no’s fill it with ones.
Eg. +18 = 0 0 0 1 0 0 1 0 ← 8 bit notation Previous
Carry
= 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 ← 16 bit notation in sign magnitude
Truth Table
–18 = 1 1 1 0 1 1 1 0 ← 2’s complement 8 bit notation
x y z C S
= 100000000110110 ← 2’s complement 16 bit notation
0 0 0 0 0
Both the sign-magnitude and 2’s complement representation
0 0 1 0 1
discussed above are often called as fixed point notation as the
0 1 0 0 1
decimal point (binary) read point is fixed and assumed to be to
the right of the rightmost digit. 0 1 1 1 0
1 0 0 0 1
3.3 INTEGER ARITHMETIC
1 0 1 1 0
Arithmetic operations occur at the machine instruction level. 1 1 0 1 0
These arithmetic operations are implemented in the ALU of the 1 1 1 1 1
processor. As given above, arithmetic operations are performed
on fixed point, floating point and binary coded decimal data. In the truth table, when all input bits are 0’s, the output is
In both fixed point signed magnitude notation and 2’s 0. The S output is equal to 1 when only one input is equal to
complement notation, the sign bit is treated as the same as the 1 or when all three inputs are equal to 1. The C output has a
other bits. carry of 1 if two or three inputs are equal to 1.

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COMPUTER ARCHITECTURE Arithmetic Unit

Hardware Implementations Note

When k-map is drawn for S and C, we have Overflow occur
For S 1. When the signs of the two operands are the same and
yz x 0 1 if the sign of the result is different.
00 1
01 1
Two circuits are possible to check overflow.
11 1 1. Implementing the expression
10 1
Overflow = x n −1 yn −1 Sn −1 + x n −1 yn −1 Sn −1

For C ∴ S = x y z + x y z + xyz + x y z 2. Implementing the expression

xy z 0 1 S= x⊕y⊕z Overflow = C n ⊕ C n −1
00
01 1
Note
11 1 1
10 1 i) If the overflow occurs, the ALU must signal this fact
so that no attempt is made to use the result.
C = xy + xz + yz
ii) Overflow can occur whether or not there is a carry.
z is carry-in, therefore
3.3.2 4-bit binary adder
x
y To implement the add micro operation with the hardware
xi Si x C we need the register that hold the data and the digital component
yi z
zi
that perform the arithmetic addition. The digital circuit that
y performs the arithmetic sum of two bits and a previous carry is
z
called a Full adder. The digital circuit that generates the
Thus the logic expression for Si can be implemented with arithmetic sum of two binary numbers of any length is called
a 3 input XOR gate and logic expression for C out(C) is the binary adder.
implemented with a two-level AND–OR logic circuit. The binary adder circuit can be constructed with full adder
A cascaded connection of n full adder can be used to add circuits connected in cascade. Here the output carry from one
two n-bit numbers. Since the carry propagates or ripples, this full adder can be connected to the input carry of the next full
cascade of full address is called n-bit ripple carry-adder. adder. The augends bits of X and the addend bits of Y are
designated by subscript numbers from right to left as shown
To perform the subtraction operation X-Y on 2’s complement
below. The carries are connected in chain through to full adders.
numbers X and Y, 2’s complement of Y is added to X.
The input carry to the binary adder is the C0 and the output

Chap–III 5
COMPUTER ARCHITECTURE Arithmetic Unit

carry to the binary adder is the C4. The S outputs of the full For signed numbers the result is (X-Y) provided there is no
adders generates the required sum bits. overflow.
The n-bit binary adder requires n-full adders. The n-data
bits for the X inputs are from one register R1 and n-data bits for Y3 Y2 Y1 Y0
the Y input come from another register R2. The sum can be transferred
to the third register or one of the source register. (R1 or R2)
M
Y3 X3 Y2 X2 Y1 X1 Y0 X0
xor X3 xor X2 xor X1 xor X0

FA C3 FA C2 FA C1 FA Cin
FA FA FA FA
C3 C2 C1 Cin
Cout S3 S2 S1 S0
Fig: 4-Bit Binary Adder Cout S3 S2 S1 S0

3.3.3 4- bit Binary adder / sub tractor

Fig: Binary Adder/ Sub tractor
The subtraction of binary numbers can be done by means of
complements. The subtraction of X and Y i.e X-Y can be done 3.3.4 4-bit binary arithmetic circuit
by taking the 2’s complement of Y and adding it to X. The 2’s
complement can be obtained by taking the 1’s complement and The 4-bit arithmetic circuit has four full adders. Constitutes
adding 1 to it. The addition and subtraction can be combined in a 4-bit adder and 4 MUX for choosing different operation.
one circuit by including the XOR gate with each full adder. The There are two 4-bit inputs A and B and 4-bit output D. The
mode input M controls the operation. When M = 0 the circuit is 4 inputs from a go directly to the X input of the binary adder.
an adder, when M = 1 the circuit is a subtractor. Each XOR Each of the 4 inputs of the B are connected to the data input
gate receives input M and one of the inputs of B. When M = 0 of the MUX. The MUX data inputs also receive the complement
we have Y 0 = Y. The full adder receives the value of B.
of B. The other two data inputs are connected to logic 0. and
the input carry is 0, and the circuit performs the X plus Y.
logic 1. The 4 MUX are controlled by selection inputs S0 and
When M = 1 we have have Y 1 = Y and C0 = 1. The S1. The input carry Cin goes to the carry input of the FA in the
Y inputs are all is complemented and 1 is added through the LSB. The other carries are connected from one stage to another.
input carry. The circuit performs X plus 2’s complement of Y.
The output of the binary adder is calculated from the
For unsigned numbers this gives the X – Y if X >= Y or the following arithmetic sum.
2’ s complement (Y–X) if X < Y.

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COMPUTER ARCHITECTURE Arithmetic Unit

D = X + B + Cin Cin C0
S1 X0
Æ 4 bit binary number at A inputs.

v
X A0
S0 FA
Y Æ 4 bit binary number at B inputs. S0 D0

vv vv vv

v
S1 B0
0 4X 1
Cin Æ Input carry which can be 0 or 1. Y0
1 M UX
Y0* 2
0 C1
By controlling the value of Y with two selection inputs S0 3
1
X1

v
and S1 and making Cin equal to 0 or 1 it is possible ot generate A1
FA
8 possible arithmetic operations. S0 B1
D1

v v vvv

v
S1
Y1 0 4X 1
Addition: When S1S0 = 00, the value of B is applied to the Y1 1 M UX
Y input of the adder. If Cin = 0 the output D = X + Y. If Cin = 1 0 2
1 3 C2

v
then the output is D = X + Y + 1. Both cases perform the add
A2
micro operation with or with out carry. X2

v
FA D2
Subtraction: When S1S0 = 01, the complemented value of Y S0 B2

vvv

v
S0
is applied to the B input of the adder. If C in = 0 the Y2 S1
S1 4 X 1
01 M U X
Y2

vv
output D=X+(Comp)Y. This is equivalent to D = X–Y-1. If 10
0
Cin = 1 then the output is D = X+(Comp)Y+1.This produces X 21

v
1 32 C3
plus the 2’s complement of Y, which is equivalent to X–Y. Both
X3 A3

v
cases perform the subtraction micro operation with or with out
borrow. FA D3
B3

v
vv
S0
S1
When S1S0=10 the input from the B are neglected all 0’s Y3

v
0 4X 1 Cout
Y3 1 M UX

vv
are applied to the B input The output becomes D = X+1
0 2
1 3

v
When S 1S 0 = 11 all 1’s are inserted in to B input of the
adder to produce the Decrement operation. D = X-1, When Cin = 0. 3.3.5 Addition & Subtraction of Signed Numbers
This is because the number with all 1’s equal to 2’s complement
We designate the magnitude of two number by A and B.
of 1. (2’s complement of 0001 = 1111). Adding a number A to
When signed number are added or subtracted we find that there
the 2’s complement of 1 produce D= X-1. are 8 different condition to consider, depending on the sign of
When Cin = 1 then D = X-1+1 = X the number and the operation performed. These conditions are
listed in the following table (1st column). The other columns

Chap–III 7
COMPUTER ARCHITECTURE Arithmetic Unit

show the actual operation to be performed with the magnitude to a 3rd register. However a saving is achieved by transferring
of the number. The last column is needed to prevent -0. the result into X and Xs. Thus X and Xs together form an
When two equal number are subtracted the result should be +0 accumulator register.
not -0.
Consider now the hardware implementation of the algorithm
Operation Add Magnitudes Subtract Magnitudes When above.
X >Y X<Y X =Y 1) First a parallel adder is needed to perform the micro
(+X) + (+Y) +(X+Y) operation X + Y.
(+X) + (-Y) + (X - Y) - (X - Y) + (X - Y) 2) A comparator circuit is needed to establish if X > Y, X = 0
(-X)+(+X) - (X - Y) + (X - Y) + (X - Y) or X < Y.
(-X) + (-Y) _- (X + Y) 3) Two parallel subtract circuits are needed to perform the micro
(+X) - (Y) + (X - Y) - (Y - X) + (X - Y) operation X – Y and Y – X
(+X) - (-Y) + (X + Y) 4) The sign relation can be determined from an XOR gate
(-X) - (+Y) - (X + Y) with Xs and Ys input.
(-X) - (-Y) - (X - Y) + (Y - X) + (X - Y) This procedure required a magnitude comparator, an adder,
and two subtractions. However a different procedure can be found
Addition Algorithm: that required less equipment.
a) When the signs of X and Y are identical add the two a) First we know that subtraction can be accomplished by means
magnitudes and attach the sign of X to the result. of complement and addition.
b) When the signs of X and Y are different compare the b) The result of a comparison can be determined from the end
magnitude and subtract the smaller number from the larger. carry after the subtraction.
Choose the sign of the result as X if X > Y or complement
The following fig shows the hardware implementation of
of the sign of X if X < Y.
the addition and subtraction operation. It consists of register
c) If the two magnitudes are equal, subtract Y from X and X and Y and sign flip flop Xs and Ys. Subtraction is done
make the result positive. by adding X to the 2’s complement of Y. The output carry
Hardware Implementation: is transferred to flip flop E. Where it can be checked to
determine the relative magnitude of the two numbers. The
To implement the two arithmetic operations with hardware
add-overflow flip flop VF holds the overflow bit when X
it is first necessary that the two numbers be stored in register.
and Y are added. The register provides other micro operation
Let X and Y be two register that hold the magnitude of the
that may be needed when we specify the sequence of steps
number and Xs and Ys be two flip flop that hold the
in the algorithm.
corresponding signs. The result of operation may be transferred

Chap–III 8
COMPUTER ARCHITECTURE Arithmetic Unit

The addition of X plus Y is done through the parallel adder. XOR gate is 0 the signs are (equal) identical, if it is 1 the signs
The S (Sum) output of the adder is applied to the input of are different.
the X register. The complement provides an output of Y or
1. For an addition operation the identical signs dictate that the
complement of Y depending on the state of mode control
magnitude be added.
M. The complementor consists of XOR gates and the parallel
adder consists of full-adder. The M signal is applied to the 2. For subtraction operation different signs dictate that
input carry of the adder. magnitude be added..

1. When M = 0, the output of Y is transferred to the adder, 3. For magnitude are added with a micro operation.
the input carry is 0 and the output of the adder is the EX Å X + Y, Where EX Å Reg that combines that combines
sum X + Y. E and X. The carry in E after the addition constitutes an
2. When M=1, the 1’s complement of Y is applied to the overflow if it is equal to 1.
adder, the input carry is 1 and the output S = X + Y +1. The value of E is transferred into the add-overflow flip-flop
This is equal to A plus 2’s complement of B. Which is VF.
equal to the subtraction X – Y.
4. The two magnitude are subtracted if the two signs are
Ys Y Register different for an addition operation or identical for subtract
operation. The magnitude is subtracted by adding X to the
number are subtracted so VF is cleared to 0.

VF Complementor 5. A 1 in E indicates that X ≥ Y and the number in X is the

M (Mode Control)
correct result. If this number is zero the sign Xs must be
made positive to avoid a negative zero.
O/P
6. A zero in E indicates that X < Y. For this case it is necessary
E Parallel Adder I/P Carry to take the 2’s complement of the value in X. This operation
Carry can be done with the micro operation X Å X + 1. However
we assume that the X register has circuits function micro
Xs X Register operation complement and increment. So the 2’s complement
Load Sum is obtained from these two micro operation. In other paths
Fig:- H/W for Signed-Magnitude addition and Subtraction of the flow charts the sign of the result is the same as the
sign of X, so no change in Xs is required. When X < Y the
H/W Algorithm sign of the - result is the complement of the original sign
of X. It is then necessary to complement Xs to obtain the
The flow chart for the H/W algorithm is shown below. The two correct sign. The final result is found in register X and its
signs As and Bs are compared by XOR gate. If the output of sign in Xs. The value in VF provides an overflow indication.

Chap–III 9
COMPUTER ARCHITECTURE Arithmetic Unit

The final value of E is immaterial. same as the other bits of the number. A carryout of the sign-bit
position is discarded. The subtraction consists of first taking 2’s
Subtract operation Add operation
complement of the subtrahend and then adding it to the minuend.

Minuend in X Augend in X When two numbers of n digits each are added and the sum
Subtrahend in Y Addend in Y occupies n+1digits. We say that an overflow occurred. An
overflow can be detected by inspecting the last two carries out
= 0 Xs (+) Ys = 1 =1 Xs (+) Ys = 0 of the addition. When the two carries are applied to the XOR
gate the overflow is detected when the output of the gate is
Xs=Ys Xs≠Ys Xs≠Ys Xs=Ys equal to 1.
EX Å X+Y+1 EA Å X+Y The register configuration for hardware implementation is
VF Å 0 shown in the figure below. This is same as the figure above but
the sign bits are not separated from the rest of the register. We
VF Å E
= 0 E = 1 name the X register XS (Accumulator) and the Y register YS.
X<Y X≥Y The left most bit in XS and YS represents the sign bits of the
number. The two sign bits are added or subtracted together with
XÅ X' ≠ 0 =0
X the other bits in the completes and parallel adder. The overflow
flip-flop V is set to 1 if there is an overflow. The output carry
XÅX+1
Xs Å Xs’ Xs Å 0 in this case is discarded.

YS register

END
(Result in X and Xs)
V Complementer & parallel adder
Fig: - Flow chart for add and subtract operation
Overflow
3.3.5.1 Addition and subtraction with signed 2’s complement data
XS register
The left most bit of a binary number represents assign bit
0Æ positive, 1Æ negative. If the sign bit is 1 the entire number The algorithm for adding and subtracting two binary number
is represented in 2’s complement form. in signed 2’s complement is shown below. The sum is obtained
Thus +33 Ex: is represented as 00100001 and by adding the contents of XS and YS (including their sign bits).
-33 as 11011111. Note that 11011111 is the 2’s complement The overflow bit V is set to 1 if XOR of the last two carries
of 00100001 and vice versa. is 1 and it is cleared to 0 otherwise.

The addition of two numbers in signed 2’s complement form The subtract operation is accomplished by adding the content
consists of adding the number with the sign bits treated the of Ac to the 2’s complement of YS. Taking the 2’s complement

Chap–III 10
COMPUTER ARCHITECTURE Arithmetic Unit

of YS has the effect of changing a positive number to negative Subtraction

and vice versa. An overflow must be checked during these +125 01111101
operation because the two number added could have the same (–) (+)
sign. +90 1 0 1 0 0 1 1 0 ← 2’s complement of 90.
Comparing this algorithm to its signed magnitude counter +35 1 00100011
part we note that it is much simpler to add and subtract number discard Carry
if negative number are maintained in signed 2’s complement
adopt this representation over the more familiar signed magnitude. 3.3.6 Design of Fast address

Subtract Add Carry Propagation

The addition of two binary numbers in parallel implies
that allthe bits of the augend and the addend are available for
Augend in XS
Minuend in XS Addend in YS computation at the same time.
Subtrahend in YS
The parallel address are ripple carry types in which the
XS← XS + YS +1 XS←XS +YS
carry output of each full adder stage is connected to the carry
V← Overflow V ← Overflow input of the next higher-order stage. The sum of carry outputs
of any stage cannot be produced unitl the input carry occurs.
This lead to a time delay in the addition process.
END END
The carry propagation delay for each full adder is the time
Fig: - Algorithm for addition& Subtraction-2’s Complement representation from the application of the input carry until the output carry
Eg. occurs, assuming that the P and Q inputs are present.
Addition Full adder 1 cannot produce a potential carry output until
a carry input is applied. i.e. the input carry to the least
significant stage has to ‘ripple’ through all the adders before
+74 01001010
+ the final sum is produced. A cumulative delay through all of
+69 01000101 the adder stages is a ‘worst-cast’ addition time. The total delay
10001111 can vary, depending on the carries produced by each stage. If
two numbers are added such that no carriers occurs between
Carry in 1 [Overflow] stages, the add time is simply the propagation time through a
has detected
and hence Cn is not single full adder from the application of the data bits on the
Carry out 0
part of the answer inputs to the occurrence of a sum output.

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COMPUTER ARCHITECTURE Arithmetic Unit
X3 Y3 X2 Y2 X1 Y1 X0 Y0 Propogate Pi = x i +y i
C3 C2 C1 C0 FA0 For first full addeer
FA3 FA2 FA1 FA0
C1 = G 0 +C 0 P0
C4 C3 C2 C1 FA1 For second full addeer
S3 S2 S1 S0 C 2 = G1 +C1P1
3.3.6.1 The Look Ahead Carry Adder
= G1 + P1 ( G 0 + C0 P0 ) [∵ C1 = G 0 + P0 C0 ]
In parallel adder, the speed with which an addition can be
performed is limited by the time required for the carries to ∴ C 2 = G1 + G 0 P1 + C0 P1P0
propagate or ripple through all of the stages of adder. One method Similarly
of speeding up this process is by climinating this ripple carry
C3 = G 2 +C 2 P2
delay is called Look-Ahead Carry addition and is based on two
functions of the full adder called the carry generate and the = G 2 + (G1 + G 0 P1 + C0 P1P0 ) P2
carry propagate function
= G 2 + G1 P2 + G 0 P1P2 + C0 P2 P1 P0
Xi Pi
Yi Si
In all the above expressions, the carry output for each full
-adder stage is dependent only on the initial input carry (C0), its G0
and P0 functions and the G and P functions of the preceeding stages.
Gi
Since, each of the G and P functions can be expressed in
C i+1
terms of the x and y inputs to the full adders, all of the output
Ci carries are immediately available and the adder circuit need not
Fig. Full-Adder-Bit Stage Cell. have to wait for a carry to ripple through all of the stages
before a final result is achieved. Thus the look ahead carry
From the full adder circuit, technique speeds up the addition process.
X 3 Y3 X2 Y2 X1 Y1 Y0
Si = x i ⊕ yi ⊕ ci
C4 C3 C2 C1 C0
ci+1 = x i yi + yi ci + ci x i FA FA FA FA

= x i yi + ci + ( x i + yi ) G3 P3 G2 P2 G1 P1 G0 P0
S3 S2 S1 S0
Generate G i = x i yi Carry Look-ahead Logic
Now the expression for the carry out co. of each full adder I I
G0 P0
stage for the four bit example. Fig. 4-bit adder.

Chap–III 12
COMPUTER ARCHITECTURE Arithmetic Unit

In general, the final expression for any carry variable is In the above fig., the carryout C4 from the low order adder
is available 3 gate delays after the input operands X, Y and C0
Ci+1 = G i + Pi G i −1 + Pi Pi −1G i − 2 + .......... are applied to the 16 bit carry lookahead adder.
+ Pi Pi −1 ........ Pi G 0 + Pi Pi −1 ....... P0 G 0
C8 is available after a further 2 gate delays, C12 is available
after a further 2 gate delays and C16 is available after a further
All carries can be obtained three gate delays after the input
2 gate delays.
signals X, Y and C0 are applied because only one gate delay is
needed to develop all Pi and Gi signals, and followed by two (i.e.) C16 is available after a total of
gate delays in the AND-OR circuit for Ci+1 (See fig. Full-
(3×2) + 3 = 9 gate delays
Adder-Bit stage cell)
If a ripple carry adder is used, C16 is available only after 31
After a further XOR gate delay, all sum bits are available.
gate delays for S15 and 32 gate delays for C16.
Therefore, independent of n, the n-bit addition process requires
only four gate delays. Higher-Level generate and propagate functions

Delays in Carry Look ahead adder By using Higher-Level block generate and propagate
X15-12 Y15-12 X11-8 Y11-8 X7-4 Y7-4 X3-0 Y3-0 functions, it is possible to use the lookahead approach to develop
the carries C4, C8, C12 ....... in parallel in a higher-level carry
C16 C12 C8 C4 lookahead circuit.
4 bit 4 bit 4 bit 4 bit C0
adder adder adder adder In Fig. 16 bit Carry Look Ahead Adder

I I S15-12 II II S11-8 II I S7-4 I I S3-0 POI = P3 P2 P1 P0 &

G3 P3 G2 P2 G1 P1 G0 P0
G = G 3 + P3G 2 + P3 P2 G1 + P3 P2 P1G 0
I
O
Carry Look-ahead Logic
and
1I
G0 P0
1I C16 can be
Fig. 16 bit Carry-Lookahead adder built from 4-bit adders.
C16 = G 3I + P3I G I2 + P3I P2I G1I + P3I P2I P1I G 0I + P3I P2I P1I P0I C0
In carry-look ahead 4-bit adder, all carries are obtained three
gate delays after the input signals X, Y and C0 are applied Gate-delays when higher level block generate and propagate
because one gate delay is needed to develop all Pi and Gi signals functions are used
followed by two gate delays in the AND-OR circuit for Ci+1. Carry generated internally by the 4-bit adder blocks are not
After a further XOR gate delay, all sum bits are available. needed because they are generated by the higher-level carry
Therefore independent of n, the n-bit addition process requires lookahead circuits.
only four gate delays.

Chap–III 13
COMPUTER ARCHITECTURE Arithmetic Unit

The sign of the product is determine from the signs of

G Ik & PkI are produced after 3 gate delays after the generation
the multiplicand and multiplier. It they are alike the sign
of Gi and Pi. of the product is positive. It they are unalike the sign of
The delay in developing the carries produced by the carry the product is negative.
lookahead circuits is two gate delays more than delay needed to Multiplication algorithm using signed - Magnitude data
I I
develop G & P k k 1) I n s t e a d o f p r o v i d i n g r e g i s t e r t o s t o r e a n d a d d
and hence totally 5 gate delays after X, Y and C0 are applied simultaneously as may binary number as there are bits
as inputs. Then the sum is produced after further 3 gate delays in the multiplier, it is convenient to provide an adder
for the summation of only two binary numbers and
(C15 after 2 gate delays when C12 is available and 1 further gate
successively accumulate the partial products in a
delay) thus totally 8 gate delays. Therefore when cascaded 4 bit
register.
adder is used, S15 and S16 are available after 10 and 9 gate
delays. When higher level carry lookahead adder is used, S15 2) Instead of shifting the multiplicand to the left, the
and C16 are available after 8 and 5 gate delays. partial product is shifted to the right, which results in
leaving the partial product and the multiplicand in the
3.3.7 Multiplication of positive numbers
required (Position) relations.
Multiplication of two fixed-point binary numbers in signed-
3) When the corresponding bit of the multiplier is 0 there
magnitude representations is done by a process of successive
is no need to add all zeros to the partial product since
shift and add operations.
it will not alter its value.
Ex:- 11 1 0 1 1 Multiplicand The H/w implementation for the multiplication is shown
9 1 0 0 1 Multiplier below. The multiplier is stored in the Q register and its
1011 sign in Qs. The sequence counter SC is initially set to a
0000 + number equal to the number of bits in the multiplier. The
0000 counter is decremented by 1 after forming each partial
1 0 11 product. When the content of the counter reaches zero, the
product is formed and the process stops.
99 1100011
Initially, the multiplicand is in register Y and the
The process consists of looking at successive bits of the
multiplier in Q. the sum of X and Y forms a partial
multiplier, LSB first. If the multiplier bit is a 1 the multiplicand
product, which is transferred to the EX reg. Both partial
is copied down; otherwise zeroes are copied down. The number
product and multiplier are shifted to the right. This shift
copied down in successive lines are shifted one position to the
will be denoted by the statement Shr EXQ to designate the
left from the previous number finally the number are added and
right shift depicted.
their sum forms a product.

Chap–III 14
COMPUTER ARCHITECTURE Arithmetic Unit

After the initialization the low order bit of the multiplier

Register X (initially 0)
in Qn is tested if it is a 1, the multiplicand in Y is added to
E Xn-1 . . . . . . . . X0 Qn-1 . . . . . . . . Q0 the present partial product in X. If it is 0 nothing is done.
Multiplier Q Register EXQ is then shifted once to the right to form the new
partial product. The sequence counter SC is decremented by I
Add/No add
control and its mew value is cheeked if it is not equal to zero the
n bit process is repeated and the new partial is formed. The process
adder Control s to ps when SC=0 note that the partial product in X is shifted
MUX
Sequence in to Q one bit at a time and eventually replaces the multiplier
the final product is available in both X and Q. With A holding
0 0
the MSBs and Q holding LSBs
Yn-1 . . . . . . . . Y0
Multiply Operation
Multiplicand Y
Fig:- H/w for multiply Operation Multiplicand in Y
Multiplier in Q
The LSB of X is shifted in to the MSB position of Q., the
bit from E is shifted in to MSB position of X. After the shift, Xs ← Qs ⊕ Ys
one bit of the partial product is shifted into Q, pasting multiplier Qs ← Qs ⊕ Ys
X ← O, E ← O
bits one position to through right. In this manner the right most SC ← n-1
FF in register Q, designated by Qn; will hold the bit of the
multiplier, which must be inspected next.

H/W algorithm:- = 0 Qn = 1

Initially the multiplicand is in Y and the multiplier in Q. EXÅX+Y

their corresponding signs are in Ys and Qs, respectively. The
signs are compared, and both X and Q are set to correspond
Shr EXQ
to the sign of the product since a double - length product will SC ÅSC - 1
be stored in reg. X and Q register X and E are cleared and the
sequence counter SC is set to a number equal to the number
of bits of the multiplier. We are assuming hear that operands ≠ 0 SC
= 0
are transferred to reg. From a memory unit that has words of
n bits. Since an operand must be stored with its sign, one bit
END
of the word will be occupied by the sign and the magnitude (Product is in AQ)
will consists of (n-1) bits.
Fig: - Flow chart for the multiply operation.

Chap–III 15
COMPUTER ARCHITECTURE Arithmetic Unit

Eg. Using this sequential hardware structure, it is clear that a

23 × 19 = 437 multiply instruction takes much more time to execute than an
Multiplicand Y = 1 0 1 1 1 ← 23 Add instruction.
Multiplier Q = 1 0 0 1 1 ← 19 3.3.7.1 Array multiplier
E X Q SCounter = no. of The multiplication of two binary number can be done
bits in the
with one loop by means of a combinational circuit that
multiplier in the
forms the product bits all at once. This is a first way of
binary form
multiplying two no since all it takes is the time for the signals
0 00000 10011 101
to propagate thought the gates that form a multiplication array
Qn=1, ADD Y 10111 however an array multiplier reg. A large no of gates and for this
First partial Product 0 10111 reason it was not economical until the development of integrated
circuits.
Shift right EXQ 0 01011 11001 100
Qn= 1 , Add y 10111 To see how an array multiplier can be implemented with a
combinational circuit consider the multiplication of two 2 - bit
Second partial Product 1 0 0 0 1 0
number as shown below.
Shift right EXQ 0 10001 01100 011
The multiplicand bits are y1 and y0 and the multiplier bits
Qn= 0 , No add are x1 and x0 and the product is p3 p2 p1 p 0.
Shr EXQ 0 01000 10110 010 The first partial product is formed by multiplying a0 by
Qn= 0 , No add y1y0. The multiplication of two bits such as x0 and y0 produces
a 1 if both bits are 1; otherwise it produces a product 0. this
Shr EXQ 0 00100 01011 001
is identical to AND operation and can be implemented with
Qn= 1 ADD Y 10111 AND gate. As shown in fig the first partial product is formed
by means of two AND gates.
11011
The second partial product is formed by multiply by x1 by
Shr EXQ 0 01101 10101 000
y1y0 and is shifted one position to the left. The two partial
Since SC becomes zero products are added with two half adder (HA) circuits. Note that
LSB of the product does not have to get through an adder since
Final product is in XQ
it is formed by o/p of first AND gate.
XQ = 0 1 1 0 1 1 0 1 0 1 ← 437

Chap–III 16
COMPUTER ARCHITECTURE Arithmetic Unit

x0 shifting and a string of is in the multiplier from bit wt 2k to wt

y1 y0 2m can be treated as (2k+1 - 2m) for ex the bin no 001110 (+14)
has a string of is from 23 to 21 (k=3,m=1) the no can be
represented as 2k+1 - 2m = 24 - 21 = 16 - 2 = 14
Therefore Multiplication M x 14 where M → multiplicand
x1 and 14 the multiplier; can be done as (M x 24 - M x 21). Thus
the product can be obtained by shifting the binary multiplicand
y1 y0 M four times to the left and subtracting M shifting left ones.
y1 y0 As in all multiplication schemes, booth algorithm register
x1 x0 examine of the multiplier bits and shifting of the partial
x0 y1 x0 y0 product prior to the sifting the multiplicand may be added to
HA HA
x1y1 x1y0 C S C S the partial product, subtracted from the partial product or left
p3 p2 p1 p0 unchanged according to the following rules
1) The multiplicand is sub from the partial product upon
p3 p2 p1 p0 encountering the first LSB 1 in a string of is in the multiplier
Fig: -2 - bit by 2 - bit array multiplier 2) The multiplicand is added to the partial product upon
encountering the first 0 (provided that there was a previous
A combinational circuit binary multiplier with more bits can
be constructed in a similar fashion. A bit of the multiplier is 1) in a string of 0’s in the multiplier.
AND ed with each bit of multiplicand in as may levels as there
3) The partial product does not change when the multiplier bit
are bits in a multiplier.
is identical to the previous multiplier bit
For j multiplier bits and k multiplicand bites need j x k
The algorithm works for positive (or) negative multiplier in
AND gates and (j-1) k-bit address to produce a product of
2’s Comp representation. This is because a negative multiplier
j + k bits.
ends with a string of 1’s and the last operation will be a
3.3.8 Signed Operand Multiplication subtraction of the appropriate weight
This topic discuss multiplication of 2’s complement signed Ex:- Multiplier equal to -14 in 2’s complement from →
operands, generating a double length product. 110010 and in treated as
3.3.8.1 Booth Multiplication Algorithm -24+22-21 = -14
Booth algorithm gives a procedure for multiplying bin The H/W implementation O’s Booth algorithm require the
integers in signed 2’ s complement representation. It operates on register configuration as shown below. This is similar to H/W
the fact that string of is in the multiplier register on add but just fig above except that the sign bits are not separated from the

Chap–III 17
COMPUTER ARCHITECTURE Arithmetic Unit

rest of the reg. To show this different we rename the reg. A, B Multiply
and Q as AC, BR and QR respectively. Qn designates the LSB
of multiplier in reg. QR. An extra FF Qm+1 is appended to QR
Multiplicand in YS
to facilitate a double bit inspection of the multiplier Multiplier in QR
YS Register Sequence Counter
XS ← 0
Qn+1 ← 0
SC ← N
Complementer &
11le adder

Qn Qn+1
Qn Qn+1
= 10 = 01

XS Register Q Register XSÅXS +YS+1 XSÅXS+YS

= 00
= 11
Fig:- H/W for Booth algorithm
Ashr (XS & QR)
SCÅ SC-1
The flow chart for Booth algorithm is shown below XS and
appended bit Qn+1 are initially cleared to O and the sequence
counter SC is set to a number n equal to the number of bits in
≠ 0 SC = 0
the multiplier. The two bits of the multiplier in Qn and Qn+1 are
inspected. It the two bits are equal to 10, it means that the first
1in a string of 1’s has been encountered. This requires a END
substitution of the multiplicand from the partial product in XS. Fig:- Booth Algorithm for multiplication of signed - 2’s complementer
Where the two bits are equal, the partial product dose not change. A numerical example of Booth algorithm for n = 5 it shows
An overflow can’t occur because the addition and subtraction of the step-by-step multiplication of (-9) x (-13)=117 note that the
the multiplicand follow each other. As a consequence, the two multiplier in QR is negative and that. The multiplicand in YS
number that an added always have opposite signs, a condition is also negative. The 10-bit product appends in XS and QR and
that excludes an overflow. The next step is to shift right the is positive. The final value of Qn+1 the original sign bit of the
partial produce and the multiplier (including Bit Qn+1). This is multiplier and should not be taken as part of the product
an arithmetic shift (ashr) operation which shift XS and YS to Example Case (i) –ve × –ve
the right and leaves the sign bit in XS unchanged. The sequence –9 × –13
counter (SC) is decremented and the computational loop in YS = 1 0 1 1 1 = –9
repeated n times.
YS + 1 = 0 1 0 0 1

Chap–III 18
COMPUTER ARCHITECTURE Arithmetic Unit

Qn Qn+1 Initial XS QR Qn+1 SC 000000000

00000 10011 0 101 11110111
0000000
1 0 Subtract
YS 01001 001001
(by 2’s sompl 0001110101 Ans Product.
addt) 01001
In the above example; the transformation
Ashr 00100 11001 1 100
1 0 0 1 1 to –1 0 +1 0 –1 is called skipping over 1’s. This
1 1 Ashr 00010 01100 1 011 term is derived from the case in which the multiplier has its 1s
0 1 Add YS 10111 grouped into a few contiguous blocks. Only a few versions of
the shifted multiplicand must be added to generate the product,
11001
thus speeding up the multiplication operation.
Ashr 11100 10110 0 010
Multiplier Version of Multiplicand
0 0 Ashr 11110 01011 0 001 Bit i Bit i–1 selected by bit i
1 0 Sub YS 01001 0 0 0 × M
00111 0 1 +1 × M

Ashr 00011 10101 1 000 1 0 –1 × M

1 1 0 × M
Final Product Fig. Booth Multiplier recording table.
Eg 2: –9 × –13 implied

10111 × Worst 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 10
10011 Case +1 –1 +1 –1 +1 –1 +1 –1 +1 –1 +1 –1 +1 –1 +1 –1 +1 –1

I Step find Booth recoding of a Multiplier implied

10 01 1 0 assumption Ordinary 1 1 0 0 0 1 0 1 1 0 1 1 1 0 0 1 0 0
Multiplir 0 –1 0 0 +1 –1 +1 0 –1 +1 0 0 –1 0 +1 –1 0
–1 0 +1 0 –1
(average)
10 11 1 × implied
–1 0 +1 0 –1 Good 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 0
0000001001 ← 2’s comp of the multiplicand 10111 Multiplir 0 0 0 +1 0 0 0 0 –1 0 0 0 +1 0 0 –1

Chap–III 19
COMPUTER ARCHITECTURE Arithmetic Unit

Booth Algorithm Advantages Case (iii) +ve × –ve 01001

(i) It handles both positive and negative multipliers uniformly. +6 × –9 ↓
↓
(ii) It achieves some efficiency in the number of additions
00110 10111 10110 +1
required when the multiplier has a few large blocks of 1’s.
BR → 0 0 1 1 0
(iii) The speed gained by skipping 1’s depends on the data.
BS + 1 → 1 1 0 0 1 +1 → 1 1 0 1 0
Case (ii) +ve × +ve
Qn Qn+1 Initial AC QR Qn+1 SC
00110 × 01001 × 110110
6 9 54 00000 10111 0 101
BR = 0 0 1 1 0 = –9 1 0 Sub BR 11010
BS + 1 = 1 1 0 0 1 +1 → 1 1 0 1 0 11010
Qn Qn+1 Initial AC QR Qn+1 SC Ashr 11101 01011 1 100
00000 01001 0 101 1 1 Ashr AC 11101 01011 1 011
1 0 Sub BR 11010 1 1 Ashr AC 11111 01010 1 010
11010 0 1 Add BR 00110
Ashr 11101 00100 1 100
00101
0 1 Ashr BR 00110
Ashr 00010 10101 0 001
00011
1 0 Sub BR 11010
Ashr 00001 10010 0 011
11100
0 0 Ashr 00000 11001 0 010
1 0 Sub BR 11010 ashr 11110 01010 1 000
11010 Final Pdt in 2’s comp form
Ashr 11101 01100 1 001 00000 10101
0 1 add BR 00110 00001 10110
00011 3.3.9 Multiplication
ashr 00001 101100 0 000 There are two techniques for speeding up the
Final Product multiplication operation.

Chap–III 20
COMPUTER ARCHITECTURE Arithmetic Unit

(i) Bit Pair Recoding of Multipliers Table of Multiplicand Selection decisions.

(ii) Carry Save Addition of Summands Multiplier bit Multiplier bit Mulitplicand Selected
Pair on the right at position i
3.3.9.1 Bit Pair Recoding of Multipliers i+1 i i–1
Guarantees that the max number of summands (versions 0 0 0 0×M
of the multiplicand) that must be added is reduced by half 0 0 1 +1 × M
and is derived from Booth’s Alg. 0 1 0 +1 × M
(i) Group the Booth recoded Multipliers bits in pairs. 0 1 1 +2 × M
1 0 0 –2 × M
Eg.
1 1 1 0 1 0 0 Implied 0 to right of LSB 1 0 1 –1 × M
Sign 1 1 0 –1 × M
Extension
0 0 -1 +1 -1 0 Recoded multiplier 1 1 1 0×M

0 -1 -2 Example 1
0 1 1 0 0 (12) × 1 1 0 0 0 (–8)
In the recoded multiplier bits,

(+1, –1) is equivalent to (0 +1) i.e. Instead of adding – Multiplier 1 1 0 0 0 0 assumption

0 –1 0 0 0
1 times the multiplicand M at shift position i to +1×M at
Method I : (Booth Multiplication)
position i+1, the same result is obtained by adding +1×M at
0 1 1 0 0 ×
position i.
0 –1 0 0 0
Similarly (+1 0) is equivalent to (0 +2) 0000000000
000000000
(–1 +1) is equivalent to (0 –1) So on.
00000000
(ii) If the Booth recoded multiplier is examined two bits at 1110100 ←2’s compl. of multiplicand with arithmetic sign extension
a time, starting from the right, it can be rewritten in a 000000
form that requires at most one version of the multiplicand 1110100000 ← 2’s comp. form since one of the operand is negative
to be added to the partial part for each pair of multiplier 0001011111 ← 1’s comp. of the result.
bits. 1 ←Take 2’s comp. of the result by adding 1 to 1’s compl.
0 0 0 1 1 0 0 0 0 0 = (–96)

Chap–III 21
COMPUTER ARCHITECTURE Arithmetic Unit

Method II : (Bit pair recording technique) I Method (Booth Multiplication)

Multiplier 1 1 1 0 0 0 0 Multiplier 0 0 1 0 1 0 assumption

Recoded 0 +1 -1 +1 -1
0 0 -1 0 0 0 Multiplier

0 -2 0 0 0 1 1 1 ×
0 +1 –1 +1 –1
0 1 1 0 0
1111111001
0 –2 0
000000111
0000000000 ← M × O
11111001
11101000 ←Take 2’s compl. of M × 2 shifted by 2 bit position. 0000111
000000 000000
1110100000 0000100011
2’s Comp form II Method (Bit Pair Recoding of Multiplier)
Multiplier
0001100000 ← (–96)
Take 2’s compl. of the result and put negative sign in front. 0 0 0 1 0 1 0
Sign
Note : Using multiplier bit pair recording, multiplication Extension 0 0 +1 -1 +1 -1
requires only half the number of summands as a normal
multiplication algorithm. 0 +1 +1

Example 2: 0 0 1 1 1 ×
Multiplicand –7 0 +1 +1
Multiplier –5 0000000111
If both multiplicand and multiplier are negative, take two’s 00000111
complement of both and do positive multiplication as the sign
000000
and value of the product will not change.
0000100011
Therefore Multiplicand 00111
As given in II Method, bit pair recoding of multipliers
Multiplier 00101
technique halves the maximum number of summands.

Chap–III 22
COMPUTER ARCHITECTURE Arithmetic Unit

3.3.9.2 Carry Save addition of summands Case (ii) Addition Using Carry save adder
Multiplication of 2 numbers involves the addition of several Wn-1 Xn-1 W1 X1 W0 X0
summands (partial products). A technique called carry save
addition speeds up the addition process.
FA FA FA 0
In ordinary multiplication process, while adding the O
summands, the carry produced by second bit position has to be yn-1 y1 y0
added with third bit position and so on. Thus the carry ripple an an-1 a1 a0
along the rows.
FA FA FA FA 0
Eg. Consider the addition of 3 numbers W, X, Y
i.e. Z = W + X + Y
Zn+1 Zn Zn-1 Z1 Z0
Case (i) Using ripple carry adders, Z = W + X + Y can be
implemented as Fig. Addition using ripple carry adder.

Wn-1 Xn-1 W2 X2 W1 X1 W0 X0 Eg.

W = 10101
yn-1 y2 y1 y0 X = 11011
FA FA FA FA 0
O
Y = 10100
Sn-1 S2 S1
Cn Cn-1 C2 C1 S = 11010

FA FA FA FA C = 10101
Z = 1000100

Zn+1 Zn Zn-1 Z1 Z1 Z0 In carry save addition, instead of letting the carries ripple
along the rows, they are saved and introduced into the next row,
at the correct weighted positions.
Eg :
Carry save addition transforms W, X & Y into S & C. Its
W = 10101
advantage is that all bits of S and C Vectors are produced in a
X = 11011 short, fixed amount of time after W, X and Y are applied. Carry
propagation takes place only in the second row.
110000
Example 2
Y = 010100
Consider the multiplication operation M × Q = P for 6 bit
Z = 1000100
operands

Chap–III 23
COMPUTER ARCHITECTURE Arithmetic Unit

1 0 1 1 0 1 (45) M Eg. 2: Using Carry Save Addition

1 1 1 1 1 1 × (63) Q W6 W5 W4 W3 W2 W1
Level 1 CSA
1 0 1 1 0 1 W1
1 0 1 1 0 1 W2 C2 S2 C1 S1
Level 2 CSA
1 0 1 1 0 1 W3
1 0 1 1 0 1 W4 C3 S3
1 0 1 1 0 1 W5 Level 3 CSA

1 0 1 1 0 1 W6
C4 S4
1 0 1 1 0 0 0 1 0 0 1 1 Level 4 CPA
+
Eg 2: Using Ripple Carry Addition Final Product Carry propagation
O mq mq mq mq mq adder
5 0 4 0 3 0 2 0 1 0
mq mq mq mq mq mq mq
5 1 4 1 3 1 2 1 1 1 0 1 0 0
Example 3
1 0 1 1 0 1 M
FA FA FA F
A FA FA 0
1 1 1 1 1 1 ×
1 0 1 1 0 1 W1
mq mq mq mq mq mq
5 2 4 2 3 2 2 2 1 2 0 2 1 0 1 1 0 1 W2
1 0 1 1 0 1 W3
FA F
A FA FA F
A FA 0 1 1 0 0 0 0 1 1 S1
0 0 1 1 1 1 0 0 C1
mq mq mq mq mq mq
5 3 4 3 3 3 2 3 1 3 0 3

1 0 1 1 0 1 W4
FA FA FA FA FA F
A 0 1 0 1 1 0 1 W5
1 0 1 1 0 1 W6
mq mq mq mq mq mq
5 4 4 4 3 4 2 4 1 4 0 4 1 1 0 0 0 0 1 1 S2
0 0 1 1 1 1 0 0 C2
F
A FA FA FA FA FA 0 1 1 0 0 0 0 1 1 S1
0 0 1 1 1 1 0 0 C1
mq
5 5
mq
4 5
mq
3 5
mq
2 5
mq
1 5
mq
0 5
1 1 0 0 0 0 1 1 S2
1 1 0 1 0 1 0 0 0 1 1 S3
FA FA FA F
A F
A FA 0
0 0 0 0 1 0 1 1 0 0 0 C3
0 0 1 1 1 1 0 0 C2
0 1 0 1 1 1 0 1 0 0 1 1 S4
P P P P P P P P P P P P 0 1 0 1 0 1 0 0 0 0 0 C4
1
1 10 9 8 7 6 5 4 3 2 1 0

Fig. Using Ripple carry addition for 6×6 bits multiplication 1 0 1 1 0 0 0 1 0 0 1 1 Product

Chap–III 24
COMPUTER ARCHITECTURE Arithmetic Unit

Delay through the carry save array is somewhat less than Note
delay through the ripple carry array. It is because the S and C No of CSA levels needed to
vector outputs from each row are produced in parallel in one reduce k summands to 2 vectors = 1.7 log2 k–1.7
full adder delay.
But if bit pair recoding of the multiplier is done instead of
Steps for addition of summands in the multiplication of longer n summands for n × n multiplication, only n/2 summands are
operands produced. This reduces the number of CSA levels required =
1. Group the summands into threes and perform carry save 1.7 log2 k–3.4.
addition to produce S and C vectors in one full adder delay.
Note
2. Group all the S and C vectors into threes and perform carry
save addition to generate further set of S and C vectors in 1. Bit pair recoding of the → reduces the number of summands
one more full adder delay. multiplier by a factor of 2
3. Do the step 2 unitl there are only two vectors remaining. 2. Carry save adder → adds the summands and produces
4. Perform ripple carry addition or carry lookahead addition to only Sum and Carry (2)
produce the desired product. 3. Carry lookahead adder → used to add the final sum and carry.
Delays in carry save addition 3.3.10 Division
For 6 × 6 array multiplier (Eg. given above) Division of two-fixed point binary number in signed
magnitude representation is done by a process of compare, shift
1 gate delay to select the summands based on multiplier bits and subtract operations. Binary division is simpler than decimal
+ division because the quotient digits are either 0 or 1.
6 gate delays (two gate delays for each CSA level) (3 CSA levels)
Consider an example the divisor Y consists of five bits and
+
the dividend X of 10 bits. The five MSB bits of the dividend
8 gate delays (for carry lookahead addition Final addt of C&S are compared with the divisor. Since the five bit number is
15 gate delay smaller than Y we try again by taking 6 MSB bits of X and
compare this number with Y. The 6 bit number is greater than
For the same 6 × 6 array multiplication, the delay when Y, so we place a 1 for the quotient bit in the 6th position above
ripple carry addition is used is the dividend. The difference is called a partial remainder, because
the division could have stopped here to obtain a quotient of 1
6(n–1)–1 = 6(6–1) = 6(5)–1 and the remainder is equal to the partial remainder. The process
is continued by comparing a partial remainder with the divisor.
= 29 gate delay If the partial remainder is greater than or equal to the divisor,
the quotient bit is equal to 1. The divisor is then shifted right
Thus carry save addition halves the delay when compared and subtracted from the partial remainder. If the partial remainder
to ordinary array multiplier that uses ripple carry addition. is smaller than the divisor, the quotient bit is 0 and no subtraction

Chap–III 25
COMPUTER ARCHITECTURE Arithmetic Unit

is needed. The divisor is shifted once to the right in any case. The best way to avoid a divide overflow is to use floating-
The result gives both a quotient and remainder. point data.
Division Overflow (i) Example 1
1 1 0 1 0 Divisor B = 10001
The division operation may result in a quotient with a 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 Quotient Q
overflow, i.e. when the operation is implemented with hardware
Dividend A
this is because the length of the register is finite and will not
hold the number that exceeds the standard length. The divide - 1 0 0 0 1 5 bits of A < B, take 6 bits of A
overflow condition must be avoided in normal computer → shift right B & Sub; enter 1 in Q 6 bit
- 0 1 0 1 1 0
operation because the entire quotient will be too long to transfer position
- - 1 0 0 0 1
into memory unit that has words of standard length, that is, 7 bits of remainder > B Shr B & subtract,
- - 0 0 1 0 1 0
same as the length of register. enter 1 in Q
- - - 0 0 1 0 1 0
- - - - 1 0 0 0 1 Remainder < B, enter 0 in Q.
When the dividend is twice as long as the divisor the
- - - - 0 0 0 1 1 0 Remainder >B Shr B and sub enter 1 in Q
condition to overflow can be stated as follows. A divide- - - - - - 0 0 0 1 1
overflow condition occurs if the high order half bits of dividend Remainder < B; enter 0 in Q
constitute a number greater than or equal to the divisor. Another Quotient → 11010 Shr B, Final remainder
fact associated with division is the fact that the division with Remainder → 00011
Zero is avoided. The divide overflow condition takes care of
this condition as well. This occurs because any dividend will (ii) Example 2 Divisor B = 0101
be greater than or equal to a divisor, which is equal to zero. 1 1 1 1 0 1
Dividend A
Overflow condition is usually detected when the special FF is 0101 1 0 0 1 1 0 0 1 0
Quotient Q
set. We will call it a divide-overflow FF and label it DVF. 0 1 0 1
4 bits of A > B; Sub enter 1 in Q Shr B
1) The occurrence of divide overflow can be handled in a 5 bits of A>B sub enter 1 in Q
variety of ways. In some computer it is the responsibility 0 1 0 0 1 6 bits of A>B ; sub Shr B Enter 1 in Q
of the programmer to check if DVF is set after each - 0 1 0 1 7 bits of A>B ; sub Shr B Enter 1 in Q
(division) divide instruction. They then can branch to a - 0 1 0 0 0 8 bits of A<B ;
subroutine that takes a corrective measure such as rescaling - - 0 1 0 1 Enter 0 in Q
the data to avoid overflow. - - 0 0 1 1 0 Shr B
- - - 0 1 0 1 A>B, sub enter 1 in Q
2) In some olden computers, the occurrence of divide overflow - - - 0 0 0 1 1
stopped the computer and this condition was referred to as - - - - 0 0 1 1 0
divide stop. Stopping the operation of computer is not
- - - - - 0 1 0 1
recommended because it is time consuming. The procedure
in most computers is to provide an interrupt required, when 0 0 0 1
DVF is set. The instruction causes the computer to suspend
the current program and branch to a service routine to Quotient 1 1 1 1 0 1 Remainder 0 0 0 1
take a corrective measure.

Chap–III 26
COMPUTER ARCHITECTURE Arithmetic Unit

3.3.10.1 Integer Division (Restoring Method) H/W Algorithm

When the division is implemented in a digital computer, it The dividend is in X and Q and the divisor in Y. The sign
is convenient to change the process slightly instead of shifting of the result is transferred to Qs to be a part of quotient. A
the divisor to the right the dividend or partial remainder, is constant is set in to sequence counter sc to specify the no of
shifted to the left thus may be achieved by adding X to the 2’s bits in a quotient. The operands are transferred to register from
complement of Y. a memory unit that has words to n-bits. Since an operand must
The H/W for implementing the division operation is identical be stored with its sign, one bit of the word will be occupied by
to that required for multiplication. Register EXQ is now shifted to the sign and the magnitude will consists of (n-1) bits.
the left with 0 inserted into Qn and previous value of E is lost.
A divide overflow condition is tested by subtracting divisor
Ex:- The divisor is stored in the Y register and the double in Y from half of the bits of the dividend stored in X. If X>Y,
length dividend is stored in register X and Q. The dividend is the divide-overflow FF DVF is set and the option is terminated
shifted to the left and the divisor is subtracted by adding its 2’s
permanently. If X<Y, no divide overflow occurs so the value of
complement value. The information about the relative magnitude
the dividend is restored by adding Y to X.
is available in E. If E=1 it signifies that X≥Y. A quotient bit 1
is inserted into the Qn and the partial remainder is shifted to the The division of magnitude starts by shifting the dividend in
left to repeat the process. If E=0 it signifies that X<Y so that XQ to the left with the high order bit shifted in to E. If the bit
quotient in Qn is 0 (inserted during the shift). The value of Y is shifted in to E is 1, we know that EX>B because EX consists
is then added to restore partial remainder in X to its previous of 1 followed by (n-1) bits while Y consists of only (n-1) bits.
value. The partial remainder is shifted to the left and the process In this case Y must be subtracted from EX and 1 inserted in to
is repeated again until all five-quotient bits are formed. The
Qn for the quotient bit. Since register X is missing the high
quotient is in Q and the final remainder is in X.
order bit of the dividend,(which is in E) its value is EX-2n-1.
Method 1 : Restoring Division Method Adding to this value the 2’s complement of Y result is
Shift left
(EX-2n-1) + (2n-1-Y) = EX-Y
The carry from this addition is not transferred to E if we
Xn Xn-1 ........ X0 Qn-1 . . . . . . . . Q0
want E to remain a 1.
Dividend Q
Quotient Setting If the shift left option inserts a 0 in to E the divisor is
Add/Subtract
subtracted by adding its 2’s complement value and the carry is
n bit Control
adder Sequence transferred in to E. If E=1, it signifies that X>Y; therefore Qn
is to 1. If E=0, it signifies that X<Y and the original no is
restored by adding Y to X. In the later case we leave a 0 in Qn
O mn-1 . . . . . . . . m0
(0 was inserted during the shift)
Divisor M
This process is repeated again with register. X holding the
Fig. Register Configuration partial remainder. After (n-1) times, the quotient magnitude is

Chap–III 27
COMPUTER ARCHITECTURE Arithmetic Unit

formed in register X. The quotient sign is in Qs and sign of the Register Q holds the dividend at the start of operation.
remainder in Xs is same as the original sign of the dividend.
Register X is initially set to 0.
Divide Operation
After division Register Q contains quotient.
Register X contains Remainder
Dividend in XQ
Divisor in Y Algorithm
Divide Magnitude 1. Shift X and Q left one binary position
2. Subtract M from X and place the answer back in X
QsÅXs⊕Ys Shl EXQ
3. If the sign of X is 1, set q0 to 0 and add M back to X
= 0 = 1 (restore X); otherwise set q0 to 1.
E

10
EXÅX+Y+1 11 1 0 0 0 8 Quotient = 2
3 2.2
EXÅX+Y+1 XÅX+Y+1 Reminder = 2
11
=1 =0 =1 X≥Y 10
Eg.:
E E
X≥Y X<Y X Q
X<Y QnÅ1
EXÅX+Y EXÅX+Y
Initial Condt 00000 1000
DVFÅ1 DVFÅ0 = 0
EXÅX+Y M 00011
Shift X & Q 00001 000
SCÅ SC -1
Sub M 11101 Cycle I
END
(Divide =0 ≠0 Set q0=0 11110
SC
overflow)
Restore M 00011
00001 0000
END (Quotient is in Q
Remainder is in X) Shift X & Q 00010 000
Sub M 11101
Fig: - Flow chart for divide operation (Restoring Method) Cycle II
Set q0=0 11111
In this configuration, Restore M 00011
Register M holds the divisor 00010 0000

Chap–III 28
COMPUTER ARCHITECTURE Arithmetic Unit

Shift X & Q 00100 000 Eg.: 8/3 = 2.2 Quotient = 2

Sub M 11101 Remainder = 2
00001 Cycle III A Q
Set q0=1 Initial Condt 00000 1000
0001 M 00011
Shift X & Q 00010 001 Shift 00001 000
Sub M 11101 Subtract M 11101 Cycle I
11111
Cycle IV Set q0=0 11110
Set q0=0
Restore M 00011
0000
00010 0010
Shift 11100 000
Remainder Quotient Add 00011
Method 2 : Non Restoring Division 11111 Cycle II
• A method to improve restoring division by avoiding the
need for restoring A after an unsuccessful subtraction. Set q0 0000
• Subtraction is said to be unsucessful if the result is negative. Shift 11110 000
• In the restoring method Add 00011
If A is positive, we shift A & Q left and sub M ie. we 00001
perform 2A – M Set q0=1 Cycle III
If A is negative, we restore A by performing A+M and then 0001
we shift it left and subtract M. Shift 00010 001
Non Restoring algorithm Sub M 11101
Step 1 : Do the following n times 11111 0010

1. If the sign of A is 0, shift A and Q left one bit position Cycle IV

and subtract M from A, otherwise, shift A and Q left and
Quotient
add M to A.
Add 11111
2. If the sign of A is 0, set q0 to 1; otherwise, so q0 to 0. Restore M 00011
Step 2 : If the sign of A is 1, add M to A 00010
Note : Restore operations are no longer needed and that exactly
one add or subtract operation is performed per cycle. Remainder

Chap–III 29
COMPUTER ARCHITECTURE Arithmetic Unit

3.3.11 Floating Point Numbers : Representation Eg.:

The floating point numbers contains the binary point variable 0 00101000 001010 ............. 0
in its position and hence these numbers are called floating point
numbers. Because the position of the binary point number is Value represented = + 1.001010 ........ 0 × 2–87
variable, it must be given explicitly in the floating point
In this representation, one bit is needed for the sign of the
representation.
number. Since the leading non-zero bit of a normalized binary
If the decimal point is placed to the right of the first mantissa must be a 1, it does not have to be included explicitly
significant digit, (non zero) the number is said to be normalized. in the representation.
A floating point number consists of sign, mantissa and an Instead of signed exponent E, the value actually stored in
exponent. the exponent field is an unsigned integer E’ = E+127. This is
called the excess –127 format.
3.3.11.1 Standard for floating point numbers
The IEEE standard describes the floating point representations Therefore the range of E’ for normal values is 1 < E′ < 254.
and the way in which the four basic arithmetic operations are to This means that the actual exponent E is in the range
be performed on these floating point operands. –126 < E < 127.
There are two types of representations for floating point Double Precision
numbers.
Double precision representation contains 11 bit excess
1. Single Precision –1023 exponent E’ which has the range 1 < E′ < 2046 for normal
2. Double Precision values. This means that the actual exponent E is in the range
–1022 < E < 1023. The 53 bit mantissa provides a precision
32 bits equivalent to about 16 decimal digits.
1 8 23 64 bits
Biased
S E M S E’ M
Exponent

Sign of 23-bit mantissa Sign 52-bit mantissa

8 bit signed bit 11 bit excess -1023 fraction
number fraction exponent
0 signifies + exponent in
1 signifies - excess -127 Fig. Double Precision.
representation
Value represented = +1 1.M × 2E′–1023.
Fig. Single precision (32 bit). If a number is not normalized, it can always be put in
Value represented = + 1.M × 2E′–127 normalized form by shifting the fraction and adjusting the
exponent.

Chap–III 30
COMPUTER ARCHITECTURE Arithmetic Unit

Eg Significand width (bits) 23 (Not including 52 (Not including

Unnormalized floating implied bits) implied bits)
9
point 0.0010110 .....X2 . Number of exponents 254 2046
No. of fractions 223 252
6
Normalized representation 1.0110.....X2 . No. of values 1.98 × 231 1.99 × 263
i
Since the scale factor is in the form 2 , shifting the mantissa
right or left by one bit position is compensated by an increase • For exponent values in the range of 1 through 254 for single
or a decrease of 1 in the exponent respectively. format and 1 through 2046 for double format, normalized
non-zero floating point numbers are represented.
Special Values
• The exponent is biased, so that the range of exponents is
When E’=0, the mantissa M is zero.
–126 thro +127 for single format and –1022 through +1023
E’=255 and M = 0, the value ∞ is represented for double format.
where ∞ is the result of dividing a normal
number by zero. • A normalized number requires a 1 bit to the left of the
binary point this bit is implied giving an effective 24-bit or
Similarly
53-bit significant.
When E’=0, and M ≠ 0, denormal numbers are
Single Precision (32 bits) Double Precision 64 bits)
represented. Sign Biased Fraction Value Sign Biased Fraction Value
Eg. + 0.M × 2–126 → denormal numbers are allowed to Exponent Exponent
represent very small numbers. Positive
Zero 0 0 0 0 0 0 0 0
When E’=255 and M ≠ 0, the value represented Negative
is Not-a-Number (NaN) → result of invalid zero 1 0 0 –0 1 0 0 –0
operation 0/0, −1 . Plus
Infinity 0 255(all 1’s) 0 ∞ 0 2047 (all 1’s) 0 ∞
IEEE 754 Format Parameters Minus
Parameter Format Infinity 1 255(all 1’s) 0 –∞ 1 2047 (all 1’s) 0 –∞
Single Double Positive
Normalized 0 0<e <255 f 2e–127(1.f) 0 0<e<2047 f 2e–1023(1.f)
Word width (bits) 32 64 non-zero
Negative
Exponent width (bits) 8 11
Normalized 1 0<e <255 f –2e–127(1.f) 1 0<e<2047 f 2e–1023(1.f)
Exponent bias 127 1023 non-zero
Max exponent 127 1023 Positive 0 0 f≠0 2e–126(0.f) 0 0 f ≠ 0 2e–1022(0.f)
denormalized
Min exponent –126 –1022 Negative 1 0 f ≠ 0 –2e–126(0.f) 1 0 f≠0 –2e–1022(0.f)
Number range (base 10) 10–38, 10+38 10–308, 10+308 denormalized

Chap–III 31
COMPUTER ARCHITECTURE Arithmetic Unit

Exceptions Operations with mantisas are same as in fixed point

representation. Operation performed with exponents are compare
If a number has the exponent value less than –126 we say
and increment (for aligning the mantisas) add and sub (for
underflow has occured.
multiplication and division) and decrement (to normalize the
If a number has the exponent value greater than +127, we result)
say overflow has occured.
Exponent Representation
Such conditions are called exceptions, Exception flag is set
if underflow, overflow, divide by zero, in exact or invalid
operations occur.
Overflow Signed Signed Signed Biased
Magnitude 2’s complement 1’s complement Exponent
When normalized mantissa are added, the sum may contain
an overflow digit. An overflow can be corrected easily by shifting
Biased Exponent
the sum once to the right and incrementing the exponent.
In this representation, the sign bit is removed from being
Underflow
a separate entity. The bias is a positive number that is added
When two numbers are subtracted, the result may contain to each exponent as the floating point number is formed, so
significant zeros. that internally all exponents are positive. Typically, the bias
equals 2k–1–1 where k is the number of bits in the binary
Eg.
exponent.
0.56780 × 105
Eg. Excess –127 representation
–0.56430 × 105
Advantages
0.00350 × 105
– Contains only positive numbers
A floating point number that has a 0 in the most significant
position of the mantissa is said to have an underflow. – simple to compare their relative magnitudes without being
concerned with their sign.
In most computers, a normalization procedure is performed
after each operation to ensure that all results are in a normalized 3.3.11.2 Arithmetic operations on floating point numbers
form. In floating point operations, it is assumed that each floating
point number has a mantissa in signed magnitude representation
Floating point multiplication and division do not require an
and biased exponent.
alignment of the mantissa.
If the exponents differ, the mantissas of floating point
Multiplication → Multiply two mantisas and add exponents.
numbers must be shifted with respect to each other before they
Division → Divite the mantisas and subtract exponents are added and subtracted.

Chap–III 32
COMPUTER ARCHITECTURE Arithmetic Unit

Eg. Exponents Mantissa

2.3742 × 102 + 5.6232 × 104 EA EB

MA MB
2 4
Rewrite 2.3742 × 10 as 0.023742 × 10 and then add
8 bit Swap
Eg. subtractor M of number
4 with smaller E
0.023742 × 10
5.623200 × 104 Sign M of number
5.646942 × 104 Shift with larger E
n bits to
Addition / Subtraction n = EA E B right
1. Choose the number with the smaller exponent and shift its SA SB
mantissa right a number of steps equal to the difference is
exponents. Add / Sub
Combinational Mantissa
2. Set the exponent of the result equal to the larger exponent. CONTROL adder / subtractor
3. Perform addition / subtraction on the mantissas and determine add/ network
subract Sign
the sign of the result.
4. Normalize the resulting value if necessary EA EB
Arithmetic Operations on Floating Point Numbers
Floating Point Arithmetic Operations MUX
Leading zeros
Numbers detector Magnitude M

( )
X + Y = Xs×BXE − YE + Ys × BYE 

 X E ≤ YE E
X = Xs×BXE
( )
X − Y = Xs×BXE − YE − Ys × BYE 

X Normalize and
round

Y = Ys×BYE X×Y = ( XS × YS ) × BXE + YE

8 bit
subtractor
X  XS  XE − YE
= × B
Y  YS  E -X
ER MR
A : SA , E ′A , A  R : SR
32 bit operands   R : SR , E′R , M R } 32 bit result R = A+B
B : SB , E ′B , B 
Result RJ

Chap–III 33
COMPUTER ARCHITECTURE Arithmetic Unit
Add / Sub 1. Check for zeros

0 0 2. Align the mantissas

=0
B A
3. Add or sub the mantissas
EA<EB EA>EB
EA : EB 4. Normalize the result
=0
Eg.
A B
0.0523 × 103 +
Shr A Shr B
Check if A or B is zero

EA EA+1 EB EB+1 0.2751 × 104

OP
Add Align
Sub Add 1. E ′A = 3
Sub OP
AS AS E ′B = 4
=0 A B =1 =1 AS BS =0
S S
2. Shift right A
0.00523 × 104

EA = A+B+1 EA A+B
0.2751 × 104

Add/Sub
3. Since the exponents are equal

A A+1 =0
add
E
AS AS =0 0.00523 × 104
=1 E

=1 0.27510 × 104
=0 =0
A
Shr A 0.28033 × 104
=1 A1 E
A1 Implementation Steps
EA EA+1
=0 A 0
Normalize 1. In the figure, the firtst step is to compare expontnets to
Sht A
determine the number of times the mantissa of the smaller
EA EA-1
exponent to be shifter.
2. The shift value n is then given to the shifter unit to shift
END the mantissa of the smaller number.
3. The sign of the exponent after subtraction determines which
The flow chart depicts the generalized approach for add/sub is smaller or which is larger no and thereby to shift the
of floating point numbers. mantissa of the smaller number.

Chap–III 34
COMPUTER ARCHITECTURE Arithmetic Unit

4. The mantissas are added / subtracted. The sign of the result Division
is determined by combinatorial control network. if E′A > E′B
1. Subtract the exponents and add 127.
then sign is positive or if E ′A < E ′B then sign is negative.
2. Divide the mantissas and determine the sign of the result.
5. The result is normalized by truncating the leading zeros and 3. Normalize the resulting value, if necessary.
by subtracting E′ by X, the number of leading zeros.
Divisor in B
Multiplication Dividend in A
1. Add the exponents and subtract 127. =0
B
2. Multiply the mantissas and determine the sign of the result. =0
=0
3. Normalize the resulting value of necessary. A
=0
Multiplicand in B Exponents in a, b, q QS AS + BS
Multiplier in Q Q 0 Q 0

=0 EA A+B+1
B
If B or Q is zero, product in
=1 =0
=0 A is zero Divide A>B E A<B
=0 by A A+B A A+B
Q zero
Exception Sht A
=0
a a +1
a q

a a + bias a a+b+1
a a+b Exponent addition
q a
a a bias
Subtract bias from a
(127) Divide magnitude of mantissa

Multiply End Quotient in Q

Mantissas
3.3.11.3 Guard bits and Truncation

Shft L AQ =0 In 32 bit single precision floating point representation the

A1 Find out leading zeros
a a 1 and normalize mantissa bits are limited to 24 bits including implicit leading 1.
=1 But some operations may result in extra bits called guard bits
End and these bits should be retained during the intermediate steps
Product is in A to increase the accuracy in final results.

Chap–III 35
COMPUTER ARCHITECTURE Arithmetic Unit

Similarly, allowing guard bits during intermediate steps results (iii) Rounding Procedure
in extended mantissa. Thus this extended mantissa should be
Rounding achieves the closest approximation to the number
truncated to 24 bits while generating final results.
being truncated and is an unbiased technique 1.A is added to
There are several ways to truncate the LSB position of the bits to be retained if there is a 1 in the
(i) Chopping MSB position of the bits being removed.
(ii) Von-Neumann rouding Eg
(iii) rounding
0.b–1 b–2 b–3 1...... is rounded to
(i) Chopping
0.b–1 b–2 b–3 (+)
Chopping is the simplest way to do truncation. i.e. Remove
the guard bits and make no changes in the retained bits. 0.001

Eg. 0.011100 is rounded to

0.b–1 b–2 b–3 000 0.011 (+)
0.b–1 b–2 b–3 111
0.001
are truncated to 0.b–1 b–2 b–3 .
0.100
Error in chopping ranges from 0 to almost 1 and results in
0.b–1 b–2 b–3 0 ..... is rounded to 0.b–1 b–2 b–3.
biased approximation of b–3 position.
There can be a tie situation, that is the bits to be removed
(ii) Von-Neumann Rounding is halfway between the two closest truncated representations.
In this method, if the bits to be removed are all 0’s, they Eg.
are simply dropped, with no changes to the retained bits.
The value 0.b–1 b–2 0100 is truncated to
If any of the bits to be removed are 1, the least significant
bit of the retained bit is set to 1. and 0.b–1 b–20 0.b–1 b–21100 is truncated
Eg. to + 0.b–1 b–20.001
truncated
0.b–1 b–2 b–3 000 to
0.b–1 b–2 b–3 To break the tie in an unbiased way, one possibility is to
choose the retained bits to be the nearest even number.
0.b–1 b–2 b–3 100 0.b–1 b–2 1
LSB to 1 • The error range is approximately –½ to +½ in LSB position
of the retained bits.
Error in this technique is larger than chopping and the
approximation is unbiased and hence results in high probability • This rounding technique is the default mode for truncation
of accuracy. specified in the IEEE floating point standard.

Chap–III 36
COMPUTER ARCHITECTURE Arithmetic Unit

PROBLEMS 2. Multiply the following pairs of signed 2’s comp numbers

using the Booth algorithm.
1. Consider the binary numbers in the follwing addition and
subtraction problems to be signed, 6 bit values in the 2’s a) A = 110011 & B = 101100
complement representation. Perform the operations indicated, = –13 × –19 = +260
specify whether or not arithmetic overflow occurs
Multiplicand BR = 1 1 0 0 1 1
(i) 010110 +2 2 Cn-1 = 0
(+) (+) 0 BR + 1 = 0 0 1 1 0 0 + 1 = 0 0 1 1 0 1
001001 + 9 Cn = 0
011111 +3 1 Qn Qn+1 Initial AC QR Qn+1 SC
Overflow does not occur
000000 101100 0 1 10
(ii) 1 1 0 1 1 1 – 9 Cn-1 = 1 0 0 Ashr AQ 000000 010110 0 101
(+) (+) 0
111001 – 7
Cn = 1 0 0 Ashr AQ 000000 001011 0 100
1 110000 –1 6
Overflow does not occur 1 0 Sub BR 001101

001101
(iii) 0 0 0 1 1 1 000111 + 7
(–) (+) (–) Ashr AQ 000110 100101 1 011
111000 001000 – 8
001111 –1 5 1 1 Ashr AQ 000011 010010 1 010

0 1 Add BR 110011
Cin-1 = 0
0
110110
Cn = 0

Overflow does not occur

Ashr AQ 111011 001001 0 001

(iv) 0 1 1 0 1 0 011010 +2 6 1 0 Sub BR 001101

(–) (+) (–)
100010 011110 –3 0 001000
111000 +5 6 Ashr AQ 000100 000100 1 000
Cn-1 = 1 1
Cn = 0 Final Product
Overflow has occured
260

Chap–III 37
COMPUTER ARCHITECTURE Arithmetic Unit

3. Using bit-pair recoding, multiply the following level I

A = 110101, B = 011011 level II

(–11) × (27) level III

Bit-pair recoding of the multiplier is level IV

01 10 1 1 0 implied zero level V

+1 0 –1 +1 0 –1 level VI
Totally 6 CSA levels are required to reduce 16 summands to 2.
2’s comp of the multiplicand (110101)
1’s compliment = 001010+1 b)
+1 = 1 L-I
2’s compliment = 0 0 1 0 1 1 L-II
Multiply:
L-III
11 0 1 0 1 ×
L-IV
+1 0 –1 +1 0 –1
L-V
00000001011
L-VI
0000000000
111110101 L-VII

00001011 L-VIII

0000000 5. Eg. Floating Point Arithmetic Operations Level 8

110101 X = 0.3 × 102 = 30

1 1 1 0 1 1 0 1 0 1 1 1 ← Result is in 2’s comp representing Y = 0.2 × 103 = 200
negative pdt
X+Y= (0.3 × 10 2−3
+ 0.2 ) × 103 = 0.23 × 103 = 230
000100101001 ← take 2’s comp & put –ve sign.
to bring the exponent
= –297 equal and then add

4. a) How many CSA levels are needed to reduce 16 X − Y = (0.3 × 102− 3 − 0.2 ) × 103 = ( −0.17 ) × 103 = −170
summands to 2.
X × Y = (0.3 × 0.2 ) ×10 2+ 3 = 0.06 × 105 = 6000
b) Draw the pattern for reducing 32 summands to 2 to
prove that the claim of 8 levels is correct. X ÷ Y = (0.3 ÷ 0.2 ) × 102− 3 = 1.5 × 10−1 = 0.15

Chap–III 38
COMPUTER ARCHITECTURE Arithmetic Unit

6) Design a 4 bit arithmetic circuit with one selection variable Xi = AiS1 + Ai S0

S and two 4-bit data inputs A & B. When S=0 the circuit
Yi = Bi S1 S0 + Bi S1
performs addition A+B. When S=1, the circuit performs A-
B (2’s complement form).
S1 S0 Ai Bi Xi Yi Function
Solution: 0 0 0 0 0 0
0 0 0 1 0 1 Xi= Ai
B3 A3 B2 A2 B1 A1 B0 A0
0 0 1 0 1 0 Yi= Bi
S 0 0 1 1 1 1
XOR XOR XOR XOR
0 1 0 0 0 0
0 1 0 1 0 0 Xi=Ai
0 1 1 0 1 0 Yi=0
FA FA FA FA 0 1 1 1 1 0
1 0 0 0 0 1
C4 S3 S2 S1 S0 1 0 0 1 0 0 Xi=0
1 0 1 0 0 1 Yi=Bi
7) An arithmetic circuit has 2 selection variables S1 and S0.
The arithmetic operation available in the unit are listed below. 1 0 1 1 0 0
Determine the circuit that must be incorporated with the full 1 1 0 0 0 1
adder in each stage of the arithmetic circuit. 1 1 0 0 0 0 Xi=Ai
1 1 0 0 1 1 Yi=Bi
S1 S0 Ci=0 Ci=1
1 1 0 0 1 0
0 0 F= A+B F=A+B+1
0 1 F=A F=A+1 8) Prove that the multiplication of two n-digit number in base
1 0 F=B F=B +1 r gives a product no more than 2n digits in length. Show
1 1 F=A+B F=A+B +1 that this statement implies that no overflow can occur in
multiplication operation.
Solution:
Solution:
Let the input to the full adder circuit can be Xi & Yi
Ci Maximum value of number is rn –1. It’s necessary to show
S1 that maximum product is less than or equal to r2n –1.
Maximum product is
S0 Combinational Xi
Circuit FA (rn –1)(rn –1) = r2n –2rn +1≤ r2n –1
Ai Fi
Yi =>2 ≤ 2rn or 1 ≤ rn
Bi
This is always true since r ≥ 2 and n ≥ 1
Ci+1

Chap–III 39
 A

COMPUTER ARCHITECTURE Arithmetic Unit

9) Derive an algorithm for evaluating the SQRT of a binary 10) Design a 4 bit combinational circuit decrementer using 4 FA’s
fixed point number. Solution
Solution: A3 1 A2 1 A1 1 A0 1

The algorithm for SQRT is similar to division with a radicand

being equivalent to the dividend and the test value being F.A F.A F.A F.A
0
equivalent to this divisor. Let A be the radicand, Q be the
SQRT and R be the remainder such that Q2 + R = A (or) S3 S2 S1 S0
√A = Q and a remainder. A-1= A + 2’S Complement of 1
= A + 1111.
Algorithm
11) Derive an algorithm in flowchart form for non-restoring
1. For K bits in A (K even), Q will have K/2 bits
method of fixed point binary division.
Q = q1q2q3 … q k/2
2. The 1st test value is 01 Refer
2nd test value is 0q101 12) Design an arithmetic circuit with one selection variable S
3rd test value is 00q1q201 and two data inputs A & B The circuit generates the
4th test value is 000q1q2q301 etc following 4 arithmetic operations in conjunction with the
3. Mark the bits of A in groups of two starting from left. input carry Cin . Draw the logic diagram for the first two
4. The procedure is similar to the division restoring method stages.
as show below.
Solution:
1101
√10101001 S Cin=0 Cin=1
01 0 D=A+B (add) D=A+1(increment)
01 1 D=A-1(decrement) D=A+B+1(sub)
0110
0101
0001 S Cin X Y
000110 0 0 A B (A+B)
001101 0 1 A 0 (A+1)
- ve
000110 1 0 A 1(A-1)
00011001 1 1 A B (A-B)
00011001
00000

Chap–III 40
COMPUTER ARCHITECTURE Arithmetic Unit

Cin 15) Derive an algorithm in flowchart form for the comparison

A0 X0 C0 of two signed binary numbers when negative numbers are
S S1 in signed 2’s complement representation.
S0 FA
B0 D0 By means of a subtraction operation with the signed 2’s
0 4X1
0 1 MUX Y0 C1 complement number.
1 2
3 Solution:
A1 X1 C1 AC= AsA1A2A3……An
FA
S D1 BR=BsB1B2B3…….Bn
S1
S0 Y1 C2
B1 If signs are unlikeÆ the one with 0 (plus) is larger.
0 4X1
0 1 MUX C2
1 2 If signs are alike Æ both numbers are either +ve or –ve.
3
start
13) Show the hardware that implements the following statement.
=10 =01
Include the logic gates for the control function and the Block
AsBs
diagram for the binary counter with the count enable input.
A<B (both –ve) =11 =00(both +ve) A>B
Solution:
xy T0 + T1 + y T2 : ARÅ AR+1 ACÅAC+BR+1 ACÅAC+BR+1
AND N –bit
count =1 =0
OR binary counter As As
enable clock
AND =/=0 A =0 =1
A
XyT T T =0
0 1 2
=/=0
14) What is the principle of BOOTH’s multiplication algorithm
Solution A>B A<B A=B A<B A>B A=B
Skipping over of 1’s. Recording of multiplier such that
when ever a series of 1’s occur the multiplication process
corresponding to it can be replaced by an addition of two
numbers.

Chap–III 41
COMPUTER ARCHITECTURE Arithmetic Unit

QUESTIONS & ANSWERS • Pipelined circuit

• Co-processor.
1) What are the types of ALU?
8) What is a co-processor
• Combinational ALU
• Sequential ALU. A co-processor a separate instruction set processor that is
closely coupled to CPU and whose instructions and registers
2) What is the disadvantage of combinational ALU
are direct extensions of CPU.
It is costly in hardware.
9) What is a co-processor trap
3) Give any 2’ complement multiplier algorithm
Even if no coprocessor is present, Co-processor instructions
• Robertson’s algorithm can be included in CPU programs, because if the CPU knows
• Booth’s algorithm. that no CO-processor is present it can transfer program to
a predetermined memory location where a software routine
4) What is spatial expansion in ALU
implementing the desired co-processor instruction is stored.
In this expansion connect K copies of the m-bit ALU in the This CPU generated interrupt is called a Co-processor trap.
manner of a ripple carry adder to form a single ALU capable
10) Define Micro operation?
of processing Km bit words directly.
A micro operation is an elementary operation performed with
5) What is temporal expansion in ALU
data stored in the register.
In this expansion use one copy of the m-bit ALU chip in
11) What are the types of micro operations
the manner of a serial adder to perform an operation on
Km-bit words in K consecutive steps. In each step the ALU There are four types of micro operations
processes a separate m-bit slice of each operand. This • Arithmetic micro operations.Æ perform arithmetic
processing is also called multi cycle or multi precision operations on the data stored in the registers.
processing.
• Logical micro operations Æ performs bit manipulation
6) When a ALU is said to be bit sliced operations on the data stored in the registers.
An ALU is said to be bit sliced if each component ALU • Register transfer micro operations Æ transfers binary
concurrently process a separate “slice” of m bits from each information from one register to another register.
Km –bit operand.
• Shift micro operationsÆ performs shift operations on
7) Give the advanced features of ALU the data stored in the registers.
• Floating point arithmetic circuit.

Chap–III 42
COMPUTER ARCHITECTURE Arithmetic Unit

12) Draw a logic circuit which performs both addition and 7) Explain briefly about arithmetic operations?
subtraction. Refer Sec. 3.1
B3 B2 B1 B0 8) Write an algorithm for Addition & Subtraction?
Refer Sec. 3.3.5
9) Explain the Addition (Subtraction) Algorithm:
M Refer Sec. 3.3.5
xor xor xor xor
A3 A2 A1 A0 10) Explain Addition and subtraction with signed 2’s
complement data
FA FA FA FA Refer Sec. 3.3.5.1
C3 C2 C1 C0 11) Write an Multiplication Algorithm ?
Refer Sec. 3.3.7
C4 S3 S2 S1 S0
12) Explain the multiplication algorithm using signed –
Magnitude data
When M =0 The above circuit behaves like a adder.
M=1 The above circuit behaves like a subtractor. Refer Sec. 3.3.7
13) Write an Booth Multiplication Algorithm ?
PART - B
Refer Sec. 3.3.8.1
1) Explain the 4-bit binary adder?
14) Explain Multiplication with Booth Algorithm.
Refer Sec. 3.3.2
Refer Sec. 3.3.8.1
2) Explain the binary adder / sub tractor with a neat block 15) Write briefly about Array multiplier ?
diagram
Refer Sec. 3.3.7.1
Refer Sec.
15) Explain Division Algorithms.
3) Explain the binary incrementer with a neat block Refer Sec. 3.3.10
diagram
16) Explain about Floating-point Arithmetic operations.
Refer Sec.
Refer Sec. 3.3.11
4) Design a 4-bit binary arithmetic circuit 17) Explain about floating point addition/subtraction algorithm.
Refer Sec. 3.3.4 Refer Sec. 3.3.11.2
5) With a neat block diagram fixed point ALU 18) Explain the multiplication of floating point numbers.
Refer Sec. 3.1 Refer Sec. 3.3.11.2
6) Explain the Bit –sliced ALU with a neat block diagram. 19) Explain the Division of two floating point numbers.
Refer Sec. 3.1 Refer Sec. 3.3.11.2

Chap–III 43
COMPUTER ARCHITECTURE Arithmetic Unit

20) Explain briefly about Decimal Arithmetic Unit? Derivation of BCD Adder
A decimal Arithmetic unit is a digital function that performs Binary SUM BCD SUM Decimal
digital micro operation. It can add or subtract decimal no. K Z8 Z4 Z2 Z1 C S8 S4 S2 S1
Usually by forming the 1’s or 10’s complement of the
0 0 0 0 0 0 0 0 0 0 0
subtracted. The unit accepts the coded decimal no and
0 0 0 0 1 0 0 0 0 1 1
generates
0 0 0 1 0 0 0 0 1 0 2
Results in the same adopted binary code. 0 0 0 0 1 1 0 0 1 1 3
A single stage decimal arithmetic unit consists of 9 binary 0 0 1 0 0 0 0 1 0 0 4
input variable and 5-binary output variable, since a min of 0 0 1 0 1 0 0 1 0 1 5
4 bits is required to represent each coded decimal digit. 0 0 1 1 0 0 0 1 1 0 6
Each stage must have 4 inputs for the augends digit, four 0 0 1 1 1 0 0 1 1 1 7
inputs for the addend digit and an input carry. The output includes 0 1 0 0 0 1 0 0 0 0 8
4 terminals for the sum digit and one for the o/p carry. 0 1 0 0 1 1 0 0 0 1 9

BCD adder 0 1 0 1 0 1 0 0 0 0 10
0 1 0 1 1 1 0 0 0 1 11
Consider the arithmetic addition of two decimal digits in
0 1 1 0 0 1 0 0 1 0 12
BCD, together with a possible carry from a previous stage.
0 1 1 0 1 1 0 0 1 1 13
Since each input digit does not exceed 9, the output sum
0 1 1 1 0 1 0 1 0 0 14
can’t be greater than 9+9+1=19, the 1 in the sum being an
0 1 1 1 1 1 0 1 0 1 15
input carry. Suppose we apply two BCD digits to a 4 bit
1 0 0 0 0 1 0 1 1 0 16
binary adder. The adder will form the sum in binary and
1 0 0 0 1 1 0 1 1 1 17
produce the result that may change from 0 to 19.These binary
1 0 0 1 0 1 1 0 0 0 18
number are labeled by K, Z8, Z4, Z2 and Z1.K is the carry
1 0 0 1 1 1 1 0 0 1 19
and the subscripts under the letter Z represents the wt. 8,4,2
and 1 that may be assigned to the 4 bits in the BCD code. One method of adding decimal not in BCD could be to
employ one 4 bit binary adder and perform the arithmetic
The first column in the table lists the binary sums as they
operation one digit at a time. The lower pair of BCD digits
appear in the output of a 4-bit binary adder. The output
is first added to produce a binary sum. If the result is equal
sum of two decimal numbers must be represented in BCD
to or greater than 1010, it is corrected by adding 0110 to
and appear in the 2nd column of the table. It is apparent that
when the binary sum is equal to or less than 1001 the the binary sum. This 2nd operation could automatically
corresponding BCD number is identical and therefore no produce an output carry for the next pair of significant digits.
conversion is needed. When the binary sum is greater than The next higher order pair of digits, together with the input
1001 we obtain a non-valid BCD representation carry is then added to produce their binary sum. If this

Chap–III 44
COMPUTER ARCHITECTURE Arithmetic Unit

result is greater than or equal to 1010, it is corrected by

adding 0110. This produce is repeated until all decimal digits
are added.
It is obvious that the correction is needed when the binary
sum has an output carry K=1. The other six combinations
from 1010 to 1111 that need a correction have a i in position
Z8. To distinguish them from binary 1000 and 1001, which
also have a 1 in position Z8, we specify further that either
Fig: - Block diagram of BCD adder
Z4 or Z2 must have a 1. The condition for a correction and
an output carry can be expressed by the Boolean function. 21) Explain about Decimal Arithmetic Operations?
C = K + Z8 Z4 + Z8 Z2 The algorithms for arithmetic operation with decimal data
are similar to the algorithms for the corresponding operation
When C=1 it is necessary to adder 0110 to the binary sum
with binary data. Except for the slight modification in the
and provide an output carry for the next stage.
multiplication and division algorithm the same flowcharts
A BCD adder is a circuit that adds two BCD digits in can be used for both types of data provided we interpret the
parallel and produces a sum digit also in BCD. A BCD micro operation symbols properly.
adder must include the correction logic in its internal Decimal numbers in BCD are stored in computer register in
construction. To add 0110 to the binary sum, we use a 2nd groups of 4-bits. Each 4-bit group represents a decimal digit.
4-bit binary adder shown in figure below. The two decimal
A bar over the register letter symbol denotes 9’s complement
digits together with the input carry are first added in the
of the decimal number stored in the register. Adding 1 to
top 4-bit binary adder to produce the binary sum. When the
the 9’s complement produces the 10’s complement. Thus for
output carry is equal to 0, nothing is added to the binary
decimal number the symbol
sum. When it is equal to 1, binary 0110 is added to the
binary sum through the bottom 4-bit binary adder. The output A Å A + B + 1
carry generated from the bottom binary adder may be denotes transfer of decimal sum formed by adding the
ignored, since it supplies information already available in original content of A to the 10’s complement of B.
the output carry terminal.
Decimal Arithmetic Micro Operation Symbols
A decimal parallel adder that adds n decimal digits needs n
Symbolic Designation Description
BCD adder stages with the output carry from one stage
connected to the input carry of the next higher order stage. AÅA+B Add decimal number and transfer
To achieve shorter propagation delays, BCD adders include sum into A.
necessary circuits for carry look a head. B 9’s Complement of B

Chap–III 45
COMPUTER ARCHITECTURE Arithmetic Unit

A Å A +B + 1 Contents of A plus 10’s 1. The parallel method uses a decimal arithmetic unit composed
complement of B into A of as many BCD adders as there are digits in the number.
The sum is formed in parallel and required only one micro
QL Å QL + 1 Increment BCD number in QL
operation.
d Shr A Decimal shift right A 0110 00 1 1 0 1 00
d Shl A Decimal shift left A
1000 0111 1001
Incrementing or decrement the register is same for binary
and decimal except for the number of states that the register
is allowed to have. A decimal counter goes through 10 states
from 0000 to 1001 and back to 0000, since 9 is the last BCD Adder BCD Adder BCD Adder
count. A binary counter goes through 16 states from 0000
to 1111 when incremented and from 1111 to 0000 when 1 0 1 0 1 0 0 0 0 0 0 1 1
decremented.
Fig: -Parallel addition (decimal) 624 + 879 = 1503
A decimal shift right or left is preceded by the letter by the
2. In the digit – serial bit – parallel method the digits and
letter d to indicate that a shift over the 4-bits that a shift
applied to the single BCD adder serially; while the bits of
is over the 4-bits that hold the decimal digits.
each coded digit will be transferred in parallel. The sum is
Ex:- Reg A Æ 7860 in BCD. bit pattern is 0111 1000 0110 formed by shifting the decimal no thru BCD adder one at
0000 a time for k decimal digits this configuration required k
Then the micro operation d shr A Æ Shift the decimal micro operation one for each decimal shift.
number to the right to give 0786. This shift is over 4-bits Augend Sum
and changes the content of the register.
0 0 0
0
000 0111 1000 0110 1 0 1 0
1 1 0 BCD 1
22) Explain BCD Addition & Subtraction in binary-signed
0 0 0 Adder 1
magnitude form?
The algorithm for addition and subtraction of binary signed- 1 0 1
0 1 0
magnitude number applies also to decimal signed-magnitude 0 1 0
number provided that we interpret the micro operation 0 1 1
symbols in the proper manner. Similarly the algorithm for 1
binary 2’s complement number applies to decimal signed Addend Carry
10’s complement number.
Decimal data can be added in three different ways. Fig:- Digit-Serial –Bit Parallel

Chap–III 46
COMPUTER ARCHITECTURE Arithmetic Unit

3. In the all serial adder, the bits are shifted one at a time thru The register organization for the decimal multiplication is
a full adder. The bin sum formed after 4 shifts must be shown below. We are assuming here 4 digits no., with each
corrected in to a valid BCD digit. This correct consists of digit occupying four bits, for a total of 16 bits for each no.
checking the binary sum. If it is greater than or equal to There are 3 register, A, B and Q each having corresponding
1010, the binary sum is corrected by adding to it 0110 and sign FF As, Bs and Qs. Register A and B have four more
bits designated by Ae and Be that provide an extension of
generating a carry for the next pain of digits.
one more digit to the Reg. The BCD arithmetic unit adds
Augend the 5 digits in 11le and places the sum in the 5-digit A
Reg. The end carry goes to FF E. The purpose Ae is to
0110 001 010 S
0 0 FA accommodate an overflow while adding the multiplicand to
C the partial product during the multiplication. The purpose of
1000 011 100 digit Be is to form the 9’s comp of the divisor when
Correction
1 1 subtracted from the partial remainder during the division
op~. The least significant digit in register Q is Ql.
Addend
B
Carry

Fig: -All serial decimal add Bs Be 103 102 101 100 Se

The parallel method is fast but required large no of adders

The digit serial bit –parallel required only our BCD adder; K=4
which is shared by all the digits. It’s slower than 11le
method. The all-serial method requires minimum amount of E BCD Arithmetic Unit
equipment but is very slow. Qs

23) Explain BCD Multiplication algorithm in binary signed-

magnitude form? As Ae 103 102 101 100 103 102 101 Ql

The multiplication of fixed – point decimal no is similar to

binary except the way the partial products are formed. A A Q Inc/dec
decimal multiplier has digits that range in value from 0 to Fig: -Registers for Decimal Arithmetic Multiplication & Division
9; where as bin multiplier has only 0 and 1 digits
Algorithm
• In the binary case the multiplicand is added to the partial
product if the multiplier bits is 1. Initially the entire A register and Be are cleared and the
sequence counter SC is set to a no. K equal to the no of
• In the decimal case, the multiplicand must be multiplied
digits in the multiplier. The low order digit of the multiplier
by the digit multiplier and the result added to the partial
product. in QL is checked. If it is not equal to 0, the multiplicand

Chap–III 47
COMPUTER ARCHITECTURE Arithmetic Unit

in B is added to the partial product in A once and QL is Next the partial product and the multiplier are shifted once
decremented QL is checked again and the process is repeated to the right. This places zero in Ae and transfers the next
until it is equal to 0. In this way the multiplicand in B is multiplier quotient in to QL. The process is then repeated
added to the partial product a no of times equal to the k times to form a double length product in AQ.
multiplier digit. Any temp overflow digit will reside in Ae
24) Explain BCD Division algorithm in binary-signed
and can range in value from 0 to 9.
magnitude form?
Multiply
Decimal Division is similar to binary Division except that
quotient digits may have any of the 10 values from 0 to 9.
Multiplicand in B In the restoring division method, the division is subtracted
Multiplier in Q from the dividend on partial remainder as may times as
necessary until a negative remainder results. The correct
remainder is then restored by adding the divisor.The decimal
As Å Qs ⊕ Bs Division algorithm is similar to binary algorithm except that
AÅ 0, Be Å 0 the way the quotient bits are formed. The dividend is shifted
SC Å K
to the left (or partial remainder) with its most significant
digit placed in Ae. The divisor is then subtracted by adding
the 10’s complement value. Since Be is initially cleared, it’s
≠0
complement value is 9 as reg. The carry in E determine the
relative magnitude of A and B. If E = 0, it signifies that
A<B. In this case the divisor is added to restore the partial
QL
remainder and QL stays at 0. (Inserted there during the
slight.). It E =1 it signifies that A>B. The quotient digit in
AÅA+B
=0 Ql Å Ql -1 Ql is incremented and divisor is subtracted again. This
d Shr AQ process is repeated until the sub~ results in a negative
SC Å SC -1 difference which is recognized by E being 0. When in this
occurs the quotient restore the positive remainder. In this
way the quotient digit is made equal to the number of times
≠0 that the partial remainder ‘goes’ in to the divisor.
SC
The partial remainder and the quotient bits are shifted once
to the left and the process is repeated k times to form k
END quotient digits. The remainder is then found in the register
(Product is in AQ) A and the quotient is in register Q. The value of E is
Fig: -Flow chart for Decimal Multiplication neglected.

Chap–III 48
COMPUTER ARCHITECTURE Arithmetic Unit

Divide B = 470 x 152 = 0 Multiply by two decimal numbers

Ae A Q Ql SC
Divisor in B Initial 0 0 0 0 1 5 2 3
Dividend in AQ
QL ≠ 0 4 7 0
0 1 5 1
QL ≠ 0 4 7 0
Check for overflow
4 7 0
QL = 0 0 1 5 0
Qs Å As ⊕ Bs 9 4 0
SC Å K; Be Å 0 d Shr 0 0 9 4 0 1 5
QL ≠ 0 4 7 0
0 0 1 4
D Shl AQ QL ≠ 0 5 6 4
4 7 0
QL ≠ 0 1 0 1 3
0 3 4
EA Å A + B + 1
4 7 0
QL ≠ 0 1 0 1 2
=0 5 0 4
E
A< B 4 7 0
Ql Å Ql + 1
QL ≠ 0 1 0 1 1
9 7 4
AÅA+B 4 7 0
QL = 0 2 0 1 0
EA Å A + B + 1
4 4 4
SC Å SC - 1 d Shr AQ 0 2 4 4 4 0 1 1
=0 E =1 QL ≠ 0 4 7 0
≠0 =0 0 4 0 0
SC
QL = 0 7 1 4
D Shr AQ 0 0 7 1 4 4 0 0
END (Quotient is in Q)
(Remainder is in A)

Product
Fig: - Flow Chart for decimal Division

Chap–III 49