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MAKAUT Class Notes For Engineering

This document describes the design and implementation of a 32-bit RISC microprocessor. It discusses the system architecture, control unit design, datapath design including components like ALU and register file, ROM design, and provides results from simulating and testing various components.

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Sagnika Mitra
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467 views8 pages

MAKAUT Class Notes For Engineering

This document describes the design and implementation of a 32-bit RISC microprocessor. It discusses the system architecture, control unit design, datapath design including components like ALU and register file, ROM design, and provides results from simulating and testing various components.

Uploaded by

Sagnika Mitra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DESIGN AND

IMPLEMENTATION OF A 32-
BIT RISC MICROPROCESSOR
NAME: SAGNIKA MITRA
ROLL NO.- 18731722010
SUBJECT CODE: PCC-CS-302
STREAM: CSE-CYBER SECURITY
SEMESTER: 3RD
INTRODUCTION:

• The design and implementation of a 32-bit Reduced Instruction Set Computer (RISC)
processor: The system architecture is illustrated together with the test bench
waveforms for the various CPU components.
• Cost and performance of components in the implementation domain are major
concerns for computer engineering and computer design. The goal of a Reduced
Instruction Set Computer (RISC) is to lessen both the quantity and complexity of the
machine's instructions. In this study, a low-cost 32-bit RISC processor has been
designed, synthesized, and some of its components have been implemented and
tested on Xilinx FPGA. For synthesis and simulation, ModelSim and the Webpack from
Xilinx have been used.
SYSTEM ARCHITECTURE AND DESIGN
OF THE CONTROL UNIT:

The RISC processor described in this study is made up of three parts:


the Control Unit (CU), the DataPath, and the ROM. Control Unit and
Datapath together are used to describe a digital system. The design of
the control unit is based on a finite state machine (FSM), and each
state can be executed in one clock cycle. The reset state initialises the
CPU's internal registers and variables. Enabling the reset signal for a
predetermined amount of clocks causes the machine to enter the
reset state. The instruction fetching and decoding stages, which will
enable the required signals for reading instruction data from the ROM
and subsequently decoding the components of the instruction, would
come after the reset state. Since each instruction has its own set of
states, the decoding state will also choose the following state based
on the instruction. The control unit will then move to the appropriate
state in accordance with the instruction. After all states of a running
instruction are finished, the last one will return to the fetch state
which will allow us to process the next instruction in the program.
DESIGN OF THE DATAPATH:
• The Data Path is made up of the subunits required for carrying out all
arithmetic and logical operations. The units required to carry out each
operation on the data selected by the control unit are included in the
datapath model. A Register File, Arithmetic/Logic Unit, Memory Interface,
and Branching Unit are among the components. The register File contains
a list of the 32 general-purpose registers that are available to the CPU. It
includes two output ports, one input port, and a 16 bit bus that is directly
connected to the Control Unit to allow for the instantaneous transfer of
data. Two input ports and one output port make up the ALU design, which
mostly operates on two operands. Similar to the control unit, which
chooses an operation based on a code provided by the ALUCL, it has a
similar design. There is a 16x32 memory created utilizing the Memory
Interface to support straightforward load/store operations. The content of
the address record and the immediate data are added to determine the
effective address. The Branch Unit determines if a condition specified by
the Control Unit is met or not, and if it is, it raises a branch flag. If the flag
is raised, the Branch Unit transmits the branch address back to the Control
Unit to replace the program counter. The processing is first carried out by
one of the other units, after which it is finally returned to the register file's
input port using the multiplexer. The register file has two output ports that
are connected to all the other units. The control unit forwards the signals
utilised in the datapath to each subcomponent as necessary.
DESIGN OF THE ROM AND RESULTS:

The CPU has a built in ROM which enables us to program simple code and execute it. It is
a basic 16x32 ROM and it is 32bit aligned. The List of signals in the ROM are:
1. Address: address sent by the control unit
2. data_out: the data that is contained the given address
3. read: the signal to enable reading from the ROM
4. ready: the signal to indicate when the ROM is ready for reading
5. clk: the main clock signal
6. reset: the initial reset sign
RESULTS:
Results of the Simulation:

In this section we are going to show some test bench waveforms that will verify the working operation of our
RISC Processor. Throughout the simulation, 5 primary signals are shown. The sim clock signal, which runs at 50
Mhz, is the simulation's clock. The instruction fetch signal indicates when the control unit requests data from the
ROM. The instruction address 32-bit bus contains the address of the instruction that is being fetched. The
instruction data 32-bit bus contains the data that is sent out from the ROM. The reset state is enabled for 3.5
cycles to give all units time to reset and initialise. After that, we can see the first instruction starting This is the
shift version of the word "SHW. Figure 5 displays the simulated results of the ALU when we try to add the values
(44 + 22). We send the add operation's opcode (33) through the ALUCL signal, and the outcome (66) is displayed
in the alu_output_32bit bus. Our RAM is a 16 slot array of 32 bit vectors, and the following data are stored in the
RAM for simulation purposes: "0x12345678" is stored in location "00," and "0x11133344" is stored in location
"04." Figure 6 shows the testbench waveform for the Memory Unit. The Register File Unit's simulation results are
displayed in Figure.7. In this simulation, we demonstrate how to send data to a specific register in the file and
store it, we tried to store the value‘48’ into register 2, thereg_test signal shows any data written to the input port
of the register file.
THANKING YOU

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