EC234AI

USN

RV COLLEGE OF ENGINEERING
Autonomous Institution affiliated to VTU
III Semester B.E. April/May -2024 Examinations
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ANALYSIS & DESIGN OF DIGITAL CIRCUITS WITH HDL
(2022 SCHEME)

Time: 03 Hours Maximum Marks: 100

Instructions to candidates:

1. Answer all questions from Part A. Part A questions should be answered in first three pages of the answer book only.
2. Answer FIVE full questions from Part B. In Part B question number 2 is compulsory. Answer any one full question from 3 and 4,
5 and 6, 7 and 8, and 9 and 10.
PART-A (Objective type for one or two marks)
(True & false and match the following questions are not permitted)
1 1.1 If the 8-bit variable “data” declared as “reg [7:0] data” is initialized to 8’b10100110,
what will be its value after execution of the following code segment?
always @(posedge clock)
begin
data =data << 1;
data[0] = data[7];
end 1
1.2 If reg [0:31] a_bus,, then a_bus[20-:8] is equal to________ 1
1.3 Suppose S=8’b00010111; then S>>>2 is______. 1
1.4 ________ type of case statement will consider both x and z as don’t care. 1
1.5 The default value for reg data type is_______ 1
1.6 For the following Verilog module the output f equal to ____. 2
module Q1 (f, a, b, c);
input a,b,c; output f,
wire t1, t2;
nand G1 (t1,a,b);
nor G2 (t2,b,c);
or G3 (f,t1,t2);
endmodule
1.7 Identify the sequece detected for the FSM shown in Fig.1 2

Fig.1
1.8 In a J-K flip flop shown below, J=Q’ and K=1.Assuming that flip flop is initially 2
cleared and then clocked for 6 pulses, the sequence at the Q output in fig1.8 will be
_____________

Fig1.8
1.9 In figure shown A=1,B=1.The input B is now replaced by a sequence 101010…The 2
outputs in Fig1.9,X and Y will be ____________respectively(Initially the value of
X=0).
 Fig 1.9
1.10 The sequential circuit shown in fig 1.10 consists of positive D-latch and a MUX. The 2
latch is initially cleared (Q =0). Write the sequence of output at Y when latch is
continuously clocked for 6 pulses according to the given sequence 010101.

Fig1.10

1.11 The characteristic equation of JK flip flop is _____________ 1

1.12 The total number of stated for a n-bit Johnson counter is __________ 1
1.13 A processor unit employs a scratch pad memory. The processor consists of 128 1
registers of 8 bits each. The size of the scratch pad memory is __________

1.14 For the following set of micro operations, write the 16-bit control word register 2
contents.
a)R1←CrcR2
b)R3←R5 XOR R5

PART-B (Maximum subdivisions is limited to 3 in each question)

UNIT-I
2 a What are the basic components of a module? Which components are mandatory? 04
Write a Verilog model for a 4-bit Binary Adder & Substractor using structural
b
modelling. Develop a test bench for the same. 06
Design full adder using 4:1 MUX. Write Verilog code for the same using behavioural
c
modelling. 06

UNIT-II
Design and develop a 4-bit carry look ahead adder. Comment on the circuit
3 a propagation delay.
8
Two decimal numbers, both between 0 and 999, need to be added to each other.
b Design a logic circuit that performs BCD addition of these two numbers.
8
OR

Design and develop a 4-bit adder/subtractor using a parallel adder. The circuit has a
control input S that controls addition or subtraction operation ,S=0 results in addition
4 a
and S=1 results subtraction operation.
8
Design a 4bit magnitude comparator using 2-bit comparators. Write the Verilog code
b
using structural modelling. 8

UNIT-III
A PN flip-flop has four operations: clear to 0, no change, complement, and set to 1,
when inputs P and N are 00, 01, 10, and 11, respectively.
(a) Tabulate the characteristic table.
5 a
(b) Derive the characteristic equation.
(c) Tabulate the excitation table.
(d) Show how the PN flip-flop can be converted to a D flip-flop. 8
Design a synchronous counter using T-flip flops such that it counts the sequence 1-3-
b
5-7-9-11-13-15-1-3-5-7-9-.....and so on. Avoid Lock out condition in the design. 8
OR
 For the state equations given, design a synchronous sequential circuit using JK- flip
flops. Consider x as input and y as output. Write the state diagram and Verilog code
using behavioural modelling.
6 a
A(t+1) = A(t)x+B(t)x
B(t+1) = A'(t)x
y = (A(t)+B(t))x' 8
The Fig 6b shows the partial two-bit counter using the T flip-flops which counts
sequence 0-2-3-1-0.....For counting this sequence what is the expression for input X

Fig6b 8

UNIT-IV
For the given timing diagram as shown in fig7a state the sequence which is detected
and Develop a Verilog code for mealy FSM, assuming that overlapping of pattern is
allowed.

7a

Fig.7a 10
b
Design a 4bit Ring counter using D Flip Flops.Also write any 2 differences between
Johnson and ring counters. 6
OR

For the state diagram shown in Fig. 8a, perform state reduction with the help for state
table. Write reduced state diagram. If input to this machine is sequence 01010110100
then, what is the output sequence produced by this machine?

8a

Fig. 8a 8
Draw the 4-bit universal shift register with the help of neat diagram for the following
conditions.
S0 S1 Operation
0 0 No change
b0 1 Shift Left
1 0 Shift Right
1 1 Parallel load

UNIT-V
 What is scratch pad memory? Explain the organization of processor unit using scratch
9 a pad memory with the help of a neat diagram.
6
Design an arithmetic and logic unit with three selection variables S2S1S0 that generate
the following operations.
Draw the logic diagram of one typical stage.
Arithmetic Operations Logical Operations
S2 S1 S0 Cin=0 Cin=1 S2 S1 S0 Cin=X
b 0 0 0 F=A F=A+1 1 0 0 OR
0 0 1 F=A+B F=A+B+ 1 0 1 XOR
1
0 1 0 F=A-B-1 F=A-B 1 1 0 AND
0 1 1 F=A-1 F=A 1 1 1 Complement
10

OR

Design an arithmetic circuit with one selection variables and two data inputs A and B.
When s=0 the circuit has to perform the addition operation F=A+B.When s = 1 the
10 a
circuit has to perform the increment operation F = A+1. Draw relevant arithmetic
circuit for 4-bits. 8
b Explain the operation of 4-bit shifter circuit. 8

Signature of Scrutinizer: Signature of Chairman

Name: Name:

COURSE CODE…………..

USN

RV COLLEGE OF ENGINEERING
Autonomous Institution affiliated to VTU
III Semester B.E. April/May -2024 Examinations
DEPARTMENT……………………………………..
COURSE TITLE……………………………………….…………
(2022 SCHEME)

Time: 02 Hours Maximum Marks: 50

Instructions to candidates:

1. Answer all questions from Part A. Part A questions should be answered in first three pages of the answer book only.
2. Answer FIVE full questions from Part B. In Part B question number 2 is compulsory. Answer any one full question from 3 and 4,
5 and 6, 7 and 8, and 9 and 10.
PART-A (Objective type for one or two marks)
(True & false and match the following questions are not permitted)
1 1.1 10
1.2
1.3
 1.4
1.5
1.6
1.7
1.8
1.9
1.10

PART-B (Maximum subdivisions is limited to 2 in each question)

UNIT-I
2 a
b 8

UNIT-II
3 a
b
OR

8
4 a
b

UNIT-III
5 a
b
OR

8
6 a
b

UNIT-IV
7a
b
OR
8
8a
b

UNIT-V
9 a
b
OR 8

10 a
b

Signature of Scrutinizer: Signature of Chairman

Name: Name: