COMP2340

+ Lecture 6

The Micro-architecture Level

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Objectives
◼ Describe how digital logic circuits are used to construct a
processor (CPU)
◼ Define assertions that can drive information transfer
between registers
◼ Combine appropriate register transfers to execute micro-
operations
◼ Introduce the micro-instruction as a set of bits that control
the operations of a data path
◼ Use microinstructions to create micro-routines that perform
useful basic operations.
+
The Multi-Level Computer System

The Digital logic level is where

basic logic circuits are used to
construct useful devices:
• Adders
• Multiplexers &
Demultiplexers
• Encoders & Decoders
• Arithmetic and Logic Unit
(ALU)
• Latches & Flip-flops
• Registers
+
Micro-Architectures

The Micro-architecture
level of a computer system,
is where these useful
digital logic devices are
organized in a structured
manner to create circuits
that comprise a processor
(the CPU).
+
Micro-Architectures
The internal organization of the parts that make up a
processor is referred to as the micro-architecture of
the processor.

Warning!!
There is no standard micro-architecture. Every
processor has it own organization. In practice, there are
many “tricks” that are used by the designers of
processors in order to meet design goals.
However, there are some common principles.
e.g. every processor is controlled by a clock, has a
control unit, an ALU, and registers at the least
+
Micro-Architectures
GOALS
• Some of the goals that are sought in designing a
processor might include:
1. Speed at which the processor can accomplish tasks.
2. Cost considerations (building the perfect processor
might not be economically feasible) - make it fast but
not too expensive.
3. Type of things the processor can do (e.g. most
modern processors include capability for processing
media. Older processors did not.)
• Processor design is to some extent a creative process
1. Some goals might be sacrificed for others.
2. “Tricks” are sometimes used to achieve some goals.
+
Micro-Architectures

All modern processors (often called microprocessors, or

CPUs) will have at least:
1. Input from a clock that is used to synchronize the
operations of the different parts of the processor.
2. A Control Unit that controls the operations of the
processor in timing with the signals that are received
from the clock.
3. Units of storage (registers) where values are kept for
use in computation.
4. One or more units that perform computations (ALU).
(ALUs do not operate on real numbers. Modern
processors will also have a Floating Point Unit –
FPU)
+
Data Paths

◼ The major portion of a processor is the organization of the

registers and computational unit (ALU) to form a data path.

◼ A data path defines paths along which data (binary values)

can be transferred from one part of the processor to the next.
◼ E.g. a value can be moved from one register to another, or from a
register to a computational unit such as the ALU.

◼ Data paths are constructed by connecting several units along

a bus.
◼ A bus is a collection of wires that transfers binary values from one
end to the next.
+
Data Paths
◼ An 8-bit bus carries 8 bits
together (like an 8 lane
highway
◼ Modern processors have 32-bit,
or 64-bit buses.
8 8 8 8
◼ A bus is shown in a circuit as a
“fat” line with an arrow
sometimes added to imply
direction of flow.

◼ As for wires that connect to a

device, a bus is annotated by a
small number that indicates its
width. Some depictions 8 wires (not
of an 8 bit bus necessarily a
bus)
+
A Simple Data Path D2
(an 8-bit processor)
In Out
8
8 Load OE

D1 8
▪ This data path has three 8-
bit registers. 8
In Out
8

Load OE
▪ Each register is given a
name.
▪ The pathways are 8-bit D0 8
buses (hence the
8

Out
processor is called an 8-bit
In
Load OE
processor).

A B F1
8-bit ALU
Output F0
Carry In
+
A Simple Data Path D2
(an 8-bit processor) In Out
8 8
Load OE
This simple ALU has four
functions that are selected as D1 8

shown below: 8 8
In Out
Load OE

F1 F0 OUTPUT
0 0 A
0 1 B
D0
1 0 B+1 8 8

1 1 A + B (SUM) In Out
Load OE
8

Note: The ALU also has a A B F1

Carry In wire which can be 8-bit ALU F0
used to add 1 to any addition Output

which is being carried out. Carry In

8
+
A Simple Data Path D2
(an 8-bit processor) In Out
8
Load OE

This design has 3 buses

D1 8
The A Bus is connected to the A
input of the ALU. 8
In Out
8

Load OE

The B Bus is connected to the B

input of the ALU.
8 D0 8

In Out
Load OE
The C Bus is connected to the
output of the ALU.
A B
F1
8-bit ALU F0
Output

Carry In
+
A Simple Data Path D2
(an 8-bit processor)
In Out
8 8
Load OE

▪ Data from a register is placed D1 8

on the B bus and is transferred
to the B input of the ALU. 8
In Out
8

Load OE
▪ This is done by asserting
(setting to 1) the OE control of
a register.
D0 8
▪ Note: Only one register can
8

Out
output at any time. If more than
In
Load OE
one register is enabled for 8

output bus contention will

result (Data will be corrupted). A B
F1
8-bit ALU F0
Output

8
Carry In
+
A Simple Data Path D2
(an 8-bit processor) In Out
8
Load OE

D1
▪ In this data path, the output of
8

the register D0 is connected 8

In Out
8

directly to the A bus. Load OE

▪ Typically this register will

always be enabled for output.
D0
▪ This means that any 8 8

value in the register In

Load OE
Out

will be present at the A

input of the ALU. 1
▪ We show this by placing a 1 A B F1
on the OE wire of Register D0. 8-bit ALU F0
Output

Carry In
+
A Simple Data Path D2
(an 8-bit processor) In Out
8
Load OE

▪ This circuit can be made to perform D1 8

a set of operations in one pulse of the

8 8
clock in the following manner: In Out
Load OE
▪ Output a value from a register
onto the B Bus.
▪ Set the ALU to perform one of its
functions. 8 D0 8

Out
▪ The value will appear at the B
In
Load OE
input of the ALU.
1
▪ The computation is performed
and the output of the ALU will be A B F1
placed on the C Bus. 8-bit ALU
Output
F0
▪ Load the value from the C Bus
into one, or more of the Registers. Carry In
+
Data Path Timing
▪ The operations can occur in one clock cycle as shown below:
▪ Using registers that are loaded on the trailing edge of the clock

3. Values on the C Bus settle

down before being
loaded into register(s).
A single
clock cycle
is
4. Value on the C Bus is
loaded into one, or more considered
registers on the trailing as having
edge of the clock cycle.
several
distinct
2. ALU performs selected
1. Value from register operation. There is a short parts
is placed on B Bus delay before the value of
and arrives at ALU the computation appears
after short delay. at the ALU output.
+
A Simple Data Path D2
(an 8-bit processor) In Out
8
Load OE

D1
▪ We can therefore command the
8

computation D2 = D1 + D0 8
In Out
8

using the following steps: Load OE

▪ Place output from D0 on

bus A by enabling output
of D0. 8 D0 8

▪ Place output from D1 on In Out

Load OE
bus B by enabling output of
D1. 1
▪ Set function of ALU to
A B F1
addition. 8-bit ALU F0
Output

▪ Allow result to be stored in Carry In

D2 by enabling Load of D2.
Register Operations
▪ Each simple instruction involves data transfer between
registers.
▪ At least one micro-operation can be performed by the ALU on
each instruction.

▪ Any micro-operation can be described as the execution of

R  f(R, R)
▪ Where f is in the set of operations allowable to the ALU.

▪ Standard notation to describe micro-operations as they

execute will therefore be valuable.
▪ Often called Register Transfer Language, or RTL
Register Operations
▪ Registers are designated by capital letters, sometimes followed by
numbers (e.g., A, R13, IR).

▪ Copying the contents of one register to another is a register transfer.

▪ Copying R1 to R2 can therefore be represented as:

R2  R1

▪ In this case the contents of register R1 are copied (loaded) into

register R2
▪ A simultaneous transfer of all bits from the source R1 to the destination
register R2, during one clock pulse.
▪ Note that this is a non-destructive to the data source; i.e., the contents
of R1 are not altered by copying (loading) them to R2.
+
Register Operations

◼A register transfer such as

R3  R5

Implies that the digital system has

◼ the data lines from the source register (R5) to the destination register
(R3)
◼ Parallel load in the destination register (R3)
◼ Control lines to perform the action
+
Control Functions

◼ Often actions need to only occur if a certain

condition is true.

◼ This is similar to an “if” statement in a programming

language.

◼ In digital systems, this is often done via a control

signal, called a control function.
◼ If the signal is 1, the action takes place.

◼ This is represented as:

P:R2  R1
Which means “if P = 1, then load the contents of register R1
into register R2”, i.e., if (P = 1) then (R2  R1).
+
Simultaneous Operations

◼ If two or more operations are to occur simultaneously,

they are separated with commas.

P:R3  R5, MAR  IR

◼ Here, if the control function P = 1, load the contents of

R5 into R3, and at the same time (clock), load the
contents of register IR into register MAR.
 Control Word D2
In Out
8

▪ For the data path discussed LD2

OE2
earlier, a set of 9 signals should D1 8
be asserted to control
calculations. 8
Out
8
In

▪ These 9 signals can all be stored

LD1
in a 9-bit word as shown below.
OE1
▪ This is called a control word
▪ (It contains a microinstruction) D0
8 8

In Out

OE0 OE1 OE2 LD0 LD1 LD2 F1 F0 Cin

LD0
OE0

A B
F1
F1 F0 OUTPUT
0 0 A 8-bit ALU F0
0 1 B Output
1 0 B+1
Carry In
1 1 A + B (SUM)
 Microinstructions D2
In Out
8
We can set the bits in a control LD2
word to accomplish a simple task. OE2
For example, to transfer the value D1 8

that is stored in D1 to D0 (D0<-D1) 8 8

we would: In Out

LD1
▪ Set OE1 to 1 (output to B bus)
OE1
▪ SET F1 to 0
▪ SET F0 to 1 8 D0 88
8

▪ SET LD0 to 1 (load ALU output In Out

into D0 from C Bus) LD0

OE0
▪ All other bits are set to 0 (BUT!
OE0 is always 1 as agreed A B
F1
earlier) 8-bit ALU F0
Output
OE0 OE1 OE2 LD0 LD1 LD2 F1 F0 Cin

1 1 0 1 0 0 0 1 0
Carry In
 Microinstructions D2
In Out
8

LD2
OE2
D1 8

To execute D0<-D2+D0 8 8
In Out

▪ Set OE2 to 1
LD1
▪ Set F1 to 1 OE1

▪ Set F0 to 1
D0 88
▪ Set LD0 to 1 8
8
In Out

LD0
OE0

OE0 OE1 OE2 LD0 LD1 LD2 F1 F0 Cin A B

F1
1 0 1 1 0 0 0 1 0 8-bit ALU F0
Output

Carry In
+
Microinstructions & Micro-routines

• Each bit that has a value 1 is called an

assertion. Cycle OE0 OE1 OE2 LD0 LD1 LD2 F1 F0 Cin

• Each control word we just described 1 1 1 0 1 0 0 0 1 0

sets assertions that accomplish a 2 1 0 1 1 0 0 1 1 0

small operation on the data path. This very basic micro-routine takes two
• The control word is said to store a cycles to complete. It performs the
microinstruction. addition of the values in D1 and D2,
• First microinstruction executed storing the result in D0.
D0<-D1.
• Second executed D0<-D0+D2. Cycle OE0 OE1 OE2 LD0 LD1 LD2 F1 F0 Cin

1 1 1 0 1 0 0 0 1 0
• If we put both instructions together
one, after the other then we have a 2 1 0 1 1 0 0 1 1 0

sequence of microinstructions that will 3 1 0 0 0 0 1 0 0 0

add the value in D1 to the value in D2
and store the result in D0. Here we have added another
• This sequence of microinstructions is microinstruction (one more cycle).
called a micro-routine. What additional task has been added?
+ Summary The Micro-
architecture Level
Lecture 6

◼ Micro-Architectures
◼ Data Paths
◼ Data Path Timing
◼ Register Operations
◼ Control Functions
◼ Control Word
◼ Microinstructions
◼ Micro-Routines

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.