1 /**

2 * @file xmc_uart.h
3 * @date 2015-06-20
4 *
5 * @cond
6 **************************************************************************************
*******************************
7 * XMClib v2.0.0 - XMC Peripheral Driver Library
8 *
9 * Copyright (c) 2015, Infineon Technologies AG
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
modification,are permitted provided that the
13 * following conditions are met:
14 *
15 * Redistributions of source code must retain the above copyright notice, this list
of conditions and the following
16 * disclaimer.
17 *
18 * Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided with the
distribution.
20 *
21 * Neither the name of the copyright holders nor the names of its contributors may be
used to endorse or promote
22 * products derived from this software without specific prior written
permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES,
25 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
DAMAGE.
31 *
32 * To improve the quality of the software, users are encouraged to share
modifications, enhancements or bug fixes with
33 * Infineon Technologies AG
dave@infineon.com).
34
*************************************************************************************
********************************
35 *
36 * Change History
37 * --------------
38 *
39 * 2015-02-20:
40 * - Initial
41 *
42 * 2015-05-20:
43 * - Description updated <br>
44 * - Added XMC_UART_CH_TriggerServiceRequest() and
XMC_UART_CH_SelectInterruptNodePointer <br>
45 *
46 * 2015-06-20:
47 * - Removed version macros and declaration of GetDriverVersion API
48 * @endcond
49 *
50 */
51
52 #ifndef XMC_UART_H
53 #define XMC_UART_H
54
 55 /*************************************************************************************
********************************
56 * HEADER FILES
57
*************************************************************************************
********************************/
58
59 #include "xmc_usic.h"
60
61 /**
62 * @addtogroup XMClib XMC Peripheral Library
63 * @{
64 */
65
66 /**
67 * @addtogroup UART
68 * @brief Universal Asynchronous Receiver/Transmitter (UART) driver for XMC
microcontroller family.
69 *
70 * The UART driver uses Universal Serial Interface Channel(USIC) module to implement
UART protocol.
71 * It provides APIs to configure USIC channel for UART communication. The driver
enables the user
72 * in getting the status of UART protocol events, configuring interrupt service
requests, protocol
73 * related parameter configuration etc.
74 *
75 * UART driver features:
76 * -# Configuration structure XMC_UART_CH_CONFIG_t and initialization function
XMC_UART_CH_Init()
77 * -# Enumeration of events with their bit masks @ref XMC_UART_CH_EVENT_t, @ref
XMC_UART_CH_STATUS_FLAG_t
78 * -# Allows the selection of input source for the DX0 input stage using the API
XMC_UART_CH_SetInputSource()
79 * -# Allows configuration of baudrate using XMC_UART_CH_SetBaudrate() and
configuration of data length using
80 XMC_UART_CH_SetWordLength() and XMC_UART_CH_SetFrameLength()
81 * -# Provides the status of UART protocol events, XMC_UART_CH_GetStatusFlag()
82 * -# Allows transmission of data using XMC_UART_CH_Transmit() and gets received data
using XMC_UART_CH_GetReceivedData()
83 *
84 * @{
85 */
86
87 /*************************************************************************************
********************************
88 * MACROS
89
*************************************************************************************
********************************/
90
91 #if defined(USIC0)
92 #define XMC_UART0_CH0 XMC_USIC0_CH0 /**< USIC0 channel 0 base address */
93 #define XMC_UART0_CH1 XMC_USIC0_CH1 /**< USIC0 channel 1 base address */
94 #endif
95
96 #if defined(USIC1)
97 #define XMC_UART1_CH0 XMC_USIC1_CH0 /**< USIC1 channel 0 base address */
98 #define XMC_UART1_CH1 XMC_USIC1_CH1 /**< USIC1 channel 1 base address */
99 #endif
100
101 #if defined(USIC2)
102 #define XMC_UART2_CH0 XMC_USIC2_CH0 /**< USIC2 channel 0 base address */
103 #define XMC_UART2_CH1 XMC_USIC2_CH1 /**< USIC2 channel 1 base address */
104 #endif
105
106 /*************************************************************************************
********************************
107 * ENUMS
108
*************************************************************************************
********************************/
109
110 /**
111 * UART driver status
112 */
113 typedef enum XMC_UART_CH_STATUS
114 {
115 XMC_UART_CH_STATUS_OK, /**< UART driver status : OK*/
116 XMC_UART_CH_STATUS_ERROR, /**< UART driver status : ERROR */
117 XMC_UART_CH_STATUS_BUSY /**< UART driver status : BUSY */
118 } XMC_UART_CH_STATUS_t;
119
120 /**
121 * UART portocol status. The enum values can be used for getting the status of UART
channel.
122 *
123 */
124 typedef enum XMC_UART_CH_STATUS_FLAG
125 {
126 XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE = USIC_CH_PSR_ASCMode_TXIDLE_Msk,
/**< UART Protocol Status transmit IDLE*/
127 XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE = USIC_CH_PSR_ASCMode_RXIDLE_Msk,
/**< UART Protocol Status receive IDLE*/
128 XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED = USIC_CH_PSR_ASCMode_SBD_Msk
, /**< UART Protocol Status synchronization break detected*/
129 XMC_UART_CH_STATUS_FLAG_COLLISION_DETECTED = USIC_CH_PSR_ASCMode_COL_Msk,
/**< UART Protocol Status collision detected*/
130 XMC_UART_CH_STATUS_FLAG_RECEIVER_NOISE_DETECTED = USIC_CH_PSR_ASCMode_RNS_Msk,
/**< UART Protocol Status receiver noise detected */
131 XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_0 = USIC_CH_PSR_ASCMode_FER0_Msk,
/**< UART Protocol Status format error in stop bit 0 */
132 XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_1 = USIC_CH_PSR_ASCMode_FER1_Msk,
/**< UART Protocol Status format error in stop bit 1 */
133 XMC_UART_CH_STATUS_FLAG_RECEIVE_FRAME_FINISHED = USIC_CH_PSR_ASCMode_RFF_Msk,
/**< UART Protocol Status receive frame finished */
134 XMC_UART_CH_STATUS_FLAG_TRANSMITTER_FRAME_FINISHED = USIC_CH_PSR_ASCMode_TFF_Msk,
/**< UART Protocol Status transmit frame finished */
135 XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY = USIC_CH_PSR_ASCMode_BUSY_Msk,
/**< UART Protocol Status transfer status busy */
136 XMC_UART_CH_STATUS_FLAG_RECEIVER_START_INDICATION = USIC_CH_PSR_ASCMode_RSIF_Msk,
/**< UART Protocol Status receive start indication flag*/
137 XMC_UART_CH_STATUS_FLAG_DATA_LOST_INDICATION = USIC_CH_PSR_ASCMode_DLIF_Msk,
/**< UART Protocol Status data lost indication flag*/
138 XMC_UART_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION = USIC_CH_PSR_ASCMode_TSIF_Msk,
/**< UART Protocol Status transmit shift indication flag*/
139 XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION = USIC_CH_PSR_ASCMode_TBIF_Msk,
/**< UART Protocol Status transmit buffer indication flag*/
140 XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_RIF_Msk,
/**< UART Protocol Status receive indication flag*/
141 XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION = USIC_CH_PSR_ASCMode_AIF_Msk
, /**< UART Protocol Status alternative receive indication flag*/
142 XMC_UART_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION =
USIC_CH_PSR_ASCMode_BRGIF_Msk /**< UART Protocol Status baudrate generator
indication flag*/
143 } XMC_UART_CH_STATUS_FLAG_t;
144
145 /**
146 * UART configuration events. The enums can be used for configuring events using the
CCR register.
147 */
148 typedef enum XMC_CH_UART_EVENT
149 {
150 XMC_UART_CH_EVENT_RECEIVE_START = (int32_t)(0x80000000U |
USIC_CH_CCR_RSIEN_Msk), /**< Receive start event */
151 XMC_UART_CH_EVENT_DATA_LOST = (int32_t)(0x80000000U |
USIC_CH_CCR_DLIEN_Msk), /**< Data lost event */
152 XMC_UART_CH_EVENT_TRANSMIT_SHIFT = (int32_t)(0x80000000U |
USIC_CH_CCR_TSIEN_Msk), /**< Transmit shift event */
153 XMC_UART_CH_EVENT_TRANSMIT_BUFFER = (int32_t)(0x80000000U |
USIC_CH_CCR_TBIEN_Msk), /**< Transmit buffer event */
154 XMC_UART_CH_EVENT_STANDARD_RECEIVE = (int32_t)(0x80000000U | USIC_CH_CCR_RIEN_Msk
), /**< Receive event */
155 XMC_UART_CH_EVENT_ALTERNATIVE_RECEIVE = (int32_t)(0x80000000U | USIC_CH_CCR_AIEN_Msk
), /**< Alternate receive event */
156 XMC_UART_CH_EVENT_BAUD_RATE_GENERATOR = (int32_t)(0x80000000U |
 USIC_CH_CCR_BRGIEN_Msk), /**< Baudrate generator event */
157
158 XMC_UART_CH_EVENT_SYNCHRONIZATION_BREAK = USIC_CH_PCR_ASCMode_SBIEN_Msk, /**< Event
synchronization break */
159 XMC_UART_CH_EVENT_COLLISION = USIC_CH_PCR_ASCMode_CDEN_Msk, /**< Event
collision */
160 XMC_UART_CH_EVENT_RECEIVER_NOISE = USIC_CH_PCR_ASCMode_RNIEN_Msk, /**< Event
receiver noise */
161 XMC_UART_CH_EVENT_FORMAT_ERROR = USIC_CH_PCR_ASCMode_FEIEN_Msk, /**< Event
format error */
162 XMC_UART_CH_EVENT_FRAME_FINISHED = USIC_CH_PCR_ASCMode_FFIEN_Msk /**< Event
frame finished */
163 } XMC_UART_CH_EVENT_t;
164
165 /**
166 * UART Input sampling frequency options
167 */
168 typedef enum XMC_UART_CH_INPUT_SAMPLING_FREQ
169 {
170 XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH =
XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH, /**< Sampling frequency input
fperiph*/
171 XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER =
XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER /**< Sampling frequency input
fractional divider*/
172 } XMC_UART_CH_INPUT_SAMPLING_FREQ_t;
173
174 /**
175 * UART input stages
176 */
177 typedef enum XMC_UART_CH_INPUT
178 {
179 XMC_UART_CH_INPUT_RXD = 0UL /**< UART input stage DX0*/
180 #if UC_FAMILY == XMC1
181 ,
182 XMC_UART_CH_INPUT_RXD1 = 3UL, /**< UART input stage DX3*/
183 XMC_UART_CH_INPUT_RXD2 = 5UL /**< UART input stage DX5*/
184 #endif
185 } XMC_UART_CH_INPUT_t;
186
187
188 /**
189 * UART channel interrupt node pointers
190 */
191 typedef enum XMC_UART_CH_INTERRUPT_NODE_POINTER
192 {
193 XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT =
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, /**< Node pointer for transmit
shift interrupt */
194 XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER =
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, /**< Node pointer for transmit
buffer interrupt */
195 XMC_UART_CH_INTERRUPT_NODE_POINTER_RECEIVE =
XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, /**< Node pointer for receive
interrupt */
196 XMC_UART_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE =
XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE, /**< Node pointer for
alternate receive interrupt */
197 XMC_UART_CH_INTERRUPT_NODE_POINTER_PROTOCOL =
XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL /**< Node pointer for protocol
related interrupts */
198 } XMC_UART_CH_INTERRUPT_NODE_POINTER_t;
199
200 /*************************************************************************************
********************************
201 * DATA STRUCTURES
202
*************************************************************************************
********************************/
203
204 /**
205 * UART initialization structure
206 */
207 typedef struct XMC_UART_CH_CONFIG
208 {
209 uint32_t baudrate; /**< Desired baudrate. \b Range:
minimum= 100, maximum= (fPERIPH * 1023)/(1024 * oversampling) */
210 uint8_t data_bits; /**< Number of bits for the data field.
Value configured as USIC channel word length. \n
211 \b Range: minimum= 1, maximum= 16*/
212 uint8_t frame_length; /**< Indicates nmber of bits in a frame.
Configured as USIC channel frame length. \n
213 \b Range: minimum= 1, maximum= 63*/
214 uint8_t stop_bits; /**< Number of stop bits. \b Range:
minimum= 1, maximum= 2 */
215 uint8_t oversampling; /**< Number of samples for a
symbol(DCTQ).\b Range: minimum= 1, maximum= 32*/
216 XMC_USIC_CH_PARITY_MODE_t parity_mode; /**< Parity mode. \b Range: @ref
XMC_USIC_CH_PARITY_MODE_NONE, @ref XMC_USIC_CH_PARITY_MODE_EVEN, \n
217 @ref XMC_USIC_CH_PARITY_MODE_ODD*/
218 } XMC_UART_CH_CONFIG_t;
219
220 /*************************************************************************************
********************************
221 * API PROTOTYPES
222
*************************************************************************************
********************************/
223
224 #ifdef __cplusplus
225 extern "C" {
226 #endif
227
228 /**
229 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
230 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
231 * @param config Constant pointer to UART configuration structure of type @ref
XMC_UART_CH_CONFIG_t.
232 * @return XMC_UART_CH_STATUS_t Status of initializing the USIC channel for UART
protocol.\n
233 * \b Range: @ref XMC_UART_CH_STATUS_OK if initialization is successful.\n
234 * @ref XMC_UART_CH_STATUS_ERROR if configuration of baudrate
failed.
235 *
236 * \par<b>Description</b><br>
237 * Initializes the USIC channel for UART protocol.\n\n
238 * During the initialization, USIC channel is enabled, baudrate is configured with
the defined oversampling value
239 * in the intialization structure. If the oversampling value is set to 0 in the
structure, the default oversampling of 16
240 * is considered. Sampling point for each symbol is configured at the half of
sampling period. Symbol value is decided by the
241 * majority decision among 3 samples.
242 * Word length is configured with the number of data bits. If the value of \a
frame_length is 0, then USIC channel frame length
243 * is set to the same value as word length. If \a frame_length is greater than 0, it
is set as the USIC channel frame length.
244 * Parity mode is set to the value configured for \a parity_mode.
245 * The USIC channel should be set to UART mode by calling the XMC_UART_CH_Start() API
after the initialization.
246 *
247 * \par<b>Related APIs:</b><BR>
248 * XMC_UART_CH_Start(), XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n
249 */
250 void XMC_UART_CH_Init(XMC_USIC_CH_t *const channel, const XMC_UART_CH_CONFIG_t *const
config);
251
252 /**
253 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
254 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
255 * @return None
256 *
257 * \par<b>Description</b><br>
258 * Sets the USIC channel operation mode to UART mode.\n\n
259 * CCR register bitfield \a Mode is set to 2(UART mode). This API should be called
after configuring
260 * the USIC channel. Transmission and reception can happen only when the UART mode is
set.
261 * This is an inline function.
262 *
263 * \par<b>Related APIs:</b><BR>
264 * XMC_UART_CH_Stop(), XMC_UART_CH_Transmit()\n\n\n
265 */
266 __STATIC_INLINE void XMC_UART_CH_Start(XMC_USIC_CH_t *const channel)
267 {
268 channel->CCR = (uint32_t)(((channel->CCR) & (~USIC_CH_CCR_MODE_Msk)) | (uint32_t)
XMC_USIC_CH_OPERATING_MODE_UART);
269 }
270
271 /**
272 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
273 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
274 * @return XMC_UART_CH_STATUS_t Status to indicate if the communication channel is
stopped successfully.\n
275 * @ref XMC_UART_CH_STATUS_OK if the communication
channel is stopped.
276 * @ref XMC_UART_CH_STATUS_BUSY if the communication
channel is busy.
277 *
278 * \par<b>Description</b><br>
279 * Stops the UART communication.\n\n
280 * CCR register bitfield \a Mode is reset. This disables the communication.
281 * Before starting the communication again, the channel has to be reconfigured.
282 *
283 * \par<b>Related APIs:</b><BR>
284 * XMC_UART_CH_Init() \n\n\n
285 */
286 XMC_UART_CH_STATUS_t XMC_UART_CH_Stop(XMC_USIC_CH_t *const channel);
287
288 /**
289 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
290 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
291 * @param rate Desired baudrate. \n
292 * \b Range: minimum value = 100, maximum value depends on the peripheral
clock frequency\n
293 * and \a oversampling. Maximum baudrate can be derived using the
formula: (fperiph * 1023)/(1024 * oversampling)
294 * @param oversampling Required oversampling. The value indicates the number of time
quanta for one symbol of data.\n
295 * This can be related to the number of samples for each logic
state of the data signal.\n
296 * \b Range: 4 to 32. Value should be chosen based on the protocol
used.
297 * @return XMC_UART_CH_STATUS_t Status indicating the baudrate configuration.\n
298 * \b Range: @ref XMC_USIC_CH_STATUS_OK if baudrate is successfully
configured,
299 * @ref XMC_USIC_CH_STATUS_ERROR if desired baudrate or
oversampling is invalid.
300 *
301 * \par<b>Description:</b><br>
302 * Sets the bus speed in bits per second.\n\n
303 * Derives the values of \a STEP and PDIV to arrive at the optimum realistic speed
possible.
304 * \a oversampling is the number of samples to be taken for each symbol of UART
protocol.
305 * Default \a oversampling of 16 is considered if the input \a oversampling is less
than 4. It is recommended to keep
306 * a minimum oversampling of 4 for UART.
307 *
308 * \par<b>Related APIs:</b><BR>
309 * XMC_UART_CH_Init(), XMC_UART_CH_Stop()
310 */
311 XMC_UART_CH_STATUS_t XMC_UART_CH_SetBaudrate(XMC_USIC_CH_t *const channel, uint32_t
rate, uint32_t oversampling);
312
313 /**
314 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
315 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
316 * @param data Data to be transmitted. \n
317 * \b Range: 16 bit unsigned data within the range 0 to 65535. Actual size of
318 * data transmitted depends on the configured number of bits for the UART
protocol in the register SCTR.
319 * @return None
320 *
321 * \par<b>Description</b><br>
322 * Transmits data over serial communication channel using UART protocol.\n\n
323 * Based on the channel configuration, data is either put to the transmit FIFO or to
TBUF register.
324 * Before putting data to TBUF, the API waits for TBUF to finish shifting its
contents to shift register.
325 * So user can continuously execute the API without checking for TBUF busy status.
Based on the number of
326 * data bits configured, the lower significant bits will be extracted for
transmission.
327 *
328 * Note: When FIFO is not configured, the API waits for the TBUF to be available.
329 * This makes the execution a blocking call.
330 *
331 * \par<b>Related APIs:</b><BR>
332 * XMC_UART_CH_GetReceivedData() \n\n\n
333 */
334 void XMC_UART_CH_Transmit(XMC_USIC_CH_t *const channel, const uint16_t data);
335
336 /**
337 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
338 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
339 * @return uint16_t Received data over UART communication channel.
340 * \par<b>Description</b><br>
341 * Provides one word of data received over UART communication channel.\n\n
342 * Based on the channel configuration, data is either read from the receive FIFO or
RBUF register.
343 * Before returning the value, there is no check for data validity. User should check
the appropriate
344 * data receive flags(standard receive/alternative receive/FIFO standard receive/FIFO
alternative receive)
345 * before executing the API. Reading from an empty receive FIFO can generate a
receive error event.
346 *
347 * \par<b>Related APIs:</b><BR>
348 * XMC_UART_CH_GetStatusFlag(), XMC_UART_CH_Transmit() \n\n\n
349 */
350 uint16_t XMC_UART_CH_GetReceivedData(XMC_USIC_CH_t *const channel);
351
352 /**
353 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
354 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
355 * @param word_length Data word length. \n
356 * \b Range: minimum= 1, maximum= 16.
357 * @return None
358 *
359 * \par<b>Description</b><br>
360 * Sets the data word length in number of bits.\n\n
361 * Word length can range from 1 to 16. It indicates the number of data bits in a data
word.
362 * The value of \a word_length will be decremented by 1 before setting the value to \a
SCTR register.
363 * If the UART data bits is more than 16, then the frame length should be set to the
actual number of bits and
364 * word length should be configured with the number of bits expected in each
transaction. For example, if number of data bits
365 * for UART communication is 20 bits, then the frame length should be set as 20. Word
length can be set based on the
366 * transmit and receive handling. If data is stored as 8bit array, then the word
length can be set to 8. In this case,
367 * a full message of UART data should be transmitted/ received as 3 data words.
368 *
369 * \par<b>Related APIs:</b><BR>
370 * XMC_UART_CH_SetFrameLength() \n\n\n
371 */
372 __STATIC_INLINE void XMC_UART_CH_SetWordLength(XMC_USIC_CH_t *const channel, const
uint8_t word_length)
373 {
374 XMC_USIC_CH_SetWordLength(channel, word_length);
375 }
376
377 /**
378 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
379 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
380 * @param frame_length Number of data bits in each UART frame. \n
381 * \b Range: minimum= 1, maximum= 64.
382 * @return None
383 *
384 * \par<b>Description</b><br>
385 * Sets the number of data bits for UART communication.\n\n
386 * The frame length is configured by setting the input value to \a SCTR register.
387 * The value of \a frame_length will be decremented by 1, before setting it to the
register.
388 * Frame length should not be set to 64 for UART communication.
389 *
390 * \par<b>Related APIs:</b><BR>
391 * XMC_UART_CH_SetWordLength() \n\n\n
392 */
393 __STATIC_INLINE void XMC_UART_CH_SetFrameLength(XMC_USIC_CH_t *const channel, const
uint8_t frame_length)
394 {
395 XMC_USIC_CH_SetFrameLength(channel, frame_length);
396 }
397
398 /**
399 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
400 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
401 * @param event Event bitmasks to enable. Use the type @ref XMC_UART_CH_EVENT_t for
naming events. \n
402 * \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref
XMC_UART_CH_EVENT_DATA_LOST,
403 * @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref
XMC_UART_CH_EVENT_TRANSMIT_BUFFER,
404 * etc.
405 * @return None
406 *
407 * \par<b>Description</b><br>
408 * Enables interrupt events for UART communication.\n\n
409 * Multiple events can be combined using the bitwise OR operation and configured in
one function call.
410 * @ref XMC_UART_CH_EVENT_t enumerates multiple event bitmasks. These enumerations
can be used as input to the API.
411 * Events are configured by setting bits in the CCR register.
412 * \par<b>Related APIs:</b><BR>
413 * XMC_UART_CH_DisableEvent(), XMC_UART_CH_SetInterruptNodePointer(),
XMC_UART_CH_GetStatusFlag() \n\n\n
414 */
415 void XMC_UART_CH_EnableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
416
417 /**
418 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
419 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
 XMC_USIC2_CH1 based on device support.
420 * @param event Bitmask of events to disable. Use the type @ref XMC_UART_CH_EVENT_t
for naming events.\n
421 * \b Range: @ref XMC_UART_CH_EVENT_RECEIVE_START, @ref
XMC_UART_CH_EVENT_DATA_LOST,
422 * @ref XMC_UART_CH_EVENT_TRANSMIT_SHIFT, @ref
XMC_UART_CH_EVENT_TRANSMIT_BUFFER,
423 * etc.
424 * @return None
425 *
426 * \par<b>Description</b><br>
427 * Disables the interrupt events by clearing the bits in CCR register.\n\n
428 * Multiple events can be combined using the bitwise OR operation and configured in
one function call.
429 * XMC_UART_CH_EVENT_FLAG_t enumerates multiple event bitmasks. These enumerations
can be used as input to the API.
430 *
431 * \par<b>Related APIs:</b><BR>
432 * XMC_UART_CH_ClearStatusFlag(), XMC_UART_CH_EnableEvent() \n\n\n
433 */
434 void XMC_UART_CH_DisableEvent(XMC_USIC_CH_t *const channel, const uint32_t event);
435
436 /**
437 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
438 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
439 * @param service_request Service request number for generating protocol interrupts.\n
440 * \b Range: 0 to 5.
441 * @return None
442 *
443 * \par<b>Description</b><br>
444 * Sets the interrupt node for UART channel protocol events.\n\n
445 * For all the protocol events enlisted in the enumeration XMC_UART_CH_EVENT_t, one
common
446 * interrupt gets generated. The service request connects the interrupt node to the
UART
447 * protocol events.
448 * Note: NVIC node should be separately enabled to generate the interrupt.
449 *
450 * \par<b>Related APIs:</b><BR>
451 * XMC_UART_CH_EnableEvent() \n\n\n
452 */
453 __STATIC_INLINE void XMC_UART_CH_SetInterruptNodePointer(XMC_USIC_CH_t *const channel,
454 const uint8_t service_request
)
455 {
456 XMC_USIC_CH_SetInterruptNodePointer(channel,
XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL,
457 (uint32_t)service_request);
458 }
459
460 /**
461 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
462 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
463 * @param interrupt_node Interrupt node pointer to be configured. \n
464 * \b Range: @ref
XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT,
465 * @ref
XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
466 * @param service_request Service request number.\n
467 * \b Range: 0 to 5.
468 * @return None
469 *
470 * \par<b>Description</b><br>
471 * Sets the interrupt node for USIC channel events. \n\n
472 * For an event to generate interrupt, node pointer should be configured with service
request(SR0, SR1..SR5).
473 * The NVIC node gets linked to the interrupt event by doing so.<br>
474 * Note: NVIC node should be separately enabled to generate the interrupt.
475 *
476 * \par<b>Related APIs:</b><BR>
477 * XMC_UART_CH_EnableEvent() \n\n\n
478 */
479 __STATIC_INLINE void XMC_UART_CH_SelectInterruptNodePointer(XMC_USIC_CH_t *const
channel,
480 const
XMC_UART_CH_INTERRUPT_NODE
_POINTER_t interrupt_node,
481 const uint32_t
service_request)
482 {
483 XMC_USIC_CH_SetInterruptNodePointer(channel, (XMC_USIC_CH_INTERRUPT_NODE_POINTER_t)
interrupt_node,
484 (uint32_t)service_request);
485 }
486
487 /**
488 * @param channel Pointer to USIC channel handler of type @ref XMC_USIC_CH_t \n
489 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
490 * @param service_request_line service request number of the event to be triggered.
\n
491 * \b Range: 0 to 5.
492 * @return None
493 *
494 * \par<b>Description</b><br>
495 * Trigger a UART interrupt service request.\n\n
496 * When the UART service request is triggered, the NVIC interrupt associated with it
will be
497 * generated if enabled.
498 *
499 * \par<b>Related APIs:</b><BR>
500 * XMC_UART_CH_SelectInterruptNodePointer() \n\n\n
501 */
502 __STATIC_INLINE void XMC_UART_CH_TriggerServiceRequest(XMC_USIC_CH_t *const channel,
const uint32_t service_request_line)
503 {
504 XMC_USIC_CH_TriggerServiceRequest(channel, (uint32_t)service_request_line);
505 }
506
507 /**
508 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
509 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
510 * @return Status of UART channel events. \n
511 * \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for
512 * event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE,
@ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE,
513 * @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc.
514 *
515 * \par<b>Description</b><br>
516 * Provides the status of UART channel events.\n\n
517 * Status provided by the API represents the status of multiple events at their bit
positions. The bitmasks can be
518 * obtained using the enumeration XMC_UART_CH_STATUS_FLAG_t. Event status is obtained
by reading
519 * the register PSR_ASCMode.
520 *
521 * \par<b>Related APIs:</b><BR>
522 * XMC_UART_CH_EnableEvent(), XMC_UART_CH_ClearStatusFlag()\n\n\n
523 */
524 __STATIC_INLINE uint32_t XMC_UART_CH_GetStatusFlag(XMC_USIC_CH_t *const channel)
525 {
526 return channel->PSR_ASCMode;
527 }
528
529 /**
530 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
531 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
532 * @param flag UART events to be cleared. \n
533 * \b Range: Use @ref XMC_UART_CH_STATUS_FLAG_t enumerations for
534 * event bitmasks. @ref XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE,
@ref XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE,
535 * @ref XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED etc.
536 * @return None
537 *
538 * \par<b>Description</b><br>
539 * Clears the status of UART channel events.\n\n
540 * Multiple events can be combined using the bitwise OR operation and configured in
one function call.
541 * XMC_UART_CH_STATUS_FLAG_t enumerates multiple event bitmasks. These enumerations
can be used as input to the API.
542 * Events are cleared by setting the bitmask to the PSCR register.
543 *
544 * \par<b>Related APIs:</b><BR>
545 * XMC_UART_CH_DisableEvent(), XMC_UART_CH_GetStatusFlag()\n\n\n
546 */
547 __STATIC_INLINE void XMC_UART_CH_ClearStatusFlag(XMC_USIC_CH_t *const channel, const
uint32_t flag)
548 {
549 channel->PSCR = flag;
550 }
551
552 /**
553 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
554 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
555 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
556 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
557 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref
XMC_UART_CH_INPUT_RXD2 (for DX5).
558 * @param source Input source select for the input stage. The table provided below
maps the decimal value with the input source.
559 * <table><tr><td>0</td><td>DXnA</td></tr><tr><td>1</td><td>DXnB</td></tr><tr><td>2</
td><td>DXnC</td></tr><tr><td>3</td><td>DXnD</td></tr>
560 * <tr><td>4</td><td>DXnE</td></tr><tr><td>5</td><td>DXnF</td></tr><tr><td>6</td><td
>DXnG</td></tr><tr><td>7</td><td>Always 1</td>
561 * </tr></table>
562 * @return None
563 *
564 * \par<b>Description</b><br>
565 * Sets input soource for the UART communication.\n\n
566 * It is used for configuring the input stage for data reception.
567 * Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage.
568 * The API can be used for the input stages DX0, DX3 and DX5.
569 *
570 * \par<b>Related APIs:</b><BR>
571 * XMC_UART_CH_EnableInputInversion() \n\n\n
572 */
573 __STATIC_INLINE void XMC_UART_CH_SetInputSource(XMC_USIC_CH_t *const channel, const
XMC_UART_CH_INPUT_t input, const uint8_t source)
574 {
575 channel->DXCR[input] = 0U;
576 XMC_USIC_CH_SetInputSource(channel, (XMC_USIC_CH_INPUT_t)input, source);
577 }
578
579 /**
580 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
581 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
582 * @param pulse_length Length of the zero pulse in number of time quanta. \n
583 * \b Range: 0 to 7.
584 * @return None
585 *
586 * \par<b>Description</b><br>
587 * Sets the length of zero pulse in number of time quanta. Value 0 indicates one time
quanta.\n\n
588 * Maximum possible is 8 time quanta with the value configured as 7.\n
589 * The value is set to PCR_ASCMode register.
590 * \par<b>Related APIs:</b><BR>
591 * XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n
592 *
593 */
594 __STATIC_INLINE void XMC_UART_CH_SetPulseLength(XMC_USIC_CH_t *const channel, const
uint8_t pulse_length)
595 {
596 channel->PCR_ASCMode = (uint32_t)(channel->PCR_ASCMode & (~
USIC_CH_PCR_ASCMode_PL_Msk)) |
597 ((uint32_t)pulse_length << USIC_CH_PCR_ASCMode_PL_Pos);
598 }
599
600 /**
601 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
602 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
603 * @param sample_point Sample point among the number of samples. \n
604 * \b Range: minimum= 0, maximum= \a oversampling (DCTQ).
605 * @return None
606 *
607 * \par<b>Description</b><br>
608 * Sets the sample point among the multiple samples for each UART symbol.\n\n
609 * The sample point is the one sample among number of samples set as oversampling.
The value should be less than
610 * the oversampling value. XMC_UART_CH_Init() sets the sample point to the sample at
the centre. For
611 * example if the oversampling is 16, then the sample point is set to 9.
612 * \par<b>Related APIs:</b><BR>
613 * XMC_UART_CH_EnableInputInversion(), XMC_UART_CH_SetSamplePoint() \n\n\n
614 */
615 __STATIC_INLINE void XMC_UART_CH_SetSamplePoint(XMC_USIC_CH_t *const channel, const
uint32_t sample_point)
616 {
617 channel->PCR_ASCMode = (uint32_t)((channel->PCR_ASCMode & (uint32_t)(~
USIC_CH_PCR_ASCMode_SP_Msk)) |
618 (sample_point << USIC_CH_PCR_ASCMode_SP_Pos));
619 }
620
621 /**
622 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
623 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
624 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
625 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
626 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref
XMC_UART_CH_INPUT_RXD2 (for DX5).
627 * @return None
628 *
629 * \par<b>Description</b><br>
630 * Enables input inversion for UART input data signal.\n\n
631 * Polarity of the input source can be changed to provide inverted data input.
632 * \par<b>Related APIs:</b><BR>
633 * XMC_UART_CH_DisableInputInversion()\n\n\n
634 */
635 __STATIC_INLINE void XMC_UART_CH_EnableInputInversion(XMC_USIC_CH_t *const channel,
const XMC_UART_CH_INPUT_t input)
636 {
637 XMC_USIC_CH_EnableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
638 }
639
640 /**
641 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
642 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
643 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
644 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
645 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref
XMC_UART_CH_INPUT_RXD2 (for DX5).
646 * @return None
647 *
648 * \par<b>Description</b><br>
649 * Disables input inversion for UART input data signal.\n\n
650 * Resets the input data polarity for the UART input data signal.
651 * \par<b>Related APIs:</b><BR>
652 * XMC_UART_CH_EnableInputInversion()\n\n\n
653 */
654 __STATIC_INLINE void XMC_UART_CH_DisableInputInversion(XMC_USIC_CH_t *const channel,
const XMC_UART_CH_INPUT_t input)
655 {
656 XMC_USIC_CH_DisableInputInversion(channel, (XMC_USIC_CH_INPUT_t)input);
657 }
658 /**
659 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
660 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
661 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
662 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
663 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref
XMC_UART_CH_INPUT_RXD2 (for DX5).
664 * @return None
665 *
666 * \par<b>Description</b><br>
667 * Enables the digital filter for UART input stage.\n\n
668 *
669 * \par<b>Related APIs:</b><BR>
670 * XMC_UART_CH_DisableInputDigitalFilter()\n\n\n
671 */
672 __STATIC_INLINE void XMC_UART_CH_EnableInputDigitalFilter(XMC_USIC_CH_t *const channel
, const XMC_UART_CH_INPUT_t input)
673 {
674 XMC_USIC_CH_EnableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input);
675 }
676 /**
677 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
678 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
679 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
680 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
681 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref
XMC_UART_CH_INPUT_RXD2 (for DX5).
682 * @return None
683 *
684 * \par<b>Description</b><br>
685 * Disables the digital filter for UART input stage.\n\n
686 *
687 * \par<b>Related APIs:</b><BR>
688 * XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
689 */
690 __STATIC_INLINE void XMC_UART_CH_DisableInputDigitalFilter(XMC_USIC_CH_t *const
channel, const XMC_UART_CH_INPUT_t input)
691 {
692 XMC_USIC_CH_DisableInputDigitalFilter(channel, (XMC_USIC_CH_INPUT_t)input);
693 }
694 /**
695 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
696 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
697 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
698 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
699 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref
XMC_UART_CH_INPUT_RXD2 (for DX5).
700 * @return None
701 * \par<b>Description</b><br>
702 * Enables synchronous input for the UART input stage.\n\n
703 *
704 * \par<b>Related APIs:</b><BR>
705 * XMC_UART_CH_DisableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
706 */
707 __STATIC_INLINE void XMC_UART_CH_EnableInputSync(XMC_USIC_CH_t *const channel, const
XMC_UART_CH_INPUT_t input)
708 {
709 XMC_USIC_CH_EnableInputSync(channel, (XMC_USIC_CH_INPUT_t)input);
710 }
711 /**
712 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
713 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
714 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
715 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
716 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref
XMC_UART_CH_INPUT_RXD2 (for DX5).
717 * @return None
718 *
719 * \par<b>Description</b><br>
720 * Disables synchronous input for the UART input stage.\n\n
721 *
722 * \par<b>Related APIs:</b><BR>
723 * XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
724 */
725 __STATIC_INLINE void XMC_UART_CH_DisableInputSync(XMC_USIC_CH_t *const channel, const
XMC_UART_CH_INPUT_t input)
726 {
727 XMC_USIC_CH_DisableInputSync(channel, (XMC_USIC_CH_INPUT_t)input);
728 }
729 /**
730 * @param channel Constant pointer to USIC channel handle of type @ref XMC_USIC_CH_t
\n
731 * \b Range: @ref XMC_USIC0_CH0, @ref XMC_USIC0_CH1 to @ref
XMC_USIC2_CH1 based on device support.
732 * @param input UART channel input stage of type @ref XMC_UART_CH_INPUT_t. \n
733 * \b Range: @ref XMC_UART_CH_INPUT_RXD (for DX0),
734 * @ref XMC_UART_CH_INPUT_RXD1 (for DX3), @ref
XMC_UART_CH_INPUT_RXD2 (for DX5).
735 * @param sampling_freq Input sampling frequency. \n
736 * \b Range: @ref XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH, @ref
XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER.
737 * @return None
738 *
739 * \par<b>Description</b><br>
740 * Sets the sampling frequency for the UART input stage.\n\n
741 *
742 * \par<b>Related APIs:</b><BR>
743 * XMC_UART_CH_EnableInputSync(), XMC_UART_CH_EnableInputDigitalFilter()\n\n\n
744 */
745 __STATIC_INLINE void XMC_UART_CH_SetInputSamplingFreq(XMC_USIC_CH_t *const channel,
746 const XMC_UART_CH_INPUT_t input,
747 const
XMC_UART_CH_INPUT_SAMPLING_FREQ_
t sampling_freq)
748 {
749 XMC_USIC_CH_SetInputSamplingFreq(channel, (XMC_USIC_CH_INPUT_t)input, (
XMC_USIC_CH_INPUT_SAMPLING_FREQ_t)sampling_freq);
750 }
751
752 #ifdef __cplusplus
753 }
754 #endif
755
756 /**
757 * @}
758 */
759
760 /**
761 * @}
762 */
763
764 #endif
765