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24 views1 page

Dummy Resume

Uploaded by

jadhav shrikant
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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KAJAL

Intern at Cadence Design System


Email: kashyapkaju853@gmail.com
Ph.:9310334664
Mehrauli, Delhi, India (110030)

Education
B.Tech in Electronics and Communication Engineering July 2020 - 2023
J.C. Bose University of Science and Technology, YMCA Faridabad CGPA – 8.7/10

Diploma in Computer Engineering July 2017 -2020


Kasturba Institute of Technology CGPA – 7.2/10

Class-10th – Central Board of Secondary Education (CBSE) April 2016 - March 2017
Ramanan Nujan Sarvodaya Kanya Vidyalaya school CGPA – 7.8/10

Skills
● Knowledge: Digital electronics, Unix, Static time Analysis, CMOS, Network Theory, Computer Organization,ASIC
Design Flow, C++, FPGA, DSA, Algorithm, RTL to GDS II
● HDL: Verilog, System Verilog, UVM
● Scripting Language: TCL, SKILL, Perl.
● Protocol: I2C, UART
● Tools: Xcelium, Allegro, OrCAD Capture, PSpice, System Capture, Integrated 3D IC, System SI, Allegro System Architect,
OrCAD X Presto, DE-HDL library, Constraint Manager, Sigrity Aurora, Tempus, Genus, Virtuoso,.
Work Experience
• Cadence Design Systems (GTD/ES) | Project Intern (SPB Team) [March 2023 – Present]
➢ Developed the whole course for all tools of the SPB (Silicon Package Board)
➢ Working on SKILL CON, SKILL AI Training Bytes
➢ Worked on Integrated 3D IC, Signal Integrity, and Power integrity, Sigrity Aurora.
➢ Worked on System SI, DE-HDL library, Allegro tools, DFM, Router, and PCB Editor.
➢ Worked on System Capture, OrCAD Capture, Constraint Manager, OrPSpice.
Projects
• Design and Implementation of 32-bit Pipelined RISC-V Processor using Verilog HDL [Jul 2022 - Nov 2022]
➢ Carried out 5-Stage Pipelining to implement limited instruction set on Xilinx Vivado
➢ Implemented Data Forwarding and Stalling to remove Data Hazards and Flushing to remove Control Hazards

• Design of MOD-6 Up-Down Synchronous Counter in 65nm technology [Aug 2022 - Oct 2022]
➢ Designed the Schematic and Layout of MOD-6 Up-Down counter at a maximum clock frequency of 6 GHz without
violating Setup time and Holding time constraints
➢ Cleared DRC, verified LVS, and performed PEX analysis on Layout using Cadence Virtuoso

• 4 BIT ALU using Verilog [Mar 2022 - Apr 2022]


➢ Involves model-sim software for simulation
➢ Behavioral modeling style with switch case statements
➢ Blocking-Non blocking assignments with a proper test bench

• Design and Implementation of I2C and UART communication protocols using Verilog [Apr 2022- Jan 2023]
➢ RTL Design and Verification on Xilinx Vivado
➢ UART project consists of three main sections: The Transmitter, The Baud Rate generator (to synchronize transmitter and
Receiver), and finally, the Receiver. The project was made using Verilog

Achievements
● Cadence Certification: - Allegro PCB Editor, System Capture, Orcad Capture, OrPspice, Xcelium, C++,
Virtuoso Studio, DE-HDL Skill, Verilog, System Verilog, Basic Static Time Analysis, RTL to GDS II, Sigrity Aurora.

● FPGA Architecture and Programming using Verilog HDL by NIELIT Calicut: 11 May 2022- 08 June 2022.
● VLSI SoC Design using Verilog HDL by Maven Silicon: 12 Jan 2022- 04 Feb 2022.
● MEMBER OF IEEE YMCA SB: I have volunteer experience for the IEEE Society of my university, arranged, managed.

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