HIGH-SPEED 3.

3V 70V09L
128K x 8 DUAL-PORT
STATIC RAM

Features
◆
True Dual-Ported memory cells which allow simultaneous ◆
M/S = VIH for BUSY output flag on Master,
access of the same memory location M/S = VIL for BUSY input on Slave
◆
High-speed access ◆
Busy and Interrupt Flags
– Commercial: 15ns (max.) ◆
On-chip port arbitration logic
– Industrial: 20ns (max.) ◆
Full on-chip hardware support of semaphore signaling
◆
Low-power operation between ports
– IDT70V09L ◆
Fully asynchronous operation from either port
Active: 440mW (typ.) ◆
LVTTL-compatible, single 3.3V (±0.3V) power supply
Standby: 660µW (typ.) ◆
Available in a 100-pin TQFP
◆
Dual chip enables allow for depth expansion without ◆
Industrial temperature range (–40°C to +85°C) is available
external logic for selected speeds
◆
IDT70V09 easily expands data bus width to 16 bits or ◆
Green parts available, see ordering information
more using the Master/Slave select when cascading more
than one device

Functional Block Diagram

R/W L R/W R
CE0L CE0R
CE1L CE1R
OE L OE R

I/O 0-7L I/O I/O

Control Control I/O 0-7R

(1,2) (1,2)
BUSY L BUSY R

128Kx8
A16L MEMORY A16R
Address Address
Decoder ARRAY Decoder
A0L 70V09 A 0R

17 17

ARBITRATION
CE 0L INTERRUPT CE0R
CE1L SEMAPHORE CE1R
LOGIC
OE L OER
R/W L R/WR

SEM L SEMR
(2)
INT L (1) INT R
(2)

M/S
4852 drw 01
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
JUNE 2019
1
©2019 Integrated Device Technology, Inc. DSC-4852/8
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description
The IDT70V09 is a high-speed 128K x 8 Dual-Port Static RAM. The reads and writes to any location in memory. An automatic power down
IDT70V09 is designed to be used as a stand-alone 1024K-bit Dual-Port feature controlled by the chip enables (either CE0 or CE1) permit the on-
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit- chip circuitry of each port to enter a very low standby power mode.
or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM Fabricated using CMOS high-performance technology, these de-
approach in 16-bit or wider memory system applications results in full- vices typically operate on only 440mW of power. The IDT70V09 is
speed, error-free operation without the need for additional discrete logic. packaged in a 100-pin Thin Quad Flatpack (TQFP).
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for

Pin Configurations(1,2,3)

SEMR
R/WR
CE0R
CE1R
GND

GND
GND
A10R
A11R
A12R
A13R
A14R
A15R
A16R

OER
A7R
A8R
A9R
NC
NC

NC
NC
NC
NC

NC
NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC
76 50
NC 77 49 NC
A6R 78 48 NC
A5R 79 47 I/O7R
A4R 80 46 I/O6R
A3R 81 45 I/O5R
A2R 82 44 I/O4R
A1R 83 43 I/O3R
A0R 84 42 Vcc
INTR 85 41 I/O2R
BUSYR 70V09
86 40 I/O1R
PNG100(4)
M/S 87 39 I/O0R
GND 88 100-Pin 38 GND
BUSYL 89 TQFP 37 Vcc
INTL 90 Top View 36 I/O0L
NC 91 35 I/O1L
A0L 92 34 GND
A1L 93 33 I/O2L
A2L 94 32 I/O3L
A3L 95 31 I/O4L
A4L 96 30 I/O5L
A5L 97 29 I/O6L
A6L 98 28 I/O7L
NC 99 27 NC
NC 100 26 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

4852 drw
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
A15L
A16L
Vcc
NC
NC
NC
NC
CE0L
CE1L
SEML
R/WL
OEL
GND
NC
NC

NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.

2
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names
Left Port Right Port Names

CE0L, CE1L CE0R, CE1R Chip Enables

R/WL R/WR Read/Write Enable

OEL OER Output Enable

A0L - A16L A0R - A16R Address

I/O0L - I/O7L I/O0R - I/O7R Data Input/Output

SEML SEMR Semaphore Enable

INTL INTR Interrupt Flag

BUSYL BUSYR Busy Flag

M/S Master or Slave Select

VCC Power

GND Ground
4852 tbl 01

Absolute Maximum Ratings(1) Recommended DC Operating

Symbol Rating Commercial Unit Conditions
& Industrial
Symbol Parameter Min. Typ. Max. Unit
VTERM(2) Terminal Voltage -0.5 to +4.6 V
with Respect VCC Supply Voltage 3.0 3.3 3.6 V
to GND GND Ground 0 0 0 V
TBIAS Temperature -55 to +125 o
C VIH Input High Voltage 2.0 ____
VCC+0.3 (2)
V
Under Bias
(1)
VIL Input Low Voltage -0.3 ____
0.8 V
TSTG Storage -65 to +150 o
C
Temperature 4852 tbl 04
NOTES:
IOUT DC Output 50 mA 1. VIL > -1.5V for pulse width less than 10ns.
Current 2. VTERM must not exceed Vcc + 0.3V.

4852 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute Capacitance(1) (TA = +25°C, f = 1.0MHz)
maximum rating conditions for extended periods may affect reliability. Symbol Parameter Conditions(2) Max. Unit
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V. CIN Input Capacitance VIN = 3dV 9 pF

COUT Output Capacitance VOUT = 3dV 10 pF

4852 tbl 05

Maximum Operating Temperature NOTES:

1. This parameter is determined by device characterization but is not produc-
and Supply Voltage tion tested.
2. 3dV represents the interpolated capacitance when the input and output signals
Grade Ambient GND Vcc
switch from 0V to 3V or from 3V to 0V.
Temperature(1)
Commercial 0OC to +70OC 0V 3.3V + 0.3V
Industrial -40 C to +85 C
O O
0V 3.3V + 0.3V
4852 tbl 03
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.

3
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table I – Chip Enable(1,2)

CE CE0 CE 1 Mode
VIL VIH Port Selected (TTL Active)
L < 0.2V >VCC -0.2V Port Selected (CMOS Active)

VIH X Port Deselected (TTL Inactive)

H X VIL Port Deselected (TTL Inactive)

>VCC -0.2V X(3) Port Deselected (CMOS Inactive)
(3)
X <0.2V Port Deselected (CMOS Inactive)
4852 tbl 06
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only.
2. 'H' = VIH and 'L' = VIL.
3. CMOS standby requires 'X' to be either < 0.2V or >VCC-0.2V.

Truth Table II – Non-Contention Read/Write Control

Inputs(1) Outputs
(2)
CE R/W OE SEM I/O0-7 Mode
H X X H High-Z Deselected: Power-Down

L L X H DATAIN Write to Memory

L H L H DATAOUT Read Memory
X X H X High-Z Outputs Disabled
4852 tbl 07
NOTES:
1. A0L — A16L ≠ A0R — A16R
2. Refer to Truth Table I - Chip Enable.

Truth Table III – Semaphore Read/Write Control(1)

Inputs Outputs
(2)
CE R/W OE SEM I/O0-7 Mode

H H L L DATAOUT Read Semaphore Flag Data Out

H ↑ X L DATAIN Write I/O0 into Semaphore Flag

L X X L ______
Not Allowed
4852 tbl 08
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2.
2. Refer toTruth Table I -Chip Enable .

4
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V09L

Symbol Parameter Test Conditions Min. Max. Unit

(1)
|ILI| Input Leakage Current VCC = 3.6V, VIN = 0V to V CC ___
5 µA

|ILO| Output Leakage Current CE(2) = VIH, VOUT = 0V to V CC ___

5 µA

VOL Output Low Voltage IOL = +4mA ___

0.4 V
VOH Output High Voltage IOH = -4mA 2.4 ___
V
4852 tbl 09
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Truth Table I - Chip Enable.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(5) (VCC = 3.3V ± 0.3V)
70V09L15 70V09L20
Com'l Only Com'l
& Ind
Symbol Parameter Test Condition Version Typ.(1) Max. Typ.(1) Max. Unit

ICC Dynamic Operating CE = VIL, Outputs Disabled COM'L L 145 235 135 205 mA
Current SEM = VIH
(Both Ports Active) f = fMAX(2) IND L ____ ____
135 220

ISB1 Standby Current CEL = CER = VIH COM'L L 40 70 35 55 mA

(Both Ports - TTL Level SEMR = SEML = VIH
Inputs) f = fMAX(2) IND L ____ ____
35 65

ISB2 Standby Current CE"A" = VIL and CE"B" = VIH (4)

COM'L L 100 155 90 140 mA
(One Port - TTL Level Active Port Outputs Disabled,
Inputs) f=fMAX(2), SEMR = SEML = VIH IND L ____ ____
90 150

ISB3 Full Standby Current Both Ports CEL and CER > VCC - 0.2V, COM'L L 0.2 3.0 0.2 3.0 mA
(Both Ports - All CMOS VIN > VCC - 0.2V or V IN < 0.2V, f = 0(3)
Level Inputs) SEMR = SEML > VCC - 0.2V IND L ____ ____
0.2 3.0

ISB4 Full Standby Current CE"A" < 0.2V and CE"B" > VCC - 0.2V(4), COM'L L 95 150 90 135 mA
(One Port - All CMOS SEMR = SEML > VCC - 0.2V,
Level Inputs) VIN > VCC - 0.2V or V IN < 0.2V, IND L ____ ____
90 145
Active Port Outputs Disabled, f = fMAX(2)
4852 tbl 10
NOTES:
1. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 90mA (Typ.)
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels of GND
to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Truth Table I - Chip Enable.

5
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions 3.3V 3.3V

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns Max. 590Ω 590Ω
Input Timing Reference Levels 1.5V DATAOUT
Output Reference Levels 1.5V BUSY DATAOUT
INT
Output Load Figures 1 and 2 435Ω 30pF 435Ω 5pF*
4852 tbl 11

4852 drw 03 4852 drw 04

Figure 1. AC Output Load Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.

Waveform of Read Cycles(5)

tRC
ADDR
(4)
tAA
(4)
CE(6) tACE

(4)
tAOE
OE

R/W

tLZ
(1) tOH
(4)
DATAOUT VALID DATA
(2)
tHZ
BUSYOUT
(3,4)
tBDD 4852 drw 05

Timing of Power-Up Power-Down

CE(6)

tPU tPD
ICC
50% 50%
.
ISB 4852 drw 06

NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Truth Table I - Chip Enable.

6
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range
70V09L15 70V09L20
Com'l Only Com'l
& Ind
Symbol Parameter Min. Max. Min. Max. Unit

READ CYCLE

tRC Read Cycle Time 15 ____

20 ____
ns

tAA Address Access Time ____

15 ____
20 ns
(3)
tACE Chip Enable Access Time ____
15 ____
20 ns

tAOE Output Enable Access Time ____

10 ____
12 ns

tOH Output Hold from Address Change 3 ____

3 ____
ns

tLZ Output Low-Z Time (1,2) 3 ____

3 ____
ns

tHZ Output High-Z Time (1,2) ____

10 ____
10 ns
(2)
tPU Chip Enab le to Power Up Time 0 ____
0 ____
ns
(2)
tPD Chip Disable to Power Down Time ____
15 ____
20 ns

tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____

10 ____
ns

tSAA Semaphore Address Access Time ____

15 ____
20 ns
4852 tbl 12

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage
70V09L15 70V09L20
Com'l Only Com'l
& Ind

Symbol Parameter Min. Max. Min. Max. Unit

WRITE CYCLE
tWC Write Cycle Time 15 ____
20 ____
ns
(3)
tEW Chip Enable to End-of-Write 12 ____
15 ____
ns
tAW Address Valid to End-of-Write 12 ____
15 ____
ns
(3)
tAS Address Set-up Time 0 ____
0 ____
ns

tWP Write Pulse Width 12 ____

15 ____
ns
tWR Write Recovery Time 0 ____
0 ____
ns
tDW Data Valid to End-of-Write 10 ____
15 ____
ns

tHZ Output High-Z Time (1,2) ____

10 ____
10 ns
tDH Data Hold Time (4) 0 ____
0 ____
ns
(1,2)
tWZ Write Enab le to Output in High-Z ____
10 ____
10 ns
(1,2,4)
tOW Output Active from End-of-Write 0 ____
0 ____
ns

tSWRD SEM Flag Write to Read Time 5 ____

5 ____
ns

tSPS SEM Flag Contention Window 5 ____

5 ____
ns
4852 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.

7
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)

tWC
ADDRESS
tHZ (7)

OE

tAW
(9,10)
CE or SEM

(6) (3)
tAS tWP (2) tWR

R/W
tWZ (7) tOW
(4) (4)
DATAOUT
tDW tDH

DATAIN
4852 drw 07

Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)

tWC
ADDRESS

tAW
(9,10)
CE or SEM
(3)
tAS (6) tEW (2) tWR

R/W
tDW tDH

DATAIN
4852 drw 08
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Truth Table I - Chip Enable.

8
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

tSAA
A0-A2 VALID ADDRESS VALID ADDRESS
tAW tWR tACE
tEW
SEM
tOH
tDW tSOP
DATA OUT(2)
I/O DATAIN VALID VALID
tAS tWP tDH
R/W

tSWRD tAOE

OE
tSOP
Write Cycle Read Cycle
4852 drw 09

NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O7) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention(1,3,4)

A0"A"-A2"A" MATCH

(2)
SIDE "A" R/W"A"

SEM"A"
tSPS

A0"B"-A2"B" MATCH

(2)
SIDE "B" R/W"B"

SEM"B"
4852 drw 10

NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.

9
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range
70V09L15 70V09L20
Com'l Only Com'l
& Ind

Symbol Parameter Min. Max. Min. Max. Unit

BUSY TIMING (M/S=VIH)
tBAA BUSY Access Time from Address Match ____
15 ____
20 ns

tBDA BUSY Disable Time from Address Not Matched ____

15 ____
20 ns

tBAC BUSY Access Time from Chip Enable Low ____

15 ____
20 ns

tBDC BUSY Access Time from Chip Enable High ____

15 ____
17 ns

tAPS Arbitration Priority Set-up Time (2) 5 ____

5 ____
ns

tBDD (3) 15 17 ns
BUSY Disable to Valid Data ____ ____

(5)
tWH Write Hold After BUSY 12 ____
15 ____
ns
BUSY TIMING (M/S=VIL)
tWB BUSY Input to Write(4) 0 ____
0 ____
ns

tWH Write Hold After BUSY(5) 12 ____

15 ____
ns
PORT-TO-PORT DELAY TIMING

tWDD Write Pulse to Data Delay (1) ____

30 ____
45 ns

tDDD Write Data Valid to Read Data Delay (1) ____

25 ____
30 ns
4852 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".

10
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
tWC

ADDR"A" MATCH
tWP

R/W"A"
tDW tDH

DATAIN "A" VALID

(1)
tAPS

ADDR"B" MATCH

tBAA tBDA tBDD

BUSY"B"

tWDD
DATAOUT "B" VALID

tDDD (3) .
4852 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL, refer to Chip Enable Truth Table.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

Timing Waveform of Write with BUSY (M/S = VIL)

tWP

R/W"A"

tWB(3)
BUSY"B" (1)
tWH

R/W"B" (2)

4852 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'slave' version.

11
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1,3)

ADDR"A"
and "B" ADDRESSES MATCH

CE"A"
tAPS (2)

CE"B"
tBAC tBDC

BUSY"B"
4852 drw 13

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing (M/S = VIH)(1)

ADDR"A" ADDRESS "N"

tAPS (2)
ADDR"B" MATCHING ADDRESS "N"
tBAA tBDA
BUSY"B"
4852 drw 14

NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Truth Table I - Chip Enable.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range
70V09L15 70V09L20
Com'l Only Com'l
& Ind
Symbol Parameter Min. Max. Min. Max. Unit

INTERRUPT TIMING
tAS Address Set-up Time 0 ____
0 ____
ns

tWR Write Recovery Time 0 ____

0 ____
ns
tINS Interrupt Set Time ____
15 ____
20 ns

tINR Interrupt Reset Time ____

15 ____
20 ns
4852 tbl 15

12
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing(1,5)

tWC
(2)
ADDR"A" INTERRUPT SET ADDRESS
(3) (4)
tAS tWR
CE"A"

R/W"A"
(3)
tINS

INT"B"
4852 drw 15

tRC
(2)
ADDR"B" INTERRUPT CLEAR ADDRESS
(3)
tAS
CE"B"

OE"B"

tINR (3)
INT"B"
4852 drw 16

NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Truth Table I - Chip Enable.

Truth Table IV — Interrupt Flag(1,4,5)

Left Port Right Port
R/WL CEL OEL A16L-A0L INTL R/WR CER OER A16R-A0R INTR Function
(2)
L L X 1FFFF X X X X X L Set Right INTR Flag
(3)
X X X X X X L L 1FFFF H Reset Right INTR Flag
X X X X L(3) L L X 1FFFE X Set Left INTL Flag

X L L 1FFFE H(2) X X X X X Reset Left INTL Flag

4852 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. Refer to Truth Table I - Chip Enable.

13
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table V —
Address BUSY Arbitration(4)
Inputs Outputs

AOL-A16L
CEL CER AOR-A16R BUSYL(1) BUSYR(1) Function

X X NO MATCH H H Normal

H X MATCH H H Normal

X H MATCH H H Normal

L L MATCH (2) (2)

Write Inhibit(3)

4852 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V09 are push-
pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Truth Table I - Chip Enable.

Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)

Functions D0 - D7 Left D0 - D7 Right Status

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

4852 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V09.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to Truth Table III - Semaphore Read/Write Control.

Functional Description
The IDT70V09 provides two ports with separate control, address 1FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
and I/O pins that permit independent access for reads or writes to any Truth Table. The left port clears the interrupt through access of
location in memory. The IDT70V09 has an automatic power down address location 1FFFE when CEL = OEL = VIL, R/W is a "don't care".
feature controlled by CE. The CE0 and CE1 control the on-chip power Likewise, the right port interrupt flag (INTR) is asserted when the left
down circuitry that permits the respective port to go into a standby port writes to memory location 1FFFF (HEX) and to clear the interrupt
mode when not selected (CE HIGH). When a port is enabled, access flag (INTR), the right port must read the memory location 1FFFF. The
to the entire memory array is permitted. message (8 bits) at 1FFFE or 1FFFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used,
Interrupts address locations 1FFFE and 1FFFF are not used as mail boxes, but
If the user chooses the interrupt function, a memory location (mail as part of the random access memory. Refer to Truth Table IV for the
box or message center) is assigned to each port. The left port interrupt interrupt operation.
flag (INTL) is asserted when the right port writes to memory location
14
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Busy Logic address signals only. It ignores whether an access is a read or write.
Busy Logic provides a hardware indication that both ports of the In a master/slave array, both address and chip enable must be valid
RAM have accessed the same location at the same time. It also allows long enough for a BUSY flag to be output from the master before the
one of the two accesses to proceed and signals the other side that the actual write pulse can be initiated with the R/W signal. Failure to
RAM is “Busy”. The BUSY pin can then be used to stall the access until observe this timing can result in a glitched internal write inhibit signal
the operation on the other side is completed. If a write operation has and corrupted data in the slave.
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding. Semaphores
The use of BUSY logic is not required or desirable for all applica- The IDT70V09 is an extremely fast Dual-Port 128K x 8 CMOS
tions. In some cases it may be useful to logically OR the BUSY outputs Static RAM with an additional 8 address locations dedicated to binary
together and use any BUSY indication as an interrupt source to flag the semaphore flags. These flags allow either processor on the left or right
event of an illegal or illogical operation. If the write inhibit function of side of the Dual-Port RAM to claim a privilege over the other processor
BUSY logic is not desirable, the BUSY logic can be disabled by placing for functions defined by the system designer’s software. As an ex-
the part in slave mode with the M/S pin. Once in slave mode the BUSY ample, the semaphore can be used by one processor to inhibit the
pin operates solely as a write inhibit input pin. Normal operation can be other from accessing a portion of the Dual-Port RAM or any other
programmed by tying the BUSY pins HIGH. If desired, unintended shared resource.
write operations can be prevented to a port by tying the BUSY pin for The Dual-Port RAM features a fast access time, with both ports
that port LOW. being completely independent of each other. This means that the
The BUSY outputs on the IDT 70V09 RAM in master mode, are activity on the left port in no way slows the access time of the right port.
push-pull type outputs and do not require pull up resistors to operate. Both ports are identical in function to standard CMOS Static RAM and
If these RAMs are being expanded in depth, then the BUSY indication can be read from or written to at the same time with the only possible
for the resulting array requires the use of an external AND gate. conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
A17
system program to avoid any conflicts in the non-semaphore portion
MASTER CE0 SLAVE CE0 of the Dual-Port RAM. These devices have an automatic power-down
Dual Port RAM Dual Port RAM
feature controlled by CE, the Dual-Port RAM enable, and SEM, the
BUSYL BUSYR BUSYL BUSYR semaphore enable. The CE and SEM pins control on-chip power
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
MASTER CE1 SLAVE CE1
Dual Port RAM Dual Port RAM III where CE and SEM are both HIGH.
Systems which can best use the IDT70V09 contain multiple
BUSYL BUSYR BUSYL BUSYR
processors or controllers and are typically very high-speed systems
.
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V09s
4852 drw 17

Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V09 RAMs.
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
Width Expansion with Busy Logic varying configurations. The IDT70V09 does not use its semaphore
Master/Slave Arrays flags to control any resources through hardware, thus allowing the
When expanding an IDT70V09 RAM array in width while using system designer total flexibility in system architecture.
BUSY logic, one master part is used to decide which side of the RAMs An advantage of using semaphores rather than the more common
array will receive a BUSY indication, and to output that indication. Any methods of hardware arbitration is that wait states are never incurred
number of slaves to be addressed in the same address range as the in either processor. This can prove to be a major advantage in very
master use the BUSY signal as a write inhibit signal. Thus on the high-speed systems.
IDT70V09 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used How the Semaphore Flags Work
as a slave (M/S pin = VIL) as shown in Figure 3. The semaphore logic is a set of eight latches which are indepen-
If two or more master parts were used when expanding in width, a dent of the Dual-Port RAM. These latches can be used to pass a flag,
split decision could result with one master indicating BUSY on one side or token, from one port to the other to indicate that a shared resource
of the array and another master indicating BUSY on one other side of is in use. The semaphores provide a hardware assist for a use
the array. This would inhibit the write operations from one port for part assignment method called “Token Passing Allocation.” In this method,
of a word and inhibit the write operations from the other port for the the state of a semaphore latch is used as a token indicating that a
other part of the word. shared resource is in use. If the left processor wants to use this
The BUSY arbitration on a master is based on the chip enable and resource, it requests the token by setting the latch. This processor then
15
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

verifies its success in setting the latch by reading it. If it was successful, question. Meanwhile, if a processor on the right side attempts to write
it proceeds to assume control over the shared resource. If it was not a zero to the same semaphore flag it will fail, as will be verified by the
successful in setting the latch, it determines that the right side fact that a one will be read from that semaphore on the right side during
processor has set the latch first, has the token and is using the shared subsequent read. Had a sequence of READ/WRITE been used
resource. The left processor can then either repeatedly request that instead, system contention problems could have occurred during the
semaphore’s status or remove its request for that semaphore to gap between the read and write cycles.
perform another task and occasionally attempt again to gain control of It is important to note that a failed semaphore request must be
the token via the set and test sequence. Once the right side has followed by either repeated reads or by writing a one into the same
relinquished the token, the left side should succeed in gaining control. location. The reason for this is easily understood by looking at the
The semaphore flags are active LOW. A token is requested by simple logic diagram of the semaphore flag in Figure 4. Two sema-
writing a zero into a semaphore latch and is released when the same phore request latches feed into a semaphore flag. Whichever latch is
side writes a one to that latch. first to present a zero to the semaphore flag will force its side of the
The eight semaphore flags reside within the IDT70V09 in a semaphore flag LOW and the other side HIGH. This condition will
separate memory space from the Dual-Port RAM. This address space
is accessed by placing a low input on the SEM pin (which acts as a chip L PORT R PORT
select for the semaphore flags) and using the other control pins
(Address, CE, and R/W) as they would be used in accessing a SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
standard Static RAM. Each of the flags has a unique address which
can be accessed by either side through address pins A0 – A2. When D0 D Q Q D D0
accessing the semaphores, none of the other address pins has any WRITE WRITE

effect.
When writing to a semaphore, only data pin D0 is used. If a low level SEMAPHORE
READ
SEMAPHORE
READ
is written into an unused semaphore location, that flag will be set to a 4852 drw 18
zero on that side and a one on the other side (see Truth Table VI). That
semaphore can now only be modified by the side showing the zero. Figure 4. IDT70V09 Semaphore Logic
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request continue until a one is written to the same semaphore request latch.
from the other side is pending) and then can be written to by both sides. Should the other side’s semaphore request latch have been written to
The fact that the side which is able to write a zero into a semaphore a zero in the meantime, the semaphore flag will flip over to the other
subsequently locks out writes from the other side is what makes side as soon as a one is written into the first side’s request latch. The
semaphore flags useful in interprocessor communications. (A thor- second side’s flag will now stay LOW until its semaphore request latch
ough discussion on the use of this feature follows shortly.) A zero is written to a one. From this it is easy to understand that, if a
written into the same location from the other side will be stored in the semaphore is requested and the processor which requested it no
semaphore request latch for that side until the semaphore is freed by longer needs the resource, the entire system can hang up until a one
the first side. is written into that semaphore request latch.
When a semaphore flag is read, its value is spread into all data bits The critical case of semaphore timing is when both sides request
so that a flag that is a one reads as a one in all data bits and a flag a single token by attempting to write a zero into it at the same time. The
containing a zero reads as all zeros. The read value is latched into one semaphore logic is specially designed to resolve this problem. If
side’s output register when that side's semaphore select (SEM) and simultaneous requests are made, the logic guarantees that only one
output enable (OE) signals go active. This serves to disallow the side receives the token. If one side is earlier than the other in making
semaphore from changing state in the middle of a read cycle due to a the request, the first side to make the request will receive the token. If
write cycle from the other side. Because of this latch, a repeated read both requests arrive at the same time, the assignment will be arbitrarily
of a semaphore in a test loop must cause either signal (SEM or OE) to made to one port or the other.
go inactive or the output will never change. One caution that should be noted when using semaphores is that
A sequence WRITE/READ must be used by the semaphore in semaphores alone do not guarantee that access to a resource is
order to guarantee that no system level contention will occur. A secure. As with any powerful programming technique, if semaphores
processor requests access to shared resources by attempting to write are misused or misinterpreted, a software error can easily happen.
a zero into a semaphore location. If the semaphore is already in use, Initialization of the semaphores is not automatic and must be
the semaphore request latch will contain a zero, yet the semaphore handled via the initialization program at power-up. Since any sema-
flag will appear as one, a fact which the processor will verify by the phore request flag which contains a zero must be reset to a one,
subsequent read (see Table VI). As an example, assume a processor all semaphores on both sides should have a one written into them
writes a zero to the left port at a free semaphore location. On a at initialization from both sides to assure that they will be free
subsequent read, the processor will verify that it has written success- when needed.
fully to that location and will assume control over the resource in

16
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information
XXXXX A 999 A A A A
Device Power Speed Package Process/
Type Temperature
Range Blank Tray
8 Tape and Reel

Blank Commercial (0°C to +70°C)

I Industrial (-40°C to +85°C)

G Green

PF 100-pin TQFP (PNG100)

15 Commercial Only Speed in nanoseconds

20 Industrial Only

L Low Power

70V09 1024K (128K x 8) Dual-Port RAM

4852 drw 19

NOTE:
1. LEAD FINISH (SnPb) are Obsolete - Product Discontinuation Notice - PDN#SP-17-02
Note that information regarding recently obsoleted parts is included in this datasheet for customer convenience.

Orderable Part Information

Speed Pkg. Pkg. Temp.
Orderable Part ID
(ns) Code Type Grade
15 70V09L15PFG PNG100 TQFP C
70V09L15PFG8 PNG100 TQFP C
20 70V09L20PFGI PNG100 TQFP I
70V09L20PFGI8 PNG100 TQFP I

17
 70V09L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Datasheet Document History:

09/30/99: Initial Public Offering
11/12/99: Page 1 & 17 Replaced IDT logo
04/10/00: Page 2 Fixed incorrect pin number
01/02/02: Page 3 Increased storage temperature parameter
Clarified TA parameter
Page 5 DC Electrical parameters–changed wording from "open" to "disabled"
Added Truth Table I - Chip Enable as note 5
Page 7 Corrected ±200mV to 0mV in footnotes
Page 5 ,7 ,10 & 12 Added Industrial Temperature range for 20ns to DC & AC Electrical Characteristics
Page 3, 5, 7, 10 & 12 Removed industrial temp option footnote from all tables
08/27/03: Removed Preliminary status
01/29/09: Page 17 Removed "IDT" from orderable part number
02/06/13: Page 1 Added green availability to Features
Page 2 Removed IDT in reference to fabrication
Page 17 Added green and T&R indicators to ordering information
12/06/17: Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
06/18/19: Page 1 & 17 Deleted obsolete Commercial speed grade 20ns in Features and Ordering Information
Page 2 Rotated PNG100 TQFP pin configuration to accurately reflect pin 1 orientation
Page 17 Added Orderable Part Information table

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18
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