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Design of an Error Tolerant Adder

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DOI: 10.3844/ajassp.2012.818.824

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American Journal of Applied Sciences 9 (6): 818-824, 2012
ISSN 1546-9239
© 2012 Science Publications

Design of an Error Tolerant Adder

1
Jayanthi, A.N. and 2C.S. Ravichandran
1
Department of Electronics and Communication Engineering,
Sri Ramakrishna Institute of Technology, Coimbatore, India
2
Department of Electrical and Electronics Engineering,
SSK College of Engineering and Technology Coimbatore, India

Abstract: Problem statement: In modern VLSI technology, the occurrence of all kinds of errors has
become inevitable. By adopting an emerging concept in VLSI design and test, Error Tolerance (ET), a
novel Error-Tolerant Adder (ETA) is proposed. The ETA is able to ease the strict restriction on
accuracy and at the same time achieve tremendous improvements in both the power consumption and
speed performance. When compared to its conventional counterparts, the proposed ETA is able to
attain improvement in the Power-Delay Product (PDP). Conclusion/Recommendations: One
important potential application of the proposed ETA is in digital signal processing systems that can
tolerate certain amount of errors. Delay and power are compared for various adders like RCA and
CLA. It is found that ETA has high speed and less power compared to its counterparts.

Key words: Error-Tolerant Adder (ETA), Error Tolerance (ET), Power-Delay Product (PDP),
Minimum Acceptable Accuracy (MAA), Least Significant Bit (LSB)

INTRODUCTION 2005; Cheemalavagu et al., 2004; Korkmaz et al.,

2006) are two of them. According to the definition, a
In conventional digital VLSI design, one usually circuit is error tolerant if: (1) it contains defects that
assumes that a usable circuit/system should always cause internal and may cause external errors and (2) the
provide definite and accurate results. But in fact, system that incorporates this circuit produces
such perfect operations are seldom needed in our acceptable results. The “imperfect” attribute seems to
nondigital worldly experiences. The world accepts be not appealing. However, the need for the error-
“analog computation,” which generates “good tolerant circuit (Breuer and Zhu, 2006; Breuer et al.,
enough” results rather than totally accurate results 2004; Breuer, 2004; Lee et al., 2005; Chong and
(Breuer, 2005). The data processed by many digital Ortega, 2005; Chung and Ortega, 2005; Kuok, 1995;
systems may already contain errors. Hsieh et al., 2007) was foretold in the 2003
In many applications, such as a communication International Technology Roadmap for
system, the analog signal coming from the outside Semiconductors (ITRS) International Technology
world must first be sampled before being converted to Roadmap for Semiconductors. To deal with error-
digital data. The digital data are then processed and tolerant problems, some truncated adders/multipliers
transmitted in a noisy channel before converting back to have been reported (Stine et al., 2005; Van and
an analog signal. During this process, errors may occur Yang, 2005) but are not able to perform well in its
anywhere. Furthermore, due to the advances in speed, power, area, or accuracy. The “flagged
transistor size scaling, factors such as noise and process prefixed adder” (Stine et al., 2005) performs better
variations which are previously insignificant are than the nonflagged version with a 1.3% speed
becoming important in today’s digital IC design enhancement but at the expense of 2% extra silicon
International Technology Roadmap for area. As for the “low-error area-efficient fixed-width
Semiconductors. Based on the characteristic of digital multipliers” (Van and Yang, 2005), it may have an
VLSI design, some novel concepts and design area improvement of 46.67% but has average error
techniques have been proposed. The concept of Error reaching 12.4%.Of course, not all digital systems can
Tolerance (ET) (Breuer and Zhu, 2006; Breuer et al., engage the error-tolerant concept. In digital systems
2004; Breuer, 2004; Lee et al., 2005; Chong and such as control systems, the correctness of the output
Ortega, 2005; Chung and Ortega, 2005; Kuok, 1995; signal is extremely important and this denies the use
Hsieh et al., 2007) and the PCMOS technology (Palem, of the error tolerant circuit.
Corresponding Author: Jayanthi, A.N., Department of Electronics and Communication Engineering,
Sri Ramakrishna Institute of Technology, Coimbatore, India
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 Am. J. Applied Sci., 9 (6): 818-824, 2012

The layout of ripple carry adder is simple, which

allows for fast design time; however, the ripple carry
adder is relatively slow, since each full adder must wait
for the carry bit to be calculated from the previous full
adder. The gate delay can easily be calculated by
inspection of the full adder circuit. Each full adder
requires three levels of logic. In a 32-bit (ripple carry)
adder, there are 32 full adders, so the critical path
(worst case) delay is 31 * 2(for carry propagation) +
3(for sum) = 65 gate delays. Table 1 and 2 shows the
result obtained for RCA.

Fig. 1: Block diagram of 4 Bit Ripple Carry Carry-look-ahead adder CLA: Carry look ahead logic
uses the concepts of generating and propagating carries.
The addition of two 1-digit inputs A and B is said to
generate if the addition will always carry, regardless of
whether there is an input carry. In the case of binary
addition, A+B generates if and only if both a and B are
1. The addition of two 1-digit inputs A and B is said to
propagate if the addition will carry whenever there is an
input carry. The propagate and generate are defined with
respect to a single digit of addition and do not depend on
any other digits in the sum. In the case of binary addition,
A+B propagates if and only if at least one of A or B is 1.
Fig. 2: Block diagram of 4bit carry-look-ahead adder Sometimes a slightly different definition of propagate is
used. By this definition, A+B is said to propagate if the
Table 1: Comparison of delay in adders addition will carry whenever there is an input carry, but
No. of bits/adder RCA (ns) CLA (ns) ETA (ns) will not carry if there is no input carry. For binary
4 bits 11.953 11.989 7.570 arithmetic, or is faster than xor and takes fewer transistors
8 bits 18.607 18.453 8.156 to implement. However, for a multiple-level carry look
12 bits 25.247 24.917 8.300 ahead adder, it is simpler to use. Block Diagram of 4bit
16 bits 31.887 31.381 7.913
32 bits 31.815 57.237 9.411 carry-look-ahead adder is as in Fig. 2.
The carry look ahead adder represents the most
Table 2: Comparison of power in adders widely used design for high-speed adders in modern
No. of bits/adder RCA CLA ETA Computers. The advantage of using a look-ahead design
4 bits 2.199 1.787 0.073 over a ripple carry adder is that the Look-ahead is faster
8 bits 4.988 142.000 0.016 in computing the solution. The carry-in values in a
12 bits 8.237 74.523 0.001 carry look-ahead design are calculated independent of
16 bits 0.142 1294.000 0.021
32 bits 0.028 0.135 0.014 each other through a series of logic circuits.
Carry look ahead depends on two things:
However, for many Digital Signal Processing (DSP)
systems that process signals relating to human senses • Calculating, for each digit position, whether that
such as hearing, sight, smell and touch, e.g., the image position is going to propagate a carry if one comes
processing and speech processing systems, the error- in from the right
tolerant circuits may be applicable (Breuer and Zhu, • Combining these calculated values so as to be able
2006; Lee et al., 2005; Chong and Ortega, 2005). to deduce quickly whether, for each group of
digits, that group is going to propagate a carry that
Conventional adders: comes in from the right
Ripple-Carry Adder (RCA): The n-bit adder built • Supposing that groups of 4 digits are chosen
from n one-bit full adders is known as a ripple carry
adder, because of the way the carry is computed. Each Then the sequence of events goes something like this:
full adder inputs a Cin, which is the Cout of the previous
adder. This kind of adder is a ripple carry adder, since • All 1-bit adders calculate their results.
each carry bit “ripples” to the next full adder. Block Simultaneously, the look ahead units perform their
diagram of Ripple Carry Adder is as in Fig. 1. calculations.
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• Suppose that a carry arises in a particular group. By sacrificing some accuracy, the ETA can attain
Within at most 3 gate delays, that carry will great improvement in both the power consumption and
emerge at the left-hand end of the group and start speed performance.
propagating through the group to its left ETA design was proposed in Zhu et al. (2010).
• If that carry is going to propagate all the way Design of low-power high-speed truncation-error-
through the next group, the look ahead unit will tolerant adder and its application in digital signal
processing. IEEE Transactions on Very Large Scale
already have deduced this. Accordingly, before the
Integration (VLSI) Syst., 18: 8. However there are
carry emerges from the next group the look ahead unit tradeoffs between speed and power.
is immediately (within 1 gate delay) able to tell the
next group to the left that it is going to receive a carry Proposed addition arithmetic: In a conventional adder
- and, at the same time, to tell the next look ahead unit circuit, the delay is mainly attributed to the carry
to the left that a carry is on its way Table 1 and 2 propagation chain along the critical path, from the Least
shows the result obtained for CLA Significant Bit (LSB) to the Most Significant Bit
(MSB). Meanwhile, a significant proportion of the
Error-tolerant adder: Before detailing the ETA, the
definitions of some commonly used terminologies power consumption of an adder is due to the glitches
shown in this study are given as follows: that are caused by the carry propagation. Therefore, if
the carry propagation can be eliminated or curtailed, a
• Overall error (OE) OE = Rc-RE, where RE, is the great improvement in speed performance and power
result obtained by the adder and Rc denotes the consumption can be achieved. In this study, we propose
correct result (all the results are represented as for the first time, an innovative and novel addition
decimal numbers) arithmetic that can attain great saving in speed and
• Accuracy (ACC): In the scenario of the error- power consumption. This new addition arithmetic can
tolerant design, the accuracy of an adder is used to be illustrated via an example shown in Fig. 3.We first
indicate how “correct” the output of an adder is for split the input operands into two parts: an accurate part
a particular input. It is defined as: ACC = (1-(OE/ that includes several higher order bits and the
Rc))/100% inaccurate part that is made-up of the remaining lower
• Its value ranges from 0-100%. order bits. The length of each part need not necessary
• Minimum Acceptable Accuracy (MAA): Although be equal. The addition process starts from the middle
some errors are allowed to exist at the output of an (joining point of the two parts) toward the two opposite
ETA, the accuracy of an acceptable output should directions simultaneously. In the example of Fig. 1, the
be “high enough” (higher than a threshold value) to two 16-bit input operands,“1011001110011010”
meet the requirement of the whole system.
(45978) and “0110100100010011” (26899), are divided
Minimum acceptable accuracy is just that threshold
equally into 8 bits each for the accurate and inaccurate
value. The result obtained whose accuracy is
higher than the minimum acceptable accuracy is parts. The addition of the higher order bits (accurate
called acceptable result. part) of the input operands is performed from right to
• Acceptance Probability (AP): Acceptance probability left (LSB to MSB) and normal addition method is
is the probability that the accuracy of an adder is applied. This is to preserve its correctness since the
higher than the minimum acceptable accuracy. higher order bits play a more important role than the
lower order bits. The lower order bits of the input
Need for error-tolerant adder: Increasingly huge data operands (inaccurate part) require a special addition
sets and the need for instant response require the adder mechanism. No carry signal will be generated or
to be large and fast. The traditional Ripple-Carry Adder
taken in at any bit position to eliminate the carry
(RCA) is therefore no longer suitable for large adders
propagation path. To minimize the overall error due to
because of its low-speed performance. Many different
types of Rc fast adders, such as the Carry-Skip Adder the elimination of the carry chain, a special strategy is
(CSK) (Lehman and Burla, 1961), Carry-Select adder adapted and can be described as follow: (1) check every
(CSL) (Bedrij, 1962) and Carry-Look-Ahead adder (CLA) bit position from left to right (MSB to LSB); (2) if both
(MacSorley, 1961), have been developed. Also, there are input bits are “0” or different, normal one-bit addition is
many low-power adder design techniques that have been performed and the operation proceeds to next bit
proposed (Yeo and Roy, 2005) However, there are always position; (3) if both input bits are “1,”the checking
trade-offs between speed and power. process stopped and from this bit onward, all sum bits
The error-tolerant design can be a potential to the right are set to “1.” Table 1 and 2 shows the
solution to this problem. result obtained for RCA.
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Fig. 5: Overall structure of carry-free addition block

Fig. 3: Proposed addition arithmetic

Fig. 6: Schematic diagram of modified XOR gate

Fig. 4: Hardware implementation of proposed ETA
The proposed partition method must therefore have at
Hardware implementation: The block diagram of the least 98% of all possible inputs reaching an accuracy of
hardware implementation of such an ETA that adopts better than 95%. If this requirement is not met, then one
our proposed addition arithmetic is provided in Fig. 4 bit should be shifted from the inaccurate part to the
This most straightforward structure consists of two accurate part and have the checking process repeated.
parts: an accurate part and an inaccurate part. The Also, due to the simplified circuit structure and the
accurate part is constructed using a conventional elimination of switching activities in the inaccurate part,
adder such as the RCA, CSK, CSL, or CLA. The putting more bits in this part yields more power saving.
carry-in of this adder is connected to ground. The
inaccurate part constitutes two blocks: a carry-free Design of the accurate part: In our proposed 32-bit
addition block and a control block. The control block is ETA, the inaccurate part has 20 bits as opposed to the
used to generate the control signals, to determine the 12 bits used in the accurate part. The overall delay is
working mode of the carry-free addition block. determined by the inaccurate part and so the accurate
part need not be a fast adder. The ripple-carry adder,
Design of a 32-bit error-tolerant adder: which is the most power-saving conventional adder, has
Strategy of dividing the adder: The first step of been chosen for the accurate part of the circuit.
designing a proposed ETA is to divide the adder into
two parts in a specific manner. The dividing strategy is Design of the inaccurate part: The inaccurate part is
based on a guess-and-verify stratagem, depending on the most critical section in the proposed ETA as it
the requirements, such as accuracy, speed and power. determines the accuracy, speed performance and power
With this partition method defined, we then check consumption of the adder. The inaccurate part consists
whether the accuracy performance of the adder meets of two blocks: the carry free addition block and the
the requirements preset by designer/customer. This can control block. The carry-free addition block is made up
be checked very quickly via some software programs. of 20 modified XOR gates and each of which is used to
For example, for a specific application, we require the generate a sum bit. The block diagram of the carry-free
minimum acceptable accuracy to be 95% and the addition block and the schematic implementation of the
acceptance probability to be 98%. modified XOR gate are presented in Fig. 5 and 6.
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(a)

Fig. 8: Propagation delay of gates

(b)

Fig. 7: (a) Overall architecture of control block (b) CSGC

In the modified XOR gate, three extra transistors, M1,
M2 and M3, are added to a conventional XOR gate.
CTL is the control signal coming from the control block of
Fig. 7 and is used to set the operational mode of the circuit. Fig. 9: Delay Vs no of bits in adders
When CTL = 0, M1 and M2 are turned on, while M3 is
turned off, leaving the circuit to operate in the normal
XOR mode. When CTL = 1 M1 and M2 are both turned
off, while M3 is turned on, connecting the output node to
VDD and hence setting the sum output to “1.” The
function of the control block is to detect the first bit
position when both input bits are “1,” and to set the
control signal on this position as well as those on its
right to high. It is made up of 20 Control Signal
Generating Cells (CSGCs) and each cell generates a
control signal for the modified XOR gate at the
corresponding bit position in the carry-free addition
block. Instead of a long chain of 20 cascaded GSGCs,
the control block is arranged into five equal-sized Fig. 10: 32 bit RCA Simulation result
groups, with additional connections between every two
neighboring groups. Two types of CSGC, labeled as
type I and II in Fig. 7a are designed and the schematic
implementations of these two types of CSGC are
provided in Fig. 7b.
The control signal generated by the leftmost cell of
each group is connected to the input of the leftmost cell
in next group. The extra connections allow the
propagated high control signal to “jump” from one group
to another instead of passing through all the 20 cells. Fig
8 shows the propagation delay that take place in gates.
Xilinx ISE was used to obtain the delay of all the 3
adders and simulation results are taken for 3 adders as
shown in Fig. 10-12. Synthesis reports are plotted as in
Fig. 9. Power Vs adders are noted in Fig. 13. ETA
shows less power consumption. Fig. 11: 32 bit CLA simulation result
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• With the steadily increasing of chip’s capacity and

density, low power consumption becomes a vital
feature for chip’s functionality and reliability. High
power density will make chip’s temperature
increasing, thus cause path delay increasing and
problem of metal immigration

Building low power VLSI system has emerged as

significant performance goal because of the fast
technology in mobile communication and computation.
The advances in battery technology have not taken
place as fast as the advances in electronic devices. So
the designers are faced with more constraint; high
Fig. 12: 32 bit ETA Simulation result speed, high throughput and at the same time,
consuming as minimal power as possible.
The goal is to extend battery life span of portable
electronics is to reduce the energy expended per
arithmetic operation, but low power consumption does
not necessarily result in low energy dissipation. To
execute an arithmetic operation, a circuit can consume
very low power by clocking at extremely low frequency
but it may take a very long time to complete the
operation. We measure the energy consumption by the
product of average power and worst case delay (power-
delay-product).
Thus ETA is found to have less delay and have less
power consumption.
Fig. 13: Power Vs Adders
CONCLUSION
Delay in adder: The combinational logic circuits can’t
compute the outputs instantaneously. There is some The ‘error tolerant adder’ was thus designed with
delay between the time the inputs are sent to the circuit an idea to minimize the delay and power consumption
and the time the output is computed. While the adders .The ETA was tested using the Xilinx ISE and was
are working in parallel, the carries must "ripple" their compared with the other conventional adders such as
way from the least significant bit and work their way to the Ripple carry adder, carry look ahead adder. The
the most significant bit. It takes T units for the carry out power consumption of the ETA was calculated using
of the rightmost column to make it as input to the adder the Micro wind/DSCH tool.
in the next to rightmost column. Extensive comparisons with conventional digital
adders showed that the proposed ETA outperformed the
Power consumption in adders: Addition is an operation conventional adders in both power consumption and
common in circuits designed for portable equipment and is speed performance. The potential applications of the
typical of the digital processing carried out in computer ETA fall mainly in areas where there is no strict
systems. In CMOS circuits most of the energy consumed requirement on accuracy or where super low power
is due to switching activity, with the number of nodes in consumption and high-speed performance are more
the circuit, the stored energy per node and the number of important than accuracy.
switching operations per second all contributing to the In future the error tolerant adder can be used in the
total power consumption. DSP application for portable devices such as cell
Power consumption was paid more and more phones, laptops.
attention to by IC designers. The motive of low power
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