M68HC11ERG/AD

Instruction Set

Instruction Set
Refer to Table 1, which shows all the M68HC11 instructions in all possible
addressing modes. For each instruction, the table shows the operand
construction, the number of machine code bytes, and execution time in
CPU E-clock cycles.

Table 1. Instruction Set (Sheet 1 of 8)

Addressing Instruction Condition Codes
Mnemonic Operation Description
Mode Opcode Operand Cycles S X H I N Z V C
ABA Add A+B⇒A INH 1B — 2 — — ∆ — ∆ ∆ ∆ ∆
Accumulators
ABX Add B to X IX + (00 : B) ⇒ IX INH 3A — 3 — — — — — — — —
ABY Add B to Y IY + (00 : B) ⇒ IY INH 18 3A — 4 — — — — — — — —
ADCA (opr) Add with Carry A+M+C⇒A A IMM 89 ii 2 — — ∆ — ∆ ∆ ∆ ∆
to A A DIR 99 dd 3
A EXT B9 hh ll 4
A IND,X A9 ff 4
A IND,Y 18 A9 ff 5
ADCB (opr) Add with Carry B+M+C⇒B B IMM C9 ii 2 — — ∆ — ∆ ∆ ∆ ∆
to B B DIR D9 dd 3
B EXT F9 hh ll 4
B IND,X E9 ff 4
B IND,Y 18 E9 ff 5
ADDA (opr) Add Memory to A+M⇒A A IMM 8B ii 2 — — ∆ — ∆ ∆ ∆ ∆
A A DIR 9B dd 3
A EXT BB hh ll 4
A IND,X AB ff 4
A IND,Y 18 AB ff 5
ADDB (opr) Add Memory to B+M⇒B B IMM CB ii 2 — — ∆ — ∆ ∆ ∆ ∆
B B DIR DB dd 3
B EXT FB hh ll 4
B IND,X EB ff 4
B IND,Y 18 EB ff 5
ADDD (opr) Add 16-Bit to D D + (M : M + 1) ⇒ D IMM C3 jj kk 4 — — — — ∆ ∆ ∆ ∆
DIR D3 dd 5
EXT F3 hh ll 6
IND,X E3 ff 6
IND,Y 18 E3 ff 7
ANDA (opr) AND A with A•M⇒A A IMM 84 ii 2 — — — — ∆ ∆ 0 —
Memory A DIR 94 dd 3
A EXT B4 hh ll 4
A IND,X A4 ff 4
A IND,Y 18 A4 ff 5
ANDB (opr) AND B with B•M⇒B B IMM C4 ii 2 — — — — ∆ ∆ 0 —
Memory B DIR D4 dd 3
B EXT F4 hh ll 4
B IND,X E4 ff 4
B IND,Y 18 E4 ff 5
ASL (opr) Arithmetic Shift EXT 78 hh ll 6 — — — — ∆ ∆ ∆ ∆
Left IND,X 68 ff 6
0
C b7 b0 IND,Y 18 68 ff 7
ASLA Arithmetic Shift A INH 48 — 2 — — — — ∆ ∆ ∆ ∆
Left A
0
C b7 b0
ASLB Arithmetic Shift B INH 58 — 2 — — — — ∆ ∆ ∆ ∆
Left B 0
C b7 b0
ASLD Arithmetic Shift INH 05 — 3 — — — — ∆ ∆ ∆ ∆
Left D 0
C b7 A b0 b7 B b0

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Table 1. Instruction Set (Sheet 2 of 8)

Addressing Instruction Condition Codes
Mnemonic Operation Description
Mode Opcode Operand Cycles S X H I N Z V C
ASR Arithmetic Shift EXT 77 hh ll 6 — — — — ∆ ∆ ∆ ∆
Right IND,X 67 ff 6
b7 b0 C IND,Y 18 67 ff 7
ASRA Arithmetic Shift A INH 47 — 2 — — — — ∆ ∆ ∆ ∆
Right A
b7 b0 C
ASRB Arithmetic Shift B INH 57 — 2 — — — — ∆ ∆ ∆ ∆
Right B
b7 b0 C
BCC (rel) Branch if Carry ?C=0 REL 24 rr 3 — — — — — — — —
Clear
BCLR (opr) Clear Bit(s) M • (mm) ⇒ M DIR 15 dd mm 6 — — — — ∆ ∆ 0 —
(msk) IND,X 1D ff mm 7
IND,Y 18 1D ff mm 8
BCS (rel) Branch if Carry ?C=1 REL 25 rr 3 — — — — — — — —
Set
BEQ (rel) Branch if = Zero ?Z=1 REL 27 rr 3 — — — — — — — —
BGE (rel) Branch if ∆ Zero ?N⊕V=0 REL 2C rr 3 — — — — — — — —
BGT (rel) Branch if > Zero ? Z + (N ⊕ V) = 0 REL 2E rr 3 — — — — — — — —
BHI (rel) Branch if ?C+Z=0 REL 22 rr 3 — — — — — — — —
Higher
BHS (rel) Branch if ?C=0 REL 24 rr 3 — — — — — — — —
Higher or Same
BITA (opr) Bit(s) Test A A•M A IMM 85 ii 2 — — — — ∆ ∆ 0 —
with Memory A DIR 95 dd 3
A EXT B5 hh ll 4
A IND,X A5 ff 4
A IND,Y 18 A5 ff 5
BITB (opr) Bit(s) Test B B•M B IMM C5 ii 2 — — — — ∆ ∆ 0 —
with Memory B DIR D5 dd 3
B EXT F5 hh ll 4
B IND,X E5 ff 4
B IND,Y 18 E5 ff 5
BLE (rel) Branch if ∆ Zero ? Z + (N ⊕ V) = 1 REL 2F rr 3 — — — — — — — —
BLO (rel) Branch if Lower ?C=1 REL 25 rr 3 — — — — — — — —
BLS (rel) Branch if Lower ?C+Z=1 REL 23 rr 3 — — — — — — — —
or Same
BLT (rel) Branch if < Zero ?N⊕V=1 REL 2D rr 3 — — — — — — — —
BMI (rel) Branch if Minus ?N=1 REL 2B rr 3 — — — — — — — —
BNE (rel) Branch if not = ?Z=0 REL 26 rr 3 — — — — — — — —
Zero
BPL (rel) Branch if Plus ?N=0 REL 2A rr 3 — — — — — — — —
BRA (rel) Branch Always ?1=1 REL 20 rr 3 — — — — — — — —
BRCLR(opr) Branch if ? M • mm = 0 DIR 13 dd mm rr 6 — — — — — — — —
(msk) Bit(s) Clear IND,X 1F ff mm rr 7
(rel) IND,Y 18 1F ff mm rr 8
BRN (rel) Branch Never ?1=0 REL 21 rr 3 — — — — — — — —
BRSET(opr) Branch if Bit(s) ? (M) • mm = 0 DIR 12 dd mm rr 6 — — — — — — — —
(msk) Set IND,X 1E ff mm rr 7
(rel) IND,Y 18 1E ff mm rr 8
BSET (opr) Set Bit(s) M + mm ⇒ M DIR 14 dd mm 6 — — — — ∆ ∆ 0 —
(msk) IND,X 1C ff mm 7
IND,Y 18 1C ff mm 8
BSR (rel) Branch to See Figure 3–2 REL 8D rr 6 — — — — — — — —
Subroutine
BVC (rel) Branch if ?V=0 REL 28 rr 3 — — — — — — — —
Overflow Clear

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Instruction Set

Table 1. Instruction Set (Sheet 3 of 8)

Addressing Instruction Condition Codes
Mnemonic Operation Description
Mode Opcode Operand Cycles S X H I N Z V C
BVS (rel) Branch if ?V=1 REL 29 rr 3 — — — — — — — —
Overflow Set
CBA Compare A to B A–B INH 11 — 2 — — — — ∆ ∆ ∆ ∆
CLC Clear Carry Bit 0⇒C INH 0C — 2 — — — — — — — 0
CLI Clear Interrupt 0⇒I INH 0E — 2 — — — 0 — — — —
Mask
CLR (opr) Clear Memory 0⇒M EXT 7F hh ll 6 — — — — 0 1 0 0
Byte IND,X 6F ff 6
IND,Y 18 6F ff 7
CLRA Clear 0⇒A A INH 4F — 2 — — — — 0 1 0 0
Accumulator A
CLRB Clear 0⇒B B INH 5F — 2 — — — — 0 1 0 0
Accumulator B
CLV Clear Overflow 0⇒V INH 0A — 2 — — — — — — 0 —
Flag
CMPA (opr) Compare A to A–M A IMM 81 ii 2 — — — — ∆ ∆ ∆ ∆
Memory A DIR 91 dd 3
A EXT B1 hh ll 4
A IND,X A1 ff 4
A IND,Y 18 A1 ff 5
CMPB (opr) Compare B to B–M B IMM C1 ii 2 — — — — ∆ ∆ ∆ ∆
Memory B DIR D1 dd 3
B EXT F1 hh ll 4
B IND,X E1 ff 4
B IND,Y 18 E1 ff 5
COM (opr) Ones $FF – M ⇒ M EXT 73 hh ll 6 — — — — ∆ ∆ 0 1
Complement IND,X 63 ff 6
Memory Byte IND,Y 18 63 ff 7
COMA Ones $FF – A ⇒ A A INH 43 — 2 — — — — ∆ ∆ 0 1
Complement
A
COMB Ones $FF – B ⇒ B B INH 53 — 2 — — — — ∆ ∆ 0 1
Complement
B
CPD (opr) Compare D to D–M:M +1 IMM 1A 83 jj kk 5 — — — — ∆ ∆ ∆ ∆
Memory 16-Bit DIR 1A 93 dd 6
EXT 1A B3 hh ll 7
IND,X 1A A3 ff 7
IND,Y CD A3 ff 7
CPX (opr) Compare X to IX – M : M + 1 IMM 8C jj kk 4 — — — — ∆ ∆ ∆ ∆
Memory 16-Bit DIR 9C dd 5
EXT BC hh ll 6
IND,X AC ff 6
IND,Y CD AC ff 7
CPY (opr) Compare Y to IY – M : M + 1 IMM 18 8C jj kk 5 — — — — ∆ ∆ ∆ ∆
Memory 16-Bit DIR 18 9C dd 6
EXT 18 BC hh ll 7
IND,X 1A AC ff 7
IND,Y 18 AC ff 7
DAA Decimal Adjust Adjust Sum to BCD INH 19 — 2 — — — — ∆ ∆ ∆ ∆
A
DEC (opr) Decrement M–1⇒M EXT 7A hh ll 6 — — — — ∆ ∆ ∆ —
Memory Byte IND,X 6A ff 6
IND,Y 18 6A ff 7
DECA Decrement A–1⇒A A INH 4A — 2 — — — — ∆ ∆ ∆ —
Accumulator
A
DECB Decrement B–1⇒B B INH 5A — 2 — — — — ∆ ∆ ∆ —
Accumulator
B

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Table 1. Instruction Set (Sheet 4 of 8)

Addressing Instruction Condition Codes
Mnemonic Operation Description
Mode Opcode Operand Cycles S X H I N Z V C
DES Decrement SP – 1 ⇒ SP INH 34 — 3 — — — — — — — —
Stack Pointer
DEX Decrement IX – 1 ⇒ IX INH 09 — 3 — — — — — ∆ — —
Index Register
X
DEY Decrement IY – 1 ⇒ IY INH 18 09 — 4 — — — — — ∆ — —
Index Register
Y
EORA (opr) Exclusive OR A A⊕M⇒A A IMM 88 ii 2 — — — — ∆ ∆ 0 —
with Memory A DIR 98 dd 3
A EXT B8 hh ll 4
A IND,X A8 ff 4
A IND,Y 18 A8 ff 5
EORB (opr) Exclusive OR B B⊕M⇒B B IMM C8 ii 2 — — — — ∆ ∆ 0 —
with Memory B DIR D8 dd 3
B EXT F8 hh ll 4
B IND,X E8 ff 4
B IND,Y 18 E8 ff 5
FDIV Fractional D / IX ⇒ IX; r ⇒ D INH 03 — 41 — — — — — ∆ ∆ ∆
Divide 16 by 16
IDIV Integer Divide D / IX ⇒ IX; r ⇒ D INH 02 — 41 — — — — — ∆ 0 ∆
16 by 16
INC (opr) Increment M+1⇒M EXT 7C hh ll 6 — — — — ∆ ∆ ∆ —
Memory Byte IND,X 6C ff 6
IND,Y 18 6C ff 7
INCA Increment A+1⇒A A INH 4C — 2 — — — — ∆ ∆ ∆ —
Accumulator
A
INCB Increment B+1⇒B B INH 5C — 2 — — — — ∆ ∆ ∆ —
Accumulator
B
INS Increment SP + 1 ⇒ SP INH 31 — 3 — — — — — — — —
Stack Pointer
INX Increment IX + 1 ⇒ IX INH 08 — 3 — — — — — ∆ — —
Index Register
X
INY Increment IY + 1 ⇒ IY INH 18 08 — 4 — — — — — ∆ — —
Index Register
Y
JMP (opr) Jump See Figure 3–2 EXT 7E hh ll 3 — — — — — — — —
IND,X 6E ff 3
IND,Y 18 6E ff 4
JSR (opr) Jump to See Figure 3–2 DIR 9D dd 5 — — — — — — — —
Subroutine EXT BD hh ll 6
IND,X AD ff 6
IND,Y 18 AD ff 7
LDAA (opr) Load M⇒A A IMM 86 ii 2 — — — — ∆ ∆ 0 —
Accumulator A DIR 96 dd 3
A A EXT B6 hh ll 4
A IND,X A6 ff 4
A IND,Y 18 A6 ff 5
LDAB (opr) Load M⇒B B IMM C6 ii 2 — — — — ∆ ∆ 0 —
Accumulator B DIR D6 dd 3
B B EXT F6 hh ll 4
B IND,X E6 ff 4
B IND,Y 18 E6 ff 5
LDD (opr) Load Double M ⇒ A,M + 1 ⇒ B IMM CC jj kk 3 — — — — ∆ ∆ 0 —
Accumulator DIR DC dd 4
D EXT FC hh ll 5
IND,X EC ff 5
IND,Y 18 EC ff 6

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Instruction Set

Table 1. Instruction Set (Sheet 5 of 8)

Addressing Instruction Condition Codes
Mnemonic Operation Description
Mode Opcode Operand Cycles S X H I N Z V C
LDS (opr) Load Stack M : M + 1 ⇒ SP IMM 8E jj kk 3 — — — — ∆ ∆ 0 —
Pointer DIR 9E dd 4
EXT BE hh ll 5
IND,X AE ff 5
IND,Y 18 AE ff 6
LDX (opr) Load Index M : M + 1 ⇒ IX IMM CE jj kk 3 — — — — ∆ ∆ 0 —
Register DIR DE dd 4
X EXT FE hh ll 5
IND,X EE ff 5
IND,Y CD EE ff 6
LDY (opr) Load Index M : M + 1 ⇒ IY IMM 18 CE jj kk 4 — — — — ∆ ∆ 0 —
Register DIR 18 DE dd 5
Y EXT 18 FE hh ll 6
IND,X 1A EE ff 6
IND,Y 18 EE ff 6
LSL (opr) Logical Shift EXT 78 hh ll 6 — — — — ∆ ∆ ∆ ∆
Left IND,X 68 ff 6
0
C b7 b0 IND,Y 18 68 ff 7
LSLA Logical Shift A INH 48 — 2 — — — — ∆ ∆ ∆ ∆
Left A
0
C b7 b0
LSLB Logical Shift B INH 58 — 2 — — — — ∆ ∆ ∆ ∆
Left B
0
C b7 b0
LSLD Logical Shift INH 05 — 3 — — — — ∆ ∆ ∆ ∆
Left Double 0
C b7 A b0 b7 B b0
LSR (opr) Logical Shift EXT 74 hh ll 6 — — — — 0 ∆ ∆ ∆
Right IND,X 64 ff 6
0
b7 b0 C IND,Y 18 64 ff 7
LSRA Logical Shift A INH 44 — 2 — — — — 0 ∆ ∆ ∆
Right A
0
b7 b0 C
LSRB Logical Shift B INH 54 — 2 — — — — 0 ∆ ∆ ∆
Right B
0
b7 b0 C
LSRD Logical Shift INH 04 — 3 — — — — 0 ∆ ∆ ∆
Right Double
0
b7 A b0 b7 B b0 C
MUL Multiply 8 by 8 A∗B⇒D INH 3D — 10 — — — — — — — ∆
NEG (opr) Two’s 0–M⇒M EXT 70 hh ll 6 — — — — ∆ ∆ ∆ ∆
Complement IND,X 60 ff 6
Memory Byte IND,Y 18 60 ff 7
NEGA Two’s 0–A⇒A A INH 40 — 2 — — — — ∆ ∆ ∆ ∆
Complement
A
NEGB Two’s 0–B⇒B B INH 50 — 2 — — — — ∆ ∆ ∆ ∆
Complement
B
NOP No operation No Operation INH 01 — 2 — — — — — — — —
ORAA (opr) OR A+M⇒A A IMM 8A ii 2 — — — — ∆ ∆ 0 —
Accumulator A DIR 9A dd 3
A (Inclusive) A EXT BA hh ll 4
A IND,X AA ff 4
A IND,Y 18 AA ff 5
ORAB (opr) OR B+M⇒B B IMM CA ii 2 — — — — ∆ ∆ 0 —
Accumulator B DIR DA dd 3
B (Inclusive) B EXT FA hh ll 4
B IND,X EA ff 4
B IND,Y 18 EA ff 5

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Table 1. Instruction Set (Sheet 6 of 8)

Addressing Instruction Condition Codes
Mnemonic Operation Description
Mode Opcode Operand Cycles S X H I N Z V C
PSHA Push A onto A ⇒ Stk,SP = SP – 1 A INH 36 — 3 — — — — — — — —
Stack
PSHB Push B onto B ⇒ Stk,SP = SP – 1 B INH 37 — 3 — — — — — — — —
Stack
PSHX Push X onto IX ⇒ Stk,SP = SP – 2 INH 3C — 4 — — — — — — — —
Stack (Lo
First)
PSHY Push Y onto IY ⇒ Stk,SP = SP – 2 INH 18 3C — 5 — — — — — — — —
Stack (Lo
First)
PULA Pull A from SP = SP + 1, A ⇐ Stk A INH 32 — 4 — — — — — — — —
Stack
PULB Pull B from SP = SP + 1, B ⇐ Stk B INH 33 — 4 — — — — — — — —
Stack
PULX Pull X From SP = SP + 2, IX ⇐ Stk INH 38 — 5 — — — — — — — —
Stack (Hi
First)
PULY Pull Y from SP = SP + 2, IY ⇐ Stk INH 18 38 — 6 — — — — — — — —
Stack (Hi
First)
ROL (opr) Rotate Left EXT 79 hh ll 6 — — — — ∆ ∆ ∆ ∆
IND,X 69 ff 6
C b7 b0 IND,Y 18 69 ff 7
ROLA Rotate Left A A INH 49 — 2 — — — — ∆ ∆ ∆ ∆

C b7 b0
ROLB Rotate Left B B INH 59 — 2 — — — — ∆ ∆ ∆ ∆

C b7 b0
ROR (opr) Rotate Right EXT 76 hh ll 6 — — — — ∆ ∆ ∆ ∆
IND,X 66 ff 6
b7 b0 C IND,Y 18 66 ff 7
RORA Rotate Right A A INH 46 — 2 — — — — ∆ ∆ ∆ ∆

b7 b0 C
RORB Rotate Right B B INH 56 — 2 — — — — ∆ ∆ ∆ ∆

b7 b0 C
RTI Return from See Figure 3–2 INH 3B — 12 ∆ ↓ ∆ ∆ ∆ ∆ ∆ ∆
Interrupt
RTS Return from See Figure 3–2 INH 39 — 5 — — — — — — — —
Subroutine
SBA Subtract B from A–B⇒A INH 10 — 2 — — — — ∆ ∆ ∆ ∆
A
SBCA (opr) Subtract with A–M–C⇒A A IMM 82 ii 2 — — — — ∆ ∆ ∆ ∆
Carry from A A DIR 92 dd 3
A EXT B2 hh ll 4
A IND,X A2 ff 4
A IND,Y 18 A2 ff 5
SBCB (opr) Subtract with B–M–C⇒B B IMM C2 ii 2 — — — — ∆ ∆ ∆ ∆
Carry from B B DIR D2 dd 3
B EXT F2 hh ll 4
B IND,X E2 ff 4
B IND,Y 18 E2 ff 5
SEC Set Carry 1⇒C INH 0D — 2 — — — — — — — 1
SEI Set Interrupt 1⇒I INH 0F — 2 — — — 1 — — — —
Mask
SEV Set Overflow 1⇒V INH 0B — 2 — — — — — — 1 —
Flag

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Instruction Set

Table 1. Instruction Set (Sheet 7 of 8)

Addressing Instruction Condition Codes
Mnemonic Operation Description
Mode Opcode Operand Cycles S X H I N Z V C
STAA (opr) Store A⇒M A DIR 97 dd 3 — — — — ∆ ∆ 0 —
Accumulator A EXT B7 hh ll 4
A A IND,X A7 ff 4
A IND,Y 18 A7 ff 5
STAB (opr) Store B⇒M B DIR D7 dd 3 — — — — ∆ ∆ 0 —
Accumulator B EXT F7 hh ll 4
B B IND,X E7 ff 4
B IND,Y 18 E7 ff 5
STD (opr) Store A ⇒ M, B ⇒ M + 1 DIR DD dd 4 — — — — ∆ ∆ 0 —
Accumulator EXT FD hh ll 5
D IND,X ED ff 5
IND,Y 18 ED ff 6
STOP Stop Internal — INH CF — 2 — — — — — — — —
Clocks
STS (opr) Store Stack SP ⇒ M : M + 1 DIR 9F dd 4 — — — — ∆ ∆ 0 —
Pointer EXT BF hh ll 5
IND,X AF ff 5
IND,Y 18 AF ff 6
STX (opr) Store Index IX ⇒ M : M + 1 DIR DF dd 4 — — — — ∆ ∆ 0 —
Register X EXT FF hh ll 5
IND,X EF ff 5
IND,Y CD EF ff 6
STY (opr) Store Index IY ⇒ M : M + 1 DIR 18 DF dd 5 — — — — ∆ ∆ 0 —
Register Y EXT 18 FF hh ll 6
IND,X 1A EF ff 6
IND,Y 18 EF ff 6
SUBA (opr) Subtract A–M⇒A A IMM 80 ii 2 — — — — ∆ ∆ ∆ ∆
Memory from A DIR 90 dd 3
A A EXT B0 hh ll 4
A IND,X A0 ff 4
A IND,Y 18 A0 ff 5
SUBB (opr) Subtract B–M⇒B A IMM C0 ii 2 — — — — ∆ ∆ ∆ ∆
Memory from A DIR D0 dd 3
B A EXT F0 hh ll 4
A IND,X E0 ff 4
A IND,Y 18 E0 ff 5
SUBD (opr) Subtract D–M:M+1⇒D IMM 83 jj kk 4 — — — — ∆ ∆ ∆ ∆
Memory from DIR 93 dd 5
D EXT B3 hh ll 6
IND,X A3 ff 6
IND,Y 18 A3 ff 7
SWI Software See Figure 3–2 INH 3F — 14 — — — 1 — — — —
Interrupt
TAB Transfer A to B A⇒B INH 16 — 2 — — — — ∆ ∆ 0 —
TAP Transfer A to A ⇒ CCR INH 06 — 2 ∆ ↓ ∆ ∆ ∆ ∆ ∆ ∆
CC Register
TBA Transfer B to A B⇒A INH 17 — 2 — — — — ∆ ∆ 0 —
TEST TEST (Only in Address Bus Counts INH 00 — * — — — — — — — —
Test Modes)
TPA Transfer CC CCR ⇒ A INH 07 — 2 — — — — — — — —
Register to A
TST (opr) Test for Zero or M–0 EXT 7D hh ll 6 — — — — ∆ ∆ 0 0
Minus IND,X 6D ff 6
IND,Y 18 6D ff 7
TSTA Test A for Zero A–0 A INH 4D — 2 — — — — ∆ ∆ 0 0
or Minus
TSTB Test B for Zero B–0 B INH 5D — 2 — — — — ∆ ∆ 0 0
or Minus
TSX Transfer Stack SP + 1 ⇒ IX INH 30 — 3 — — — — — — — —
Pointer to X

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Table 1. Instruction Set (Sheet 8 of 8)

Addressing Instruction Condition Codes
Mnemonic Operation Description
Mode Opcode Operand Cycles S X H I N Z V C
TSY Transfer Stack SP + 1 ⇒ IY INH 18 30 — 4 — — — — — — — —
Pointer to Y
TXS Transfer X to IX – 1 ⇒ SP INH 35 — 3 — — — — — — — —
Stack Pointer
TYS Transfer Y to IY – 1 ⇒ SP INH 18 35 — 4 — — — — — — — —
Stack Pointer
WAI Wait for Stack Regs & WAIT INH 3E — ** — — — — — — — —
Interrupt
XGDX Exchange D IX ⇒ D, D ⇒ IX INH 8F — 3 — — — — — — — —
with X
XGDY Exchange D IY ⇒ D, D ⇒ IY INH 18 8F — 4 — — — — — — — —
with Y
Cycle
* Infinity or until reset occurs
** 12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock
cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).

Operands
dd = 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)
ff = 8-bit positive offset $00 (0) to $FF (255) (is added to index)
hh = High-order byte of 16-bit extended address
ii = One byte of immediate data
jj = High-order byte of 16-bit immediate data
kk = Low-order byte of 16-bit immediate data
ll = Low-order byte of 16-bit extended address
mm = 8-bit mask (set bits to be affected)
rr = Signed relative offset $80 (–128) to $7F (+127)
(offset relative to address following machine code offset byte))

Operators Condition Codes

() Contents of register shown inside parentheses — Bit not changed
⇐ Is transferred to 0 Bit always cleared
⇑ Is pulled from stack 1 Bit always set
⇓ Is pushed onto stack ∆ Bit cleared or set, depending on operation
• Boolean AND ↓ Bit can be cleared, cannot become set
+ Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
⊕ Exclusive-OR
∗ Multiply
: Concatenation
– Arithmetic subtraction symbol or negation symbol (two’s complement)

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Special Operations

Special Operations

JSR, JUMP TO SUBROUTINE RTI, RETURN FROM INTERRUPT

MAIN PROGRAM INTERRUPT ROUTINE 7 STACK 0
PC $9D = JSR PC $3B = RTI SP
DIRECT dd SP+1 CCR
RTN NEXT MAIN INSTR. SP+2 ACCB
SP+3 ACCA
MAIN PROGRAM SP+4 IXH
PC $AD = JSR SP+5 IXL
INDEXED, X ff 7 STACK 0 SP+6 IYH
RTN NEXT MAIN INSTR.
⇑ SP–2 SP+7 IYL
MAIN PROGRAM SP–1 RTNH SP+8 RTNH
SP RTNL ⇑ SP+9 RTNL
PC $18 = PRE
INDEXED, Y $AD = JSR SWI, SOFTWARE INTERRUPT
RTN ff MAIN PROGRAM 7 STACK 0
NEXT MAIN INSTR. PC $3F = SWI ⇑ SP–9
MAIN PROGRAM SP–8 CCR
PC $BD = PRE SP–7 ACCB
hh SP–6 ACCA
INDEXED, Y
RTN ll SP–5 IXH
WAI, WAIT FOR INTERRUPT
NEXT MAIN INSTR. SP–4 IXL
MAIN PROGRAM SP–3 IYH
PC $3E = WAI SP–2 IYL
BSR, BRANCH TO SUBROUTINE SP–1 RTNH
SP RTNL
MAIN PROGRAM 7 STACK 0
PC $8D = BSR ⇑ SP–2 LEGEND:
SP–1 RTNH RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO
SP RTNL BE EXECUTED UPON RETURN FROM SUBROUTINE
RTNH = MOST SIGNIFICANT BYTE OF RETURN ADDRESS
RTNL = LEAST SIGNIFICANT BYTE OF RETURN ADDRESS
RTS, RETURN FROM ⇑ = STACK POINTER POSITION AFTER OPERATION IS COMPLETE
SUBROUTINE dd = 8-BIT DIRECT ADDRESS ($0000–$00FF) (HIGH BYTE ASSUMED
MAIN PROGRAM 7 STACK 0 TO BE $00)
ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (255) IS ADDED TO INDEX
PC $39 = RTS SP hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
SP+1 RTNH ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
rr = SIGNED RELATIVE OFFSET $80 (–128) TO $7F (+127) (OFFSET
⇑ SP+2 RTNL RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE
OFFSET BYTE)

MOTOROLA M68HC11E Series Programming Reference Guide 21

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 M68HC11ERG/AD

M68HC11E Series Registers

Figure 6 provides a summary of the M68HC11E registers. Note that the
128-byte register block can be remapped to any 4K boundary.

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

Read:
Port A Data Register PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
$1000 Write:
(PORTA)
Reset: I 0 0 0 I I I I
$1001 Reserved R R R R R R R R

Read:
Parallel I/O Control Register STAF STAI CWOM HNDS OIN PLS EGA INVB
$1002 Write:
(PIOC)
Reset: 0 0 0 0 0 U 1 1
Read:
Port C Data Register PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
$1003 Write:
(PORTC)
Reset: Indeterminate after reset
Read:
Port B Data Register PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
$1004 Write:
(PORTB)
Reset: 0 0 0 0 0 0 0 0
Read:
Port C Latched Register PCL7 PCL6 PCL5 PCL4 PCL3 PCL2 PCL1 PCL0
$1005 Write:
(PORTCL)
Reset: Indeterminate after reset
$1006 Reserved R R R R R R R R

Read:
Port C Data Direction Register DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
$1007 Write:
(DDRC)
Reset: 0 0 0 0 0 0 0 0
Read:
Port D Data Register 0 0 PD5 PD4 PD3 PD2 PD1 PD0
$1008 Write:
(PORTD)
Reset: U U I I I I I I
Read:
Port D Data Direction Register DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
$1009 Write:
(DDRD)
Reset: 0 0 0 0 0 0 0 0
Read:
Port E Data Register PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
$100A Write:
(PORTE)
Reset: Indeterminate after reset
Read:
Timer Compare Force Register FOC1 FOC2 FOC3 FOC4 FOC5
$100B Write:
(CFORC)
Reset: 0 0 0 0 0 0 0 0
= Unimplemented R = Reserved U = Unaffected
I = Indeterminate after reset
Figure 6. Register and Control Bit Assignments (Sheet 1 of 6)

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 M68HC11ERG/AD
M68HC11E Series Registers

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

Read:
Output Compare 1 Mask Register OC1M7 OC1M6 OC1M5 OC1M4 OC1M3
$100C Write:
(OC1M)
Reset: 0 0 0 0 0 0 0 0
Read:
Output Compare 1 Data Register OC1D7 OC1D6 OC1D5 OC1D4 OC1D3
$100D Write:
(OC1D)
Reset: 0 0 0 0 0 0 0 0
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Timer Counter Register High Write:
$100E
(TCNTH)
Reset: 0 0 0 0 0 0 0 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Timer Counter Register Low Write:
$100F
(TCNTL)
Reset: 0 0 0 0 0 0 0 0
Read:
Timer Input Capture 1 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$1010 Write:
High (TIC1H)
Reset: Indeterminate after reset
Read:
Timer Input Capture 1 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$1011 Write:
Low (TIC1L)
Reset: Indeterminate after reset
Read:
Timer Input Capture 2 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$1012 Write:
High (TIC2H)
Reset: Indeterminate after reset
Read:
TImer Input Capture 2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$1013 Write:
Low (TIC2L)
Reset: Indeterminate after reset
Read:
Timer Input Capture 3 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$1014 Write:
High (TIC3H)
Reset: Indeterminate after reset
Read:
Timer Input Capture 3 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$1015 Write:
Low (TIC3L)
Reset: Indeterminate after reset
Read:
Timer Output Compare 1 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$1016 Write:
High (TOC1H)
Reset: 1 1 1 1 1 1 1 1
Read:
Timer Output Compare 1 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$1017 Write:
Low (TOC1L)
Reset: 1 1 1 1 1 1 1 1
= Unimplemented R = Reserved U = Unaffected
I = Indeterminate after reset
Figure 6. Register and Control Bit Assignments (Sheet 2 of 6)

MOTOROLA M68HC11E Series Programming Reference Guide 23

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 M68HC11ERG/AD

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

Read:
Timer Output Compare 2 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$1018 Write:
High (TOC2H)
Reset: 1 1 1 1 1 1 1 1
Read:
Timer Output Compare 2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$1019 Write:
Low (TOC2L)
Reset: 1 1 1 1 1 1 1 1
Read:
Timer Output Compare 3 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$101A Write:
High (TOC3H)
Reset: 1 1 1 1 1 1 1 1
Read:
Timer Output Compare 3 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$101B Write:
Low (TOC3L)
Reset: 1 1 1 1 1 1 1 1
Read:
Timer Output Compare 4 Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$101C Write:
High (TOC4H)
Reset: 1 1 1 1 1 1 1 1
Read:
Timer Output Compare 4 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$101D Write:
Low (TOC4L)
Reset: 1 1 1 1 1 1 1 1
Timer Input Capture 4/Output Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
$101E Compare 5 Register High Write:
(TI4/O5) Reset: 1 1 1 1 1 1 1 1
Timer Input Capture 4/Output Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$101F Compare 5 Register Low Write:
(TI4/O5) Reset: 1 1 1 1 1 1 1 1
Read:
Timer Control Register 1 OM2 OL2 OM3 OL3 OM4 OL4 OM5 OL5
$1020 Write:
(TCTL1)
Reset: 0 0 0 0 0 0 0 0
Read:
Timer Control Register 2 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A
$1021 Write:
(TCTL2)
Reset: 0 0 0 0 0 0 0 0
Read:
Timer Interrupt Mask 1 Register OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I
$1022 Write:
(TMSK1)
Reset: 0 0 0 0 0 0 0 0
Read:
Timer Interrupt Flag 1 OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F
$1023 Write:
(TFLG1)
Reset: 0 0 0 0 0 0 0 0
= Unimplemented R = Reserved U = Unaffected
I = Indeterminate after reset
Figure 6. Register and Control Bit Assignments (Sheet 3 of 6)

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 M68HC11ERG/AD
M68HC11E Series Registers

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

Read:
Timer Interrupt Mask 2 Register TOI RTII PAOVI PAII PR1 PR0
$1024 Write:
(TMSK2)
Reset: 0 0 0 0 0 0 0 0
Read:
Timer Interrupt Flag 2 Write: TOF RTIF PAOVF PAIF
$1025
(TFLG2)
Reset: 0 0 0 0 0 0 0 0
Read:
Pulse Accumulator Control Write: DDRA7 PAEN PAMOD PEDGE DDRA3 I4/O5 RTR1 RTR0
$1026
Register (PACTL)
Reset: 0 0 0 0 0 0 0 0
Read:
Pulse Accumulator Count Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$1027 Write:
Register (PACNT)
Reset: Indeterminate after reset
Read:
Serial Peripheral Control Register Write: SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0
$1028
(SPCR)
Reset: 0 0 0 0 0 1 U U
Read:
Serial Peripheral Status Register Write: SPIF WCOL MODF
$1029
(SPSR)
Reset: 0 0 0 0 0 0 0 0
Read:
Serial Peripheral Data I/O Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$102A Write:
Register (SPDR)
Reset: Indeterminate after reset
Read: (1)
Baud Rate Register Write: TCLR SCP2 SCP1 SCP0 RCKB SCR2 SCR1 SCR0
$102B
(BAUD)
Reset: 0 0 0 0 0 U U U
Read:
Serial Communications Control Write: R8 T8 M WAKE
$102C
Register 1 (SCCR1)
Reset: I I 0 0 0 0 0 0
Read:
Serial Communications Control Write: TIE TCIE RIE ILIE TE RE RWU SBK
$102D
Register 2 (SCCR2)
Reset: 0 0 0 0 0 0 0 0
Read:
Serial Communications Status Write: TDRE TC RDRF IDLE OR NF FE
$102E
Register (SCSR)
Reset: 1 1 0 0 0 0 0 0
1. SCP2 adds ÷ 39 to SCI prescaler and is present only in MC68HC(7)11E20.
Read:
Serial Communications Data R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
$102F Write:
Register (SCDR)
Reset: Indeterminate after reset
= Unimplemented R = Reserved U = Unaffected
I = Indeterminate after reset
Figure 6. Register and Control Bit Assignments (Sheet 4 of 6)

MOTOROLA M68HC11E Series Programming Reference Guide 25

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 M68HC11ERG/AD

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

Read: CCF
Analog-to-Digital Control Status SCAN MULT CD CC CB CA
$1030 Write:
Register (ADCTL)
Reset: 0 0 Indeterminate after reset
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Analog-to-Digital Results Register
$1031 Write:
1 (ADR1)
Reset: Indeterminate after reset
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Analog-to-Digital Results Register
$1032 Write:
2 (ADR2)
Reset: Indeterminate after reset
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Analog-to-Digital Results Register
$1033 Write:
3 (ADR3)
Reset: Indeterminate after reset
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Analog-to-Digital Results Register
$1034 Write:
4 (ADR4)
Reset: Indeterminate after reset
Read:
Block Protect Register PTCON BPRT3 BPRT2 BPRT1 BPRT0
$1035 Write:
(BPROT)
Reset: 0 0 0 1 1 1 1 1
Read:
EPROM Programming Control MBE ELAT EXCOL EXROW T1 T0 PGM
$1036 Write:
Register (EPROG)(1)
Reset: 0 0 0 0 0 0 0 0
1. MC68HC711E20 only
$1037 Reserved R R R R R R R R

$1038 Reserved R R R R R R R R

Read:
System Configuration Options ADPU CSEL IRQE(1) DLY(1) CME CR1(1) CR0(1)
$1039 Write:
Register (OPTION)
Reset: 0 0 0 1 0 0 0 0
Read:
Arm/Reset COP Timer Circuitry Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$103A Write:
Register (COPRST)
Reset: 0 0 0 0 0 0 0 0
EPROM and EEPROM Read:
ODD EVEN ELAT(2) BYTE ROW ERASE EELAT EPGM
$103B Programming Control Register Write:
(PPROG) Reset: 0 0 0 0 0 0 0 0
Highest Priority I Bit Interrupt and Read:
RBOOT SMOD MDA IRV(NE) PSEL3 PSEL2 PSEL1 PSEL0
$103C Miscellaneous Register Write:
(HPRIO) Reset: 0 0 0 0 0 1 1 0
= Unimplemented R = Reserved U = Unaffected
I = Indeterminate after reset
Figure 6. Register and Control Bit Assignments (Sheet 5 of 6)

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 M68HC11ERG/AD
M68HC11E Series Registers

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0

Read:
RAM and I/O Mapping Register RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0
$103D Write:
(INIT)
Reset: 0 0 0 0 0 0 0 1
$103E Reserved R R R R R R R R

Read:
System Configuration Register NOSEC NOCOP ROMON EEON
$103F Write:
(CONFIG)
Reset: 0 0 0 0 U U 1 U
Read:
System Configuration Register Write: EE3 EE2 EE1 EE0 NOSEC NOCOP EEON
$103F
(CONFIG)(3)
Reset: 1 1 1 1 U U 1 1
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during special modes.
2. MC68HC711E9 only
3. MC68HC811E2 only
= Unimplemented R = Reserved U = Unaffected
I = Indeterminate after reset
Figure 6. Register and Control Bit Assignments (Sheet 6 of 6)

A/D Control/Status Register (ADCTL)

Address: $1030
Bit 7 6 5 4 3 2 1 Bit 0
Read: CCF
SCAN MULT CD CC CB CA
Write:
Reset: 0 0 Indeterminate after reset
= Unimplemented
CCF — Conversion Complete Flag
This bit is set after an A/D conversion cycle and cleared when ADCTL is
written.
Bit 6 — Unimplemented
Always reads 0
SCAN — Continuous Scan Control
0 = Do four conversions and stop
1 = Convert four channels in selected group continuously
MULT — Multiple Channel/Single Channel Control
0 = Convert single channel selected
1 = Convert four channels in selected group
CD:CA — Channel Selects D:A
Refer to the following table.

MOTOROLA M68HC11E Series Programming Reference Guide 27

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