Double Pulse Test

1. Objectives of the Test

The main objective of the DPT is to experimentally gather the current and voltage
waveforms of the power devices to evaluate their switching behaviors in an actual
power converter. The double-pulse test is used to observe the switching transients
of a transistor without having to heat the device. The double-pulse test is normally
done with a purely inductive load, i.e., a load inductor. The first pulse should turn
on the transistor and charge a current through the inductor. This means that the
first pulse should be a wide pulse, which charges the load current to the magnitude
that is interesting to analyze. Then, a short break followed by a second short pulse
should appear. Such a double pulse gives the possibility of analyzing the rising
edge (turn on) and the falling edge (turn off) of a hard-switching transient of the
transistor at the exact transistor current that is desired. A double-pulse signal is
depicted in Figure 1.

Figure 1: Double-pulse signal

By adjusting the pulse width of the first pulse supplied to the gate driver, it is
possible to adjust the transistor current magnitude. The double pulses are supplied
at a very low frequency, e.g. 1 Hz. This gives the transistor time to remove the
generated heat, and the load inductor time to discharge between the double pulses.
2. Schematic of the Test

Schematic of DPT device being an N type MOSFET (SiHB100N60E)

3. Test Procedure and Waveforms

In DPT, two pulses are sent to the device under test in a clamped Inductive load
circuit, shown above. By regulating the DC bus voltage and the first pulse
duration, the DUT’s switching transients can be captured under any desired
voltage and current conditions
Gate Voltage

Gate to Source Voltage

Drain to Source Voltage

Drain Current
4. Design Criteria of Inductor
The load inductor is used to establish the desired current during the first pulse and keep this current
nearly constant during the following turn-off and turn-on transients. Therefore, the selected load
inductance L should be large enough to limit the inductive current variation ΔIL during the
switching transient yielding. Usually, the switching performance of the DUT is characterized
under several different operating points. the worst condition for load inductance selection is under
the maximum operating voltage and minimum current. According to this required inductance
along with the maximum operating current, the inductor is then physically designed. In addition,
it is preferred to construct the load inductor by connecting several small equivalent inductors in
series. Each inductor has only one layer of windings to minimize its equivalent parallel capacitance
(EPC). WBG devices with fast switching speed are highly sensitive to parasitics, so load inductor
EPC minimization is critical.

5. Power Losses in Single MOSFETs

A double-pulse test of a MOSFET makes it possible to determine the switching power losses of
a high-frequency switching MOSFET. In a double-pulse test, it is possible to analyze both the
turn-on and the turn-off transients of the transistor at a given drain-to-source voltage and drain
current. This makes it possible to determine the total switching power losses in the transistor. The
power loss 𝑝𝑇,𝑙𝑜𝑠𝑠 in a single MOSFET is given by

𝑝T,loss = 𝑣𝑑𝑠(𝑡) ∙ 𝑖𝑑(𝑡)

𝑣𝑑𝑠 is the drain-to-source voltage and 𝑖𝑑 is the drain current of the switching transistor.When the
transistor is off, 𝑖𝑑 is close to zero, due to very low leakage current. The off-state conduction losses
are thus negligible. When the transistor is on, there are conduction power losses due to the on-state
drain-to-source resistance 𝑅𝑑𝑠(𝑜𝑛) of the transistor. The conduction power losses are given by

𝑝𝑇,𝑐𝑜𝑛𝑑(𝑡) = 𝑅𝑑𝑠(𝑜𝑛) ∙ 𝑖𝑑2(𝑡)

The conduction losses are not easily found through the double-pulse test, as the drain current is
constantly increasing due to the purely inductive load. Thus, the double-pulse test does not
represent the transistor conduction losses in a good way. However, for a high-frequency switching
transistor, the average value during one switching period 𝑇𝑠𝑤 can be found using

𝐼𝑑,𝑟𝑚𝑠 is the RMS drain current in the transistor.

6. Results

• Drain to Source Voltage

• Gate to Source Voltage
• Drain Current

Power Dissipation in the Device

With Average power dissipation = 1.06 micro Watt
Voltage across the Gate Resistance, Rg =10 ohm

Transfer Characteristic
Gate to Source Voltage for different values of Rg

Diode Current for different values of Rg

Diode Current for different values of Lload

7. LTspice Script for Measurements
8. Spice Measuremets

Measurement: vmax
step MAX(v(vd)) FROM TO
1 400.916 7e-006 7.14e-006
2 400.916 7e-006 7.14e-006
3 400.916 7e-006 7.14e-006
4 400.916 7e-006 7.14e-006
5 400.915 7e-006 7.14e-006

Measurement: id_overshoot
step MAX(ix(m1:d)) FROM TO
1 24.0938 8.96e-006 9.04e-006
2 24.1252 8.96e-006 9.04e-006
3 24.1571 8.96e-006 9.04e-006
4 24.1902 8.96e-006 9.04e-006
5 24.2636 8.96e-006 9.04e-006

Measurement: deriv_vd
step D(v(vd)) at
1 397.722 7.043e-006
2 1.615e+011 7.043e-006
3 2.85931e+008 7.043e-006
4 3.39489e+007 7.043e-006
5 7.93946e+006 7.043e-006

Measurement: deriv_id
step D(ix(m1:d)) at
1 3.97241e+006 7e-006
2 3.96245e+006 7e-006
3 3.95867e+006 7e-006
4 3.94887e+006 7e-006
5 3.93846e+006 7e-006

Measurement: t_eon1
step time at
1 8.9847e-006 8.9847e-006
2 8.98469e-006 8.98469e-006
3 8.99689e-006 8.99689e-006
4 8.99849e-006 8.99849e-006
5 8.99949e-006 8.99949e-006

Measurement: t_eon2
step time at
1 9.02289e-006 9.02289e-006
2 9.04262e-006 9.04262e-006
3 9.06369e-006 9.06369e-006
4 9.08711e-006 9.08711e-006
5 9.13728e-006 9.13728e-006
Measurement: eon
step INTEG(v(vd)*ix(m1:d)) FROM
TO
1 3.03199e-005 8.9847e-006 9.02289e-006
2 4.89943e-005 8.98469e-006 9.04262e-006
3 6.59112e-005 8.99689e-006 9.06369e-006
4 8.37818e-005 8.99849e-006 9.08711e-006
5 0.000116201 8.99949e-006 9.13728e-006

Measurement: t_eoff1
step time at
1 7.01443e-006 7.01443e-006
2 7.02621e-006 7.02621e-006
3 7.03793e-006 7.03793e-006
4 7.04955e-006 7.04955e-006
5 7.07395e-006 7.07395e-006

Measurement: t_eoff2
step time at
1 7.03543e-006 7.03543e-006
2 7.05601e-006 7.05601e-006
3 7.08088e-006 7.08088e-006
4 7.10288e-006 7.10288e-006
5 7.15251e-006 7.15251e-006

Measurement: eoff
step INTEG(v(vd)*ix(m1:d)) FROM
TO
1 1.0557e-005 7.01443e-006 7.03543e-006
2 2.36595e-005 7.02621e-006 7.05601e-006
3 3.95354e-005 7.03793e-006 7.08088e-006
4 5.58308e-005 7.04955e-006 7.10288e-006
5 9.08527e-005 7.07395e-006 7.15251e-006

Measurement: e_switching
step INTEG(v(vd)*ix(m1:d)) FROM
TO
1 0.000263334 0 1.2e-005
2 0.000312507 0 1.2e-005
3 0.000365239 0 1.2e-005
4 0.000420351 0 1.2e-005
5 0.000532359 0 1.2e-005

Measurement: t_vslew1
step time at
1 7.02225e-006 7.02225e-006
2 7.04091e-006 7.04091e-006
3 7.05956e-006 7.05956e-006
4 7.07816e-006 7.07816e-006
5 7.11533e-006 7.11533e-006
Measurement: t_vslew2
step time at
1 7.0246e-006 7.0246e-006
2 7.0442e-006 7.0442e-006
3 7.06374e-006 7.06374e-006
4 7.0832e-006 7.0832e-006
5 7.1223e-006 7.1223e-006

Measurement: vslew_off
step 360/(t_vslew2-t_vslew1)
1 1.52995e+011
2 1.09442e+011
3 8.60669e+010
4 7.13546e+010
5 5.16906e+010

The End