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Ade Lab Manual Final

The document describes a laboratory on analog and digital electronics including topics like RC circuits, diode clipping circuits, and a JK flip flop implementation in VHDL.

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Mahesh A.V
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29 views36 pages

Ade Lab Manual Final

The document describes a laboratory on analog and digital electronics including topics like RC circuits, diode clipping circuits, and a JK flip flop implementation in VHDL.

Uploaded by

Mahesh A.V
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DEPARTMENT OF INFORMATION SCIENCE AND ENGINEERING

ANALOG AND DIGITAL ELECTRONICS


LABORATORY (18CSL37)

Prepared By,

RANJITHA R
Asst. Professor
Department of ISE
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
R1
R1 R2

1 1 3
T 10 1ms)
f 103

3
T 10
R 5K
2C 2 10 7

R1
Vc Vsat
R1 R2

Dept. of Information Science & Engineering, VKIT


Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
entity jk_ff is
port(j,k,cr,pr,clk:in std_logic;
q,qbar:out std_logic);
end jk_ff;
architecture behavioural of jk_ff is
signal input:std_logic_vector(1 downto 0);
begin
input<=j&k;
process(clk,j,k,pr,cr)
variable temp:std_logic:='0';
begin
if(cr='1' and pr='1')then
if rising_edge(clk) then
case input is
when "10"=> temp:='1';
when "01"=> temp:='0';
when "11"=> temp:=not temp;
when others=> null;
end case;
end if;
else
temp:='0';

Dept. of Information Science & Engineering, VKIT


end if;
q<=temp;
qbar<=not temp;
end process;
end behavioural;

Dept. of Information Science & Engineering, VKIT


Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT
Dept. of Information Science & Engineering, VKIT

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