Chapter 1 Background

-- The Simplified Instructional Computer (SIC)

Tzong-Jye Liu
Department of Information Engineering and Computer Science
Feng Chia University
tjliu@fcu.edu.tw

Outline

n The simplified instructional computer (SIC)

n Architecture
n SIC programming

System Programming 2
Simplified Instructional Computer (SIC)

n A hypothetical computer that includes the

hardware features most often found on real
machines
n SIC standard model
n SIC/XE
n Upward compatible
n Programs for SIC can run on SIC/XE

System Programming 3

SIC machine architecture

n Memory
n 8-bit bytes
n 3 consecutive bytes form a word
n Addressed by the lowest number byte
n 215 (32768) bytes in the computer memory

A word (3 bytes)

…
0 1 2 3 4 5 6

32768 = 215 bytes

System Programming 4
 void main(void){
int a;
f1()

SIC machine architecture

a = 1
}
void f1(void){
f2()
}
n Registers (5 registers / each 24-bits) void f2(void){
Mnemonic Number Special use }

A 0 Accumulator; used for arithmetic operations

X 1 Index register; used for addressing
L 2 Linkage register; the Jump to Subroutine (JSUB)
instruction stores the return address in this register
PC 8 Program counter; contains the address of the next
instruction to be fetched for execution
SW 9 Status word; contains a variety of information,
including a Condition Code (CC)

n SIC does not have any stack. It uses the linkage register to store the
return address.
n It is difficult to write the recursive program. A programmer has to
maintain memory for return addresses when he write more than one
layer of function call.
System Programming 5

SIC machine architecture

n Data formats
n Characters
n 8-bit ASCII codes
n Integers
n 24-bit binary numbers
n 2’s complement for negative values
n -N Û 2n – N
n Ex: -1 Û 25 – 1 = (11111)2 ,if n = 5.

n No floating-point numbers (exist in SIC/XE)

System Programming 6
 SIC machine architecture

n Instruction formats
n 24-bits format
opcode (8) x address (15)

n Note that the memory size of SIC is 215 bytes

n x is to indicate index addressing mode
n X is the index register

n Addressing modes
Mode Indication Target address calculation
直接定址 Direct x=0 TA = address
索引定址 Indexed x=1 TA = address + (X)
(ex: array)
System Programming 7

SIC machine architecture LDA

…
ALPHA

ALPHA RESW 1

n Define storage ALPHA 為記憶體中的一個位址

(ALPHA) 為 ALPHA 位址中的值
n WORD/BYTE
n Reserve one word/byte of storage
n RESW/RESB
n Reserve one or more words/bytes of storage
n Example
ALPHA RESW 1
FIVE WORD 5
CHARZ BYTE C’Z’
C1 RESB 1
n Instruction set
n Load and store instruction
n LDA, LDX, STA, STX, LDCH, STCH
n Ex: LDA ALPHA Û (A) ¬ (ALPHA)
STA ALPHA Û (ALPHA) ¬ (A)
System Programming 8
 Programming examples
- Data movement

n Page 13, Figure 1.2 (a)

LDA FIVE LOAD CONSTANT 5 INTO REGISTER A

STA ALPHA STORE IN ALPHA
LDCH CHARZ LOAD CHARACTER 'Z' INTO REGISTER A
STCH C1 STORE IN CHARACTER VARIABLE C1
.
.
ALPHA RESW 1 ONE-WORD VARIABLE
FIVE WORD 5 ONE-WORD CONSTANT
CHARZ BYTE C'Z' ONE-BYTE CONSTANT
C1 RESB 1 ONE-BYTE VARIABLE

LDA FIVE Û (A) ¬ (FIVE)

STA ALPHA Û (ALPHA) ¬ (A)

System Programming 9

Programming examples
- Data movement

Address opcode (8) x address (15)

LDA FIVE 000000 LDA 00 0 000F
STA ALPHA 000003 STA 0C 0 000C
LDCH CHARZ
000006 LDCH 50 0 0012
STCH C1
ALPHA RESW 1
000009 STCH 54 0 0013
FIVE WORD 5 00000C 000000
CHARZ BYTE C'Z' 00000F 000005
C1 RESB 1 000012 5A00

Direct Addressing
LDA FIVE Û (A) ¬ (FIVE)
STA ALPHA Û (ALPHA) ¬ (A)

In Memory
00000 00 00 0F 0C 00 0C 50 00 12 54 00 13 00 00 00 00
00010 00 05 5A 00

System Programming 10
SIC machine architecture
n Instruction set
n Arithmetic instruction
n Involve register A and a word in memory
n ADD, SUB, MUL, DIV
n Ex: ADD ALPHA Û (A) ¬ (A) + (ALPHA)

System Programming 11

Programming examples
- Arithmetic
n Page 15, Figure 1.3 (a)
(BETA) ß (ALPHA) + (INCR) – (ONE)
(DELTA) ß (GAMMA) + (INCR) – (ONE)
LDA ALPHA LOAD ALPHA INTO REGISTER A
ADD INCR ADD THE VALUE OF INCR
SUB ONE SUBTRACT 1
練習： STA BETA STORE IN BETA
(ALPHA) LDA
ß (BETA)
GAMMA* (GAMMA)
LOAD GAMMA + (INCR)
INTO REGISTER A
ADD INCR ADD THE VALUE OF INCR
(ALPHA) SUB
ß (BETA)
ONE + (GAMMA)
SUBTRACT 1 * (INCR)
STA DELTA STORE IN DELTA
.
.
ONE WORD 1 ONE-WORD CONSTANT
. ONE-WORD VARIABLES
ALPHA RESW 1
BETA RESW 1
GAMMA RESW 1
DELTA RESW 1
INCR RESW 1 System Programming 12
 SIC machine architecture

n Instruction set
n Comparison instruction
n Involve register A and a word in memory
n Save result in the condition code (CC) of SW
n COMP
Ex: COMP ALPHA Û CC ¬(<,=,>) of (A)?(ALPHA)
n TIX m
X ß (X) + 1; (X) ? (m)
n Conditional jump instructions
n according to CC
n JLT, JEQ, JGT
n Test CC and jump accordingly

System Programming 13

Programming examples
-Looping and indexing
Index addressing mode
n Page 16, Figure 1.4 (a)
LDX ZERO INITIALIZE INDEX REGISTER TO 0
MOVECH LDCH STR1, X LOAD CHARACTER FROM STR1 INTO REG A
STCH STR2, X STORE CHARACTER INTO STR2
TIX ELEVEN ADD 1 TO INDEX, COMPARE RESULT TO 11
JLT MOVECH LOOP IF INDEX IS LESS THAN 11
.
.
STR1 BYTE C'TEST STRING' 11-BYTE STRING CONSTANT
STR2 RESB 11 11-BYTE VARIABLE
.
ZERO WORD 0
ELEVEN WORD 11

op x address
LDCH STR1, X LDCH x=1 STR1
X
TA (Target Address) = disp + (X) è STR1 + (X)
Reg. A[Rightmost Byte] ß (TA) STR1
Reg. A[Rightmost Byte] ß STR[X]
System Programming 14
 Programming examples
- Indexing and looping
n Page 17, Figure 1.5 (a)
LDA ZERO INITIALIZE INDEX VALUE TO 0
STA INDEX
ADDLP LDX INDEX LOAD INDEX VALUE INTO REGISTER X
LDA ALPHA,X LOAD WORD FROM ALPHA INTO REGISTER A
ADD BETA,X ADD WORD FROM BETA
STA GAMMA,X STORE THE RESULT IN A WORD IN GAMMA
SIC 中只有 A 可以運算 LDA INDEX ADD 3 TO INDEX VALUE
ADD THREE
STA INDEX
(A) ? (K300) COMP K300 COMPARE NEW INDEX VALUE TO 300
JLT ADDLP LOOP IF INDEX IS LESS THAN 300
.
INDEX RESW 1 ONE-WORD VARIABLE FOR INDEX VALUE
. ARRAY VARIABLES—100 WORDS EACH
ALPHA RESW 100
BETA RESW 100
GAMMA RESW 100
. ONE-WORD CONSTANTS
ZERO WORD 0
K300 WORD 300
THREE WORD 3 1 word = 3 bytes
System Programming 15

SIC machine architecture

n Input and output

n Input and output are performed by transferring 1 byte at
a time to or from the rightmost 8 bits of register A
n Each device is assigned a unique 8-bits code
n Three I/O instructions
n Test Device(TD)
n Test whether the addressed device is ready to
send or receive a byte of data
n CC : < : ready
n CC : = : busy
n Read Data (RD)
n Write Data (WD)

System Programming 16
 Simple I/O example for SIC

n Page 19, Figure 1.6 cc : = denotes device busy

INLOOP TD INDEV TEST INPUT DEVICE

JEQ INLOOP LOOP UNTIL DEVICE IS READY
RD INDEV READ ONE BYTE INTO REGISTER A
STCH DATA STORE BYTE THAT WAS READ

OUTLP TD OUTDEV TEST OUTPUT DEVICE

JEQ OUTLP LOOP UNTIL DEVICE IS READY
LDCH DATA LOAD DATA BYTE INTO REGISTER A
WD OUTDEV WRITE ONE BYTE TO OUTPUT DEVICE

INDEV BYTE X’F1’ INPUT DEVICE NUMBER

OUTDEV BYTE X’05’ OUTPOUT DEVICE NUMBER
DATA RESB 1 ONE-BYTE VARIABLE

System Programming 17

SIC machine architecture

n Instruction set
n Subroutine linkage instructions
n JSUB
n Jump and place the return address in register L
n RSUB
n Return to the address in L

System Programming 18
 Programming examples
- Subroutine call and record input
n Page 20, Figure 1.7 (a)
JSUB READ CALL READ SUBROUTINE
L .
. SUBROUTINE TO READ 100-BYTE RCORD
READ LDX ZERO INITAILIZE INDEX REGISTER TO 0
RLOOP TD INDEV TEST INPUT DEVICE
JEQ RLOOP LOOP IF DEVICE IS BUSY
RD INDEV READ ONE BYTE INTO REGISTER A
STCH RECORD,X STORE DATA BYTE INTO RECORD
TIX K100 ADD 1 TO INDEX AND COMPARE TO 100
JLT RLOOP LOOP IF INDEX IS LESS THAN 100
RSUB EXIT FROM SUBROUTINE
.
INDEV BYTE X’F1’ INPUT DEVICE NUMBER
RECORD RESB 100 100-BYTE BUFFER FOR INPUT RECORD
. ONE-WORD CONSTANTS
ZERO WORD 0
K100 WORD 100

System Programming 19

Special symbols (SIC & SIC/XE)

n # : immediate addressing
n Ex: LDA #5 A ß 5
n @ : indirect addressing
n + : format 4
n * : the current value of PC
n C’ ‘ : character string
n X’ ‘ : hexadecimal number
n op m, x : x denotes the index addressing
n SIC assembler directive
n START : specify name & starting address (memory location)
n END : end of source program, specify the first
execution instruction
System Programming 20
SIC/XE machine architecture
n Memory
n Maximum memory available on a SIC/XE system is 1 megabyte
(220 bytes)
n Instruction format and addressing modes are changed
n Register (Additional registers)
Mnemonic Number Special use
B 3 Base register; used for addressing
S 4 General working register - no special use
T 5 General working register - no special use
F 6 Floating-point accumulator (48bits)

n Registers S and T are only for storing data. They can not use for
accumulator
n Ex: ADDR S, A A ¬ A+S
COMPR X, T
System Programming 21

SIC/XE machine architecture

n Data formats
n There is a 48-bit floating-point data type
1 11 36
s exponent fraction

n sign bit s (0: +, 1: -)

n fraction f: a value between 0 and 1
n exponent e: unsigned binary number between 0 and
2047
n value: s * f * 2 (e-1024)
n Ex: 5 = 22+20=(2-1+2-3)*23= (2-1+2-3)*21027-1024
0,10000000011,1010000….0

System Programming 22
SIC/XE machine architecture

n Instruction formats
n Since the memory used by SIC/XE may be 220 bytes,
the instruction format of SIC is not enough.
8 1 15
n Solutions opcode x address
n Use relative addressing
n Extend the address field to 20 bits

n SIC/XE instruction formats

Format 1 (1 byte) op (8)
Format 2 (2 byte) op (8) r1 (4) r2 (4)
Format 3 (3 byte) op (6) n i x b p e disp (12)
Format 4 (4 byte) op (6) n i x b p e address (20)
e = 0: format 3, e = 1: format 4
System Programming 23

SIC/XE machine architecture

n Addressing modes
n New relative addressing modes for format 3
Mode Indication Target address calculation
Base relative b = 1, p = 0 TA = (B) + disp (0 ≦ disp ≦ 4095)
Program-counter b = 0, p = 1 TA = (PC) + disp (-2048 ≦ disp ≦ 2047)
relative

n When base relative mode is used, disp is a 12-

bits unsigned integer
n When program-counter relative mode is used, disp
is a 12-bits signed integer
n 2’s complement
n Direct addressing for formats 3 and 4 if b=p=0
n These two addressing mode can combine with
index addressing if x=1

System Programming 24
 SIC/XE machine architecture

n Addressing modes
n Bits x, b, p, e: how to calculate the target address
n relative, direct, and indexed addressing
modes (e = 0/1, format 3/4)
n Bits i and n: how to use the target address (TA)
Mode Indication Operand value
Immediate addressing n=0, i=1 TA: TA is used as the operand value,
no memory reference
Indirect addressing n=1, i=0 ((TA)): The word at the TA is fetched.
Value of TA is taken as the address of
the operand value
Simple addressing n=0, i=0 Standard SIC
n=1, i=1 (TA): TA is taken as the address of the
operand value
System Programming 25

Addressing mode summary

Addressing Flag bits Assembler language Calculation of target Operand Notes
type nixbpe notation address TA
Simple 110000 op c disp (TA) D
110001 +op m addr (TA) 4D
110010 op m (PC)+disp (TA) A
110100 op m (B)+disp (TA) A
111000 op c,X disp+(X) (TA) D
111001 +op m,X addr+(X) (TA) 4D
111010 op m,X (PC)+disp+(X) (TA) A
111100 op m,X (B)+disp+(X) (TA) A
000 --- op m b/p/e/disp (TA) D S
001 --- op m,X b/p/e/disp+(X) (TA) D S
Indirect 100000 op @c disp ((TA)) D
100001 +op @m addr ((TA)) 4D
100010 op @m (PC)+disp ((TA)) A
100100 op @m (B)+disp ((TA)) A
Immediate 010000 op #c disp TA D
010001 +op #m addr TA 4D
010010 op #m (PC)+disp TA A
010100 op #m (B)+disp TA A

System Programming 26
 Immediate n=0, i=1

Indirect n=1, i=0

Addressing mode example Simple n=0, i=0

n=1, i=1

(B) = 006000
(PC) = 003000 Machine instruction Target Value loaded
(X) = 000090 Hex op n i x b p e disp/address Address into register A
. . 032600 000000 1 1 0 0 1 0 0110 0000 0000 3600 103000
.
.
.
. 練習: Simple + PC relative disp = 600 TA = (PC) + disp (3600)
02C300 000000 1 0 1 1 0 0 0011 0000 0000 6390 003030
3030 003600 03C300 000000 1 1Indirect
1 1 0 0 0011 disp = 0000
0000 300 TA= 6000+90+300
6390 ((6390))
00C303
. . Simple + index + base relative disp = 300 TA = (B) + disp + (X) (6390)
. .
. .
012C30 000000 0
022030 000000 1 10 00 00 11 00 000011000011
00110000
0000 2C30
3030 002C30
103000
3600 103000 Immediate
Indirect + PC relative disp
disp = C30
= 030 TA
TA==3000
(PC) – 3D0
+ disp 2C30
((3030))
. .
. .
. . 010030 000000 0 1 0 0 0 0 0000 0011 0000 30 000030
. . Immediate disp = 030 TA = disp 30
. .

6390 00C303
003600 000000 0 0 0 0 1 1 0110 0000 0000 3600 103000
. . Simple (SIC) disp = 3600 TA = disp (3600)
. .
. .
0310C303 000000 1 1 0 0 0 1 0000 1100 0011 0000 0011 C303 003030
C303 003030
Simple disp = C303 TA = disp (C303)
. .
. .
. . System Programming 27

SIC/XE machine architecture

n Instruction set
n Standard SIC’s instruction
n Load and store registers (B, S, T, F)
n LDB, STB, …
n Floating-point arithmetic operations
n ADDF, SUBF, MULF, DIVF
n Register-register arithmetic operations
n ADDR, SUBR, MULR, DIVR
n Register move operations
n RMO
n Supervisor call (SVC)
n generates an interrupt for OS (Chap 6)
n Input/Output
n SIO, TIO, HIO: start, test, halt the operation of I/O device

System Programming 28
 SIC/XE machine architecture

n Instruction set
n Refer to Appendix A for all instructions (Page 496)
n Notations for appendix
n A ¬ (m..m+2): move word begin at m to A
n P: privileged instruction
n X: instruction available only in SIC/XE
n C: condition code CC

System Programming 29

SIC, SIC/XE Instruction Table (1/4)

Mnemonic Format Opcode Effect Notes
------------ ------ ------ ----------------------------------- ------
ADD m 3/4 18 A <-- (A) + (m..m+2)
ADDF m 3/4 58 F <-- (F) + (m..m+5) X F
ADDR r1,r2 2 90 r2 <-- (r2) + (r1) X
AND m 3/4 40 A <-- (A) & (m..m+2)
CLEAR r1 2 B4 r1 <-- 0 X
COMP m 3/4 28 A : (m..m+2)
COMPF m 3/4 88 F : (m..m+5) X F C
COMPR r1,r2 2 A0 (r1) : (r2) X F C
DIV m 3/4 24 A : (A) / (m..m+2)
DIVF m 3/4 64 F : (F) / (m..m+5) X F
DIVR r1,r2 2 9C (r2) <-- (r2) / (r1) X
FIX 1 C4 A <-- (F) [convert to integer] X F
FLOAT 1 C0 F <-- (A) [convert to floating] X F
HIO 1 F4 Halt I/O channel number (A) P X
J m 3/4 3C PC <-- m
JEQ m 3/4 30 PC <-- m if CC set to =
JGT m 3/4 34 PC <-- m if CC set to >
JLT m 3/4 38 PC <-- m if CC set to <
JSUB m 3/4 48 L <-- (PC); PC <-- m
SIC Instructions are in blue
System Programming 30
 SIC, SIC/XE Instruction Table (2/4)
Mnemonic Format Opcode Effect Notes
------------ ------ ------ ----------------------------------- ------
LDA m 3/4 00 A <-- (m..m+2)
LDB m 3/4 68 B <-- (m..m+2) X
LDCH m 3/4 50 A [rightmost byte] <-- (m)
LDF m 3/4 70 F <-- (m..m+5) X F
LDL m 3/4 08 L <-- (m..m+2)
LDS m 3/4 6C S <-- (m..m+2) X
LDT m 3/4 74 T <-- (m..m+2) X
LDX m 3/4 04 X <-- (m..m+2)
LPS m 3/4 D0 Load processor status from P X
information beginning at
address m (see Section
6.2.1)
MUL m 3/4 20 A <-- (A) * (m..m+2)
MULF m 3/4 60 F <-- (F) * (m..m+5) X F
MULR r1,r2 2 98 r2 <-- (r2) * (r1) X
NORM 1 C8 F <-- (F) [normalized] X F
OR m 3/4 44 A <-- (A) | (m..m+2)
RD m 3/4 D8 A [rightmost byte] <-- data P
from device specified by (m)
System Programming 31

SIC, SIC/XE Instruction Table (3/4)

Mnemonic Format Opcode Effect Notes
------------ ------ ------ ----------------------------------- ------
RMO r1,r2 2 AC r2 <-- (r1) X
RSUB 3/4 4C PC <-- (L)
SHIFTL r1,n 2 A4 r1 <-- (r1); left circular X
shift n bits. {In assembled
instruction, r2=n-1}
SHIFTR r1,n 2 A8 r1 <-- (r1); right shift n X
bits with vacated bit
positions set equal to
leftmost bit of (r1).
{In assembled instruction,
r2=n-1}
SIO 1 F0 Start I/O channel number (A); P X
address of channel program
is given by (S)
SSK m 3/4 EC Protection key for address m P X
<-- (A) (see Section 6.2.4)
STA m 3/4 0C m..m+2 <-- (A)
STB m 3/4 78 m..m+2 <-- (B) X
STCH m 3/4 54 m <-- (A) [rightmost byte]
STF m 3/4 80 m..m+5 <-- (F) X 32
 SIC, SIC/XE Instruction Table (4/4)
Mnemonic Format Opcode Effect Notes
------------ ------ ------ ----------------------------------- ------
STI m 3/4 D4 Interval timer value <-- P X
(m..m+2) (see Section
6.2.1)
STL m 3/4 14 m..m+2 <-- (L)
STS m 3/4 7C m..m+2 <-- (S) X
STSW m 3/4 E8 m..m+2 <-- (SW) P
STT m 3/4 84 m..m+2 <-- (T) X
STX m 3/4 10 m..m+2 <-- (X)
SUB m 3/4 1C A <-- (A) - (m..m+2)
SUBF m 3/4 5C F <-- (F) - (m..m+5) X F
SUBR r1,r2 2 94 r2 <-- (r2) - (r1) X
SVC n 2 B0 Generate SVC interrupt. {In X
assembled instruction, r1=n}
TD m 3/4 E0 Test device specified by (m) P C
TIO 1 F8 Test I/O channel number (A) P X C
TIX m 3/4 2C X <-- (X) + 1; (X) : (m..m+2) C
TIXR r1 2 B8 X <-- (X) + 1; (X) : (r1) X C
WD m 3/4 DC Device specified by (m) <-- (A) P
[rightmost byte]
System Programming 33

Programming examples (SIC/XE)

- Data movement

n Page 13, Figure 1.2 (b)

EX1 START 0
FIRST LDA #5 LOAD VALUE 5 INTO REGISTER A
STA ALPHA STORE IN ALPHA
LDA #90 LOAD ASCII CODE FOR ‘Z’ INTO REG A
STCH C1
.
.
ALPHA RESW 1 ONE-WORD VARIABLE
C1 RESB 1 ONE-BYTE VARIABLE
END FIRST

System Programming 34
 Programming examples (SIC/XE)
- Arithmetic

n Page 15, Figure 1.3 (b)

LDS INCR LOAD VALUE OF INCR INTO REGISTER S
LDA ALPHA LOAD ALPHA INTO REGISTER A
ADDR S, A ADD THE VALUE OF INCR
SUB #1 SUBTRACT 1
STA BETA STORE IN BETA
LDA GAMMA LOAD GAMMA INTO REGISTER A
ADDR S, A ADD THE VALUE OF INCR
SUB #1 SUBTRACT 1
STA DELTA STORE IN DELTA
.
.
. ONE WORD VARIABLES
ALPHA RESW 1
BETA RESW 1
GAMMA RESW 1
DELTA RESW 1
INCR RESW 1
System Programming 35

Programming examples (SIC/XE)

-Looping and indexing

n Page 16, Figure 1.4 (b)

LDT #11 INITIALIZE REGISTER T TO 11
LDX #0 INITIALIZE INDEX REGISTER TO 0
MOVECH LDCH STR1, X LOAD CHARACTER FROM STR1 INTO REG A
STCH STR2, X SOTRE CHARACTER INTO STR2
TIXR T ADD 1 TO INDEX, COMPARE RESULT TO 11
JLT MOVECH LOOP IF INDEX IS LESS THAN 11
.
.
STR1 BYTE C'TEST STRING’ 11-BYTE STRING CONSTANT
STR2 RESB 11 11-BYTE VARIABLE

System Programming 36
 Programming examples (SIC/XE)
- Indexing and looping
n Page 17, Figure 1.5 (b)
LDS #3 INITIALIZE REGISTER S TO 3
LDT #300 INITIALIZE REGISTER T TO 300
LDX #0 INITIALIZE INDEX REGISTER TO 0
ADDLP LDA ALPHA, X LOAD WORD FROM ALPHA INTO REGISTER A
ADD BETA, X ADD WORD FROM BETA
STA GAMMA, X STORE THE RESULT IN A WORD IN GAMMA
ADDR S, X ADD 3 TO INDEX VALUE
COMPR X, T COMPARE NEW INDEX VALUE TO 300
JLT ADDLP LOOP IF INDEX VALUE IS LESS THAN 300
.
.
. ARRAY VARIABLES—100 WORDS EACH
ALPHA RESW 100
BETA RESW 100
GAMMA RESW 100

System Programming 37

Programming examples (SIC/XE)

- Subroutine call and record input
n Page 20, Figure 1.7 (b)
JSUB READ CALL READ SUBROUTINE
.
.
. SUBROUTINE TO READ 100-BYTE RECORD
READ LDX #0 INITIALIZE INDEX REGISTER TO 0
LDT #100 INITIALIZE REGISTER T TO 100
RLOOP TD INDEV TEST INPUT DEVICE
JEQ RLOOP LOOP IF DEVICE IS BUSY
RD INDEV READ ONE BYTE INTO REGISTER A
STCH RECORD,X STORE DATA BYTE INTO RECORD
TIXR T ADD 1 TO INDEX AND COMPARE TO 100
JLT RLOOP LOOP IF INDEX IS LESS THAN 100
RSUB EXIT FROM SUBROUTINE
.
.
INDEV BYTE X'F1’ INPUT DEVICE NUMBER
RECORD RESB 100 100-BYTE BUFFER FOR INPUT RECORD

System Programming 38
Programming examples (SIC/XE)
- SWAP the values of two variables
BEGIN START 1000
LDS #ALPHASWAP ALPHAS <-- Address of ALPHA
BETA
LDT #BETA Parameter?T <-- Address of BETA
JSUB SWAP
LDS #DATA1SWAP DATA1 DATA2
LDT #DATA2Parameters?
JSUB SWAP
END BEGIN
ALPHA WORD 1
BETA WORD 2
DATA1 WORD 3
DATA2 WORD 4

System Programming 39

Programming examples (SIC/XE)

- SWAP the values of two variables
.
. SUBROUTINE TO SWAP TWO WORDS,
. TWO PARAMETERS:
. RESGITERS S AND T STORE THE ADDRESS OF TWO WORDS

SWAP STS ADDR1

STT ADDR2
LDA @ADDR1 TEMP <- @ADDR1
STA TEMP
LDA @ADDR2 @ADDR1 <- @ADDR2
STA @ADDR1
LDA TEMP @ADDR2 <- TEMP
STA @ADDR2
RSUB
ADDR1 RESW 1
ADDR2 RESW 1
TEMP RESW 1

System Programming 40