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MEL ZG632 EC-3R First SEM 2023-2024

The document contains 4 questions about analog IC design. Question 1 asks to calculate properties of an amplifier circuit including DC gate voltage, transconductance, output resistance and gain. Question 2 asks similar calculations for a differential amplifier circuit. Question 3 asks about open loop gain, feedback factor, closed loop gain, and input/output impedances with and without feedback for another amplifier. Question 4 asks to calculate mid-band gain and pole frequencies for another circuit.

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Adithyan J
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28 views4 pages

MEL ZG632 EC-3R First SEM 2023-2024

The document contains 4 questions about analog IC design. Question 1 asks to calculate properties of an amplifier circuit including DC gate voltage, transconductance, output resistance and gain. Question 2 asks similar calculations for a differential amplifier circuit. Question 3 asks about open loop gain, feedback factor, closed loop gain, and input/output impedances with and without feedback for another amplifier. Question 4 asks to calculate mid-band gain and pole frequencies for another circuit.

Uploaded by

Adithyan J
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Birla Institute of Technology & Science, Pilani

Work-Integrated Learning Programmes Division


First Semester 2023-2024
End Semester Exam
(EC-3 Regular)
Course No. : MEL ZG632
Course Title : ANALOG IC DESIGN
Nature of Exam : Open Book
Pattern of Exam : Type Only No. of Pages =
Weightage : 40% No. of Questions = 4
Duration : 2:30 Hours
Date of Exam :
Note:
1. Please follow all the Instructions to Candidates given on the test portal.
2. Assumptions made if any, should be stated clearly at the beginning of your answer.

Q.1. For amplifier shown below I_Bias = 200 µA. VDD = 3 V. All transistors are in saturation. All
transistors have W/L = 80 µm / 2 µm. Neglect body effect. Channel length modulation is to be
neglected for DC analysis. Find: -
(i) The DC voltage at the gates of the pMOSFETs. (2)
(ii) Transconductance gm of Q1 (2)
(iii) Small signal output resistance rout (2)
(iv) Small signal gain (2)
Total 8 Marks
Q.2.
For amplifier shown below DC voltage at VO1 = VO2 = 3V. RD1 = RD2 = 5 K. All transistors are in
saturation and have W/L = 80 µm / 2 µm. Neglect body effect and channel length modulation. Find: -
(i) The I_Bais (2)
(ii) Transconductance gm of Q1 and Q2 (2)
(iii) Small signal differential gain (V02-V01) / (Vin+ - Vin-) (2)
(iv) Common mode gain (1)
(v) CMMR (1)
(vi) Max VCM for transistors to be in saturation (neglecting small signal Vin+ and Vin-) (1)
(vii) If Vin+ = - Vin- = 100 mV sin 2π (1KHz)t, find V01 and VO2 (2)
(viii) If Vin+ = Vin- = 0 and VCM = 100 mV sin 2π (1KHz)t find V01 and VO2 (1)
Total 12 Marks
Q.3.
For the amplifier shown below the transconductance gm of both transistors is 1 mA/V. Neglect body
effect and channel length modulation. Find: -

(i) Open circuit gain without feedback 2 Marks


(ii) Feedback factor 𝞫 2 Marks
(iii) Closed Loop gain with feedback 2 Marks
(iv) Input Impedance without feedback 1 Mark
(v) Input Impedance with feedback 1 Mark
(vi) Output Impedance without feedback 1 Mark
(vii) Output Impedance with feedback 1 Mark
(viii) If the open loop BW is 10 MHz find the BW after feedback. 2 Mark
Total 12 Marks
Q.4.
For the amplifier shown below the transconductance gm of the transistors is 6 mA/V. Neglect channel
length modulation. For the MOSFET, Cgd = 2 pF and Cgs = 4 pF. Find mid-bad gain. C2 is large and
can be assumed to be short for ac signals. Find all the poles (frequencies in MHz) that start attenuation
of high frequency signals. RS = 100 .
Total 08 Marks

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