SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003

D Meet or Exceed Standards TIA/EIA-422-B SN65C1167 . . . DB OR NS PACKAGE

and ITU Recommendation V.11 SN75C1167 . . . DB, N, OR NS PACKAGE
(TOP VIEW)
D BiCMOS Process Technology
D Low Supply-Current Requirements: 1B 1 16 VCC
9 mA Max 1A 2 15 1D
D Low Pulse Skew 1R 3 14 1Y
RE 1Z
D Receiver Input Impedance . . . 17 kΩ Typ
4 13
2R 5 12 DE
D Receiver Input Sensitivity . . . ±200 mV 2A 6 11 2Z
D Receiver Common-Mode Input Voltage 2B 7 10 2Y
Range of −7 V to 7 V GND 8 9 2D
D Operate From Single 5-V Power Supply
D Glitch-Free Power-Up/Power-Down SN65C1168 . . . N, NS, OR PW PACKAGE
Protection SN75C1168 . . . DB, N, NS, OR PW PACKAGE
(TOP VIEW)
D Receiver 3-State Outputs Active-Low
Enable for SN65C1167 and SN75C1167 Only 1B 1 16 VCC
D Improved Replacements for the MC34050 1A 2 15 1D
and MC34051 1R 3 14 1Y
1DE 4 13 1Z
description/ordering information 2R 5 12 2DE
2A 6 11 2Z
The SN65C1167, SN75C1167, SN65C1168,
and SN75C1168 dual drivers and receivers are 2B 7 10 2Y
integrated circuits designed for balanced GND 8 9 2D
transmission lines. The devices meet
TIA/EIA-422-B and ITU recommendation V.11.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP (N) Tube SN75C1167N SN75C1167N
SOP (NS) Tape and reel SN75C1167NSR 75C1167
SSOP (DB) Tape and reel SN75C1167DBR CA1167
PDIP (N) Tube SN75C1168N SN75C1168N
0°C to 70°C
SOP (NS) Tape and reel SN75C1168NSR 75C1168
SSOP (DB) Tape and reel SN75C1168DBR CA1168
Tube SN75C1168PW
TSSOP (PW) CA1168
Tape and reel SN75C1168PWR
SOP (NS) Tape and reel SN65C1167NSR 65C1167
SSOP (DB) Tape and reel SN65C1167DBR CB1167
PDIP (N) Tube SN65C1168N SN65C1168N
−40°C to 85°C
SOP (NS) Tape and reel SN65C1168NSR 65C1168
Tube SN65C1168PW
TSSOP (PW) CB1168
Tape and reel SN65C1168PWR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

     !"   #!$% &"' Copyright  2003, Texas Instruments Incorporated
&!   #" #" (" "  ") !"
&& *+' &! #", &"  ""%+ %!&"
",  %% #""'

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1




 

 
 

SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003

description/ordering information (continued)

The SN65C1167 and SN75C1167 combine dual 3-state differential line drivers and 3-state differential line
receivers, both of which operate from a single 5-V power supply. The driver and receiver have active-high and
active-low enables, respectively, which can be connected together externally to function as direction control.
The SN65C1168 and SN75C1168 drivers have individual active-high enables.

Function Tables

EACH DRIVER
INPUT ENABLE OUTPUTS
D DE Y Z
H H H L
L H L H
X L Z Z

SN75C1167, EACH RECEIVER

DIFFERENTIAL INPUTS ENABLE OUTPUT
A−B RE R
VID ≥ 0.2 V L H
−0.2 V < VID < 0.2 V L ?
VID ≤ −0.2 V L L
X H Z
Open L H
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)

logic diagram (positive logic)

SN65C1167/SN75C1167 SN65C1168, SN75C1168

12 4
DE 1DE 14
15 1Y
4 1D 13
RE 1Z
2
14 3 1A
15 1Y 1R 1
1D 13 1B
1Z 12
2DE 10
2 2Y
3 1A 9
1R 1 2D 11
1B 2Z
6
10 5 2A
9 2Y 2R 7
2D 11 2B
2Z
6
5 2A
2R 7
2B

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




 

 
 

SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003

schematics of inputs

EQUIVALENT OF DRIVER ENABLE INPUT EQUIVALENT OF A OR B INPUT

VCC
VCC

17 kΩ 1.7 kΩ
NOM NOM
Input Input
288 kΩ 1.7 kΩ
NOM NOM

VCC (A)
or
GND GND (B)

GND

schematics of outputs

TYPICAL OF EACH DRIVER OUTPUT TYPICAL OF EACH RECEIVER OUTPUT

VCC VCC

Output

Output

GND
GND

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3




 

 
 

SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input voltage range, VI (A or B, Receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −11 V to 14 V
Differential input voltage range, VID, Receiver (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −14 V to 14 V
Output voltage range, VO, Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to 7 V
Clamp current range, IIK or IOK, Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output current range, IO, Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±150 mA
Supply current, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
GND current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −200 mA
Output current range, IO, Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Operating virtual junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Package thermal impedance, θJA (see Notes 3 and 4): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values except differential input voltage are with respect to the network GND.
2. Differential input voltage is measured at the noninverting terminal with respect to the inverting terminal.
3. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Selecting the maximum of 150°C can affect reliability.
4. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
Common-mode input voltage
VIC Receiver ±7 V
(see Note 5)
VID Differential input voltage Receiver ±7 V
VIH High-level input voltage Except A, B 2 V
VIL Low-level input voltage Except A, B 0.8 V
Receiver −6
IOH High-level output current mA
Driver −20
Receiver 6
IOL Low-level output current mA
Driver 20
SN75C1167, SN75C1168 0 70
TA Operating free-air temperature °C
SN65C1167, SN65C1168 −40 85
NOTE 5: Refer to TIA/EIA-422-B for exact conditions.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




 

 
 

SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003

DRIVER SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIK Input clamp voltage II = −18 mA −1.5 V
VOH High-level output voltage VIH = 2 V, VIL = 0.8 V, IOH = −20 mA 2.4 3.4 V
VOL Low-level output voltage VIH = 2 V, VIL = 0.8 V, IOL = 20 mA 0.2 0.4 V
|VOD1| Differential output voltage IO = 0 mA 2 6 V
|VOD2| Differential output voltage 2 3.1 V
Change in magnitude of differential
∆|VOD| ±0.4 V
output voltage
RL = 100 Ω, See Figure 1 and Note 5
VOC Common-mode output voltage ±3 V
Change in magnitude of common-mode
∆|VOC| ±0.4 V
output voltage
VO = 6 V 100 µA
IO(OFF) Output current with power off (see Note 3) VCC = 0 V
VO = −0.25 V −100 µA
VO = 2.5 V 20
IOZ High-impedance-state output current µA
A
VO = 5 V −20
IIH High-level input current VI = VCC or VIH 1 µA
IIL Low-level input current VI = GND or VIL −1 µA
IOS Short-circuit output current VO = VCC or GND, See Note 6 −30 −150 mA
No load, VI = VCC or GND 4 6
ICC Supply current (total package) mA
Enabled VI = 2.4 or 0.5 V, See Note 7 5 9
Ci Input capacitance 6 pF
† All typical values are at VCC = 5 V and TA = 25°C.
NOTES: 5. Refer to TIA/EIA-422-B for exact conditions.
6. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
7. This parameter is measured per input, while the other inputs are at VCC or GND.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
tPHL Propagation delay time, high- to low-level output R1 = R2 = 50 Ω, R3 = 500 Ω, 7 12 ns
tPLH Propagation delay time, low- to high-level output C1 = C2 = C3 = 40 pF, S1 is open, 7 12 ns
tsk(p) Pulse skew See Figure 2 0.5 4 ns

tr Rise time R1 = R2 = 50 Ω, R3 = 500 Ω, 5 10 ns

C1 = C2 = C3 = 40 pF, S1 is open,
tf Fall time See Figure 3 5 10 ns

tPZH Output enable time to high level R1 = R2 = 50 Ω, R3 = 500 Ω, 10 19 ns

C1 = C2 = C3 = 40 pF, S1 is closed,
tPZL Output enable time to low level See Figure 4 10 19 ns

tPHZ Output disable time from low level R1 = R2 = 50 Ω, R3 = 500 Ω, 7 16 ns

C1 = C2 = C3 = 40 pF, S1 is closed,
tPLZ Output disable time from high level See Figure 4 7 16 ns
† All typical values are at VCC = 5 V and TA = 25°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5




 

 
 

SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003

RECEIVER SECTION

electrical characteristics over recommended ranges of common-mode input voltage, supply

voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
Positive-going input threshold voltage,
VIT+ 0.2 V
differential input
Negative-going input threshold voltage,
VIT− −0.2‡ V
differential input
Vhys Input hysteresis (VIT+ − VIT−) 60 mV
VIK Input clamp voltage, RE SN75C1167 II = −18 mA −1.5 V
VOH High-level output voltage VID = 200 mV, IOH = −6 mA 3.8 4.2 V
VOL Low-level output voltage VID = −200 mV, IOL = 6 mA 0.1 0.3 V
High-impedance-state output
IOZ SN75C1167 VO = VCC or GND ±0.5 ±5 µA
current
VI = 10 V 1.5
II Line input current Other input at 0 V mA
VI = −10 V −2.5
II Enable input current, RE SN75C1167 VI = VCC or GND ±1 µA
ri Input resistance VIC = −7 V to 7 V, Other input at 0 V 4 17 kΩ
VI = VCC or GND 4 6
ICC Supply current (total package) No load, Enabled VIH = 2.4 V or 0.5 V, mA
5 9
See Note 5
† All typical values are at VCC = 5 V and TA = 25°C.
‡ The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 5: Refer to TIA/EIA-422-B for exact conditions.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 8)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
tPLH Propagation delay time, low- to high-level output 9 17 27 ns
See Figure 5
tPHL Propagation delay time, high- to low-level output 9 17 27 ns
tTLH Transition time, low- to high-level output 4 9 ns
VIC = 0 V, See Figure 5
tTHL Transition time, high- to low-level output 4 9 ns
tPZH Output enable time to high level 13 22 ns
tPZL Output enable time to low level 13 22 ns
RL = 1 kW, See Figure 6
tPHZ Output disable time from high level 13 22 ns
tPLZ Output disable time from low level 13 22 ns
† All typical values are at VCC = 5 V and TA = 25°C.
NOTE 8: Measured per input while the other inputs are at VCC or GND

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




 

 
 

SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003

PARAMETER MEASUREMENT INFORMATION

RL
2
VOD2
RL
2 VOC

Figure 1. Driver Test Circuit, VOD and VOC

3V
Input
(see Note B) 1.3 V 1.3 V
0V

Y tPLH tPHL
VOH
C2 R1
R3 Y 50% 50%
Input 1.3 V 1.3 V
C1 1.5 V VOL
S1 tsk(p) tsk(p)
C3 R2
VOH
Z
50% 50%
See Note A Z 1.3 V 1.3 V VOL
tPHL tPLH

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. C1, C2, and C3 include probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf ≤ 6 ns.

Figure 2. Driver Test Circuit and Voltage Waveforms

Input 3V
(see Note B)
C2 R1 0V
Input VOD R3
C1 1.5 V
S1 Differential 90% 90%
C3 R2
Output 10% 10%

See Note A tr tf

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. C1, C2, and C3 include probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf ≤ 6 ns.

Figure 3. Driver Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7




 

 
 

SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003

PARAMETER MEASUREMENT INFORMATION

3V
Input DE
1.3 V 1.5 V
0V
C2 R1 tPLZ tPZL
0V R3
or C1 1.5 V 1.5 V
3V S1 Output VOL + 0.3 V 0.8 V
C3 R2 VOL
Pulse tPHZ tPZH
DE VOH
Generator
50 Ω See Note A VOL − 0.3 V
See Note B Output 2V
1.5 V
TEST CIRCUIT VOLTAGE WAVEFORMS
NOTES: A. C1, C2, and C3 include probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf ≤ 6 ns.

Figure 4. Driver Test Circuit and Voltage Waveforms

VCC
S1
tTLH tTHL

Output VOH
90% 90%
(see Note B) 10% 50% 50% 10%
VOL
RL tPLH tPHL
A Input Device
Under 2.5 V
B Input Test B Input 0V
CL = 50 pF A Input = 0 V
(see Note A) −2.5 V

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr = tf ≤ 6 ns.

Figure 5. Receiver Test Circuit and Voltage Waveforms

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265




 

 
 

SLLS159E − MARCH 1993 − REVISED NOVEMBER 2003

PARAMETER MEASUREMENT INFORMATION

3V
RE Input 1.3 V 1.3 V
VCC
S1 0V
tPLZ 0.5 V tPZL
VCC
Output 50%
VOL
RE Input RL
Device tPHZ tPZH
Under VOH
VID = −2.5 V Test Output 50%
or 2.5 V CL = 50 pF
(see Note A) GND
0.5 V
tPZL, tPLZ Measurement: S1 to VCC
tPZH, tPHZ Measurement: S1 to GND

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr = tf ≤ 6 ns.

Figure 6. Receiver Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

MECHANICAL

MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

16 PINS SHOWN

PINS **
14 16 18 20
DIM

0.775 0.775 0.920 1.060

A A MAX
(19,69) (19,69) (23,37) (26,92)

16 9 0.745 0.745 0.850 0.940

A MIN
(18,92) (18,92) (21,59) (23,88)

0.260 (6,60) MS-100

AA BB AC AD
0.240 (6,10) C VARIATION

1 8
0.070 (1,78)
D
0.045 (1,14)

0.045 (1,14) 0.325 (8,26)

0.020 (0,51) MIN
0.030 (0,76) D 0.300 (7,62)
0.015 (0,38)

0.200 (5,08) MAX Gauge Plane

Seating Plane

0.125 (3,18) MIN 0.010 (0,25) NOM

0.100 (2,54) 0.430 (10,92) MAX

0.021 (0,53)
0.015 (0,38)
0.010 (0,25) M

14/18 PIN ONLY

20 pin vendor option D
4040049/E 12/2002

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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