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S-R Flip Flop MCQ Quiz - Objective Question with Answer for S-R Flip Flop -
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Last updated on Jan 29, 2024

Latest S-R Flip Flop MCQ Objective Questions

S-R Flip Flop Question 1:

For an RS flip flop:

(A) R = 0, S = 0, Qn+1 = 1

(B) R = 0, S = 0, Qn+1 = = Q̅ n

(C) R = 0, S = 0, Qn+1 = Qn

(D) R = 1, S = 0, Qn+1 = 0

(E) R = 0, S = 1, Qn+1 = 1

Choose the correct answer from the options given below:

1. (C), (D), (E) only

Home
2. (A),Digital Electronics
(D), (E) only Sequential Circuits Memory Elements S-R Flip Flop

3. (B), (D), (E) only

4. (C) and (D) only

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Answer (Detailed Solution Below)

Option 1 : (C), (D), (E) only

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S-R Flip Flop Question 1 Detailed Solution

RS Flip flop

In the flip-flop, R represents the reset state. It means the output will always be low for
any value of the input.

S represents the set state. It means the output will always be high for any value of the
input.

The truth table of the RS flip-flop is given below:

RSQn+1

0 0 Qn

100

011

1 1 Invalid state

Hence, the correct answer is option 1.

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S-R Flip Flop Question 2:

If the counter has 3 flip-flops, then the maximum binary number that it counts is
equal to:

1. 101

2. 011

3. 111

4. 110

Answer (Detailed Solution Below)

Option 3 : 111

S-R Flip Flop Question 2 Detailed Solution

Concept:

The maximum no. of states that can be represented by N flip-flops is given by:

No. of states = 2N

Calculation:

Given, N = 3

No. of states = 23 = 8

The states from 0 to 7 are represented by 3 flip-flops.

Octal Symbol Binary equivalent
English
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

The maximum binary number is 111

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S-R Flip Flop Question 3:

The data sheet of a certain flip-flop specifies that the minimum HIGH time tw(H) for the
clock pulse is 16 nanoseconds and the minimum LOW time tw(L) is 29 nanoseconds.
What is the maximum operating frequency for the given flip-flop?

1. 62⋅50 MHz

2. 31⋅25 MHz

3. 22⋅22 MHz

4. 11⋅11 MHz

Answer (Detailed Solution Below)

Option 3 : 22⋅22 MHz

S-R Flip Flop Question 3 Detailed Solution English

TON = 16 ns

TOFF = 29 ns

T = TON + TOFF

T = 16 + 29

T = 45 ns

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S-R Flip Flop Question 4:

How many flip-flops are required to build a binary counter circuit to count from 0 to
1023 ?

1. 1

2. 6

3. 10

4. 23
Answer (Detailed Solution Below) English

Option 3 : 10

S-R Flip Flop Question 4 Detailed Solution

The correct option is 10.

Concept:

Counters:

It is a sequential logic circuit that has a clock input signal and a group of output
signals
It represents an integer "counts" value.
Internally, counters use flip-flops to represent the current counts and to retain the
counts between clocks.
N values can be counted with n number of flip flops. its relation is given by:

where, N = number of counts

n = number of flip flops

Calculation-

Given- N= 1023

Hence total of 10 flip flops are required to count from 0 to 1023.

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S-R Flip Flop Question 5:

In which of the following condition the SR flip flop are unstable?

 1. S = 0, R = 1 English

2. S = 1, R = 0

3. S = 0, R = 0

4. S = 1, R = 1

Answer (Detailed Solution Below)

Option 4 : S = 1, R = 1

S-R Flip Flop Question 5 Detailed Solution

An un-clocked R-S flip flop using NOR gates is as shown:

The truth table for the circuit is shown:

Inputs (S R)Output (Qn+1) Action

00 Q No change

01 0 Reset

10 1 Set

Indeterminate
11 0
(Undefined)
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Top S-R Flip Flop MCQ Objective Questions

S-R Flip Flop Question 6 Download Soln PDF

The S-R latch is an example of:

1. Combinational circuit

2. Synchronous sequential circuit

3. One-bit memory element

4. One-clock delay element

Answer (Detailed Solution Below)

Option 3 : One-bit memory element

S-R Flip Flop Question 6 Detailed Solution Download Soln PDF

Explanation:

Latches and Flip-Flop:

Latches and flip-flops are the basic elements to store 1-bit of data. Hence they are
also known as a one-bit memory element.
Latches change the output continuously when there is a change in the input, i.e.
they are level triggered.
Flip-flop is a combination of latch and clock. It changes the output that is adjusted
by the clock.
The main difference between a latch and a flip-flop is that a flip-flop has a clock
signal, whereas a latch does not.
We can say that a flip-flop without a clock is a latch.
 Latches are asynchronous, which means that the output of a latch depends on its
input. English
Basically, there are 4 types of latches: SR latch, JK latch, D latch, T latch.

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S-R Flip Flop Question 7 Download Soln PDF

Identify the following sequential component.

1. Master-slave flip flop

2. Clocked flip flop

3. J-K flip flop

4. R-S flip flop

Answer (Detailed Solution Below)

Option 4 : R-S flip flop

S-R Flip Flop Question 7 Detailed Solution English Download Soln PDF

Explanation:

The given sequential component is of RS Flip Flop.

Here A = R and B = S

The truth table for the circuit is shown:

Inputs (SR)Output (Qn+1) Action

00 Q No change

01 0 Reset

10 1 Set

11 0 Forbidden (Undefined)

The difference between latches and flip flops is shown

Latches Flip Flops

Latches are building block of sequential Flip flops are also building blocks of
circuits and they are built using logic sequential circuits but they are made using
gates latches

Latches continuously change input and Flip flop output changes only when the clock
output changes correspondingly is applied

Latches are level sensitive Flip flops are edge sensitive

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S-R Flip Flop Question 8 Download Soln PDF

In which of the following condition the SR flip flop are unstable?

1. S = 0, R = 1

2. S = 1, R = 0

3. S = 0, R = 0

4. S = 1, R = 1

Answer (Detailed Solution Below)

Option 4 : S = 1, R = 1

S-R Flip Flop Question 8 Detailed Solution Download Soln PDF

An un-clocked R-S flip flop using NOR gates is as shown:

The truth table for the circuit is shown:
English

Inputs (S R)Output (Qn+1) Action

00 Q No change

01 0 Reset

10 1 Set

Indeterminate
11 0
(Undefined)

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S-R Flip Flop Question 9 Download Soln PDF

How many flip-flops are required to build a binary counter circuit to count from 0 to
1023 ?

1. 1

2. 6

3. 10

4. 23
Answer (Detailed Solution Below) English

Option 3 : 10

S-R Flip Flop Question 9 Detailed Solution Download Soln PDF

The correct option is 10.

Concept:

Counters:

It is a sequential logic circuit that has a clock input signal and a group of output
signals
It represents an integer "counts" value.
Internally, counters use flip-flops to represent the current counts and to retain the
counts between clocks.
N values can be counted with n number of flip flops. its relation is given by:

where, N = number of counts

n = number of flip flops

Calculation-

Given- N= 1023

Hence total of 10 flip flops are required to count from 0 to 1023.

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S-R Flip Flop Question 10 Download Soln PDF

If the counter has 3 flip-flops, then the maximum binary number that it counts is
equal to: English

1. 101

2. 011

3. 111

4. 110

Answer (Detailed Solution Below)

Option 3 : 111

S-R Flip Flop Question 10 Detailed Solution Download Soln PDF

Concept:

The maximum no. of states that can be represented by N flip-flops is given by:

No. of states = 2N

Calculation:

Given, N = 3

No. of states = 23 = 8

The states from 0 to 7 are represented by 3 flip-flops.

Octal Symbol Binary equivalent

0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

The maximum binary number is 111

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S-R Flip Flop Question 11 Download Soln PDF

For SR flip-flop with NOR gates, the undefined state is

1. S = 0, R = 0

2. S = 0, R = 1

3. S = 1, R = 1

4. S = 1, R = 0

Answer (Detailed Solution Below)

Option 3 : S = 1, R = 1

S-R Flip Flop Question 11 Detailed Solution Download Soln PDF

An unclocked R-S flip flop using NOR gates is as shown:

The truth table for the circuit is shown:
English

Inputs (S R)Output (Qn+1) Action

00 Q No change

01 0 Reset

10 1 Set

11 0 Forbidden (Undefined)

The difference between latches and flip flops is shown

Latches Flip Flops

Latches are building block of sequential Flip flops are also building blocks of
circuits and they are built using logic sequential circuits but they are made using
gates latches

Latches continuously changes input and Flip flop output changes only when clock is
output changes correspondingly applied

Latches are level sensitive Flip flops are edge sensitive

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S-R Flip Flop Question 12 Download Soln PDF

A feature that distinguishes the JK flip flop from the SR flipEnglish
flop is the

1. Toggle condition

2. Preset input

3. Type of clock

4. Clear input

Answer (Detailed Solution Below)

Option 1 : Toggle condition

S-R Flip Flop Question 12 Detailed Solution Download Soln PDF

In J-K flip flop when both inputs are HIGH, the output toggles i.e. it changes from
high to low and low to high periodically when both the inputs are 1.
For an SR flip flop, however, when both the inputs are HIGH, we encounter an
invalid state, which is not present for a JK flip flop.
This is explained with the help of the following function table:

SRCLK Q

00 ↑ Q0 (no change)

10 ↑ 1

01 ↑ 0
 1 1 ↑ Ambiguous (Invalid) English

​ imilarly, for a JK flip flop, the block diagram along with the function table is as
S
shown:

JKCLK Q

00 ↑ Q0 (no change)

10 ↑ 1

01 ↑ 0

11 ↑ Q̅ 0 (toggles)

Features that distinguish:

a) When both S and R inputs are 1, output goes to a metastable state but when
both the inputs of J and K are 1 output is in toggle state with respect to the
previous state.

b) JK flip flop is often termed as Universal flip flop because all other flips like D, T,
and SR can be derived from that while this is not the case with respect to SR flip
flops.

c) SR flip flops when used as latch can be helpful in the bounce elimination of the
switches which is one of its major advantages while this is not the case with JK
flip flops.

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S-R Flip Flop Question 13 Download Soln PDF

What is one disadvantage of an S-R flip-flop ?

1. It has no Enable input

2. It has a RACE condition

3. It has no clock input

4. It has only single output

Answer (Detailed Solution Below)

Option 2 : It has a RACE condition

S-R Flip Flop Question 13 Detailed Solution Download Soln PDF

An unclocked R-S flip flop using NOR gates is as shown:

The truth table for the circuit is shown:

SR Q+

00 Q (no change)
01 0 (Reset) English

10 1 (set)

1 1 Invalid/Forbidden state

When the S and R inputs of an SR flipflop are at logical 1, then the output becomes
unstable and it is known as a race condition.

So, the main disadvantage of the SR flip flop is invalid output when both inputs are
high.

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S-R Flip Flop Question 14 Download Soln PDF

A negative edge triggered flip flop transfers data from input to output on the:

1. WITHOUT transition of clock pulse

2. LOW to HIGH transition of clock pulse

3. HIGH to LOW transition of clock pulse

4. BEFORE transition of clock pulse

Answer (Detailed Solution Below)

Option 3 : HIGH to LOW transition of clock pulse
English

S-R Flip Flop Question 14 Detailed Solution Download Soln PDF

An edge-triggered flip-flop change states either at the positive edge (rising edge) or at
the negative edge (falling edge) of the clock pulse on the control input.

A negative edge triggered flip flop transfers data from input on the high to low
transition of the clock pulse.

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S-R Flip Flop Question 15 Download Soln PDF

The correct combination of characteristic equation Qn+1 of S-R flipflop and J-K flipflop
respectively is

1. QnR + S̅ and JQn + K̅Qn

2. Q̅ nR + S and J̅Qn + K̅Qn

3. QnR̅ + S and JQn + K̅Q̅ n

 4. QnR̅ + S and JQ̅ n + K̅Qn English

Answer (Detailed Solution Below)

Option 4 : QnR̅ + S and JQ̅ n + K̅Qn

S-R Flip Flop Question 15 Detailed Solution Download Soln PDF

SR flip flop:

Characteristic Table of SR flip flop

SRQnQn+1

00 0 0

00 1 1

01 0 0

01 1 0

10 0 1

10 1 1

11 0 X

11 1 X

Qn+1 = S + R̅ Qn

JK flip flop:
Characteristic Table of JK flip flop
English

JKQnQn+1

00 0 0

00 1 1

01 0 0

01 1 0

10 0 1

10 1 1

11 0 1

11 1 0

Qn+1 = JQ̅n + K̅Qn

Flip – flopCharacteristic equation

SR Qn+1 = S + R̅ Qn

J-K Qn+1 = TQn̅ + T̅Qn

D Qn+1 = JQ̅n + K̅Qn

T Q (t+1) = D

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