GYAN GANGA COLLEGE OF TECHNOLOGY, JABALPUR

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

LAB MANUAL

Computer Org. & Architecture

(CS-404)

NAME:

ENROLLMENT NUMBER:

SESSION: 2023-24
 Gyan Ganga College of Technology, Jabalpur

Computer Science & Engineering

Mission and Vision of the Institution:

Vision of Institute:

Initially to seek autonomy and eventually grow the Group in a renowned University by :

1. Imparting the best technical and professional education to students.

2. Creating the most congenial and cordial environment of Teaching learning and Research.
3. Conceiving world - class Education, Ethics and Employability for students in a global
perspective.

Mission of Institute

To explore and ensure the best environment to transform students into creative, knowledge-able,
principled engineers and managers compatible with their abilities in the ever-changing socio-economic
and competitive scenario, by:

1. Imparting intensive teaching and training using the latest technology.

2. Motivating the teachers for higher learning and innovative research activities along with social
services.
3. Generating maximum opportunities for placement of students in National and Multi-National
companies and nurturing entrepreneurship quality.
4. Producing engineers and managers with highly ethical and professional challenges to face the
global environment
5. Producing highly intellectual citizens through technical education to constitute an ideal society
and for meeting social challenges.
 Gyan Ganga College of Technology, Jabalpur

Computer Science & Engineering

Mission and Vision of the Department:

Vision

To ensure the world to save time and other depletable resources and free it from complexity by

providing efficient computing services."

Mission

" To become a pace setting centre by providing knowledge, skills and wisdom to the incumbent
by imparting values based education to enable them to solve complex system by simple
algorithm and to make them innovative, research oriented to serve the global society, by
imbibing highest ethical values “.
 Gyan Ganga College of Technology, Jabalpur

Computer Science & Engineering

Program Objectives
Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage
in independent and life-long learning in the broadest context of technological change.
 Gyan Ganga College of Technology, Jabalpur

Computer Science & Engineering

PSO : Program Specific Outcomes

PSO 1- Able to apply the knowledge gained during the course of the program from Mathematics,
Science & amp; Engineering to solve computation task, and ability to understand, analyze,
design and develop computer programs in the areas related to algorithms, system software,
multi-media, web designing, data analytics and networking. (PO1, PO2, PO3)

PSO 2- Able to comprehend the technological advancements by lifelong learning and usage of
modern tools for analysis and design of application and system software with varying
complexity. (PO4, PO5, PO12)

PSO 3- Able to communicate effectively in oral and written forms with good leadership quality,
team work, managerial skill to work in multi-disciplinary environment, involve in development
of commercially viable projects, demonstrating the practice of professional ethics for sustainable
development of society. (PO6, PO7, PO8, PO9, PO10, PO11)
 Gyan Ganga College of Technology, Jabalpur

Computer Science & Engineering

COURSE OUTCOMES

CO1: Design and verify the combinational circuits

CO2: Understand and realize the Interfacing of memory & various I/O devices with 8085
microprocessor

.
 Gyan Ganga College of Technology, Jabalpur

Computer Science & Engineering

List of Experiment as per University

1 Study of Multiplexer and Demultiplexer

2 Study of Half Adder and Subtractor
3 Study of Full Adder and Subtractor
4 WAP to add two 8 bit numbers and store the result at memory location 2000
5 WAP to multiply two 8 bit numbers stored at memory location 2000 and
2001 and stores the result at memory location 2000 and 2001.
6 WAP to add two 16-bit numbers. Store the result at memory address starting
from 2000.
7 WAP which tests if any bit is '0' in a data byte specified at an address 2000.
If it is so, 00 would be stored at address 2001 and if not so then FF should be
storedat the same address.
8 Assume that 3 bytes of data are stored at consecutive memory addresses of
the data memory starting at 2000. Write a program which loads register C
with (2000), i.e. with data contained at memory address2000, D with (2001),
E with (2002) and A with (2001).
9 Sixteen bytes of data are specified at consecutive data-memory locations
starting at 2000. Write a program which increments the value of all sixteen
bytes by 01.
10 WAP to add t 10 bytes stored at memory location starting from 3000. Store
the result at memory location 300A
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Computer Science & Engineering

List of Experiment with enhancement by The Institute

1 Design & verify the Multiplexer and Demultiplexer .

2 Design & verify the Half Adder and Subtractor
3 Design & verify the Full Adder and Subtractor
4 WAP to add two 8 bit numbers and store the result at memory location 2000
5 WAP to subtract two 8 bit numbers and store the result at memory location 2000
6 WAP to multiply two 8 bit numbers stored at memory location 2000 and
2001 and stores the result at memory location 2000 and 2001.
7 WAP to add two 16-bit numbers. Store the result at memory address starting
from 2000.
8 Assume that 3 bytes of data are stored at consecutive memory addresses of
the data memory starting at 2000. Write a program which loads register C
with (2000), i.e. with data contained at memory address2000, D with (2001),
E with (2002) and A with (2001).
9 Sixteen bytes of data are specified at consecutive data-memory locations
starting at 2000. Write a program which increments the value of all sixteen
bytes by 01.
10 WAP to add t 10 bytes stored at memory location starting from 3000. Store
the result at memory location 300A
 Gyan Ganga College of Technology, Jabalpur

Computer Science & Engineering

Schedule of Practical List Performed

Batch A Batch B
S. Name of Ma Type Catego CO PO PSO Complet Complet Sig
N Experiment
ppi of ry Mappin Mappi Mappi ion ion n
o.
ng Exp. g ng ng
with
Unit
1 Design & I Verifi Core CO1 1,2 PSO 1
verify the cation
Multiplexer &
and Desig
Demultiplex ning
er
2 Design & I Verifi Core CO1 1,2 PSO 1
verify the cation
Half Adder &
and
Desig
Subtractor
ning

3 Design & I Verifi 1,2 PSO 1

verify the cation Core CO1
Full Adder &
and
Desig
Subtractor
ning

4 WAP to add I Code 1,2 PSO 1

two 8 bit
Core CO2
numbers and
store the
result at
memory
location
2000
5 WAP to I Code 1,2 PSO 1
multiply two
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Computer Science & Engineering

8 bit Core CO2

numbers
stored at
memory
location
2000 and
2001
6 WAP to I Code Core CO2 1 PSO 1
subtract two
8 bit
numbers and
store the
result at
memory
location
2000.

7 WAP to add I Code 1,2 PSO 1

two 16-bit
Core CO2
numbers.
Store the
result at
memory
address
starting from
2000.

8 Assume that I Code 1,2 PSO 1

3 bytes of
Core CO2
data are
stored at
consecutive
memory
addresses of
the data
memory
starting at
2000. Write
a program
which loads
register C
with (2000),
i.e. with data
 Gyan Ganga College of Technology, Jabalpur

Computer Science & Engineering

contained at
memory
address
2000, D with
(2001), E
with (2002)
and A with
(2001).

9 Sixteen I Code Core CO2 3 PSO 1

bytes of data
are specified
at
consecutive
data-memory
locations
starting at
2000. Write
a program
which
increments
the value of
all sixteen
bytes by 01.

10 WAP to add I Code CO2 1 PSO 1

t 10 bytes
Core
stored at
memory
location
starting from
3000. Store
the result at
memory
location
300A
 Gyan Ganga College of Technology, Jabalpur

Computer Science & Engineering

Sr.
No Topics/Sub Topics Date Grade Signature Remark
.
Design & verify the Multiplexer and
1
Demultiplexer
3 Design & verify the Half Adder and Subtractor

3 Design & verify the Full Adder and Subtractor

WAP to add two 8 bit numbers and store the
4
result at memory location 2000
WAP to multiply two 8 bit numbers stored at
5
memory location 2000 and 2001
WAP to subtract two 8 bit numbers and store
6 the result at memory location 2000.

WAP to add two 16-bit numbers. Store the

7 result at memory address starting from 2000.

Assume that 3 bytes of data are stored at

consecutive memory addresses of the data
memory starting at 2000. Write a program
8 which loads register C with (2000), i.e. with
data contained at memory address 2000, D
with (2001), E with (2002) and A with (2001).

Sixteen bytes of data are specified at

consecutive data-memory locations starting at
9 2000. Write a program which increments the
value of all sixteen bytes by 01.

WAP to add t 10 bytes stored at memory

location starting from 3000. Store the result at
10
memory location 300A
 Gyan Ganga College of Technology, Jabalpur

Computer Science & Engineering

Practical No. 1

Aim:

Construction and verification of Multiplexer and Demultiplexer

Software:

CEDAR Logic Simulator

Theory:

Multiplexer

A multiplexer is a circuit which has a number of inputs but only 1 output or we can say
multiplexer is a circuit which transmits a large number of information signals(inputs) over a
small number of signal lines(output).Digital multiplexer is a combinational logic circuit and its
function is to select information in binary from one of many inputs and outputs the information
along a single selected output. These circuits are especially useful when a complex logic circuit
is to be shared by a number of input signals. The information to be outputted is selected by the
address line.
In case of 4:1 multiplexer, it has four input lines having a signals as I0,I1,I2 AND I3.For
selecting one of the four input signals we require address which can be a two bit word. The
address lines are designated as S1 and S2. For each combination of selection signals (S1 and S0)
one of the inputs is outputted.
Truth Table:

SELECTION INPUT OUTPUT

S.No
S1 S2 Y
1. 0 0 I0
2. 0 1 I1
3. 1 0 I2
4. 1 1 I3

Circuit Diagram:
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Demultiplexer

Demultiplexer as the name indicates, it has only data input D with 4 outputs namely Q0, Q1, Q2,
Q3 It has two data selector inputs namely S0,S1, at which control bits are applied.

The data bit is transmitted to the data bit Q0, Q1, Q2, Q3 of the output lines. Which particular
output line will be chosen will depend on the value of S1, S0 the control input. Consider the case when S1
S0=00 now the upper AND gate is enable while all other AND gate are disabled. Hence it is not possible
to activate any output other than Y0. Thus Q0=D, if D is low Q0 will be low and if D is high, Q0 will be
high. Considering another case,S1,S0=01. We find that Q1 is activated because second AND gate is
enable. Similarly if S1 S0=11.

Truth Table:

Data Select Outputs

Input Inputs

Din S1 S0 Q3 Q2 Q1 Q0

D 0 0 0 0 0 D
D 0 1 0 0 D 0
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Computer Science & Engineering

D 1 0 0 D 0 0
D 1 1 D 0 0 0

Circuit Diagram:

Result:- Thus ,we have verified the operation of 1:4 Multiplexer and 1:4 De-multiplexer on
CEDAR Logic Simulator.
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Computer Science & Engineering

Practical No. 2

Aim:

Construction and verification of Half Adder and Subtractor.

Software:
CEDAR Logic Simulator

Theory:

Half Adder
It is combinational circuits that perform addition of two bits. This circuit has two inputs A and B
(augend and added) and two outputs- Sum (S) and Carry (C).The sum is a 1 when A and B are
different and carry is a 1when A and B are 1.The truth table for a half adder can be constructed
using the addition table for binary numbers
Truth Table
INPUTS OUTPUTS
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
From the truth table, we can write logical expression for S and C outputs as

S = AB + AB = A exor B

C = AB
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From the equation it is clear that this 1-bit adder can be easily implemented with the help of
EXOR Gate for the output ‘SUM’ and an AND Gate for the carry. Take a look at the
implementation below.

Fig:1 Logic Circuit Diagram of Implementation of Half Adder

For complex addition, there may be cases when you have to add two 8-bit bytes together. This
can be done only with the help of full-adder logic.

Half Subtractor:

A combinational circuit which performs the subtraction of two bits is called half subtractor. The
input variables designate the minuend and the subtrahend bit, whereas the output variables
produce the difference and borrow bits. Half subtractor

The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It
has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).

INPUTS OUTPUTS
A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
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Computer Science & Engineering

Result:- Thus ,we have verified the truth table of Half Adder and Full Subtractor on CEDAR
Logic Simulator.
 Gyan Ganga College of Technology, Jabalpur

Computer Science & Engineering

Practical No. 3
Aim:

Construction and verification Full Adder and Subtractor

Software:

CEDAR Logic Simulator

Theory:

Full Adder
This type of adder is a little more difficult to implement than a half-adder. The main difference
between a half-adder and a full-adder is that the full-adder has three inputs and two outputs. The
first two inputs are A and B and the third input is an input carry designated as CIN. When a full
adder logic is designed we will be able to string eight of them together to create a byte-wide
adder and cascade the carry bit from one adder to the next.
The output carry is designated as COUT and the normal output is designated as S. Take a look at
the truth-table.
INPUTS OUTPUTS
A B CIN COUT S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
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From the above truth-table, the full adder logic can be implemented. We can see that the output S
is an EXOR between the input A and the half-adder SUM output with B and CIN inputs. We
must also note that the COUT will only be true if any of the two inputs out of the three are
HIGH.

S=A EXOR B EXOR

Cin
Cout = AB + ACin + BCin

Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will
half adder will be used to add A and B to produce a partial Sum. The second half adder logic can
be used to add CIN to the Sum produced by the first half adder to get the final S output. If any of
the half adder logic produces a carry, there will be an output carry. Thus, COUT will be an OR
function of the half-adder Carry outputs.
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Computer Science & Engineering

.
Fig 2 Full Adder using Half Adder.
Single Bit full Adder
With this type of symbol, we can add two bits together taking a carry from the next lower order
of magnitude, and sending a carry to the next higher order of magnitude. In a computer, for a
multi-bit operation, each bit must be represented by a full adder and must be added
simultaneously. Thus, to add two 8-bit numbers, you will need 8 full adders which can be formed
by cascading two of the 4-bit blocks. The addition of two 4-bit numbers is shown below.

Full Subtractor

A combinational circuit which performs the subtraction of three input bits is called full
subtractor. The three input bits include two significant bits and a previous borrow bit. A full
subtractor circuit can be implemented with two half subtractors and one OR gate. As in the case
of the addition using logic gates, a full subtractor is made by combining two half-subtractors and
an additional OR-gate. A full subtractor has the borrow in capability (denoted as BIN in the
diagram below) and so allows cascading which results in the possibility of multi-bit subtraction.
The circuit diagram for a full subtractor is given below.
Inputs Outputs

Minuend Subtrahend Borrow in Difference Borrow out

X Y Bin D Bout

0 0 0 0 0

0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
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Result:- Thus ,we have verified the truth table of Full Adder and Subtractor on CEDAR
Logic Simulator.
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Computer Science & Engineering

Practical No. 4
Aim:

WAP to add two 8 bit numbers and store the result at memory location 2000

Software:

JUBIN-8085SIMULATOR

Theory

The first data is brought to Accumulator A and the second one in any one of the other registers,
say B. The addition is done using ADD. The result is then stored at 2000. The ADD instruction
affects flags depending on result.

Algorithm –

1. First add contents of memory location 2000 and 2001 using “ADD” instruction and storing at
2000H.
2. The carry generated is recovered using JNC command and is stored at memory location 2001H.

Source program:-

MVI A, 3 // Move immediate the value 3 in accumulator

MVI B, 6 // Move immediate the value 3 in register B

MVI D,0 // Intialize the value of D (used for carry)

ADD B // Add the content of B with accumulator (A=A+B) and store the result in Accumulator

JNC NEXT // (if carry=0, jump on NEXT)

INR D // if carry=1 then incremnet the value of D by one
NEXT: STA 2000H //Store the value of Accumulator at memory location 2000
MOV A, D // M ove the value of register D in the Accumulator (A)
STA 2001H
HLT //Terminate program execution
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RESULT
Thus the Addition of two 8 bit numbers is stored in the resultant memory
RESULT STORED AT 2000 LOCATION IS 9H

Practical No. 5

WAP to subtract two 8 bit numbers and store the result at memory location
2000

Software:

JUBIN-8085SIMULATOR

Theory

The first data is brought to Accumulator A and the second one in any one of the other registers,
say B. The subtraction is done using SUB. The result is then stored at 2000.

Algorithm –
1. Move immediate the first value in accumulator.
2. Move immediate the first value in accumulator
3. Subtract the content of B with accumulator (A<-A-B) and store the result in Accumulator
4. Store the content of Accumulator in memory location 2000

Source program:-
MVI A, 8 //Move immediate the value 8 in accumulator
MVI B, 4 //Move immediate the value 4 in register B
SUB B //Subtract the content of B with accumulator (A A-B) and store the result in
Accumulator
STA 2000 //Store the content of Accumulator in memory location 2000
HLT //Terminate program execution

RESULT
Thus the Subtraction of two 8 bit numbers is stored in the resultant memory
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AC=4H AND RESULT STORED AT 2000 LOCATION IS 4H

Practical No. 6
Aim:

WAP to multiply two 8 bit numbers stored at memory location 2000 and 2001

Software:

JUBIN-8085SIMULATOR

Algorithm:

Store one of the data in a register (say C register). Move the second data to accumulator. Move the
accumulator content to another register (say B register). Set the data in the C register as a counter. Set the
accumulator value equal to zero. Add the data in B register to the content of accumulator. Decrement the
value in C register. Repeat the addition until the value in the counter register C is zero. The final value in
the accumulator will be the product of the two values.

Source program:-

LDA 2000 // Load Accumulator Directly from Memory 2000

MOV B, A // Copy the content of A (accumulator) in B
LDA 2001 // Load Accumulator Directly from Memory 2001
MOV C, A // Copy the content of A (accumulator) in C (counter)
MVI A, 0 // Initialize Accumulator=0
XYZ: ADD B // Loop Start: Add the content of Accumulator with B and store result in A
DCR C // Decrement the value of Register C by one
JNZ XYZ // If C is not equal to zero then go on loop xyz
STA 2002 // Store the content of Accumulator (Result) in memory location 2000
HLT // Terminate program execution
//Store data at Memory location
#ORG 2000H
#DB 4,5
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RESULT
Thus the Multiplication of two 8 bit numbers is stored in the resultant memory
CONTENT AT LOCATION 2000 IS 4H
CONTENT AT LOCATION 2001 IS 5H

AC=14 AND RESULT STORED AT 2002 LOCATION IS 14H

Practical No. 7

Aim:
WAP to add two 16-bit numbers. Store the result at memory address starting from 2000

Software:

JUBIN-8085SIMULATOR

Algorithm:

1. We are adding two 16 bits number using DAD

2. Store the result in memory location 2000
Source program:-

LHLD 4000 //Load H & L Registers Directly from Memory 4000 L:-4000 and H:-4001
XCHG //Exchange H & L with D & E
LHLD 4002 //Load H & L Registers Directly from Memory 4002 L:-4002 and H:-4003
DAD D //Double Register Add; Add Content of Register Pair H & L with register pair D
&E and Store Result Register Pair H & L

SHLD 2000 //Store I6-bit result of Register Pair H & L in memory locations 2000 and 2001.
HLT //Terminate program execution
//Store data at Memory location begin from 4000H
#ORG 4000H
#DB 6,2,5,4
Result:-
Thus we have add two 16 bit numbers at locations 2000 and 2001H.
Content at location 2000H is 0B
Content at location 2001H is 06
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Practical No. 8
Aim:

Assume that 3 bytes of data are stored at consecutive memory addresses of the data
memory starting at 2000. Write a program which loads register C with (2000), i.e. with
data contained at memory address 2000, D with (2001), E with (2002) and A with (2001).

Software:

JUBIN-8085SIMULATOR

Source program:-

LDA 2000H //Load Accumulator Directly from Memory 2000

MOV C, A //Copy the content of A (accumulator) in C
LDA 2002H //Load Accumulator Directly from Memory 2002
MOV E, A //Copy the content of A (accumulator) in E
LDA 2001H //Load Accumulator Directly from Memory 2001
MOV D, A //Copy the content of A (accumulator) in D
HLT // Terminate program execution
//Store data at Memory location begin from 2000H

#ORG 2000H
#DB 4,3,5
Result:-
Thus data is stored in register C,D, & E.
Content in register C is 04

Content in register D is 03

Content in register E is 05
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Computer Science & Engineering

Practical No. 9
Aim:

Sixteen bytes of data are specified at consecutive data-memory locations starting at 2000.
Write a program which increments the value of all sixteen bytes by 01.

Software:

JUBIN-8085SIMULATOR

Source program:-

MVI H,20H //Move Immediate data 20 in Register H

MVIL,20H //Move Immediate data 00 in Register L (Now HL pair is holding Memory
Address 2000H)
MVI C,16 //Move Immediate data 16 in Register C (C is counter)
GO: INR M //Increment the value of M by 1 (M hold the value of Memory Location that HL
pair Hold)
INX H //Increment the value of register pair by one
DCR C //Decrement the value of Register C by one
JNZ GO //If value of Register C is not equal to zero then go to loop xyz
HLT // Terminate program execution

Result:-
Thus. We have increments the value of all sixteen bytes by 01
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Practical No. 10

Aim:
WAP to add the 10 bytes stored at memory location starting from 3000. Store the result at
memory location 300AH

Software:

JUBIN-8085SIMULATOR
Algorithm:

Move first data to accumulator. Initialize counter register. Add the next data with data in the accumulator.
If there is a carry increments carry register. Decrement the count register. If it is zero store the result. Else
fetch the next data and add with value in the accumulator. Repeat until carry register is zero.

Source program:-

MVI H,20H //Move Immediate data 20 in Register H

MVIL,20H //Move Immediate data 00 in Register L (Now HL pair is holding Memory
Address 2000H)
MVI C,10 //Move Immediate data 16 in Register C (C is counter)
GO: ADD M //ADD the content of accumulator with M (M hold the value of Memory
Location that HL pair Hold)
INX H //Increment the value of register pair by one
DCR C //Decrement the value of Register C by one
JNZ GO //If value of Register C is not equal to zero then go to loop xyz
HLT // Terminate program execution
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Result:-

Thus, we have add 10 bytes number and store the result at memory location 3000H

Viva Questions
1. Simulator:- GNU8085

GNUSim8085 is a graphical simulator, assembler and debugger for the Intel 8085
microprocessor in Linux and Windows

2. What are the various registers in 8085?

Ans: - Accumulator register, Temporary register, Instruction register, Stack Pointer, Program
Counter are the various registers in 8085 .

3. In 8085 name the 16 bit registers?

Ans:- Stack pointer and Program counter all have 16 bits.

4. What are the various flags used in 8085?

Ans:- Sign flag, Zero flag, Auxillary flag, Parity flag, Carry flag.

5. What is Stack Pointer?

Ans:- Stack pointer is a special purpose 16-bit register in the Microprocessor, which holds the
address of the top of the stack.

6. What is Program counter?

Ans:- Program counter holds the address of either the first byte of the next instruction to be
fetched for execution or the address of the next byte of a multi byte instruction, which has not
been completely fetched. In both the cases it gets incremented automatically one by one as the
instruction bytes get fetched. Also Program register keeps the address of the next instruction.

7. Which Stack is used in 8085?

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Ans:- LIFO (Last In First Out) stack is used in 8085.In this type of Stack the last stored
information can be retrieved first.

8. What happens when HLT instruction is executed in processor?

Ans:- The Micro Processor enters into Halt-State and the buses are tri-stated.

9. What is meant by a bus?

Ans:- A bus is a group of conducting lines that carriers data, address, & control signals.

10. In what way interrupts are classified in 8085?

Ans:- In 8085 the interrupts are classified as Hardware and Software interrupts.

11. .Name 5 different addressing modes?

Ans:- Immediate, Direct, Register, Register indirect, Implied addressing modes.

12. .How many interrupts are there in 8085?

Ans:- There are 12 interrupts in 8085.

13. What are input & output devices?

Ans:- Keyboards, Floppy disk are the examples of input devices. Printer, LED / LCD display,
CRT Monitor are the examples of output devices.

14. Difference between 8085 & 8086

The differences between 8085 and 8086microprocessors are: 8085 microprocessor was
developed in 1977 whereas 8086 was developed in 1978. 8085 microprocessor is a 8 bit
microprocessor whereas 8086 is a 16 bit microprocessor. 8085contains 16 bit address bus
and 8086 microprocessor contains 20 bit address bus

15. What is a multiplexer and its types?

Ans. Multiplexer is the device which has n inputs and only one output. It selects one of the input
and passes to the output. There is one more terminal called as select input which decides which
input terminal is to be selected to send output.

Multiplexer Types

Multiplexers are classified into four types:

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2-1 multiplexer ( 1 select line)

4-1 multiplexer (2 select lines)

8-1 multiplexer (3 select lines)

16-1 multiplexer (4 select lines)

16. What are the applications of multiplexer?

 Applications of Multiplexers

Multiplexers are used in various applications wherein multiple-data need to be transmitted by

using single line.

Communication System

A communication system has both a communication network and a transmission system. By

using a multiplexer, the efficiency of the communication system can be increased by allowing
the transmission of data, such as audio and video data from different channels through single
lines or cables.

Computer Memory

Multiplexers are used in computer memory to maintain a huge amount of memory in the
computers, and also to reduce the number of copper lines required to connect the memory to
other parts of the computer.

Telephone Network

In telephone networks, multiple audio signals are integrated on a single line of transmission with
the help of a multiplexer.

Transmission from the Computer System of a Satellite

Multiplexer is used to transmit the data signals from the computer system of a spacecraft or a
satellite to the ground system by using a GSM satellite.

17. Important points for adder and subtractor

 Half subtractor is a combinational circuit which is used to perform subtraction of two
bits, namely minuend and subtrahend.
 There are two outputs required for the implementation of a subtractor. One for the output
and another for borrow
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 Full subtractor is used to perform subtraction of 3 bits, namely minuend bit, subtrahend
bit and borrow from the previous stage.
 Half adder has two inputs while full adder has three outputs; this is the difference
between them.

18. Learn this chart

19. What Is Virtual Memory In Computer?

Answer :
Virtual memory is that when the available RAM memory is not sufficient for the system to run
the current applications it will take some memory from hard disk.This memory is termed as
Virtual memory.
20. Cache Memory:-

1) Cache Memory is very high speed memory used to increase the speed of program by making
current program & data available to the CPU at a rapid rate.
2) Access time to cache memory is less compared to main memory. It contains a copy of potions
of the main memory.
3) When CPU attempts to read a word from main memory, check is made to determine if the
word is in cache. It so, then word is delivered form cache.
4) If word is not there in cache then a block of main memory consisting some word along with
that word, is read into cache and the required word is delivered to CPU. This is called “Principle
of Locality of Reference”.
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5) During a miss if there are no empty blocks in the cache, then some replacement policies such
as FIFO, LRU, LFU, etc. are used.

Cache Mapping Technique:-

The three different types of mapping used for the purpose of cache memory are as follow,
Associative mapping, Direct mapping and Set-Associative mapping.

- Associative mapping: In this type of mapping the associative memory is used to store content
and addresses both of the memory word. This enables the placement of the any word at any place
in the cache memory. It is considered to be the fastest and the most flexible mapping form.

- Direct mapping: In direct mapping the RAM is made use of to store data and some is stored in
the cache. An address space is split into two parts index field and tag field. The cache is used to
store the tag field whereas the rest is stored in the main memory. Direct mapping`s performance
is directly proportional to the Hit ratio.

- Set-associative mapping: This form of mapping is a modified form of the direct mapping where
the disadvantage of direct mapping is removed. Set-associative mapping allows that each word
that is present in the cache can have two or more words in the main memory for the same index
address. (Learn all these mapping)